INTRODUCTION TO VHDL

VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware
Description Language. It is a hardware description language that can be used to
model a digital system at many levels of abstraction, ranging from the algorithmic
level to gate level. VHDL is an IEEE standard.

MAIN FEATURES:
• Supports the whole design process:
1. system level
2. RT level
3. logic level
4. circuit level (to some extent)

• Suitable for specification in

1. behavioral domain
2. structural domain

• Precise simulation semantics is associated with the language

constructs

Basic Constructs:
• The basic building block of a VHDL model is the entity
• An entity is described as a set of design units:
• entity declaration
• architecture body
• package declaration
• package body
• configuration declaration

Using VHDL for design synthesis:

• Define the design requirement
• Describe the design in VHDL code
• Simulate the source code
• Synthesize, optimize, and fit the design
• Simulate the design
• Implement the design
History:
VHDL was developed as an alternative to huge, complex manuals which were
subject to implementation-specific details. The idea of being able to simulate this
documentation was so obviously attractive that logic simulators were developed
that could read the VHDL files. The next step was the development of logic
synthesis tools that read the VHDL, and output a definition of the physical
implementation of the circuit. The same VHDL code could be synthesized
differently for lowest area, lowest power consumption, highest clock speed, or
other requirements. It has become now one of industry’s standard languages
used to describe digital systems.
Important dates:
• 1983: development started with support from US government.
• 1987: adopted by IEEE as a standard (IEEE Std. 1076 - 1987).
• 1993: VHDL’92 adopted as a standard after revision of the initial
version (IEEE Std. 1076 - 1993).

Levels of representation and abstraction:

A digital system can be represented at different levels of abstraction. This keeps

the description and design of complex systems manageable.

The highest level of abstraction is the behavioral level that describes a system in
terms of what it does (or how it behaves) rather than in terms of its components
and interconnection between them. A behavioral description specifies the
relationship between the input and output signals.

The structural level, on the other hand, describes a system as a collection of

gates and components that are interconnected to perform a desired function.
Types of modeling in VHDL:

Behavioral Modeling: Sequential Statements

The basis for sequential modeling is the process construct.

A process statement is the main construct in behavioral modeling that allows you
to use sequential statements to describe the behavior of a system over time. The
syntax for a process statement is

[process_label:] process [ (sensitivity_list) ] [is]

[ process_declarations]

begin

list of sequential statements such as:

signal assignments

variable assignments

case statement

exit statement

if statement

loop statement

next statement

null statement

procedure call

wait statement

end process [process_label];

Structural Modeling:

A structural way of modeling describes a circuit in terms of components and

its interconnection. Each component is supposed to be defined earlier (e.g. in
package) and can be described as structural, a behavioral or dataflow model.
At the lowest hierarchy each component is described as a behavioral model,
using the basic logic operators defined in VHDL. In general structural
modeling is very good to describe complex digital systems, though a set of
components in a hierarchical fashion.

Dataflow Modeling – Concurrent Statements:

The dataflow modeling describes a circuit in terms of its function and the flow of
data through the circuit. Concurrent signal assignments are event triggered and
executed as soon as an event on one of the signals occurs. The syntax is as
follows:

Target_signal <= expression;

in which the value of the expression transferred to the target_signal. As soon as

an event occurs on one of the signals, the expression will be evaluated. The type
of the target_signal has to be the same as the type of the value of the
expression.