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A B C D E Compal Confidential Model Name : P5WE0 File Name : LA-6901P
A
B
C
D
E
Compal Confidential
Model Name : P5WE0
File Name : LA-6901P
1
1
BOM P/N:43
Compal Confidential
2
2
P5WE0 M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P GS/GV
2010-08-11
3
3
REV:0.1
4
4
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2010/08/11
2010/08/11
2010/08/11
2011/08/11
2011/08/11
2011/08/11
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Cover Page
Cover Page
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.1
0.1
P5WE0 M/B LA-6901P Schematic
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
P5WE0 M/B LA-6901P Schematic
P5WE0 M/B LA-6901P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 27, 2010
Friday, August 27, 2010
Friday, August 27, 2010
Sheet
Sheet
Sheet
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of
59
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A B C D E Fan Control page 38 1 1 PEG(DIS) 100MHz PCI-E 2.0x16
A
B
C
D
E
Fan Control
page 38
1
1
PEG(DIS)
100MHz
PCI-E 2.0x16
5GT/s PER LANE
Intel
Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X2
Nvidia
133MHz
Dual Channel
Sandy Bridge
BANK 0, 1, 2, 3
page 12,13
N12P GS/GV
Processor
1.5V DDRIII 1066/1333
page23~31
rPGA989
page 5~11
HDMI(DIS)
CRT(DIS)
LVDS(DIS)
USB 2.0 conn x2
Bluetooth
CMOS Camera
3G connector
FDI x8
DMI x4
Conn
USB port 9,12 on 3G/B
HDMI Conn.
CRT Conn.
LVDS Conn.
USB port 0,1 on
USB/B
USB port 13
USB port 10
100MHz
100MHz
page 39
page 39
page 32
page 32
page 34
page 33
page 32
2.7GT/s
1GB/s x4
USBx14
3.3V 48MHz
2
2
LVDS(UMA/OPTIMUS)
Intel
CRT(UMA/OPTIMUS)
HD Audio
3.3V 24MHz
Cougar Point-M
TMDS(UMA/OPTIMUS)
PCH
HDA Codec
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
100MHz
989pin BGA
ALC271X/277X
port 5
port 2,3
port 1
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
100MHz
page 43
SPI
page 14~22
LAN(GbE) &
USB 3.0 conn x1
MINI Card x2
Card Reader
WLAN, WWAN
BCM57785
USB port 12,13
SPI ROM x1
Int. Speaker
Phone Jack x 2
page 45
page 38
page 36
page 14
port 0,1
port 2
page 44
page 44
SATA HDD
SATA CDROM
Card Reader
RJ45
Conn.
Conn.
LPC BUS
3
3
page 35
page 35
Conn.
page 37
page 37
33MHz
ENE KB930
Sub-board
page 40
LS-6901P
LF-6901P
RTC CKT.
USB 2.0/B 2Port
USB Port0,1
FPC for USB3.0
CPU XDP
page 39
page 14
Touch Pad
Int.KBD
page 6
page 41
page 41
LS-6902P
Power On/Off CKT.
PWR/B
PCH XDP
page 42
page 39
BIOS ROM
page 14
page 40
DC/DC Interface CKT.
LS-6903P
page 46
3G/B
4
4
page 41
Power Circuit DC/DC
LS-6904P
page 48~56
USB 3.0 /B
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2010/08/11
2010/08/11
2010/08/11
2011/08/11
2011/08/11
2011/08/11
Title
Title
Title
1 port as USB3.0
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Block Diagrams
Block Diagrams
Block Diagrams
1 port as USB2.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
page 41
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.1
0.1
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
P5WE0 M/B LA-6901P Schematic
P5WE0 M/B LA-6901P Schematic
P5WE0 M/B LA-6901P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 27, 2010
Friday, August 27, 2010
Friday, August 27, 2010
Sheet
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59
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A B C D E Voltage Rails SIGNAL STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V
A
B
C
D
E
Voltage Rails
SIGNAL
STATE
SLP_S1#
SLP_S3#
SLP_S4#
SLP_S5#
+VALW
+V
+VS
Clock
Power Plane
Description
S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
Full ON
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
BATT+
Battery power supply (12.6V)
N/A
N/A
N/A
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
1
1
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
+VGA_CORE
Core voltage for GPU
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
+VGFX_CORE
Core voltage for UMA graphic
ON
OFF
OFF
+0.75VS
+0.75VP to +0.75VS switched power rail for DDR terminator
ON
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
+1.05VSDGPU
+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
ON
OFF
OFF
+1.05VS_VTT
+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
ON
OFF
OFF
Board ID / SKU ID Table for AD channel
+1.05VS_PCH
+1.05VS_VCCP to +1.05VS_PCH power for PCH
ON
OFF
OFF
+1.5V
+1.5VP to +1.5V power rail for DDRIII
ON
ON
OFF
Vcc
3.3V +/- 5%
+1.5VS
+1.5V to +1.5VS switched power rail
ON
OFF
OFF
Ra/Rc/Re
100K +/- 5%
+1.5VSDGPU
+1.5VS to +1.5VSDGPU switched power rail for GPU
ON
OFF
OFF
Board ID
Rb / Rd / Rf
V
min
V
typ
AD_BID
AD_BID
V AD_BID max
+1.8VS
(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
ON
OFF
OFF
0
0
0 V
0 V
0 V
EVT
+1.8VSDGPU
+1.8VS to +1.8VSDGPU switched power rail for GPU
ON
OFF
OFF
1
8.2K +/- 5%
0.216
V
0.250
V
0.289
V
DVT
+3VALW
+3VALW always on power rail
ON
ON
ON*
2
18K +/- 5%
0.436
V
0.503
V
0.538
V
PVT
+3VALW_EC
+3VALW always to KBC
ON
ON
ON*
3
33K +/- 5%
0.712
V
0.819
V
0.875
V
Pre-MP
+3V_LAN
+3VALW to +3V_LAN power rail for LAN
ON
ON
ON*
4
56K +/- 5%
1.036
V
1.185
V
1.264
V
+3VALW_PCH
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
ON
ON
ON*
5
100K +/- 5%
1.453
V
1.650
V
1.759
V
2
2
+3VS
+3VALW to +3VS power rail
ON
OFF
OFF
6
200K +/- 5%
1.935
V
2.200
V
2.341
V
+5VALW
+5VALWP to +5VALW power rail
ON
ON
ON*
7
NC
2.500
V
3.300
V
3.300
V
+5VALW_PCH
+5VALW to +5VALW_PCH power rail for PCH (Short resister)
ON
ON
ON*
+5VS
+5VALW to +5VS switched power rail
ON
OFF
OFF
BOARD ID Table
BTO Option Table
+VSB
+VSBP to +VSB always on power rail for sequence control
ON
ON
ON*
BTO Item
BOM Structure
+RTCVCC
RTC power
ON
ON
ON
Board ID
PCB Revision
UMA Only
UMAO@
0
0.1
UMA with OPTIMUS
UMA@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
1
0.2
Dis with OPTIMUS
DIS@
2
EC SM Bus1 address
EC SM Bus2 address
0.3
DIS Only
DISO@
3
1.0
OPTIMUS
OPT@
Device
Address
Device
Address
4
Non-OPTIMUS
NOPT@
Smart Battery
0001 011X b
5
3G
3G@
6
Blue Tooth
BT@
7
USB2.0
USB20@
PCH SM Bus address
USB3.0
USB30@
VRAM
X76@
3
3
Device
Address
USB Port Table
Connector
CONN@
Clock Generator (9LVS3199AKLFT,
1101 0010b
Unpop
@
RTM890N-631-VB-GRT)
3 External
USB 2.0
USB 1.1
Port
LAN Chip A0 version
A0@
DDR DIMM0
1001 000Xb
USB Port
LAN Chip B0 version
B0@
DDR DIMM2
1001 010Xb
0
USB/B (Right Side)
UHCI0
1
USB/B (Right Side)
3G & BT & USB30 & USB20 Config
2
USB 2.0 & USB3.0 Conn.
3G SKU: 3G@
BT SKU: BT@
USB30 SKU: USB30@
USB20 SKU: USB20@
OPTMIUS SKU: OPT@
Non-OPTMIUS SKU: NOPT@
UHCI1
3
EHCI1
4
LAN Chip A0 version: A0@
LAN chip B0 Version: B0@
UHCI2
5
6
UHCI3
7
BOM Config
8
Mini Card 1(WLAN)
UHCI4
UMA Only:
BT@/3G@/USB30@/UMA@/UMAO@/NOPT@/A0@
9
3G/B(WWAN)
OPTIMUS:
BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@
10
Camera
EHCI2
UHCI5
DIS Only:
BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@
11
Mini Card 2(Reserved)
4
4
VRAM BOM Config
12
SIM Card (3G/B)
UHCI6
X76***BOL01:
Samsung
13
Blue Tooth
X76***BOL02:
Hynix
VRAM P/N :
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
2010/08/11
2010/08/11
2010/08/11
2011/08/11
2011/08/11
2011/08/11
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Notes List
Notes List
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.1
0.1
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
P5WE0 M/B LA-6901P Schematic
P5WE0 M/B LA-6901P Schematic
P5WE0 M/B LA-6901P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 27, 2010
Friday, August 27, 2010
Friday, August 27, 2010
Sheet
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www.vinafix.vn

 

5

4

3

2

1

 
 

+1.05VS_VTT

 
R517 R517 12
R517 R517
12

24.9_0402_1% 24.9_0402_1%

PEG_ICOMPI and PEG_RCOMPO signals should be shorted and routed, max length = 500 mils,trace width=4mils PEG_ICOMPO signals should be routed with - max

 
 

JCPU1A

JCPU1A

   

length = 500 mils,trace width=12mils spacing =15mils

 

D

   

J22

PEG_COMP

D

 

PEG_ICOMPI

J21

  PEG_ICOMPI J21  
 
 

15

15

DMI_CRX_PTX_N0

DMI_CRX_PTX_N1

DMI_CRX_PTX_N2

DMI_CRX_PTX_N3

 

B27

PEG_ICOMPO

H22

B25

A25B25 B24

B24

DMI_RX#[0]

DMI_RX#[1]

DMI_RX#[2]

 

PEG_RCOMPO

   

15

   

15

K33

PEG_GTX_C_HRX_N15

C46

C46

1

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_N15

 
 

DMI_RX#[3]

 

PEG_RX#[0]

PEG_GTX_C_HRX_N14

M35

C49

C49

1

1

1

2

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_N14

PEG_GTX_HRX_N13

0.22U_0402_10V6K

0.22U_0402_10V6K

15

15

15

15

DMI_CRX_PTX_P0

DMI_CRX_PTX_P1

DMI_CRX_PTX_P2

DMI_CRX_PTX_P3

 

B28

PEG_RX#[1]

L34

PEG_GTX_C_HRX_N13

C51

C51

B26

A24B26 B23

B23

DMI_RX[0]

PEG_RX#[2]

J35

PEG_GTX_C_HRX_N12

C53

C53

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_N12

DMI_RX[1]

PEG_RX#[3]

J32

PEG_GTX_C_HRX_N11

C60

C60

C75

C75

C82

C82

1

C92

C92

1

1

1

1

1

2

2

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_N11

PEG_GTX_HRX_N10

PEG_GTX_HRX_N[0PEG_GTX_HRX_P[0 15] 15]

PEG_GTX_HRX_P[0

15]

15]

22

22

DMIIntel(R)

DMIeDP

Intel(R) FDI

DMI_RX[2]

DMI_RX[3]

DMI_TX#[0]

DMI_TX#[1]

DMI_TX#[2]

DMI_TX#[3]

DMI_TX[0]

DMI_TX[1]

DMI_TX[2]

DMI_TX[3]

FDI0_TX#[0]

FDI0_TX#[1]

FDI0_TX#[2]

FDI0_TX#[3]

FDI1_TX#[0]

FDI1_TX#[1]

FDI1_TX#[2]

FDI1_TX#[3]

FDI0_TX[0]

FDI0_TX[1]

FDI0_TX[2]

FDI0_TX[3]

FDI1_TX[0]

FDI1_TX[1]

FDI1_TX[2]

FDI1_TX[3]

PEG_RX#[4]

PEG_GTX_C_HRX_N10

H34

C71

C71

 

PEG_RX#[5]

H31

PEG_GTX_C_HRX_N9

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_N9

PEG_GTX_HRX_N8

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_N7

PEG_GTX_HRX_N6

0.22U_0402_10V6K

0.22U_0402_10V6K

15

15

15

15

DMI_CTX_PRX_N0

DMI_CTX_PRX_N1

DMI_CTX_PRX_N2

DMI_CTX_PRX_N3

PEG_RX#[6]

PEG_GTX_C_HRX_N8

G33

PEG_HTX_C_GRX_N[0PEG_HTX_C_GRX_P[0

PEG_HTX_C_GRX_P[0

15]

15]

22

22

G21 E22 F21 D21

E22

F21

D21

PEG_RX#[7]

PEG_GTX_C_HRX_N7

G30

PEG_RX#[8]

PEG_GTX_C_HRX_N6

F35

C93

C93

PEG_RX#[9]

PEG_GTX_C_HRX_N5

E34

C102

C102

C111

C111

1 DIS@

2

1 DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_N5

PEG_GTX_HRX_N4

0.22U_0402_10V6K

0.22U_0402_10V6K

   
 

PEG_RX#[10]

PEG_GTX_C_HRX_N4

E32

15

DMI_CTX_PRX_P0

PEG_RX#[11]

PEG_GTX_C_HRX_N3

D33

C113

C113

2

1 DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_N3

15

15

DMI_CTX_PRX_P1

DMI_CTX_PRX_P2

G22 D22 F20 C21

D22

F20

C21

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_RX#[12]

PEG_RX#[13]

PEG_RX#[14]

PEG_RX#[15]

PEG_RX[0]

PEG_RX[1]

PEG_RX[2]

PEG_RX[3]

PEG_RX[4]

PEG_RX[5]

PEG_RX[6]

PEG_RX[7]

PEG_RX[8]

PEG_RX[9]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]

PEG_TX#[10]

PEG_TX#[11]

PEG_TX#[12]

PEG_TX#[13]

PEG_TX#[14]

PEG_GTX_C_HRX_N2

D31

PEG_GTX_C_HRX_N1

B33

C125

C125

C129

C129

1 DIS@

2

1 DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_N2

PEG_GTX_HRX_N1

15

DMI_CTX_PRX_P3

PEG_GTX_C_HRX_N0

C32

J33

PEG_GTX_C_HRX_P15

C144

C144

C47

C47

1 DIS@

2

1 DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_N0

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_P15

 

L35

K34

PEG_GTX_C_HRX_P14

PEG_GTX_C_HRX_P13

C50

C50

C52

C52

C56

C56

C66

1 DIS@

1 DIS@

2

2

1 DIS@

2

1 DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_P14

PEG_GTX_HRX_P13

PEG_GTX_HRX_P12

PEG_GTX_HRX_P11

PEG_GTX_HRX_P10

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

 

15

FDI_CTX_PRX_N0

 

A21

PEG_GTX_C_HRX_P12

H35

15

15

FDI_CTX_PRX_N1

FDI_CTX_PRX_N2

H19

E19

F18

B21

C20H19 E19 F18 B21 D18 E17

D18

E17

PEG_GTX_C_HRX_P11

PEG_GTX_C_HRX_P10

G34

H32

C66

C

15

15

15

15

FDI_CTX_PRX_N3

FDI_CTX_PRX_N4

FDI_CTX_PRX_N5

FDI_CTX_PRX_N6

G31

F33

F30

E35

PEG_GTX_C_HRX_P9

PEG_GTX_C_HRX_P8

PEG_GTX_C_HRX_P7

PEG_GTX_C_HRX_P6

C68

C68

C81

C81

C86

C86

C89

C89

C100

C100

1 DIS@

2

1 DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_P9

PEG_GTX_HRX_P8

1 DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_P7

PEG_GTX_HRX_P6

1 1 DIS@

2

2

C

15

FDI_CTX_PRX_N7

PEG_GTX_C_HRX_P5

E33

PEG_GTX_C_HRX_P4

F32

C105

C105

1 DIS@

2

PEG_GTX_HRX_P5

PEG_GTX_HRX_P4

0.22U_0402_10V6K

0.22U_0402_10V6K

 
EDP_COMP
EDP_COMP

EDP_COMP

 

PEG_GTX_C_HRX_P3

D34

PEG_GTX_C_HRX_P2

C106

C106

C117

C117

1 DIS@

2

1 DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_P3

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_P2

 

15

15

15

15

FDI_CTX_PRX_P0

FDI_CTX_PRX_P1

FDI_CTX_PRX_P2

FDI_CTX_PRX_P3

A22

G19

E20

G18

E31

C33

PEG_GTX_C_HRX_P1

PEG_GTX_C_HRX_P0

B32

C119

C119

C135

C135

C138

C138

1 DIS@

2

1 DIS@

2

1 DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_P1

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_GTX_HRX_P0

15

15

FDI_CTX_PRX_P4

FDI_CTX_PRX_P5

B20

PEG_HTX_GRX_N15

M29

C516

C516

 

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_N14

C19

PEG_HTX_GRX_N14

M32

C520

C520

1 2

1 DIS@

2

+1.05VS_VTT 15 15 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 D19 F17 M31 L32 L29 PEG_HTX_GRX_N13 PEG_HTX_GRX_N12

+1.05VS_VTT

15

15

FDI_CTX_PRX_P6

FDI_CTX_PRX_P7

D19

F17

M31

L32

L29

PEG_HTX_GRX_N13

PEG_HTX_GRX_N12

PEG_HTX_GRX_N11

PEG_HTX_GRX_N10

C529

C529

1 DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_N13

PEG_HTX_C_GRX_N12

C534

C534

1

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_N11

C538

C538

1

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_N10

 
C538 C538 1 2 DIS@ DIS@ 0.22U_ 0402_10V6K 0.22U_ 0402_10V6K PEG_HTX_C_GRX_N10  

15

15

FDI_FSYNC0

FDI_FSYNC1

J18

J17

FDIeDP

FDI0_FSYNC

FDI1_FSYNC

FDI_INT

FDI0_LSYNC

FDI1_LSYNC

eDP_COMPIO

eDP_ICOMPO

eDP_HPD

eDP_AUX

eDP_AUX#

eDP_TX[0]

eDP_TX[1]

eDP_TX[2]

eDP_TX[3]

 

K31

K28

J30

PEG_HTX_GRX_N9

PEG_HTX_GRX_N8

PEG_HTX_GRX_N7

1

C544

C544

C542

C542

1

C540

C540

1

2

2

2

DIS@

DIS@

DIS@

DIS@

1 DIS@

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_N9

PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_N7

C546

C546

 

eDP_COMPIO and ICOMPO signals should

12

R145

R145

24.9_0402_1%

24.9_0402_1%

15

FDI_INT

H20

J28

H29

PEG_HTX_GRX_N6

PEG_HTX_GRX_N5

C548

C548

2

1 DIS@

2

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_N6

PEG_HTX_C_GRX_N5

15

FDI_LSYNC0

J19

G27

PEG_HTX_GRX_N4

C550

C550

1 DIS@

2

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_N4

be shorted near balls, Trace Width for EDP_COMPIO=4mils,

EDP_ICOMPO=12mils,

and both length less than 500 mils should not be left floating ,even if disable eDP function

15 FDI_LSYNC1

H17

E29

F27

D28

F26

PEG_HTX_GRX_N3

PEG_HTX_GRX_N2

PEG_HTX_GRX_N1

PEG_HTX_GRX_N0

E25

C552

C552

C558

C558

C560

C560

1 DIS@

DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_N3

PEG_HTX_C_GRX_N2

C554

C554

C556

C556

DIS@

DIS@

DIS@

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

DIS@

DIS@

1 DIS@

DIS@

2

1

1

1

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_N1

PEG_HTX_C_GRX_N0

2

   

A18

 

PEG_TX#[15]

 

B

B A17 B16 PEG_TX[0] PEG_TX[1] M28 M33 M30 PEG_HTX_GRX_P15 PEG_HTX_GRX_P14 PEG_HTX_GRX_P13 PEG_HTX_GRX_P12

A17

B16A17

PEG_TX[0]

PEG_TX[1]

M28

M33

M30

PEG_HTX_GRX_P15

PEG_HTX_GRX_P14

PEG_HTX_GRX_P13

PEG_HTX_GRX_P12

C515

C515

C533

C533

C528

C528

1

1 DIS@

DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_P15

PEG_HTX_C_GRX_P14

PEG_HTX_C_GRX_P13

PEG_HTX_C_GRX_P12

1

2

DIS@

DIS@

2

DIS@

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

B

 

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

L31

PEG_HTX_GRX_P11

C539

C539

C536

C536

1 1 2

2

DIS@

DIS@

DIS@

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_P11

PEG_HTX_C_GRX_P10

 

C15  L28 PEG_HTX_GRX_P10  

L28

PEG_HTX_GRX_P10

 

D15K30 PEG_HTX_GRX_P9 C541 C541 C543 C543 C545 C545 1 DIS@ 2 DIS@ 2 1 DIS@

K30

PEG_HTX_GRX_P9

C541

C541

C543

C543

C545

C545

1 DIS@

2

DIS@

2

1 DIS@

DIS@

DIS@

DIS@

2

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_P9

PEG_HTX_C_GRX_P8

PEG_HTX_C_GRX_P7

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

 

K27

PEG_HTX_GRX_P8

J29

PEG_HTX_GRX_P7

 

C17  J27 PEG_HTX_GRX_P6 C547 C547 1 1 2 DIS@ DIS@ 0.22U_0402_10V6K 0.22U_0402_10V6K PEG_HTX_C_GRX_P6

J27

PEG_HTX_GRX_P6

C547

C547

1

1 2

DIS@

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_P6

F16

H28

PEG_HTX_GRX_P5

C549

C549

C551

C551

1

1

1

2

2

DIS@

DIS@

2

DIS@

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_P5

PEG_HTX_C_GRX_P4

PEG_HTX_C_GRX_P3

DIS@

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

C16  PEG_HTX_GRX_P4 G28

 

PEG_HTX_GRX_P4

G28

G15E28 PEG_HTX_GRX_P3 C553 C553 E28 PEG_HTX_GRX_P3 C553 C553

E28

PEG_HTX_GRX_P3

C553

C553

 

F28

PEG_HTX_GRX_P2

C555

C555

1

2

DIS@

DIS@

DIS@

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_P2

PEG_HTX_C_GRX_P1

0.22U_0402_10V6K

0.22U_0402_10V6K

 

C18  eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] PEG_HTX_GRX_P1 D27 C557 C557 1 2

eDP_TX#[0]

eDP_TX#[1]

eDP_TX#[2]

eDP_TX#[3]

PEG_HTX_GRX_P1

D27

C557

C557

1

2

E16

D16E16 F15 E16 F15

F15E16 D16

E26

PEG_HTX_GRX_P0

C559

C559

1

2

DIS@

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

PEG_HTX_C_GRX_P0

D25

 

C561

C561

DIS@

DIS@

0.22U_0402_10V6K

0.22U_0402_10V6K

 
 
1 2
1
2
 
   
 

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

   

CONN@ CONN@

Typ- suggest 220nF. The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s)

 

A

A

 

Security Classification

Security Classification

Security Classification

 

Compal Secret Data

Compal Secret Data

Compal Secret Data

   
 

Issued Date

Issued Date

Issued Date

 

2010/08/11

2010/08/11

2010/08/11

Deciphered Date

Deciphered Date

Deciphered Date

2011/08/11

2011/08/11

2011/08/11

Title

Title

Title

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

 
 

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Size

Size

Size

Custom

Custom

Custom

Document Number

Document Number

Document Number

P5WE0 M/B LA-6901P Schematic

P5WE0 M/B LA-6901P Schematic

P5WE0 M/B LA-6901P Schematic

Rev

Rev

Rev

0.1

0.1

0.1

Date:

Date:

Date:

Friday, August 27, 2010

Friday, August 27, 2010

Friday, August 27, 2010

Sheet

Sheet

Sheet

4

4

4

of

of

of

59

59

59

 

5

 

4

   

3

 

2

 

1

www.vinafix.vn

5 4 3 2 1 +1.05VS_VTT +1.05VS_VTT +1.05VS_VTT @JXDP1 @ JXDP1 1 2 GND0 GND1
5
4
3
2
1
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
@JXDP1 @
JXDP1
1
2
GND0
GND1
XDP_PREQ#
3
4
OBSFN_A0
OBSFN_C0
XDP_PRDY#
5
6
OBSFN_A1
OBSFN_C1
1
1
7
8
GND2
GND3
XDP_BPM#0
Place near JXDP1
9
10
OBSDATA_A0
OBSDATA_C0
XDP_BPM#1
11
12
13 OBSDATA_A1
OBSDATA_C1
@
@
@
@
14
2
2
XDP_BPM#2
GND4
GND5
16
XDP_BPM#3
15 OBSDATA_A2
OBSDATA_C2
17
18
+3VS
R58 R58
19 OBSDATA_A3
OBSDATA_C3
20
GND6
GND7
4.7K_0402_5% 4.7K_0402_5%
21
22
D
23 OBSFN_B0
OBSFN_D0
D
1
2
+3VS
24
25 OBSFN_B1
OBSFN_D1
26
XDP_BPM#4
GND8
GND9
28
1 SMB_DATA_S3
XDP_BPM#5
27 OBSDATA_B0
OBSDATA_D0
14,37
PCH_SMBDATA
6
29
30
31 OBSDATA_B1
OBSDATA_D1
+3VS
32
XDP_BPM#6
GND10
GND11
Q6A Q6A
33
34
XDP_BPM#7
35 OBSDATA_B2
OBSDATA_D2
XDP_DBRESET#
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
R40
R40
36
2
1 1K_0402_5%
1K_0402_5%
OBSDATA_B3
OBSDATA_D3
@ @
R59
R59
37
38
+3VS
H_CPUPWRGD
H_CPUPWRGD_XDP
39 GND12
GND13
CLK_CPU_ITP
R54
R54
1 @
@
2
1K_0402_5%
1K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
40
CLK_CPU_ITP
14
CFD_PWRBTN#_XDP
PWRGOOD/HOOK0
ITPCLK/HOOK4
CLK_CPU_ITP#
1 2
+3VS
15,39
PBTN_OUT#
R55
R55
1 @
@
2
0_0402_5%
0_0402_5%
42
CLK_CPU_ITP#
14
41 HOOK1
ITPCLK#/HOOK5
44
CFG0
XDP_HOOK2
43 VCC_OBS_AB
VCC_OBS_CD
XDP_RST#_R
R56
R56
R39
R39
1 1K_0402_5%
1K_0402_5%
7
CFG0
1 @
@
2
1K_0402_5%
1K_0402_5%
2 @ @
45
46
PLT_RST# 17,35,38,39,45
4 SMB_CLK_S3
SYS_PWROK
SYS_PWROK_XDP
47 HOOK2
RESET#/HOOK6
XDP_DBRESET#
14,37
PCH_SMBCLK
R57
R57
1 @
@
2
0_0402_5%
0_0402_5%
3
48
HOOK3
DBR#/HOOK7
50
SMB_DATA_S3
49 GND14
GND15
XDP_TDO
Q6B Q6B
51
52
SMB_CLK_S3
53 SDA
TD0
XDP_TRST#
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
54
SCL
XDP_TDI
TRST#
@ @
55
56
XDP_TCK
57 TCK1
TDI
XDP_TMS
58
59 TCK0
TMS
60
GND16
GND17
SAMTE_BSH-030-01-L-D-A
SAMTE_BSH-030-01-L-D-A
JCPU1B
JCPU1B
C
SNB_IVB# had changed the name to
PROC_SELCT#,function for future platform,
connect to the DF_TVS strap on the PCH
C
CLK_CPU_DMI
A28
14
CLK_CPU_DMI
BCLK
CLK_CPU_DMI#
17 H_SNB_IVB#
C26
A27
14
CLK_CPU_DMI#
SNB_IVB#
BCLK#
If use External Graphic or
AN34
SKTOCC#
A16
R516
R516
2
1 1K_0402_5%
1K_0402_5%
use integrated without eDP
DPLL_REF_SSCLK
R518
R518
2
1 1K_0402_5%
1K_0402_5%
A15
+1.05VS_VTT
DPLL_REF_SSCLK#
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
H_CATERR#
T6
T6
PAD
PAD
AL33
CATERR#
@
@
R93
R93
0_0402_5%
0_0402_5%
H_PECI_ISO
SM_DRAMRST#
Processor Pullups
18,39
H_PECI
1
2
AN33
R8
SM_DRAMRST# 6
PECI
SM_DRAMRST#
H_CPUPWRGD_R
C128
C128
+1.05VS_VTT
R84
R84
10K_0402_5%
10K_0402_5%
R91 R91
62_0402_5%
62_0402_5%
R92
R92
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
2
1
H_PROCHOT#
56_0402_5%
56_0402_5%
H_PROCHOT#_R
SM_RCOMP0
R231
R231
140_0402_1%
140_0402_1%
39,49
H_PROCHOT#
AK1
2
1
AL32
SM_RCOMP[0]
SM_RCOMP1
1
2
PROCHOT#
A5
SM_RCOMP[1]
SM_RCOMP2
R566
R566
2
1
25.5_0402_1%
25.5_0402_1%
R97 R97
A4
R571
R571
2
1
200_0402_1%
200_0402_1%
C59
C59
SM_RCOMP[2]
0_0402_5%
0_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
H_THEMTRIP#_R
DDR3 Compensation Signals
18 H_THRMTRIP#
AN32
1
2
THERMTRIP#
PU/PD for JTAG signals
+1.05VS_VTT
Buffered reset to CPU
XDP_TMS
+3VS
0_0402_5% 0_0402_5%
R106
R106
2
1
51_0402_5%
51_0402_5%
XDP_PRDY#_R
XDP_PRDY#
AP29
2
@
@
1
R80
R80
XDP_TDI_R
PRDY#
XDP_PREQ#_R
XDP_PREQ#
R99
R99
51_0402_5%
51_0402_5%
AP27
2
@
@
1
R83
R83
2
1
PREQ#
0_0402_5%
0_0402_5%
XDP_TCK
XDP_TDO
+1.05VS_VTT
ESD request
2010/07/27
1
AR26
R105
R105
R96 R96
XDP_TMS
2
1
51_0402_5%
51_0402_5%
TCK
C162 C162
B
AR27
0_0402_5%
0_0402_5%
H_PM_SYNC_R
XDP_TRST#
XDP_TCK
B
TMS
0.1U_0402_16V4Z 0.1U_0402_16V4Z
15 H_PM_SYNC
AM34
AP30
1
2
R111
R111
2
1
51_0402_5%
51_0402_5%
PM_SYNC
TRST#
2
XDP_TDI
XDP_TRST#
XDP_TDI_R
AR28
R81
R81
XDP_TDO_R
R100
R100
0_0402_5%
0_0402_5%
XDP_TDO
TDI
2
R90 R90
R95 R95
2
1
51_0402_5% 51_0402_5%
AP26
1 1 R110
R110
0_0402_5%
H_CPUPWRGD_R
2
0_0402_5%
0_0402_5%
0_0402_5%
TDO
75_0402_5% 75_0402_5%
18 H_CPUPWRGD
AP33
1
2
UNCOREPWRGOOD
@
@
R87 R87
U7 U7
UNCOREPWRGOOD: CORE OK
1 R782 R782
2
BUFO_CPU_RST#
43_0402_1%
43_0402_1%
BUF_CPU_RST#
DBRESET#_R
XDP_DBRESET#
1
AL35
XDP_DBRESET# 15
0_0402_5%
0_0402_5%
PM_DRAM_PWRGD_R
1 R101
R101
2
0_0402_5%
0_0402_5%
PLT_RST#
NC
1
2
DBR#
4
V8
Y
1 R64 R64
SM_DRAMPWROK
2
2
A
XDP_BPM#0_R
XDP_BPM#0
0_0402_5%
0_0402_5%
SN74LVC1G07DCKR_SC70-5 SN74LVC1G07DCKR_SC70-5
SM_DRAMPWROK:DRAM power ok
@
@
AT28
0_0402_5%
0_0402_5%
2
@ @
1
R79
R79
XDP_BPM#1_R
XDP_BPM#1
BPM#[0]
R88 R88
AR29
XDP_BPM#2_R
XDP_BPM#2
BPM#[1]
0_0402_5%
0_0402_5%
2
@
@
1
R75
R75
0_0402_1% 0_0402_1%
BUF_CPU_RST#
AR30
XDP_BPM#3_R
0_0402_5%
0_0402_5%
@
@
R73
R73
XDP_BPM#3
BPM#[2]
2
0_0402_5%
0_0402_5%
2
@
@
1 1 R66
R66
AR33
AT30
RESET#
XDP_BPM#4_R
XDP_BPM#4
BPM#[3]
AP32
XDP_BPM#5_R
XDP_BPM#5
RESET#: ok CPU reset
BPM#[4]
0_0402_5%
0_0402_5%
0_0402_5%
AR31
0_0402_5%
2
2
@
@
@
@
1
R51
R51
R62
R62
XDP_BPM#6_R
1 XDP_BPM#6
BPM#[5]
AT31
XDP_BPM#7_R
0_0402_5%
0_0402_5%
2
@ @
R52
R52
XDP_BPM#7
BPM#[6]
0_0402_5%
0_0402_5%
2
@ @
1 1 R53
R53
AR32
BPM#[7]
+3VALW
ESD request
2010/07/27
+1.5V_CPU_VDDQ
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
1
C307 C307
0.1U_0402_16V4Z 0.1U_0402_16V4Z
R205 R205
2
200_0402_5% 200_0402_5%
U11 U11
A
A
74AHC1G09GW_TSSOP5 74AHC1G09GW_TSSOP5
15 SYS_PWROK
PM_SYS_PWRGD_BUF
PM_DRAM_PWRGD_R
1
1
2
B
15 PM_DRAM_PWRGD
4
R204
R204
0_0402_1%
0_0402_1%
O
2
A
R203 R203
39_0402_1% 39_0402_1%
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
@
@
2010/08/11
2010/08/11
2010/08/11
2011/08/11
2011/08/11
2011/08/11
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
www.vinafix.vn
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
P5WE0 M/B LA-6901P Schematic
0.1
P5WE0 M/B LA-6901P Schematic
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
P5WE0 M/B LA-6901P Schematic
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 27, 2010
Friday, August 27, 2010
Friday, August 27, 2010
Sheet
Sheet
Sheet
5
5
of
of
of
59
59
5
4
5
59
3
2
1
3
5
G
P
2
5
3
5
G
P
12
12
12
12
MISCTHERMALPWR
MISCTHERMALPWR
MANAGEMENT
MANAGEMENT
JTAG & BPM
JTAG & BPM
DDR3
DDR3
CLOCKS
CLOCKS
MISC
MISC
5 4 3 2 1 JCPU1C JCPU1C JCPU1D JCPU1D AB6 AE2 11 DDR_A_D[0 63] SA_CLK[0]
5
4
3
2
1
JCPU1C
JCPU1C
JCPU1D
JCPU1D
AB6
AE2
11 DDR_A_D[0 63]
SA_CLK[0]
11
12 DDR_B_D[0 63]
SB_CLK[0]
AA6
SA_CLK_DDR0
12
AD2
11
SB_CLK#[0]
DDR_A_D0
SA_CLK#[0]
SB_CLK_DDR0
SB_CLK_DDR#0
12
DDR_B_D0
C5
V9
SA_CLK_DDR#0
C9
R9
DDRA_CKE0_DIMMA
11
SB_DQ[0]
SB_CKE[0]
DDRB_CKE0_DIMMB
12
DDR_A_D1
SA_DQ[0]
SA_CKE[0]
DDR_B_D1
D5
A7
SB_DQ[1]
DDR_A_D2
SA_DQ[1]
DDR_B_D2
D3
D10
DDR_A_D3
SA_DQ[2]
SB_DQ[2]
DDR_B_D3
D2
C8
DDR_A_D4
SA_DQ[3]
SB_DQ[3]
DDR_B_D4
D6
AA5
A9
AE1
11
D
DDR_A_D5
SA_DQ[4]
SA_CLK[1]
SA_CLK_DDR1
SB_DQ[4]
SB_CLK[1]
12
D
DDR_B_D5
C6
AB5
A8
AD1
SA_CLK_DDR#1
11
SB_CLK_DDR#1
DDR_A_D6
SB_DQ[5]
SB_CLK#[1]
12
SA_DQ[5]
SA_CLK#[1]
DDR_B_D6
SB_CLK_DDR1
C2
V10
D9
R10
DDRA_CKE1_DIMMA
11
DDRB_CKE1_DIMMB
12
DDR_A_D7
SA_DQ[6]
SA_CKE[1]
SB_DQ[6]
SB_CKE[1]
DDR_B_D7
C3
D8
DDR_A_D8
SA_DQ[7]
SB_DQ[7]
DDR_B_D8
F10
G4
DDR_A_D9
SA_DQ[8]
SB_DQ[8]
DDR_B_D9
F8
F4
DDR_A_D10
SA_DQ[9]
SB_DQ[9]
DDR_B_D10
G10
F1
AB4
AB2
DDR_A_D11
SA_DQ[10]
SA_CLK[2]
DDR_B_D11
SB_DQ[10]
SB_CLK[2]
G9
G1
AA4
AA2
DDR_A_D12
SA_DQ[11]
SB_DQ[11]
SA_CLK#[2]
DDR_B_D12
SB_CLK#[2]
F9
G5
W9
T9
DDR_A_D13
SA_DQ[12]
DDR_B_D13
SB_DQ[12]
SA_CKE[2]
SB_CKE[2]
F7
F5
DDR_A_D14
SA_DQ[13]
DDR_B_D14
SB_DQ[13]
G8
F2
DDR_A_D15
SA_DQ[14]
DDR_B_D15
SB_DQ[14]
G7
G2
DDR_A_D16
SA_DQ[15]
DDR_B_D16
SB_DQ[15]
K4
J7
AB3
AA1
DDR_A_D17
SA_DQ[16]
DDR_B_D17
SB_DQ[16]
SB_CLK[3]
SA_CLK[3]
J8
K5
AB1
AA3
DDR_A_D18
SA_DQ[17]
SA_CLK#[3]
DDR_B_D18
SB_DQ[17]
SB_CLK#[3]
K10
K1
T10
W10
DDR_A_D19
SA_DQ[18]
SA_CKE[3]
DDR_B_D19
SB_DQ[18]
SB_CKE[3]
K9
J1
DDR_A_D20
SA_DQ[19]
DDR_B_D20
SB_DQ[19]
J9
J5
DDR_A_D21
DDR_B_D21
SB_DQ[20]
SA_DQ[20]
J10
J4
DDR_A_D22
DDR_B_D22
SB_DQ[21]
SA_DQ[21]
K8
J2
AK3
DDRA_CS0_DIMMA#
11
AD3
DDRB_CS0_DIMMB#
12
DDR_A_D23
DDR_B_D23
SB_DQ[22]
SA_DQ[22]
SA_CS#[0]
SB_CS#[0]
K7
DDR_A_D24
K2
AL3
DDRA_CS1_DIMMA#
11
AE3
DDRB_CS1_DIMMB#
12
SA_CS#[1]
DDR_B_D24
SB_DQ[23]
SA_DQ[23]
SB_CS#[1]
M5
AD6
DDR_A_D25
M8
AG1
DDR_B_D25
SB_DQ[24]
SA_DQ[24]
SB_CS#[2]
SA_CS#[2]
N4
DDR_A_D26
N10
AE6
AH1
DDR_B_D26
SB_DQ[25]
SA_DQ[25]
SB_CS#[3]
SA_CS#[3]
N2
DDR_A_D27
N8
DDR_B_D27
SB_DQ[26]
SA_DQ[26]
N1
DDR_A_D28
N7
DDR_B_D28
SB_DQ[27]
SA_DQ[27]
M4
DDR_A_D29
M10
DDR_B_D29
SB_DQ[28]
SA_DQ[28]
N5
AE4
DDR_A_D30
M9
AH3
SA_ODT0 11
SB_ODT[0]
SB_ODT0 12
SA_DQ[29]
SA_ODT[0]
DDR_B_D30
SB_DQ[29]
AG3
SA_ODT1 11
M2
AD4
DDR_A_D31
N9
SB_ODT1 12
SA_ODT[1]
DDR_B_D31
SB_DQ[30]
SB_ODT[1]
SA_DQ[30]
M1
AD5
DDR_A_D32
M7
AG2
DDR_B_D32
SB_DQ[31]
SB_ODT[2]
SA_DQ[31]
SA_ODT[2]
AM5
DDR_A_D33
AE5
AG6
AH2
DDR_B_D33
SB_DQ[32]
SB_ODT[3]
SA_DQ[32]
SA_ODT[3]
AM6
DDR_A_D34
AG5
DDR_B_D34
SB_DQ[33]
SA_DQ[33]
AR3
DDR_A_D35
AK6
DDR_B_D35
SB_DQ[34]
SA_DQ[34]
DDR_A_D36
AP3
AK5
DDR_B_D36
SB_DQ[35]
SA_DQ[35]
C
AN3
C
DDR_A_D37
AH5
DDR_A_DQS#0
DDR_A_DQS#[0
7]
11
7]
12
DDR_B_D37
SB_DQ[36]
DDR_B_DQS#0
SA_DQ[36]
D7
DDR_A_D38
AN2
AH6
C4
DDR_A_DQS#1
SA_DQS#[0]
DDR_B_D38
SB_DQ[37]
SB_DQS#[0]
DDR_B_DQS#1
SA_DQ[37]
DDR_A_D39
AN1
F3
AJ5
G6
DDR_A_DQS#2
DDR_B_D39
SA_DQS#[1]
SB_DQ[38]
SB_DQS#[1]
DDR_B_DQS#2
SA_DQ[38]
AP2
K6
DDR_A_D40
AJ6
J3
DDR_A_DQS#3
DDR_B_D40
SB_DQ[39]
SB_DQS#[2]
DDR_B_DQS#3
SA_DQ[39]
SA_DQS#[2]
DDR_A_D41
AP5
N3
AJ8
M6
DDR_A_DQS#4
DDR_B_D41
SB_DQ[40]
SB_DQS#[3]
DDR_B_DQS#4
SA_DQ[40]
SA_DQS#[3]
AN9
AN5
DDR_A_D42
AK8
AL6
DDR_A_DQS#5
DDR_B_D42
SB_DQ[41]
SB_DQS#[4]
DDR_B_DQS#5
SA_DQ[41]
SA_DQS#[4]
AP9
DDR_A_D43
AT5
AJ9
AM8
DDR_A_DQS#6
DDR_B_D43
SB_DQ[42]
SB_DQS#[5]
DDR_B_DQS#6
SA_DQ[42]
SA_DQS#[5]
AT6
AK12
DDR_A_D44
AK9
AR12
DDR_A_DQS#7
DDR_B_D44
SB_DQ[43]
SB_DQS#[6]
DDR_B_DQS#7
SA_DQ[43]
SA_DQS#[6]
AP15
DDR_A_D45
AP6
DDR_B_DQS#[0
AH8
AM15
DDR_B_D45
SB_DQ[44]
SB_DQS#[7]
SA_DQ[44]
SA_DQS#[7]
DDR_A_D46
AN8
AH9
DDR_B_D46
SB_DQ[45]
DDR_A_D47
SA_DQ[45]
AR6
AL9
DDR_B_D47
SB_DQ[46]
SA_DQ[46]
DDR_A_D48
AR5
AL8
DDR_B_D48
SB_DQ[47]
SA_DQ[47]
DDR_A_D49
DDR_A_DQS0
DDR_A_DQS[0
7]
11
AR9
7]
12
AP11
DDR_B_D49
SB_DQ[48]
DDR_B_DQS0
SA_DQ[48]
C7
DDR_A_D50
D4
DDR_A_DQS1
AJ11
AN11
DDR_B_D50
SB_DQS[0]
SB_DQ[49]
DDR_B_DQS1
SA_DQS[0]
DDR_A_D51
SA_DQ[49]
G3
AT8
F6
DDR_A_DQS2
AL12
DDR_B_D51
SB_DQS[1]
SB_DQ[50]
DDR_B_DQS2
SA_DQS[1]
DDR_A_D52
SA_DQ[50]
J6
K3
DDR_A_DQS3
AT9
AM12
DDR_B_D52
SB_DQS[2]
SB_DQ[51]
DDR_B_DQS3
SA_DQS[2]
DDR_A_D53
SA_DQ[51]
M3
N6
DDR_A_DQS4
DDR_B_D53
AH11
AM11
SB_DQS[3]
SB_DQ[52]
DDR_B_DQS4
SA_DQS[3]
DDR_A_D54
SA_DQ[52]
AN6
AR8
AL5
DDR_A_DQS5
SB_DQS[4]
AL11
DDR_B_D54
SB_DQ[53]
DDR_B_DQS5
SA_DQS[4]
DDR_A_D55
SA_DQ[53]
AP8
DDR_A_DQS6
AJ12
AM9
DDR_B_D55
SB_DQS[5]
AP12
SB_DQ[54]
DDR_B_DQS6
DDR_A_D56
SA_DQS[5]
SA_DQ[54]
AK11
DDR_A_DQS7
AH12
AR11
DDR_B_D56
SB_DQS[6]
AN12
DDR_B_DQS7
SB_DQ[55]
DDR_A_D57
SA_DQS[6]
SA_DQ[55]
AP14
DDR_B_DQS[0
AM14
DDR_B_D57
AT11
SB_DQS[7]
AJ14
SB_DQ[56]
DDR_A_D58
SA_DQS[7]
SA_DQ[56]
AN14
DDR_B_D58
AH14
SB_DQ[57]
DDR_A_D59
SA_DQ[57]
DDR_B_D59
AR14
AL15
SB_DQ[58]
DDR_A_D60
SA_DQ[58]
DDR_B_D60
AT14
AK15
SB_DQ[59]
DDR_A_D61
SA_DQ[59]
DDR_A_MA0
DDR_A_MA[0
15]
11
DDR_B_D61
AT12
DDR_B_MA[0
15]
12
DDR_B_MA0
AL14
SB_DQ[60]
DDR_A_D62
SA_DQ[60]
AA8
DDR_A_MA1
AD10
DDR_B_D62
AN15
SB_MA[0]
AK14
SB_DQ[61]
DDR_B_MA1
DDR_A_D63
SA_MA[0]
SA_DQ[61]
T7
DDR_A_MA2
DDR_B_D63
AR15
W1
SB_MA[1]
DDR_B_MA2
AJ15
SB_DQ[62]
SA_MA[1]
SA_DQ[62]
R7
DDR_A_MA3
AT15
W2
SB_MA[2]
DDR_B_MA3
AH15
SB_DQ[63]
SA_MA[2]
SA_DQ[63]
DDR_A_MA4
T6
W7
SB_MA[3]
DDR_B_MA4
SA_MA[3]
DDR_A_MA5
T2
V3
SB_MA[4]
DDR_B_MA5
SA_MA[4]
DDR_A_MA6
T4
V2
SB_MA[5]
DDR_B_MA6
SA_MA[5]
DDR_A_MA7
T3
W3
SB_MA[6]
DDR_B_MA7
B
B
11
DDR_A_BS0
SA_MA[6]
AA9
DDR_A_MA8
12 DDR_B_BS0
R2
AE10
SB_BS[0]
W6
SB_MA[7]
DDR_B_MA8
SA_BS[0]
11
DDR_A_BS1
SA_MA[7]
AA7
DDR_A_MA9
12
DDR_B_BS1
T5
AF10
SB_BS[1]
V1
SB_MA[8]
DDR_B_MA9
SA_BS[1]
11
DDR_A_BS2
SA_MA[8]
R6
DDR_A_MA10
12
DDR_B_BS2
R3
V6
SB_BS[2]
W5
SB_MA[9]
DDR_B_MA10
SA_BS[2]
SA_MA[9]
DDR_A_MA11
AB7
AD8
SB_MA[10]
DDR_B_MA11
SA_MA[10]
DDR_A_MA12
R1
V4
SB_MA[11]
DDR_B_MA12
SA_MA[11]
DDR_A_MA13
T1
W4
SB_MA[12]
DDR_B_MA13
11
DDR_A_CAS#
SA_MA[12]
AA10
DDR_A_MA14
12
DDR_B_CAS#
AB10
AE8
SB_CAS#
AF8
SB_MA[13]
DDR_B_MA14
11
DDR_A_RAS#
SA_CAS#
SA_MA[13]
DDR_A_MA15
AB8
12
DDR_B_RAS#
R5
AD9
SB_RAS#
DDR_B_MA15
V5
SB_MA[14]
11
DDR_A_WE#
SA_RAS#
SA_MA[14]
AB9
12 DDR_B_WE#
R4
AF9
SB_WE#
V7
SB_MA[15]
SA_WE#
SA_MA[15]
D
D
G G
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
S
S
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
CONN@ CONN@
+1.5V
Follow CRB1.0
@ R184
@ R184
0_0402_5%
0_0402_5%
R217
R217
CPU DIMM reset
1
2
1K_0402_5%
1K_0402_5%
R155 R155
SM_DRAMRST#
DIMM_DRAMRST#_R
1K_0402_5%
1K_0402_5%
5 SM_DRAMRST#
DIMM_DRAMRST# 11,12
3
1
1
2
Q12
Q12
BSS138_NL_SOT23-3 BSS138_NL_SOT23-3
S0
R186 R186
RST_GATE hgih ,MOS ON
A
4.99K_0402_1% 4.99K_0402_1%
A
<BOM <BOM Structure> Structure>
SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH
Dimm not reset
S3
11,12,14
RST_GATE
RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# HIGH
Dimm not reset
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
1
S4,5
RST_GATE Low ,MOS OFF
2010/08/11
2010/08/11
2010/08/11
2011/08/11
2011/08/11
2011/08/11
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
C293 C293
SM_DRAMRST# lo,DIMM_DRAMRST# low
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
0.047U_0402_16V7K 0.047U_0402_16V7K
2
Dimm reset
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
P5WE0 M/B LA-6901P Schematic
0.1
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
P5WE0 M/B LA-6901P Schematic
0.1
P5WE0 M/B LA-6901P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 27, 2010
Friday, August 27, 2010
Friday, August 27, 2010
Sheet
Sheet
Sheet
6
6
6
of
of
of
59
59
59
5
4
3
2
1
1
2
2
12
DDR DDR SYSTEM SYSTEM MEMORY MEMORY A A
DDR DDR SYSTEM SYSTEM MEMORY MEMORY B B

www.vinafix.vn

5 4 3 2 1 CFG Straps for Processor CFG2 R112 R112 1K_0402_1% 1K_0402_1% D
5
4
3
2
1
CFG Straps for Processor
CFG2
R112
R112
1K_0402_1%
1K_0402_1%
D
D
JCPU1E
JCPU1E
PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches
L7
RSVD28
CFG2
AG7
socket pin map definition
RSVD29
CFG0
AK28
5
CFG0
AE7
CFG[0]
RSVD30
AK29
AK2
CFG[1]
RSVD31
CFG2
0:Lane Reversed
AL26
W8
CFG[2]
RSVD32
*
AL27
CFG[3]
CFG4
AK26
CFG[4]
CFG5
CFG4
AL29
AT26
CFG[5]
CFG6
RSVD33
AL30
AM33
CFG[6]
RSVD34
CFG7
@
@
AM31
AJ27
CFG[7]
RSVD35
AM32
CFG[8]
R109 R109
AM30
CFG[9]
AM28
1K_0402_1% 1K_0402_1%
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
T8
CFG[13]
RSVD37
AN26
J16
CFG[14]
RSVD38
AM27
H16
CFG[15]
RSVD39
AK31
G16
CFG[16]
RSVD40
AN29
CFG[17]
Display Port Presence Strap
C
C
AJ31 change to VAXG_VAL_SENSE
AH31 change to VSSAXG_VAL_SENSE
AJ33 change to VCC_VAL_SENSE
AH33 change to VSS_VAL_SENSE
1
: Disabled; No Physical Display Port
AR35
RSVD41
*
T4T4
PADPAD @@
CFG4
AJ31
AT34
attached to Embedded Display Port
RSVD1
RSVD42
T2T2
PADPAD @@
AH31
AT33
RSVD2
RSVD43
T3T3
PADPAD @@
AJ33
AP35
RSVD3
RSVD44
T5T5
PADPAD @@
0
: Enabled; An external Display Port device is
AH33
AR34
RSVD4
RSVD45
connected to the Embedded Display Port
AJ26
RSVD6 and RSVD7 had changed to
SA_DIMM_VREFDQ and SB_DIMMVREFDQ
RSVD5
CFG6
B34
SA_DIMM_VREFDQ
RSVD46
11 SA_DIMM_VREFDQ
B4
A33
SB_DIMM_VREFDQ
RSVD6
RSVD47
CFG5
12 SB_DIMM_VREFDQ
D1
A34
RSVD7
RSVD48
B35
RSVD49
SA_DIMM_VREFDQ
C35
RSVD50
R107
R107
R108
R108
SB_DIMM_VREFDQ
For Future CPU M3 support,
Sandey bridge not supportM3,
Check list1.0&CRB say can NC
1K_0402_1% @
1K_0402_1% @
@
@
1K_0402_1%
1K_0402_1%
F25
R154 R154
R164
R164
RSVD8
F24
1K_0402_1% 1K_0402_1%
1K_0402_1%
1K_0402_1%
RSVD9
F23
RSVD10
D24
AJ32
RSVD11
RSVD51