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IRF630, RF1S630SM

Data Sheet June 1999 File Number 1578.2

9A, 200V, 0.400 Ohm, N-Channel Power Features


MOSFETs • 9A, 200V
These are N-Channel enhancement mode silicon gate
• rDS(ON) = 0.400Ω
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a • Single Pulse Avalanche Energy Rated
specified level of energy in the breakdown avalanche mode • SOA is Power Dissipation Limited
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching • Nanosecond Switching Speeds
convertors, motor drivers, relay drivers, and drivers for high • Linear Transfer Characteristics
power bipolar switching transistors requiring high speed and
• High Input Impedance
low gate drive power. These types can be operated directly
from integrated circuits. • Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Formerly developmental type TA17412.
Components to PC Boards”
Ordering Information Symbol
PART NUMBER PACKAGE BRAND D

IRF630 TO-220AB IRF630

RF1S630SM TO-263AB RF1S630 G

NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in the tape and reel, i.e., RF1S630SM9A. S

Packaging
JEDEC TO-220AB JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN (FLANGE) GATE
SOURCE

4-202 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
IRF630, RF1S630SM

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified


IRF630, RF1S630SM UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 200 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 200 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID 9 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID 6 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 36 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 75 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 150 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 260 oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to 125oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified


PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 200 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2 - 4 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 9 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 5A, VGS = 10V (Figure 8, 9) - 0.25 0.4 Ω
Forward Transconductance (Note 2) gfs VDS > ID(ON) x rDS(ON)MAX, ID = 5A (Figure 12) 3 4.8 - S
Turn-On Delay Time td(ON) VDD = 90V, ID ≈ 9A, RGS = 9.1Ω, VGS = 10V - - 30 ns
RL = 9.6Ω
Rise Time tr - - 50 ns
MOSFET Switching Times are Essentially
Turn-Off Delay Time td(OFF) Independent of Operating Temperature - - 50 ns
Fall Time tf - - 40 ns
Total Gate Charge Qg(TOT) VGS = 10V, ID = 9A, VDS = 0.8 x Rated BVDSS - 19 30 nC
(Gate to Source + Gate to Drain) Ig(REF) = 1.5mA (Figure 14)
Gate Charge is Essentially Independent of
Gate to Source Charge Qgs - 10 - nC
Operating Temperature
Gate to Drain “Miller” Charge Qgd - 9 - nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 600 - pF
Output Capacitance COSS - 250 - pF
Reverse Transfer Capacitance CRSS - 80 - pF
Internal Drain Inductance LD Measured From the Modified MOSFET - 3.5 - nH
Contact Screw on Tab to Symbol Showing the
Center of Die Internal Devices
Inductances
Measured From the Drain - 4.5 - nH
D
Lead, 6mm (0.25in) From
Package to Center of Die LD
Internal Source Inductance LS Measured From the - 7.5 - nH
Source Lead, 6mm G
(0.25in) From Header to LS
Source Bonding Pad
S

Thermal Resistance Junction to Case RθJC - - 1.67 oC/W

Thermal Resistance Junction to Ambient RθJA Free Air Operation - - 80 oC/W

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IRF630, RF1S630SM

Source to Drain Diode Specifications


PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET - - 9 A
D
Symbol Showing the
Pulse Source to Drain Current ISDM - - 36 A
Integral Reverse
(Note 3)
P-N Junction Diode
G

S
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 9A, VGS = 0V (Figure 13) - - 2 V
Reverse Recovery Time trr TJ = 150oC, ISD = 9A, dISD/dt = 100A/µs - 450 - ns
Reverse Recovery Charge QRR TJ = 150oC, ISD = 9A, dISD/dt = 100A/µs - 3 - µC
NOTES:
2. Pulse Test: Pulse width ≤ 300µs, Duty Cycle ≤ 2%.
3. Repetitive rating: Pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 20V, starting TJ = 25oC, L = 3.37mH, RG = 50Ω, peak IAS = 9A.

Typical Performance Curves Unless Otherwise Specified

1.2 10
POWER DISSIPATION MULTIPLIER

1.0
8
ID, DRAIN CURRENT (A)

0.8
6

0.6
4
0.4

2
0.2

0 0
0 50 100 150 25 50 75 100 125 150
TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

1.0
ZθJC, NORMALIZED TRANSIENT
THERMAL IMPEDANCE

0.5

0.2
0.1 PDM
0.1 0.05
0.02
0.01 t1
SINGLE PULSE t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 1 10
t1, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE

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IRF630, RF1S630SM

Typical Performance Curves Unless Otherwise Specified (Continued)

100
20
VGS = 10V PULSE DURATION = 80µs
VGS = 8V DUTY CYCLE = 0.5% MAX
16
ID, DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)


VGS = 7V
10 10µs
100µs
12
VGS = 6V
1ms

OPERATION IN THIS 8
1 AREA MAY BE 10ms
LIMITED BY rDS(ON) 100ms VGS = 5V
DC 4
TJ = MAX RATED
VGS = 4V
TC = 25oC
0.1 0
1 10 100 1000 0 20 40 60 80 100
VDS, DRAIN TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

10 10
PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX VGS = 10V DUTY CYCLE = 0.5% MAX
VDS > ID(ON) x rDS(ON)MAX
8 VGS = 9V ID, DRAIN CURRENT (A) 8
ID, DRAIN CURRENT (A)

VGS = 8V
VGS = 7V
6 VGS = 6V 6

125oC
VGS = 5V
4 4 25oC
-55oC

2 2
VGS = 4V

0 0
0 1 2 3 4 5 0 1 2 3 4 5 6 7
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

0.8 2.2
2µs PULSE TEST PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE

VGS = 10V VGS = 10V, ID = 5A


rDS(ON), DRAIN TO SOURCE

1.8
0.6
ON RESISTANCE

ON RESISTANCE

1.4
0.4

1
VGS = 20V
0.2
0.6

0 0.2
0 10 20 30 40 -40 0 40 80 120
ID, DRAIN CURRENT (A) TJ , JUNCTION TEMPERATURE (oC)

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 9. NORMALIZED DRAIN TO SOURCE ON


VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE

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IRF630, RF1S630SM

Typical Performance Curves Unless Otherwise Specified (Continued)

1.25 2000
VGS = 0V, f = 1MHz
ID = 250µA
NORMALIZED DRAIN TO SOURCE

CISS = CGS + CGD, CDS


1.15 1600 CRSS = CGD
BREAKDOWN VOLTAGE

COSS = CDS + CGD

C, CAPACITANCE (pF)
1.05 1200

0.95 800
CISS

0.85 400
COSS
CRSS
0.75 0
-40 0 40 80 120 160 1 10 20 30 40 50
TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE

10 PULSE DURATION = 80µs


PULSE DURATION = 80µs
ISD, SOURCE TO DRAIN CURRENT (A)
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX 100
gfs, TRANSCONDUCTANCE (S)

6 55oC
25oC 150oC
10
4 25oC
125oC

0
1
0 2 4 6 8 10 0 1 2 3 4
ID , DRAIN CURRENT (A) VSD, SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

20
ID = 9A
VGS, GATE TO SOURCE VOLTAGE (V)

VDS = 40V
15 V20
DS = 100V

10 VDS = 160V
IRF630, IRF632

0
0 8 16 24 32 40
Qg, GATE CHARGE (nC)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

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IRF630, RF1S630SM

Test Circuits and Waveforms

VDS
BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS


+ VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0
0.01Ω
tAV

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

tON tOFF

td(ON) td(OFF)

tr tf
RL VDS
90% 90%

+
VDD 10% 10%
RG
- 0

DUT 90%

VGS 50% 50%


PULSE WIDTH
VGS 10%
0

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

VDS
CURRENT (ISOLATED
REGULATOR SUPPLY)
VDD

SAME TYPE Qg(TOT)


AS DUT VGS
12V
0.2µF 50kΩ Qgd
BATTERY
0.3µF
Qgs

D
VDS

G DUT
0

Ig(REF) S
0
VDS IG(REF)
IG CURRENT ID CURRENT
SAMPLING SAMPLING
RESISTOR RESISTOR 0

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

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IRF630, RF1S630SM

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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