Fabrication, Layout, and Simulation

CHAPTER 3
Kyeong-Sik Min, Kookmin Univ.
Overview of chip
chip-making
making process
Photolithography
 A process which transforms designer’s pattern on
silicon wafer.
 Incredibly, small and narrow things are able to be
transformed onto silicon wafer.
 Photolithography is a key process in silicon
processing and the most expensive equipments are
used in this process.
Cont.
 Coating a photo-resistive material on top of wafer
by spinning wafer
Cont.
 Place a glass mask over wafer
 Expose
p photo-resist
p to UV
 Exposed area can be soluble to a specific chemical.
Cont.
 Photo-resist can be a barrier to subsequent etching,
implanting, etc.
Cont.
 Final step in photolithography is removing the
photo-resist.
Cont.
 To gain more resolution in photolithography, optical
proximity correction is needed in most modern
silicon processes under 0.18um node.

As design

Characterization of
process nonlinearities
Cont.

OPC correction

Performance after correction

Making transistors
 Define well and active
Cont.
 Gate oxide growing
Cont.
 Define gate
Cont.
 Making source and drain by self-align
Cont.
 Deposit silicide material
Making wires
 CVD oxide deposition and chemical and mechanical
polishing
Cont.
 Define contact
Cont.
 Define metal
Cont.
 Low-k Inter-metal dielectric deposited
Deep sub
sub-micron
micron CMOS structure
Key steps in making transistors
 Self-align
 Salicide,, p
polyside
y
 Oxide spacer
 Thi oxide
Thin id growingi
 Shallow trench isolation
 Source/drain extension
Multi-layer
Multi layer metals
Geometry of wire R and C
Cross-sectional view of multi-layer
metals
 Lateral coupling and vertical coupling considered
 Coupling
p g capacitance
p extraction is a veryy
complicated job.
Wire scaling
 As devices are scaled down, the wire dimensions
are also needed to be shrunk.
How do we pass our layout DB?
 GDSII is a standard
Design rules: resolution & alignment
Transistor layout
 To layout small transistor, we need extra area, as
shown in (b).
 We need bulk contact as shown in (a).
MOS models in SPICE
Cont.
 Mxxx D G S B mname L=value W=value AD=value
PD=value AS=value PS=value
 Mxxx: instance name of MOSFET
 D: drain node
 G: gate node
 S: source node
 B: bulk node
 Mname: model name
Cont.
 L: channel length
 W: channel width
 AD: area of drain diffusion bottom
 PD perimeter
PD: i t off d drain
i area
 AS: area of source diffusion bottom
 PS: perimeter of source area
 Leff L L
Leff=L-L
 Weff=W- W
SPICE MOS level
level=1
1

kT  NSUB 
PHI  2 ln 
q  ni 
 ox
Cox 
Tox
2 si qNSUB
NSUB
GAMMA 
Cox

VT  VT 0  GAMMA PHI  VBS  PHI 
Cont.
 Linear region

KP  U 0  Cox

I DS 
Weff KP
Leff 2
 
2(VGS  VT )VDS  VDS (1  LAMBDA  VDS )
2

VGS  VT VDS  VGS  VT

Cont.
 Saturation region

I DS 
Weff KP
Leff 2
 
(VGS  VT ) 2 (1  LAMBDA  VDS )

VGS  VT VDS  VGS  VT

MOS parameter extraction
BSIM3 model
 Berkeley Short-channel IGFET Model
 There are over 300 pparameters in the complete
p
BSIM3 model.
 BSIM3 is targeting Very Deep Sub-Micron devices.
devices
Cont.
 Model binning process in BSIM3
Cont.
 Short-channel threshold voltage
VT  VTH 0   ( PHI  VBS  PHI )
kT  NCH 
PHI  2 ln 
q  ni 
2 si q  NCH 2 si q  NSUB
1  , 2 
Cox Cox
 ox
Cox 
TOX
K1  f ( 2 , PHI ), K 2  f ( 1 ,  2 , PHI )

VT  VTH 0  K1 PHI  VBS  PHI  K 2  VBS 
Reverse short channel effect
 Impurities gather at point defects at the tow gate
edges during oxidation, the surface doping levels in
the channel region at the short channel devices may
be higher than the long channel.
 Drain-induced
Drain induced barrier lowering

VT  VTH 0  K1( PHI  VBS  PHI )

 K 2  VBS  VDS
Mobility model

U0

 VGS  VT  VGS  VT 
2

1  UA   UB   UC  VBS
 tox   tox 
Additional problems in MOS
 Source/drain resistance
 Parameter variations
 Temperature effects
Latch up
Latch-up
Silicon on insulator (SOI)
 SOI is faster, dissipates less power, and not
susceptible to latch-up.
 Bulk is floating, kink can occur.