Compal La-B751p, La-B753p Echo 15 17 With Nvidia GFX Rev 0.1 (x00)

A B C D E
MODEL NAME : Echo 15 17 nVidia

1
PCB NO : LA-B751P/LA-B753P 1
BOM P/N : 4319UA31L01 / 4319UA31L02 for NV

4319UB31L01 for AMD
Compal Confidential
2
Echo 15 17 with nVidia GFX 2
Schematic Document
Broadwell H-type
Rev: 0.1(X00)
3
2014/01/02 3
@ : Nopop Component DIS@ : Discrete Part

EMC@ : EMI part NV@ AMD@ : Board ID
ESD@ : ESD part
RF@ : RF part
CONN@ : Connector Component ZZZ1 PCB
4 BDW@ : Intel BOARDWELL DAB0000P000

PCB 18F LA-B752P REV0 M/B 8
4
12L
AOAC@ : Intel AOAC
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/2/11 Deciphered Date 2014/2/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B751P
Date: Wednesday, March 26, 2014 Sheet 1 of 69
A B C D E
A B C D E
Echo 15"/17'' Block Diagram

eDP panel eDP 1.3
Page25
1
FFS Fan Control XDP connector
1
Page27
HDMI HDMI 1.4a (DDI1) LNG3DMTR ADM1032
connector
mini DP DP 1.2 (DDI2) Broadwell M-Processor Memory Bus Dual Channel

1.35V DDR3L 1600 MHz
connector
Page26
4C + GT2 204pin SO-DIMM x2
Page14~15
50W,75W dGPU
PCI-E(GEN3)x8 47W , BGA1364 balls
port0~port7
nVIDIA / AMD
4pcs GDDR5 128bit
6pcs GDDR5 192bit
8pcs GDDR5 256bit
Page7~13
Page46~55
DMI x 4
PCI-E(GEN3)x4
2 2
port8~port11 SATA3.0 port0
HDD connector Page36
Caldera USB3.0 port5 USB2.0 port3

connector AlienFX / ELC , C8051F347 Page37
USB2.0 port2
Page41
USB2.0 port5
Touch screen Page25
RJ45 Page30 LAN(Gigabit) PCI-E2.0 port3 USB2.0 port6

Digital camera(with digital MIC)
connector Killer E2201
Page30
USB3.0 port1
USB2.0 port0 USB connector 1 , Right side
3 in 1 Page31 Card reader PCI-E2.0 port5 Page34
Card slot RTS5227Page31 USB3.0 port2

Wildcat Point-LP PCH USB2.0 port7 USB connector 2 , Right side Page34
NGFF (M.2) SATA3.0 port1

Gen3 USB3.0 port6
SSD 1 Page29 USB connector 3 , Left side
3 BGA 696 balls USB2.0 port1
USB power share Page35
3

Gen3 USB3.0 port3
SSD 2 Page29 USB2.0 port8 USB connector 4 , Lift side Page35

Gen3 HP/MIC Global headset
SSD 3 Page29
Page30 combo JACK Page32

Echo 17" only SSD 4 Page29 Gen2 only HD Audio
Audio codec
HP/MIC Retaskable
Creative
Sound Core3D-EX combo JACK Page32
PCI-E2.0 port4
NGFF (M.2)
WLAN+BT USB2.0 port4 Page32 TI TPA3111 Sub-woofer
Page16~24
DC in 1.05V dGPU SPI ROM SPI Echo 17" only
Battery Core 64Mbit Page19
TI TPA3131D2
LPC Bus Page32
Daughter Board
3V/5V 1.5V Charger USB2.0
4 4
Int. KBD
System CPU dGPU ENE KB9012 Speaker
Touch pad
1.35V Vcore 1.35V ENE KC3810 Page43
Page43
Block diagram
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
A B C D E
A B C D E
Compal Confidential
Project Code : AAP10/AAP20
File Name : LA-XXXXP
1 1
M/B
Camera
FFC LS-9335P FFC
? pin ? pin
POWER BUTTON/B
Touch Pad on/off SW
44 pin eDP Panel
Led x 2 Coaxial/Wire Combo
FFC Daughter/B USB3.0

? pin
Sub-woofer Amplifier USB3.0
2 LS-9336P 2
INDICATOR/B
Headphone combo JACK
Led-HDD
Led-Wireless 50pin Wire-Set Headphone combo JACK
Led-CapsLock Lid
KSI/KSO Backlight Wire

12pin
? pin
? pin
3 3
LOGO /B
Keyboard
Led x 2
Wire Wire Wire

6pin Hot Bar Hot Bar 6pin Hot Bar 6pin
Alien Slits-R Light/B Alien head badge/B Alien Slits-L Light/B
Led x 2 Led x 2 Led x 2
4 4

Block Diagram
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
A
Caldera(Echo graphic expander) block diagram

PCIE x4 TX/RX
PCIE x4 TX/RX
PCIE x4 Redriver PCIE Mux Pericom , PCIE x8 TX/RX
CALDERA PRSNT# TI , DS8OPCI402 PI3PCIE3415ZHEX
SMBUS
TO EC Control CALDERA PWRGD

REFCLK +/- Desktop PCIE x16 connector
Caidera connector CPERST#
CALDERA_ON
CALDERA PRSNT#
PEG PRSNT_LOOPBACK
USB3.0 USB3.0 HUB 4x USB3.0

USB2.0 SMSC , USX2064
4 ports USB3.0
1 1
CALDERA PWRGD
Dock +3.3VAW
19.5V IN
3.3V/5V always VR's(for USB wake support) Dock +5VAW
All POWER ready

Dock +3.3V
Dock +12V
DC-DC VR's(main)
VR_ON#
CALDERA_ON
BUTTON#
EC Control RED LED Removal Request
WHITE LED Button and WHTE/RED
on Connctor overmold CALDERA PRSNT#

Caldera block diagram
A
A
USB3.0
Board ID Table for AD channel
Vcc 3.3V +/- 1% Port1 Right side1
Ra 100K +/- 1%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Port2 Right side2
0 0 0.000V 0.000V 0.300V 0x00 - 0x0B
1 12K +/- 1% 0.347V 0.354V 0.360V 0x0C - 0x1C Port3 Left side 1
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1D - 0x26
3 20K +/- 1% 0.541V 0.550V 0.559V 0x27 - 0x30 Port4
4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3B NVIDIA
5 33K +/- 1% 0.807V 0.819V 0.831V 0x3C - 0x46 Graphic Port5 Caldera
6 43K +/- 1% 0.978V 0.992V 1.006V 0x47 - 0x54
7 56K +/- 1% 1.169V 1.185V 1.200V 0x55 - 0x64 Port6 Left side 2
8 75K +/- 1% 1.398V 1.414V 1.430V 0x65 - 0x76
9 100K +/- 1% 1.634V 1.650V 1.667V 0x77 - 0x87 USB2.0
10 130K +/- 1% 1.849V 1.865V 1.881V 0x88 - 0x96
11 160K +/- 1% 2.015V 2.031V 2.046V 0x97 - 0xA3 Port0 Right side1
12 200K +/- 1% 2.185V 2.200V 2.215V 0xA4 - 0xAD
13 240K +/- 1% 2.316V 2.329V 2.343V 0xAE - 0xB7 Port1 Left side 1 (PowerShare)
14 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xC0 AMD
15 330K +/- 1% 2.521V 2.533V 2.544V 0xC1 - 0xC9 Graphic Port2 Caldera
16 430K +/- 1% 2.667V 2.677V 2.687V 0xCA - 0xD3
17 560K +/- 1% 2.791V 2.800V 2.808V 0xD4 - 0xDC Port3 ELC
18 750K +/- 1% 2.905V 2.912V 2.919V 0xDD - 0xE6
19 NC 3.000V 3.300V 3.300V 0xE7 - 0xFF Port4 BT
Port5 Touch screen

BDW Port6 Camera
Board ID TABLE
ID PCB Revision Port7 / 8 Right side 2 Left side 2
1 1
NV AMD PCI EXPRESS

0 10 EVT-1
1 11 DVT-1 Lane 1
2 12 DVT-2
3 13 MP Lane 2
Lane 3 10/100/1000 LAN
Lane 4 M.2 Card WLAN
CLOCK SIGNAL Lane 5 PCIE 4x MUX
CLKOUT_PCIE0 Lane 6
CLKOUT_PCIE1 SATA
CLKOUT_PCIE2 10/100/1000 LAN SATA0 HDD
CLKOUT_PCIE3 M.2 Card WLAN SATA1 NGFF SSD
CLKOUT_PCIE4 dGPU (N15P) SATA2 NGFF SSD
CLKOUT_PCIE5 DGPU (Caldera) SATA3

Symbol Note :
: means Digital Ground

: means Analog Ground Security Classification
Issued Date 2014/2/11
Compal Secret Data
Deciphered Date 2014/2/11 Title
Compal Electronics, Inc.
Notes list
Size
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
5 4 3 2 1
2.2K 10K
D
SMBUS Address [0x9a] D
2.2K
+3.3V_ALW_PCH 10K
+3VS
N-MOS
AP2 MEM_SMBCLK DDR_XDP_WLAN_TP_SMBCLK 202 DIMMA SMBUS Address [A0]
N-MOS
AH1 MEM_SMBDATA DDR_XDP_WLAN_TP_SMBDAT 200
1K
202 DIMMB SMBUS Address [A4]
1K
+3.3V_ALW_PCH
200
Broadwell AN1 SML0CLK

0 ohm
AK1 SML0DATA DDR_XDP_SMBCLK_R1 53 XDP1 SMBUS Address [TBD]
2.2K
0 ohm
DDR_XDP_SMBDAT_R1 51
2.2K
+3.3V_ALW_PCH
30 M.2 NGFF SMBUS Address [TBD]
N-MOS 32
AN1 SML1_SMBCLK EC_SMB_CK2
N-MOS
C AK1 SML1_SMBDATA EC_SMB_DA2 C
5 JTP SMBUS Address [TBD]

6
2.2K
2.2K
+3VALW
0 ohm N-MOS 0 ohm UV28

79 EC_SMB_CK2 CSCL CIICSCL 13 LVDS SMBUS Address [TBD]
0 ohm N-MOS 0 ohm
80 EC_SMB_DA2 CSDA CIICSDA 14 Translator
2.2K
2.2K
+3VS_VGA
KBC N-MOS UV28

B
KB9012A4 N-MOS
VGA_SMB_CK2
VGA_SMB_DA2
T4
T3
GPU SMBUS Address [0xXX] B
2.2K
2.2K
+3VALW
0 ohm PU701
77 EC_SMB_CK1 SCL 11 POWER SMBUS Address [0x12]
0 ohm
78 EC_SMB_DA1 SDA 10 Charger
100 ohm
CPU,C 3 PD1 4 BAT_ALERT 3 PBATT1 SMBUS Address [0x16]
100 ohm
DDR,D 1 6 BATT_PRS 5
GPU,DP,HDMI,EDP,V
LAN,L
AUDIO,A
NGFF,N
USB,U
A
CALDERA,M A
HDD,S
ELC,E
FAN,F
TP,T
KBC,K
DC,O SMBus block diagram
Size
0.1
5 4 3 2 1
5 4 3 2 1
+VCOMP_OUT
PEG_GTX_HRX_P[0..7] <46>
PEG_COMP 2 1 PEG_GTX_HRX_N[0..7] <46>
24.9_0402_1% RC1
PEG_HTX_C_GRX_P[0..7] <46>
N5P-GX
D PEG_HTX_C_GRX_N[0..7] <46> D
Note:
Trace width=12 mils ,Spacing=15mils
Max length= 400 mils. PEG_GTX_HRX_P[8..11] <41>
PEG_GTX_HRX_N[8..11] <41>
Caldera
HASWELL_BGA PEG_HTX_C_GRX_N[8..11] <41>
CPU1A
AH6 PEG_COMP
PEG_RCOMP E10 PEG_GTX_HRX_N0
DMI_CRX_PTX_N0 AB2 PEG_RXN0 C10 PEG_GTX_HRX_N1
<17> DMI_CRX_PTX_N0 AB3 DMI_RXN0 PEG_RXN1 B10
DMI_CRX_PTX_N1 PEG_GTX_HRX_N2
<17> DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 AC3 DMI_RXN1 PEG_RXN2 E9 PEG_GTX_HRX_N3
<17> DMI_CRX_PTX_N2 AC1 DMI_RXN2 PEG_RXN3 D9
DMI_CRX_PTX_N3 PEG_GTX_HRX_N4
<17> DMI_CRX_PTX_N3 DMI_RXN3 PEG_RXN4 B9 PEG_GTX_HRX_N5
DMI_CRX_PTX_P0 AB1 PEG_RXN5 L5 PEG_GTX_HRX_N6
<17> DMI_CRX_PTX_P0 AB4 DMI_RXP0 PEG_RXN6 L2
DMI_CRX_PTX_P1 PEG_GTX_HRX_N7
<17> DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 AC4 DMI_RXP1 PEG_RXN7 M4 PEG_GTX_HRX_N8
<17> DMI_CRX_PTX_P2 DMI_RXP2 PEG_RXN8
DMI
DMI_CRX_PTX_P3 AC2 L4 PEG_GTX_HRX_N9
<17> DMI_CRX_PTX_P3 DMI_RXP3 PEG_RXN9 M2 PEG_GTX_HRX_N10
DMI_CTX_PRX_N0 AF2 PEG_RXN10 V5 PEG_GTX_HRX_N11
<17> DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 AF4 DMI_TXN0 PEG_RXN11 V4
<17> DMI_CTX_PRX_N1 DMI_TXN1 PEG_RXN12
PEG
DMI_CTX_PRX_N2 AG4 V1
<17> DMI_CTX_PRX_N2 AG2 DMI_TXN2 PEG_RXN13 Y3
DMI_CTX_PRX_N3
<17> DMI_CTX_PRX_N3 DMI_TXN3 PEG_RXN14 Y2
DMI_CTX_PRX_P0 AF1 PEG_RXN15 F10 PEG_GTX_HRX_P0
<17> DMI_CTX_PRX_P0 AF3 DMI_TXP0 PEG_RXP0 D10
DMI_CTX_PRX_P1 PEG_GTX_HRX_P1
<17> DMI_CTX_PRX_P1 AG3 DMI_TXP1 PEG_RXP1 A10
DMI_CTX_PRX_P2 PEG_GTX_HRX_P2
<17> DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 AG1 DMI_TXP2 PEG_RXP2 F9 PEG_GTX_HRX_P3
<17> DMI_CTX_PRX_P3 DMI_TXP3 PEG_RXP3 C9 PEG_GTX_HRX_P4
C PEG_RXP4 A9 PEG_GTX_HRX_P5 C
PEG_RXP5 M5 PEG_GTX_HRX_P6
PEG_RXP6 L1 PEG_GTX_HRX_P7
PEG_RXP7 M3 PEG_GTX_HRX_P8
FDI_CSYNC F11 PEG_RXP8 L3 PEG_GTX_HRX_P9
<17> FDI_CSYNC FDI_INT F12 FDI_CSYNC PEG_RXP9 M1 PEG_GTX_HRX_P10
<17> FDI_INT DISP_INT PEG_RXP10 Y5 PEG_GTX_HRX_P11
PEG_RXP11 V3
PEG_RXP12 V2
PEG_RXP13 Y4
PEG_RXP14 Y1
PEG_RXP15 B6 PEG_HTX_GRX_N0 CC1 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N0
PEG_TXN0 C5 PEG_HTX_GRX_N1 CC2 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N1
FDI PEG_TXN1 E6 PEG_HTX_GRX_N2 CC3 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N2
PEG_TXN2 D4 PEG_HTX_GRX_N3 CC4 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N3
PEG_TXN3 G4 PEG_HTX_GRX_N4 CC5 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N4
PEG_TXN4 E3 PEG_HTX_GRX_N5 CC6 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N5
PEG_TXN5 J5 PEG_HTX_GRX_N6 CC7 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N6
PEG_TXN6 G3 PEG_HTX_GRX_N7 CC8 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N7
PEG_TXN9 T6 PEG_HTX_GRX_N10 CC11 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N10
PEG_TXN10 R6 PEG_HTX_GRX_N11 CC12 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N11
PEG_TXN11 R2
PEG_TXN12 R4
PEG_TXN13 T4
PEG_TXN14 T1
PEG_TXN15 C6 PEG_HTX_GRX_P0 CC13 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P0
PEG_TXP0 B5 PEG_HTX_GRX_P1 CC14 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P1
PEG_TXP1 D6 PEG_HTX_GRX_P2 CC15 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P2
PEG_TXP2 E4 PEG_HTX_GRX_P3 CC16 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P3
PEG_TXP3 G5 PEG_HTX_GRX_P4 CC17 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P4
B PEG_TXP4 E2 PEG_HTX_GRX_P5 CC18 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P5 B
PEG_TXP5 J6 PEG_HTX_GRX_P6 CC19 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P6
PEG_TXP6 G2 PEG_HTX_GRX_P7 CC20 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P7
PEG_TXP9 T5 PEG_HTX_GRX_P10 CC23 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P10
PEG_TXP10 R5 PEG_HTX_GRX_P11 CC24 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P11
PEG_TXP11 R1
PEG_TXP12 R3
PEG_TXP13 T3
PEG_TXP14 T2
PEG_TXP15
Near MXM Connector x4 Gen3
1 OF 12
HASWELL_BGA1364
A A

PROCESSOR(1/7) DMI,FDI,PEG
5 4 3 2 1
5 4 3 2 1
+VCCIO_OUT
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 1
+VCCIO_OUT +VCCIO_OUT
CC25
CC26
XDP@
2 2 XDP@ JXDP1
1 2
XDP_PREQ#_R 3 GND0 GND1 4 CFG17
XDP_PRDY# 5 OBSFN_A0 OBSFN_C0 6 CFG16 CFG17 <11>
7 OBSFN_A1 OBSFN_C1 8 CFG16 <11>
CFG0 9 GND2 GND3 10 CFG8
Place near JXDP1 <11> CFG0
CFG1 11 OBSDATA_A0 OBSDATA_C0 12 CFG9
CFG8 <11>
D <11> CFG1 13 OBSDATA_A1 OBSDATA_C1 14 CFG9 <11> D
+3V_PCH <11> CFG2
1 2 CFG3_R 17 OBSDATA_A2 OBSDATA_C2 18 CFG11 CFG10 <11>
<11> CFG3 19 OBSDATA_A3 OBSDATA_C3 20 CFG11 <11>
RC2 XDP@ 1K_0402_1%~D
XDP_OBS0 21 GND6 GND7 22 CFG19
23 OBSFN_B0 OBSFN_D0 24 CFG19 <11>
XDP_OBS1 CFG18
1 2 SYS_PWROK_XDP 25 OBSFN_B1 OBSFN_D1 26 CFG18 <11>
RC3 @ 1K_0402_1%~D CFG4 27 GND8 GND9 28 CFG12
<11> CFG4 CFG5 29 OBSDATA_B0 OBSDATA_D0 30 CFG13 CFG12 <11>
<11> CFG5 31 OBSDATA_B1 OBSDATA_D1 32 CFG13 <11>
<11> CFG6 CFG7 35 OBSDATA_B2 OBSDATA_D2 36 CFG15 CFG14 <11>
<11> CFG7 37 OBSDATA_B3 OBSDATA_D3 38 CFG15 <11>
RC5 need to close to JCPU1 GND12 GND13
H_CPUPWRGD RC4 1 XDP@ 2 1K_0402_1%~D H_CPUPWRGD_XDP 39 40 CLK_XDP RH1 1 XDP@ 2 0_0402_5%~D
1 XDP@ 2 0_0402_5%~D CFD_PWRBTN#_XDP 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 CLK_XDP# 1 XDP@ 2 0_0402_5%~D CLK_CPU_ITP <18>
RC5 RH2
<17,43> PBTN_OUT# 43 HOOK1 ITPCLK#/HOOK5 44 CLK_CPU_ITP# <18>
RC6 1 XDP@ 2 0_0402_5%~D CPU_PWR_DEBUG_R 45 VCC_OBS_AB VCC_OBS_CD 46 XDP_RST#_R 2 XDP@ 1 CPU_PLTRST#
<12> CPU_PWR_DEBUG 1 XDP@ 2 0_0402_5%~D SYS_PWROK_XDP 47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET#
RC8 RC7 1K_0402_1%~D
<17,65> IMVP_PWRGD 49 HOOK3 DBR#/HOOK7 50
RC9 1 XDP@ 2 0_0402_5%~D DDR_XDP_SMBDAT_R1 51 GND14 GND15 52 XDP_TDO
<14,15,19,36> PCH_SMBDATA 1 XDP@ 2 0_0402_5%~D 53 SDA TD0 54
RC10 DDR_XDP_SMBCLK_R1 XDP_TRST#
<14,15,19,36> PCH_SMBCLK 55 SCL TRST# 56 XDP_TDI
XDP_TCLK_R 57 TCK1 TDI 58 XDP_TMS
59 TCK0 TMS 60 CFG3_R
GND16 GND17
SAMTE_BSH-030-01-L-D-A CONN@
C C
Follow Intel schematic
+VCCIO_OUT
review-0930 +1.35V
Note:
2
CPU1B HASWELL_BGA
PECI/THERMTRIP:
1
MISC RC12
Trace width=4 mils ,Spacing=18mil
DDR3L
RC11 C51 BB51 SM_RCOMP0 @ 470_0402_5%
62_0402_5% PROC_DETECT SM_RCOMP0 BB53 SM_RCOMP1
Zo=50 ohm SM_RCOMP1
THERMAL
T1 H_CATERR# G50 BB52 SM_RCOMP2
1
H_PECI G51 CATERR SM_RCOMP2 BE51 H_DRAMRST# 1 R1 2
<43> H_PECI DDR3_DRAMRST# <14,15>
2
PECI SM_DRAMRST 0_0402_5%

1 1 0.1U_0402_16V7K
1 2 H_PROCHOT#_R E50 N53 XDP_PRDY#
<43,58,59> H_PROCHOT# H_THERMTRIP# D53 PROCHOT PRDY N52 XDP_PREQ# RC13 1 2 0_0402_5% XDP_PREQ#_R CC28
R2 56_0402_5% @ CC27
<21> H_THERMTRIP# THERMTRIP PREQ N54 XDP_TCLK RC14 1 2 0_0402_5% XDP_TCLK_R
@ 100P_0402_50V8J @ESD@
TCK M51 XDP_TMS 2 @ESD@ 2
JTAG
TMS M53 T2
XDP_TRST#
D52 TRST N49 T3
H_PM_SYNC XDP_TDI_R RC15 1 @ 2 0_0402_5% XDP_TDI
<17> H_PM_SYNC PM_SYNC TDI
PWR
H_CPUPWRGD F50 M49 XDP_TDO_R RC16 1 @ 2 0_0402_5% XDP_TDO ESD 9/5
<21> H_CPUPWRGD PM_SYS_PWRGD_BUF AP48 PWRGOOD TDO F53 RC17 1
XDP_DBRESET#_R @ 2 0_0402_5% XDP_DBRESET#
SM_DRAMPWROK DBR XDP_DBRESET# <17> Place near SODIMM side,
2
1 CPU_PLTRST# L54
<21> CPU_PLTRST# PLTRSTIN R51
CC29 RC19 1
XDP_BPM#0_R @ 2 0_0402_5% XDP_OBS0
RC18 100P_0402_50V8J BPM#0 R50 RC20 1
XDP_BPM#1_R @ 2 0_0402_5% XDP_OBS1
10K_0402_5% CLK_CPU_DPLL# AC6 BPM#1 P49 XDP_BPM#2
2 <18> CLK_CPU_DPLL# CLK_CPU_DPLL AE6 DPLL_REF_CLKN BPM#2 N50 XDP_BPM#3 T4
@ESD@
<18> CLK_CPU_DPLL T5
1
DPLL_REF_CLKP BPM#3
CLOCK
CLK_CPU_SSC_DPLL# V6 R49 XDP_BPM#4
ESD 9/5<18> CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL Y6 SSC_DPLL_REF_CLKN BPM#4 P53 XDP_BPM#5
T6
<18> CLK_CPU_SSC_DPLL AB6 SSC_DPLL_REF_CLKP BPM#5 U51 T7
CLK_CPU_DMI# XDP_BPM#6
<18> CLK_CPU_DMI#
<18> CLK_CPU_DMI
CLK_CPU_DMI AA6 BCLKN
BCLKP
BPM#6
BPM#7
P51 XDP_BPM#7 T8
T9
DDR3 COMPENSATION SIGNALS
CAD Note:
Avoid stub in the PWRGD path remove by SIT phase SM_RCOMP0 1
RC21 2 100_0402_1%
B while placing resistor RC5 2 OF 12 B
SM_RCOMP1 1
RC22 2 75_0402_1%
HASWELL_BGA1364
SM_RCOMP2 1
RC23 2 100_0402_1%
Note:
SM_DRAMPWROK with DDR Power Gating Topology Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mils
+3V_PCH +3V_PCH
+1.35V_CPU_VDDQ
1
CC30 @ PU/PD for JTAG signals
1
0.1U_0402_16V7K
1
DS3@ DS3@
RC24 RC25 2 RC26 +3VS
100K_0402_5% 100K_0402_5% 1.8K_0402_1%
UC1 XDP_DBRESET#_R RC27 2 1 1K_0402_5%
2
DS3@
2
1 +1.05VS
P
<12,17,43> SYS_PWROK B 4 PM_SYS_PWRGD_BUF

2 O XDP_TMS RC28 2 @ 1 51_0402_5%
<17> PM_DRAM_PWRGD A
G
XDP_TDI_R RC29 2 @ 1 51_0402_5%

1
1 74AHC1G09GW_TSSOP5 RP1
3
DS3@ RC30 XDP_TDO_R 1 8

CC31 3.3K_0402_1% XDP_TCLK 2 7
0.01U_0402_16V7K XDP_TRST# 3 6
2 4 5
2
A A
RC31 1 2 0_0402_5% 51_0804_8P4R_5%
NODS3@ TMS/TDI no require pull high on Check list

PROCESSOR(2/7) PM,XDP,CLK
5 4 3 2 1
5 4 3 2 1
D CPU1C HASWELL_BGA D
CPU1D HASWELL_BGA
<14> DDR_A_D[0..63] DDR_A_D0 AH54 BD31 <15> DDR_B_D[0..63]
DDR_A_D1 AH52 SA_DQ0 RSVD BE25 M_CLK_DDR#0 DDR_B_D0 AC54 AY36
DDR_A_D2 AK51 SA_DQ1 SA_CKN0 BF25 M_CLK_DDR0 M_CLK_DDR#0 <14> DDR_B_D1 AC52 SB_DQ0 RSVD AW27 M_CLK_DDR#2
AK54 SA_DQ2 SA_CK0 BE34 DDR_CKE0_DIMMA M_CLK_DDR0 <14> AE51 SB_DQ1 SB_CKN0 AV27 M_CLK_DDR2 M_CLK_DDR#2 <15>
DDR_A_D3 DDR_B_D2
DDR_A_D4 AH53 SA_DQ3 SA_CKE0 BD25 M_CLK_DDR#1 DDR_CKE0_DIMMA <14> DDR_B_D3 AE54 SB_DQ2 SB_CK0 AU36 DDR_CKE2_DIMMB M_CLK_DDR2 <15>
DDR_A_D5 AH51 SA_DQ4 SA_CKN1 BC25 M_CLK_DDR1 M_CLK_DDR#1 <14> DDR_B_D4 AC53 SB_DQ3 SB_CKE0 AW26 M_CLK_DDR#3 DDR_CKE2_DIMMB <15>
DDR_A_D6 AK52 SA_DQ5 SA_CK1 BF34 DDR_CKE1_DIMMA M_CLK_DDR1 <14> DDR_B_D5 AC51 SB_DQ4 SB_CKN1 AV26 M_CLK_DDR3 M_CLK_DDR#3 <15>
AK53 SA_DQ6 SA_CKE1 BE23 DDR_CKE1_DIMMA <14> AE52 SB_DQ5 SB_CK1 AU35 DDR_CKE3_DIMMB M_CLK_DDR3 <15>
DDR_A_D7 DDR_B_D6
DDR_A_D8 AN54 SA_DQ7 SA_CKN2 BF23 DDR_B_D7 AE53 SB_DQ6 SB_CKE1 BA26 DDR_CKE3_DIMMB <15>
DDR_A_D9 AN52 SA_DQ8 SA_CK2 BC34 DDR_B_D8 AU47 SB_DQ7 SB_CKN2 AY26
DDR_A_D10 AR51 SA_DQ9 SA_CKE2 BD23 DDR_B_D9 AU49 SB_DQ8 SB_CK2 AV35
DDR_A_D11 AR53 SA_DQ10 SA_CKN3 BC23 DDR_B_D10 AV43 SB_DQ9 SB_CKE2 BA27
DDR_A_D12 AN53 SA_DQ11 SA_CK3 BD34 DDR_B_D11 AV45 SB_DQ10 SB_CKN3 AY27
DDR_A_D13 AN51 SA_DQ12 SA_CKE3 DDR_B_D12 AU43 SB_DQ11 SB_CK3 AV36
DDR_A_D14 AR52 SA_DQ13 BE16 DDR_CS0_DIMMA# DDR_B_D13 AU45 SB_DQ12 SB_CKE3
DDR_A_D15 AR54 SA_DQ14 SA_CS#0 BC17 DDR_CS1_DIMMA# DDR_CS0_DIMMA# <14> DDR_B_D14 AV47 SB_DQ13 BA20 DDR_CS2_DIMMB#
AV52 SA_DQ15 SA_CS#1 BE17 DDR_CS1_DIMMA# <14> AV49 SB_DQ14 SB_CS#0 AY19 DDR_CS3_DIMMB# DDR_CS2_DIMMB# <15>
DDR_A_D16 DDR_B_D15
DDR_A_D17 AV53 SA_DQ16 SA_CS#2 BD16 DDR_B_D16 BC49 SB_DQ15 SB_CS#1 AU19 DDR_CS3_DIMMB# <15>
DDR_A_D18 AY52 SA_DQ17 SA_CS#3 BC16 M_ODT0 DDR_B_D17 BE49 SB_DQ16 SB_CS#2 AW20
DDR_A_D19 AY51 SA_DQ18 SA_ODT0 BF16 M_ODT1 M_ODT0 <14> DDR_B_D18 BD47 SB_DQ17 SB_CS#3
DDR_A_D20 AV51 SA_DQ19 SA_ODT1 BF17 M_ODT1 <14> DDR_B_D19 BC47 SB_DQ18 AY20 M_ODT2
DDR_A_D21 AV54 SA_DQ20 SA_ODT2 BD17 DDR_B_D20 BD49 SB_DQ19 SB_ODT0 BA19 M_ODT3 M_ODT2 <15>
DDR_A_D22 AY54 SA_DQ21 SA_ODT3 BC20 DDR_A_BS0 DDR_B_D21 BD50 SB_DQ20 SB_ODT1 AV19 M_ODT3 <15>
AY53 SA_DQ22 SA_BS0 BD21 DDR_A_BS1 DDR_A_BS0 <14> BE47 SB_DQ21 SB_ODT2 AW19
DDR_A_D23 DDR_B_D22
DDR_A_D24 AY47 SA_DQ23 SA_BS1 BD32 DDR_A_BS2 DDR_A_BS1 <14> DDR_B_D23 BF47 SB_DQ22 SB_ODT3 AY23 DDR_B_BS0
DDR_A_D25 AY49 SA_DQ24 SA_BS2 DDR_A_BS2 <14> DDR_B_D24 BE44 SB_DQ23 SB_BS0 BA23 DDR_B_BS1 DDR_B_BS0 <15>
BA47 SA_DQ25 BC21 BD44 SB_DQ24 SB_BS1 BA36 DDR_B_BS2 DDR_B_BS1 <15>
DDR_A_D26 DDR_B_D25
BA45 SA_DQ26 VSS BF20 DDR_A_RAS# BC42 SB_DQ25 SB_BS2 AU30 DDR_B_BS2 <15>
DDR_A_D27 DDR_B_D26
DDR_A_D28 AY45 SA_DQ27 SA_RAS BF21 DDR_A_WE# DDR_A_RAS# <14> DDR_B_D27 BF42 SB_DQ26 VSS AV23 DDR_B_RAS#
DDR_A_D29 AY43 SA_DQ28 SA_WE BE21 DDR_A_CAS# DDR_A_WE# <14> DDR_B_D28 BF44 SB_DQ27 SB_RAS AW23 DDR_B_WE# DDR_B_RAS# <15>
C DDR_A_D30 BA49 SA_DQ29 SA_CAS DDR_A_CAS# <14> DDR_B_D29 BC44 SB_DQ28 SB_WE AV20 DDR_B_CAS# DDR_B_WE# <15> C
DDR_A_D31 BA43 SA_DQ30 BD28 DDR_A_MA0 DDR_A_MA[0..15] <14> DDR_B_D30 BD42 SB_DQ29 SB_CAS DDR_B_CAS# <15>
DDR_A_D32 BF14 SA_DQ31 SA_MA0 BD27 DDR_A_MA1 DDR_B_D31 BE42 SB_DQ30 BA30 DDR_B_MA0 DDR_B_MA[0..15] <15>
DDR_A_D33 BC14 SA_DQ32 SA_MA1 BF28 DDR_A_MA2 DDR_B_D32 BA16 SB_DQ31 SB_MA0 AW30 DDR_B_MA1
DDR_A_D34 BC11 SA_DQ33 SA_MA2 BE28 DDR_A_MA3 DDR_B_D33 AU16 SB_DQ32 SB_MA1 AY30 DDR_B_MA2
DDR_A_D35 BF11 SA_DQ34 SA_MA3 BF32 DDR_A_MA4 DDR_B_D34 BA15 SB_DQ33 SB_MA2 AV30 DDR_B_MA3
DDR_A_D36 BE14 SA_DQ35 SA_MA4 BC27 DDR_A_MA5 DDR_B_D35 AV15 SB_DQ34 SB_MA3 AW32 DDR_B_MA4
DDR_A_D37 BD14 SA_DQ36 SA_MA5 BF27 DDR_A_MA6 DDR_B_D36 AY16 SB_DQ35 SB_MA4 AY32 DDR_B_MA5
DDR_A_D38 BD11 SA_DQ37 SA_MA6 BC28 DDR_A_MA7 DDR_B_D37 AV16 SB_DQ36 SB_MA5 AT30 DDR_B_MA6
DDR_A_D39 BE11 SA_DQ38 SA_MA7 BE27 DDR_A_MA8 DDR_B_D38 AY15 SB_DQ37 SB_MA6 AV32 DDR_B_MA7
DDR_A_D40 BC9 SA_DQ39 SA_MA8 BC32 DDR_A_MA9 DDR_B_D39 AU15 SB_DQ38 SB_MA7 BA32 DDR_B_MA8
DDR_A_D41 BE9 SA_DQ40 SA_MA9 BD20 DDR_A_MA10 DDR_B_D40 AU12 SB_DQ39 SB_MA8 AU32 DDR_B_MA9
DDR_A_D42 BE6 SA_DQ41 SA_MA10 BF31 DDR_A_MA11 DDR_B_D41 AY12 SB_DQ40 SB_MA9 AU23 DDR_B_MA10
DDR_A_D43 BC6 SA_DQ42 SA_MA11 BC31 DDR_A_MA12 DDR_B_D42 BA10 SB_DQ41 SB_MA10 AY35 DDR_B_MA11
DDR_A_D44 BD9 SA_DQ43 SA_MA12 BE20 DDR_A_MA13 DDR_B_D43 AU10 SB_DQ42 SB_MA11 AW35 DDR_B_MA12
DDR_A_D45 BF9 SA_DQ44 SA_MA13 BE32 DDR_A_MA14 DDR_B_D44 AV12 SB_DQ43 SB_MA12 AU20 DDR_B_MA13
DDR_A_D46 BE5 SA_DQ45 SA_MA14 BE31 DDR_A_MA15 DDR_B_D45 BA12 SB_DQ44 SB_MA13 AW36 DDR_B_MA14
DDR_A_D47 BD6 SA_DQ46 SA_MA15 DDR_B_D46 AY10 SB_DQ45 SB_MA14 BA35 DDR_B_MA15
BB4 SA_DQ47 AJ52 DDR_A_DQS#0 DDR_A_DQS#[0..7] <14> AV10 SB_DQ46 SB_MA15
DDR_A_D48 DDR_B_D47
DDR_A_D49 BC2 SA_DQ48 SA_DQSN0 AP53 DDR_A_DQS#1 DDR_B_D48 AU8 SB_DQ47 AD52 DDR_B_DQS#0 DDR_B_DQS#[0..7] <15>
DDR_A_D50 AW3 SA_DQ49 SA_DQSN1 AW52 DDR_A_DQS#2 DDR_B_D49 BA8 SB_DQ48 SB_DQSN0 AU46 DDR_B_DQS#1
DDR_A_D51 AW2 SA_DQ50 SA_DQSN2 AY46 DDR_A_DQS#3 DDR_B_D50 AV6 SB_DQ49 SB_DQSN1 BD48 DDR_B_DQS#2
DDR_A_D52 BB3 SA_DQ51 SA_DQSN3 BD12 DDR_A_DQS#4 DDR_B_D51 BA6 SB_DQ50 SB_DQSN2 BD43 DDR_B_DQS#3
DDR_A_D53 BB2 SA_DQ52 SA_DQSN4 BE7 DDR_A_DQS#5 DDR_B_D52 AV8 SB_DQ51 SB_DQSN3 AW16 DDR_B_DQS#4
DDR_A_D54 AW4 SA_DQ53 SA_DQSN5 BA3 DDR_A_DQS#6 DDR_B_D53 AY8 SB_DQ52 SB_DQSN4 AW10 DDR_B_DQS#5
DDR_A_D55 AW1 SA_DQ54 SA_DQSN6 AT2 DDR_A_DQS#7 DDR_B_D54 AU6 SB_DQ53 SB_DQSN5 AW8 DDR_B_DQS#6
DDR_A_D56 AU3 SA_DQ55 SA_DQSN7 AW39 DDR_B_D55 AY6 SB_DQ54 SB_DQSN6 AL2 DDR_B_DQS#7
AU1 SA_DQ56 RSVD AJ53 DDR_A_DQS0 DDR_A_DQS[0..7] <14> AM2 SB_DQ55 SB_DQSN7 BE38
DDR_A_D57 DDR_B_D56
DDR_A_D58 AR1 SA_DQ57 SA_DQS0 AP52 DDR_A_DQS1 DDR_B_D57 AM3 SB_DQ56 RSVD AD53 DDR_B_DQS0 DDR_B_DQS[0..7] <15>
DDR_A_D59 AR4 SA_DQ58 SA_DQS1 AW53 DDR_A_DQS2 DDR_B_D58 AK1 SB_DQ57 SB_DQS0 AV46 DDR_B_DQS1
DDR_A_D60 AU2 SA_DQ59 SA_DQS2 BA46 DDR_A_DQS3 DDR_B_D59 AK4 SB_DQ58 SB_DQS1 BE48 DDR_B_DQS2
DDR_A_D61 AU4 SA_DQ60 SA_DQS3 BE12 DDR_A_DQS4 DDR_B_D60 AM1 SB_DQ59 SB_DQS2 BE43 DDR_B_DQS3
B DDR_A_D62 AR2 SA_DQ61 SA_DQS4 BD7 DDR_A_DQS5 DDR_B_D61 AM4 SB_DQ60 SB_DQS3 AW15 DDR_B_DQS4 B
DDR_A_D63 AR3 SA_DQ62 SA_DQS5 BA2 DDR_A_DQS6 DDR_B_D62 AK2 SB_DQ61 SB_DQS4 AW12 DDR_B_DQS5
SA_DQ63 SA_DQS6 AT3 DDR_A_DQS7 DDR_B_D63 AK3 SB_DQ62 SB_DQS5 AW6 DDR_B_DQS6
+SM_VREF AM6 SA_DQS7 AW40 SB_DQ63 SB_DQS6 AL3 DDR_B_DQS7
+SM_VREF SM_VREF RSVD SB_DQS7
+SA_DIMM_VREFDQ +SA_DIMM_VREFDQ AR6 BD38
+SB_DIMM_VREFDQ AN6 SA_DIMM_VREFDQ BA40 RSVD
+SB_DIMM_VREFDQ SB_DIMM_VREFDQ RSVD AY40 BF39
BC53 RSVD BA39 RSVD BE39
RSVD RSVD AY39 RSVD BF37
RSVD AV40 RSVD BE37
RSVD AU40 RSVD BD39
RSVD AV39 RSVD BC39
RSVD AU39 RSVD BC37
RSVD RSVD BD37
RSVD
3 OF 12
4 OF 12
HASWELL_BGA1364
HASWELL_BGA1364
A A
Security Classification Compal Secret Data

PROCESSOR(3/7) DDRIII
5 4 3 2 1
5 4 3 2 1
D D
COMPENSATION PU FOR eDP

+VCOMP_OUT
CPU1J HASWELL_BGA
EDP Panel EDP_COMP 2 1

24.9_0402_1% RC32
CPU_HDMI_N2 C25 F15 CPU_EDP_AUX#
<27> CPU_HDMI_N2 D25 DDIB_TXN0 EDP_AUXN F14 CPU_EDP_AUX# <25>
CPU_HDMI_P2 CPU_EDP_AUX
<27> CPU_HDMI_P2 CPU_HDMI_N1 A25 DDIB_TXP0 EDP_AUXP E14 EDP_HPD_R CPU_EDP_AUX <25> Note:
<27> CPU_HDMI_N1 CPU_HDMI_P1 B25 DDIB_TXN1 EDP_HPD Trace width=20 mils ,Spacing=25mil,
<27> CPU_HDMI_P1 DDIB_TXP1
HDMI <27> CPU_HDMI_N0
CPU_HDMI_N0 C24
DDIB_TXN2 EDP_TXN0
C14 CPU_EDP_TX0N
CPU_EDP_TX0N <25>
Max length=100 mils.
CPU_HDMI_P0 D24 A12 CPU_EDP_TX1N
<27> CPU_HDMI_P0 A24 DDIB_TXP2 EDP_TXN1 D14 CPU_EDP_TX1N <25>
CPU_HDMI_N3 CPU_EDP_TX0P
<27> CPU_HDMI_N3 CPU_HDMI_P3 B24 DDIB_TXN3 EDP_TXP0 B12 CPU_EDP_TX1P CPU_EDP_TX0P <25>
<27> CPU_HDMI_P3 DDIB_TXP3 EDP_TXP1 CPU_EDP_TX1P <25>
CPU_mDP_N0 C21 AG6 EDP_COMP
<26> CPU_mDP_N0 D21 DDIC_TXN0 EDP_RCOMP E12
CPU_mDP_P0 EDP_DISP_UTIL 1 2
<26> CPU_mDP_P0 CPU_mDP_N1 A21 DDIC_TXP0 EDP_DISP_UTIL PCH_INV_PWM <17,25>
RC33 @ 0_0402_5%
<26> CPU_mDP_N1 CPU_mDP_P1 B21 DDIC_TXN1 C12 CPU_EDP_TX2N
C
mDP
<26>
<26>
CPU_mDP_P1
CPU_mDP_N2
CPU_mDP_N2 C20 DDIC_TXP1
DDIC_TXN2
FDI_TXN0
FDI_TXP0
D12 CPU_EDP_TX2P CPU_EDP_TX2N <25>
CPU_EDP_TX2P <25>
HPD INVERSION FOR EDP C
CPU_mDP_P2 D20 A14 CPU_EDP_TX3N
<26> CPU_mDP_P2 CPU_mDP_N3 A20 DDIC_TXP2 FDI_TXN1 B14 CPU_EDP_TX3P CPU_EDP_TX3N <25> +VCCIO_OUT
<26> CPU_mDP_N3 B20 DDIC_TXN3 FDI_TXP1 CPU_EDP_TX3P <25>
CPU_mDP_P3
<26> CPU_mDP_P3 DDIC_TXP3
10K_0402_5%
2
C16
DDID_TXN2
RC34
D16
A16 DDID_TXP2
B16 DDID_TXN3
DDID_TXP3
1
EDP_HPD_R
C17
D17 DDID_TXN0 QC1
DDID_TXP0
1
A17 D
B17 DDID_TXN1 LBSS138LT1G_SOT-23-3 2
DDID_TXP1 CPU_EDP_HPD <25>
G
RC35
S
100K_0402_5%
1
10 OF 12
HASWELL_BGA1364
2
HPD is a active-high signal from device.
B
The HPD processor input is B
active-low signal.
A A

PROCESSOR(4/7) eDP,DP and HDMI
5 4 3 2 1
5 4 3 2 1
CPU1K HASWELL_BGA CFG Straps for Processor

F1
RSVD_TP E1 T10 CFG2
BE4 RSVD_TP A5 T11
T12 RSVD_TP RSVD_TP T13
2
BD3 A6
T14 RSVD_TP RSVD_TP T15
RC36
D F6 R54 CFG_RCOMP 1K_0402_1% D
T16 G6 RSVD_TP CFG_RCOMP Y52 CFG16 @
T17 RSVD_TP CFG16 V53 CFG17 CFG16 <8>
CFG17 <8>
1
G21 CFG18 Y51 CFG18
T18 G24 RSVD_TP CFG17 V52 CFG19 CFG18 <8>
T19 F21 RSVD_TP CFG19 CFG19 <8>
H_CPU_RSVD
G19 TESTLOW_F21 B50
F51 VSS RSVD AH49 T20
VSS RSVD T21 PEG Static Lane Reversal - CFG2 is for the 16x
F52 AM48
F22 VSS RSVD AU27 T22
+VCC_CORE VCC RSVD T23
AU26 1: Normal Operation; Lane # definition matches
T25
T27
L52
L53 RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
BD4
BC4
AL6
T24
T26
T28
CFG2 * socket pin map definition
L51 RSVD F8 T29
T30 RSVD_TP RSVD T31 0:Lane Reversed
F24
T32 F25 RSVD_TP
T33 F20 RSVD_TP
H_CPU_TESTLO CFG4
TESTLOW_F20
1
CFG0 AG49 F16
<8> CFG0 CFG1 AD49 CFG0 RSVD T34
<8> CFG1 CFG2 AC49 CFG1 RC37
<8> CFG2 CFG3 AE49 CFG2 1K_0402_1%
<8> CFG3 CFG4 Y50 CFG3
<8> CFG4
2
CFG5 AB49 CFG4
<8> CFG5 CFG6 V51 CFG5 G12
<8> CFG6 CFG7 W51 CFG6 RSVD_TP G10 T35
<8> CFG7 Y49 CFG7 RSVD_TP T36
CFG8 Embedded Display Port Presence Strap
<8> CFG8 Y54 CFG8 H54
CFG9
<8> CFG9 CFG10 Y53 CFG9 VSS H53
<8> CFG10 CFG11 W53 CFG10 VSS
C <8> CFG11 CFG11 1 : Disabled; No Physical Display Port C
CFG12 U53 H51 CFG4
<8> CFG12 CFG13 V54 CFG12 VSS H52 attached to Embedded Display Port
<8> CFG13 CFG14 R53 CFG13 VSS
<8> CFG14 R52 CFG14 N51
CFG15 0 : Enabled; An external Display Port device is
<8> CFG15
T37
L50
L49
CFG15
RSVD
RSVD
RSVD
RSVD
G53
H50
T38
* connected to the Embedded Display Port
1 2 T39 E5 RSVD
H_CPU_TESTLO
T40 RSVD
RC38 49.9_0402_1%
1 2 CFG_RCOMP 11 OF 12 CFG5
RC39 49.9_0402_1%
1 2 HASWELL_BGA1364
H_CPU_RSVD CFG6
RC40 49.9_0402_1%
2
CPU1L HASWELL_BGA
RC41 RC42
1K_0402_1% 1K_0402_1%
1
B3_A3 A3
A4 RSVD
T41 RSVD
BF51
RSVD BF52 BE52_BF52 T42
A51 RSVD BF53 BE53_BF53
T43 RSVD RSVD PCIE Port Bifurcation Straps
A52_B52 A52
A53_B53 A53 RSVD C1 C1_C2
RSVD RSVD C2 C1_C2
RSVD 11: (Default) x16 - Device 1 functions 1 and 2 disabled
C3 C3_B2
C3_B2 B2 RSVD
RSVD CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
B3_A3 B3 C54 B54_C54
RSVD RSVD D1
disabled
A52_B52 B52 RSVD T44
B RSVD 01: Reserved - (Device 1 function 1 disabled ; function B
A53_B53 B53 D54
B54_C54 B54 RSVD RSVD T45 2 enabled)
RSVD
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
BC1
*
T46 BC54 RSVD CFG7
T47 BE1_BD1 BD1 RSVD
RSVD
2
BE54_BD54 BD54 @ RC43
BE1_BD1 BE1 RSVD AN35 1K_0402_1%
BE2_BF2 BE2 RSVD RSVD AN37
BE3_BF3 BE3 RSVD RSVD AF9
1
BE52_BF52 BE52 RSVD RSVD AE9
BE53_BF53 BE53 RSVD RSVD G14
BE54_BD54 BE54 RSVD RSVD G17
BE2_BF2 BF2 RSVD RSVD AD45
BE3_BF3 BF3 RSVD RSVD AG45
BF4 RSVD RSVD
T48 RSVD PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

CFG7 * de assertion
0: PEG Wait for BIOS for training

12 OF 12
HASWELL_BGA1364
A A

PROCESSOR(5/7) RSVD,CFG
5 4 3 2 1
5 4 3 2 1
+1.35V_CPU_VDDQ Source
Note:
Intel Shark Bay
Removed the S3 power reduction circuit.
+1.35V +1.35V_CPU_VDDQ +1.35V_CPU_VDDQ

+1.35V
JP1 @
C1 @
2 1 0.1U_0402_16V7K
1 2
JUMP_43X118
@ C2 @
D JP2 D
0.1U_0402_16V7K
2 1 1 2
55A
+VCC_CORE
JUMP_43X118 +VCC_CORE +VCC_CORE
CPU1E HASWELL_BGA
CPU1F HASWELL_BGA
J17 B43
T49 RSVD VCC
J21 B45 AB45 H33
T50 J26 RSVD VCC B46 AB46 VCC VCC H34
T51 RSVD VCC VCC VCC
+1.35V_CPU_VDDQ J31 B48 AB8 H36
C27 AC46 H37
+VCC_CORE AR29 VCC C28 AC47 VCC VCC H38
VCC_SENSE AR31 VDDQ
VDDQ
VCC
VCC
C31 AC8 VCC
VCC
VCC
VCC
H39
AR33 C32 AC9 H40
VDDQ VCC VCC VCC
100_0402_1%
Note: AT13 C34 AD46 H42

VDDQ VCC VCC VCC
1
AT19 C36 AD8 H43

0 ohm Resistor should be placed VDDQ VCC VCC VCC
RC44
AT23 C38 AE46 H45

cloose to CPU AT27 VDDQ VCC C39 AE47 VCC VCC H46
AT32 VDDQ VCC C42 AE8 VCC VCC H48
AT36 VDDQ VCC C43 AF8 VCC VCC H8
2
AV37 VDDQ VCC C45 AG46 VCC VCC H9

AW22 VDDQ VCC C46 AG8 VCC VCC J10
VCCSENSE 2 @ 1 VCCSENSE_R AW25 VDDQ VCC C48 AH46 VCC VCC J14
<65> VCCSENSE AW29 VDDQ VCC D27 AH47 VCC VCC J19
RC45 0_0402_5%
AW33 VDDQ VCC D28 AH8 VCC VCC J24
AY18 VDDQ VCC D31 AJ45 VCC VCC J29
VSSSENSE 2 @ 1 VSSSENSE_R BB21 VDDQ VCC D32 AJ46 VCC VCC J33
<65> VSSSENSE VSSSENSE_R <13> VDDQ VCC VCC VCC
RC46 0_0402_5% BB22 D34 AK46 J36
BB26 VDDQ VCC D36 AK47 VCC VCC J37
VDDQ VCC VCC VCC
1
100_0402_1%
BB27 D38 AK8 J38

BB30 VDDQ VCC D39 AL45 VCC VCC J39
VDDQ VCC VCC VCC
R3
BB31 D42 AL46 J40

2
BD22 VDDQ VCC D46 AM46 VCC VCC J45

BD26 VDDQ VCC D48 AM47 VCC VCC J46
BD30 VDDQ VCC E27 AM8 VCC VCC J48
BD33 VDDQ VCC E28 AM9 VCC VCC J8
C C
BE18 VDDQ VCC E31 AN10 VCC VCC J9
BE22 VDDQ VCC E32 AN12 VCC VCC K38
VDDQ VCC E39 AN16 VCC VCC K45
AN31 VCC E42 AN17 VCC VCC K46
L6 E43 AN19 K48
+VCC_CORE VCC VCC VCC VCC
M6 E45 AN20 K8
AN22 VCC VCC E46 AN21 VCC VCC K9
T54 AN18 RSVD VCC E48 AN23 VCC VCC L37
F27 AN24 L38
VCCSENSE_R C50 VCC F28 AN25 VCC VCC L39
+VCCIO_OUT Broadwell/Haswell AH9 VCC_SENSE VCC F31 AN26 VCC VCC L40
Note: SVID ALERT HSW_BDW
T56
+VCCIO_OUT D51 RSVD
VCCIO_OUT
VCC
VCC
F32 AN27 VCC
VCC
VCC
VCC
L42
F17 F34 AN29 L43
Place the UP resistor close to CPU Compatibility CKT +VCCIO2PCH
AK6 RSVD VCC F36 AN30 VCC VCC L44
+VCOMP_OUT VCOMP_OUT VCC VCC VCC
1
RC47 Close to CPU 300-1500mil T57

AN33
RSVD VCC
F38 AN32
VCC VCC
L46
RC47 W9 F39 AN34 L47
75_0402_1% J12 F42 AN36 L8
AR49 RSVD VCC F43 AN38 VCC VCC M37
F45 AN39 M38
2
RC48 1 2 43_0402_5% H_CPU_SVIDALRT# J53 VCC F46 AN40 VCC VCC M39
<65> VIDALERT_N J52 VIDALERT VCC F48 AN41 VCC VCC M40
VIDSCLK
<65> VIDSCLK VIDSCLK VCC VCC VCC
VIDSOUT J50 G27 AN42 M42
<65> VIDSOUT VIDSOUT VCC G29 AN43 VCC VCC M43
B51 VCC G31 AN44 VCC VCC M44
VSS VCC VCC VCC
1
CPU_PWR_DEBUG F19 G32 AN45 M45

SVID DATA RC49 <8> CPU_PWR_DEBUG E52 PWR_DEBUG
VSS
VCC
VCC
G34 AN46 VCC
VCC
VCC
VCC
M46
Note: 130_0402_1% V49 G36 AN8 M8
T60 U49 RSVD_TP VCC G38 AN9 VCC VCC M9
Place the UP resistor close to CPU T61
IVR_ERROR AM49 RSVD_TP VCC G39 AP10 VCC VCC N37
T62
2
RC49 Close to CPU 300-1500mil IST_TRIGGER W49 RSVD_TP VCC G42 AP12 VCC VCC N38
+1.05VS T63 V50 RSVD_TP VCC G43
HSW BDW AP13 VCC VCC N39
+VCCIO_OUT AN49 VSS VCC G45 AP14 VCC VCC N40
AJ49 VSS VCC G46 AP15 VCC VCC N42
VSS VCC RC54 X V VCC VCC
2
AG50 G48 AP16 N43

B +VCCIO_OUT AK49 VSS VCC H11 AP17 VCC VCC N44 B
150_0402_1% AJ50 VSS VCC H12 AP18 VCC VCC N46

RC50 AP49 VSS VCC H13
CC45 X V AP19 VCC VCC N47
+1.05VS +VCCIO_OUT VSS VCC VCC VCC
2.2U_0603_10V6K
AB50 H14 AP20 N8

1
VSS VCC VCC VCC

CC32
CPU_PWR_DEBUG AP50 H16 AP21 N9

1
AD50 VSS VCC H17
CC46 X V AP22 VCC VCC P45
VSS VCC VCC VCC
2
2 1 AM50 H18 AP23 P46

@ RC51 0_0603_5% RC52 VSS VCC H19 AP24 VCC VCC P8
2 10K_0402_5% A36 VCC H20
RC53 X V AP25 VCC VCC R46
+VCC_CORE VCC VCC VCC VCC
RESISTOR STUFFING OPTIONS ARE @ A38 H21 AP26 R47
A39 VCC VCC H23 AP27 VCC VCC R8
PROVIDED FOR TESTING PURPOSES RC55 X V
1
A42 VCC VCC H24 AP29 VCC VCC R9

A43 VCC VCC H25 AP30 VCC VCC T45
A45 VCC VCC H26 AP31 VCC VCC T46
A46 VCC VCC H27 AP32 VCC VCC U46
A48 VCC VCC H29 AP33 VCC VCC U47
AA46 VCC VCC AP34 VCC VCC U8
VDDQ DECOUPLING (Follow INTEL DG) AA47 VCC Broadwell/Haswell AP35 VCC VCC U9
AA8 VCC D5 FC_D5 AP36 VCC VCC V45
VCC FC_D5 +VCCIO2PCH VCC VCC
+1.35V_CPU_VDDQ AA9 D3 FC_D3 AP37 V46
VCC FC_D3 AP38 VCC VCC V8
Close to CPU Close to CPU Close to CPU 5 OF 12 AP39 VCC VCC W46
HSW_BDW compatibility CKT AP40 VCC VCC W47
HASWELL_BGA1364 AP41 VCC VCC W8
VCC VCC
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
RESET_OUT# AP42 Y45

SYS_PWROK <17,43,8> VCC VCC
330U_D2_2V_Y
330U_D2_2V_Y
1 1 1 1 1 1 1 1 1 1 1 1 AP43 Y46
VCC VCC
CC33
CC34
CC35
CC36
CC37
CC38
CC39
CC40
CC41
CC42
AP44 Y8
VCC VCC
1
CC43
CC44
+ + AP46 A27
@ @ @ BDW@ AP47 VCC VCC A28
2 2 2 2 2 2 2 2 2 2 @ RC53 AP8 VCC VCC A31
2 2 HSW_BDW compatibility CKT 6.04K_0402_1% AP9 VCC VCC A32
AR35 VCC VCC A34
2
V0.1A V0.1A +1.05VS +VCCIO2PCH AR37 VCC VCC B27

FC_D3 AR39 VCC VCC B28
AR41 VCC VCC B31
BDW@ RC54 2 1 0_0603_5% AR43 VCC VCC B32
VCC VCC
1
0.1U_0402_10V7K
AR45 B34
VCC VCC
BDW@ CC45
22U_0805_6.3V6M
BDW@ CC46
A 1 1 BDW@ AR46 B36 A

RC55 H30 VCC VCC B38
VCC VCC
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
2.67K_0402_1% H31 B39

H32 VCC VCC B42
1 1 1 1 1 1 1 1 1 1 1
2
2 2 VCC VCC
C3
C4
C5
C6
C7
C8
CC47
CC48
CC49
CC50
CC51
place CC45 close to CPU 6 OF 12

HASWELL_BGA1364
@ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2

V0.1A
Close to CPU Close to CPU PROCESSOR(6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
5 4 3 2 1
5 4 3 2 1
CPU1I HASWELL_BGA CPU1G HASWELL_BGA

CPU1H HASWELL_BGA
BC10 G20 A11 AJ48
BC12 VSS VSS G23 AT40 AY50 A15 VSS VSS AJ51
BC15 VSS VSS G25 AT42 VSS VSS AY9 A19 VSS VSS AJ54
BC18 VSS VSS G26 AT43 VSS VSS B11 A22 VSS VSS AK48
D BC33 VSS VSS G44 AT5 VSS VSS B30 A40 VSS VSS AL1 D
BC36 VSS VSS G49 AT50 VSS VSS B33 A44 VSS VSS AL4
BC38 VSS VSS G52 AT51 VSS VSS B37 AA1 VSS VSS AL48
BC46 VSS VSS G8 AT54 VSS VSS B49 AA4 VSS VSS AM5
BC48 VSS VSS G9 AT6 VSS VSS B8 AA48 VSS VSS AM51
BC5 VSS VSS H44 AT8 VSS VSS BA13 AA5 VSS VSS AM52
BC50 VSS VSS H49 AT9 VSS VSS BA18 AA7 VSS VSS AM53
BC52 VSS VSS H7 AU13 VSS VSS BA22 AB5 VSS VSS AM54
BC7 VSS VSS J44 AU18 VSS VSS BA25 AB51 VSS VSS AM7
BD10 VSS VSS J49 AU22 VSS VSS BA29 AB52 VSS VSS AN1
BD41 VSS VSS K1 AU37 VSS VSS BA42 AB9 VSS VSS AN48
BD46 VSS VSS K2 AU42 VSS VSS BA5 AC48 VSS VSS AN5
BE10 VSS VSS K5 AV1 VSS VSS BA52 AC7 VSS VSS AP51
BE15 VSS VSS K6 AV13 VSS VSS BA53 AD48 VSS VSS AP54
BE36 VSS VSS K7 AV18 VSS VSS BA9 AD51 VSS VSS AP7
BE41 VSS VSS L48 AV2 VSS VSS BB10 AD54 VSS VSS AR12
BE46 VSS VSS L7 AV22 VSS VSS BB11 AD7 VSS VSS AR14
BF10 VSS VSS L9 AV25 VSS VSS BB12 AD9 VSS VSS AR16
BF12 VSS VSS M48 AV29 VSS VSS BB14 AE1 VSS VSS AR18
BF30 VSS VSS N48 AV5 VSS VSS BB20 AE5 VSS VSS AR5
BF33 VSS VSS N7 AV50 VSS VSS BB23 AE50 VSS VSS AR50
C BF36 VSS VSS P1 AV9 VSS VSS BB25 AE7 VSS VSS AR7 C
BF38 VSS VSS P2 AW13 VSS VSS BB28 AF5 VSS VSS AR8
BF41 VSS VSS P3 AW18 VSS VSS BB32 AF6 VSS VSS AR9
BF43 VSS VSS P4 AW37 VSS VSS BB33 AF7 VSS VSS AT1
BF46 VSS VSS P48 AW42 VSS VSS BB37 AG48 VSS VSS AT10
C11 VSS VSS P52 AW46 VSS VSS BB41 AG52 VSS VSS AT16
C26 VSS VSS R48 AW50 VSS VSS BB46 AG9 VSS VSS AT25
C30 VSS VSS R7 AW51 VSS VSS BB47 AH1 VSS VSS AT26
C33 VSS VSS T48 AW54 VSS VSS BB48 AH2 VSS VSS AT29
C37 VSS VSS U1 AW9 VSS VSS BB49 AH3 VSS VSS AT33
C4 VSS VSS U2 AY13 VSS VSS BB5 AH4 VSS VSS AT35
C52 VSS VSS U5 AY33 VSS VSS AH7 VSS VSS
C8 VSS VSS U50 AY37 VSS VSS 7 OF 12
D11 VSS VSS U52 AY42 VSS
D15 VSS VSS U54 VSS HASWELL_BGA1364
8 OF 12
D19 VSS VSS U6
D22 VSS VSS U7 HASWELL_BGA1364
D26 VSS VSS V48
D30 VSS VSS V7
D33 VSS VSS V9
D37 VSS VSS W48
D40 VSS VSS W50
D44 VSS VSS W52
D49 VSS VSS W54
B D8 VSS VSS W7 B
E11 VSS VSS Y48
E15 VSS VSS Y7
E16 VSS VSS Y9
E17 VSS VSS
E19 VSS AR22
E20 VSS VSS AB48
E21 VSS VSS P9
E22 VSS VSS G18
E24 VSS VSS
E25 VSS A49
E26 VSS VSS_NCTF A50
E30 VSS VSS_NCTF A8
E33 VSS VSS_NCTF B4
E37 VSS VSS_NCTF BA1
E40 VSS VSS_NCTF BA54
E44 VSS VSS_NCTF BB1
E49 VSS VSS_NCTF BB54
E51 VSS VSS_NCTF BD2
E53 VSS VSS_NCTF BD53
E8 VSS VSS_NCTF BF49
F2 VSS VSS_NCTF BF5
F26 VSS VSS_NCTF BF50
F3 VSS VSS_NCTF BF6
F30 VSS VSS_NCTF C53
F33 VSS VSS_NCTF D2
F37 VSS VSS_NCTF E54
F4 VSS VSS_NCTF F54
F40 VSS VSS_NCTF G1
F44 VSS VSS_NCTF
F49 VSS D50
VSS VSS_SENSE VSSSENSE_R <12>
F5
A G11 VSS A
G13 VSS
G16 VSS
VSS
9 OF 12
HASWELL_BGA1364

PROCESSOR(7/7) VSS
5 4 3 2 1
5 4 3 2 1
+1.35V +1.35V <9> DDR_A_D[0..63]

3A@1.35V
<9> DDR_A_DQS[0..7]
DDR3 SO-DIMM A <9> DDR_A_DQS#[0..7]
JDIMM1 CONN@
+VREF_DQ_DIMMA 1 2 <9> DDR_A_MA[0..15]
3 VREF_DQ VSS 4 DDR_A_D4
VSS DQ4
2.2U_0603_10V6K
0.1U_0402_16V7K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5
CD1
CD2
1 1 DDR_A_D1 7 8 Layout Note:
9 DQ1 VSS 10 DDR_A_DQS#0
11 VSS DQS0# 12 DDR_A_DQS0
Layout Note: Place near JDIMM1
13 DM0 DQS0 14 Place near JDIMM1
2 2 DDR_A_D2 15 VSS VSS 16 DDR_A_D6
D DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7 D
19 DQ3 DQ7 20
DDR_A_D8 21 VSS VSS 22 DDR_A_D12 +0.675VS +1.35V
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS VSS 28
DQS1# DM1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CD40 330U_2.5V_M
DDR_A_DQS1 29 30 DDR3_DRAMRST# 1
DQS1 RESET# DDR3_DRAMRST# <15,8>
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
31 32 1 1 1 1 1 1 1 1 1 1 1 1
VSS VSS
CD7
CD8
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
CD17
CD18
DDR_A_D10 33 34 DDR_A_D14 +
DQ10 DQ14 1 1 1 1
CD3
CD4
CD5
CD6
DDR_A_D11 35 36 DDR_A_D15 @ @
37 DQ11 DQ15 38
DDR_A_D16 39 VSS VSS 40 DDR_A_D20 2 2 2 2 2 2 2 2 2 2 2 2 2
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 2 2 2 2
43 DQ17 DQ21 44
DDR_A_DQS2 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_A_D22
DDR_A_D18
DDR_A_D19
51
53
55
VSS
DQ18
DQ19
DQ22
DQ23
VSS
52
54
56
DDR_A_D23
DDR_A_D28
DDR3L SODIMM ODT GENERATION Add 330u Solid Cap
VSS DQ28 Place near JDIMM1 pin203 pin204
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
65 DM3 DQS3 66
DDR_A_D26 67 VSS VSS 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS VSS Layout Note:
Place near JDIMM1
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<9> DDR_CKE0_DIMMA 75 CKE0 CKE1 76 DDR_CKE1_DIMMA <9>
C 77 VDD VDD 78 DDR_A_MA15 C
DDR_A_BS2 79 NC A15 80 DDR_A_MA14
<9> DDR_A_BS2 81 BA2 A14 82 +0.675VS +1.35V
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
VDD VDD
10P_0402_50V8J
10P_0402_50V8J
DDR_A_MA8 89 90 DDR_A_MA6
A8 A6
1
@RF@
@RF@
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
CD41
CD42
93 94
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2
2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD VDD 102 M_CLK_DDR1
<9> M_CLK_DDR0 M_CLK_DDR#0 103 CK0 CK1 104 M_CLK_DDR#1 M_CLK_DDR1 <9>
<9> M_CLK_DDR#0 105 CK0# CK1# 106 M_CLK_DDR#1 <9>
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
109 A10/AP BA1 110 DDR_A_BS1 <9>
DDR_A_BS0 DDR_A_RAS#
<9> DDR_A_BS0 111 BA0 RAS# 112 DDR_A_RAS# <9>
DDR_A_WE# 113 VDD VDD 114 DDR_CS0_DIMMA#
<9> DDR_A_WE# DDR_A_CAS# 115 WE# S0# 116 M_ODT0 DDR_CS0_DIMMA# <9>
<9> DDR_A_CAS# 117 CAS# ODT0 118 M_ODT0 <9>
DDR_A_MA13 119 VDD VDD 120 M_ODT1
DDR_CS1_DIMMA# 121 A13 ODT1 122 M_ODT1 <9>
<9> DDR_CS1_DIMMA# 123 S1# NC 124
125 VDD VDD 126 +VREF_CA
127 TEST VREF_CA 128
VSS VSS
0.1U_0402_16V7K
2.2U_0603_10V6K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36
CD19
CD20
DDR_A_D33 131 132 DDR_A_D37 1 1
133 DQ33 DQ37 134
DDR_A_DQS4 137 DQS4# DM4 138 +SM_VREF +1.35V
139 DQS4 VSS 140 DDR_A_D38 2 2 *M3+M1:Default Recommendation
B DDR_A_D34 141 VSS DQ38 142 DDR_A_D39 M1:VREF_DQ driven by a voltage Divider Network during B
DQ34 DQ39 Note:
2
DDR_A_D35 143 144 Processor power-off state.
145 DQ35 VSS 146 DDR_A_D44 VREF trace width:20 mils at least RD1 M3:VREF_DQ driven by Processor.
DDR_A_D40 147 VSS DQ44 148 DDR_A_D45 Spacing:20mils to other signal/planes
DQ40 DQ45 1K_0402_1%
DDR_A_D41 149 150
1
153 VSS DQS5# 154 DDR_A_DQS5 RD2
155 DM5
VSS
DQS5
VSS
156 CPU DRIVER 1 2 +VREF_CA
+VREF_CA <15>
DDR_A_D42 157 158 DDR_A_D46 2.2_0402_1%
DQ42 DQ46 VREF PATH IS
2
0.022U_0402_16V7K
CD21
DDR_A_D43 159 160 DDR_A_D47
161 DQ43 DQ47 162 RD3
DDR_A_D48 163 VSS VSS 164 DDR_A_D52 DEFAULT 1K_0402_1%
1 2
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
1
DDR_A_DQS#6 169 VSS VSS 170 RD4
DDR_A_DQS6 171 DQS6# DM6 172 +SA_DIMM_VREFDQ +1.35V
DQS6 VSS 24.9_0402_1%
173 174 DDR_A_D54
DDR_A_D50 175 VSS DQ54 176 DDR_A_D55
2
DDR_A_D51 177 DQ50 DQ55 178
DQ51 VSS
2
179 180 DDR_A_D60
DDR_A_D56 181 VSS DQ60 182 DDR_A_D61
Note: RD5
DDR_A_D57 183 DQ56 DQ61 184 VREF trace width:20 mils at least 1K_0402_1%
185 DQ57 VSS 186 DDR_A_DQS#7 Spacing:20mils to other signal/planes
1
189 DM7 DQS7 190
DDR_A_D58 191 VSS VSS 192 DDR_A_D62 1 RD6 2 +VREF_DQ_DIMMA
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 2.2_0402_1%
DQ59 DQ63
2
0.022U_0402_16V7K
C9
195 196
1 2 197 VSS VSS 198 RD9
199 SA0 EVENT# 200 M_THERMAL# <15,43>
RD7 10K_0402_5% PCH_SMBDATA 1K_0402_1%
+3VS PCH_SMBDATA <15,19,36,8>
1 2
VDDSPD SDA
2.2U_0603_10V6K
0.1U_0402_16V7K
1 2 201 202 PCH_SMBCLK

SA1 SCL PCH_SMBCLK <15,19,36,8>
CD22
CD23
RD8 10K_0402_5% 1 1 203 204

+0.675VS
1
A VTT VTT RD10 A
205 206 0.65A@0.675V 24.9_0402_1%
207 GND1 GND2 208
2 2 BOSS1 BOSS2
2
LCN_DAN06-K4406-0103
SP07000LT00
DDRIII-SODIMM SLOT1
5 4 3 2 1
5 4 3 2 1
3A@1.35V
+1.35V +1.35V <9> DDR_B_D[0..63]
<9> DDR_B_DQS[0..7]
JDIMM2 CONN@
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D4 <9> DDR_B_DQS#[0..7]
DDR_B_D0 5 VSS2 DQ4 6 DDR_B_D5
7 DQ0 DQ5 8 <9> DDR_B_MA[0..15]
DDR_B_D1
DQ1 VSS3
2.2U_0603_10V6K
0.1U_0402_16V7K
9 10 DDR_B_DQS#0
VSS4 DQS#0
CD24
CD25
1 1 11 12 DDR_B_DQS0
13 DM0 DQS0 14
DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6
DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
D 2 2 19 DQ3 DQ7 20 D
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
31 DQS1 RESET# 32 DDR3_DRAMRST# <14,8> Layout Note:
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14 Place near JDIMM2
37 DQ11 DQ15 38
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21 +0.675VS
Layout Note:
43 DQ17 DQ21 44 Place near JDIMM3
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
VSS18 DQ22
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54 +0.675VS +1.35V
DQ19 VSS19 1 1 1 1
C10
C11
C12
C13
55 56 DDR_B_D28
DDR_B_D25 59 DQ24 DQ29 60
DQ25 VSS21 2 2 2 2
10P_0402_50V8J
10P_0402_50V8J
61 62 DDR_B_DQS#3
VSS22 DQS#3
1
@RF@
@RF@
63 64 DDR_B_DQS3
DM3 DQS3
CD43
CD44
65 66
2
71 DQ27 DQ31 72
VSS25 VSS26 Place near JDIMM2 pin203 pin204
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<9> DDR_CKE2_DIMMB 75 CKE0 CKE1 76 DDR_CKE3_DIMMB <9>
C 77 VDD1 VDD2 78 DDR_B_MA15 C
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<9> DDR_B_BS2 81 BA2 A14 82
Layout Note:
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11 Place near JDIMM2
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94 +1.35V
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
VDD9 VDD10
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
M_CLK_DDR2 101 102 M_CLK_DDR3
<9> M_CLK_DDR2 M_CLK_DDR#2 103 CK0 CK1 104 M_CLK_DDR#3 M_CLK_DDR3 <9>
<9> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <9> 1 1 1 1 1 1 1 1 1 1 1 1
CD26
CD27
CD28
CD29
CD30
CD31
CD32
CD33
CD35
CD36
CD37
105 106
VDD11 VDD12
CD34
DDR_B_MA10 107 108 DDR_B_BS1 @ @
109 A10/AP BA1 110 DDR_B_BS1 <9>
DDR_B_BS0 DDR_B_RAS#
<9> DDR_B_BS0 111 BA0 RAS# 112 DDR_B_RAS# <9> 2 2 2 2 2 2 2 2 2 2 2 2
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB#
<9> DDR_B_WE# DDR_B_CAS# 115 WE# S0# 116 M_ODT2 DDR_CS2_DIMMB# <9>
<9> DDR_B_CAS# 117 CAS# ODT0 118 M_ODT2 <9>
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
DDR_CS3_DIMMB# 121 A13 ODT1 122 M_ODT3 <9>
<9> DDR_CS3_DIMMB# 123 S1# NC2 124
125 VDD17 VDD18 126
127 NCTEST VREF_CA 128 +VREF_CA <14>
VSS27 VSS28
0.1U_0402_16V7K
2.2U_0603_10V6K
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
C14
C15
DDR_B_D33 131 132 DDR_B_D37 1 1
133 DQ33 DQ37 134
DDR_B_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDR_B_D38 2 2 +SB_DIMM_VREFDQ +1.35V
B DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 B
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
VSS34 DQ44
2
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
Note: RD11
151 DQ41 VSS35 152 DDR_B_DQS#5 VREF trace width:20 mils at least 1K_0402_1%
153 VSS36 DQS#5 154 DDR_B_DQS5 Spacing:20mils to other signal/planes
155 DM5 DQS5 156
1
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47 1 RD12 2 +VREF_DQ_DIMMB
161 DQ43 DQ47 162 2.2_0402_1%
VSS39 VSS40
1
0.022U_0402_16V7K
CD38
DDR_B_D48 163 164 DDR_B_D52
DQ48 DQ52
2
DDR_B_D49 165 166 DDR_B_D53
167 DQ49 DQ53 168 RD13
1 2
DQS#6 DM6 1K_0402_1%
DDR_B_DQS6 171 172
173 DQS6 VSS43 174 DDR_B_D54 RD14
1
DQ50 DQ55 24.9_0402_1%
DDR_B_D51 177 178
+3VS 179 DQ51 VSS45 180 DDR_B_D60
2
DDR_B_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_B_DQS#7
VSS48 DQS#7
1
187 188 DDR_B_DQS7

RD15 189 DM7 DQS7 190
10K_0402_5% DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196
2
1 2 197 VSS51 VSS52 198

199 SA0 EVENT# 200 M_THERMAL# <14,43>
RD16 10K_0402_5% PCH_SMBDATA
+3VS 201 VDDSPD SDA 202 PCH_SMBDATA <14,19,36,8>
PCH_SMBCLK
203 SA1 SCL 204 PCH_SMBCLK <14,19,36,8>
VTT1 VTT2 +0.675VS
A 0.65A@0.675V A
2.2U_0603_10V6K
0.1U_0402_16V7K
1 1 205 206
G1 G2
CD39
C16
LCN_DAN06-K4806-0103
SP07000M200
2 2

DDRIII-SODIMM SLOT2
Size
0.1
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
330K_0402_1%~D
1
RH3
D
2 D
PCH_INTVRMEN
330K_0402_1%~D
1
@ RH4
2
INTVRMEN - INTEGRATED SUS 1.05V VRM

ENABLE
High - Enable Internal VRs
Low - Enable External VRs
+3V_PCH
+3VS RH60 10K_0402_5%~D
1 2 PCH_GPIO13
1 2 HDA_SPKR 1 2 PCH_AZ_SDOUT
@ RH5 10K_0402_5%~D @ RH6 1K_0402_1%~D
+3VS
NO REBOOT STRAP FLASH DESCRIPTOR SECURITY OVERRIDE
DISABLED WHEN LOW (DEFAULT)
ENABLED WHEN HIGH
LOW = DESABLED (DEFAULT)
HIGH = ENABLED
YH1 Change to SJ10000LD00 (ESR=50Kohm) PCH_GPIO21
10K_0402_5%~D
1 2
RH7
PCH_GPIO19 2 1
CH1 @ 4.7K_0402_5%~D RH8
1 2 PCH_RTCX1_R 2 1 PCH_RTCX1 PCH_SATALED# 1 2
RH9 0_0402_5% 10K_0402_5%~D RH10
18P_0402_50V8J~D
1
+3VS
LPT_PCH_M_EDS
C YH1 RH11 UH1A C
32.768KHZ_12.5PF_9H03220008 10M_0402_5%~D
1 2 PCH_GPIO33 BC8 SATA_PRX_DTX_N0
2
B5 5 SATA_RXN_0 BE8 SATA_PRX_DTX_N0 <36>
RH14 @ 100K_0402_5%~D SATA_PRX_DTX_P0
2
RTCX1 SATA_RXP_0 SATA_PRX_DTX_P0 <36>
CH2 HDD
1 2 PCH_RTCX2 B4 AW8 SATA_PTX_DRX_N0
RTCX2 SATA_TXN_0 AY8 SATA_PTX_DRX_N0 <36>
SATA_PTX_DRX_P0
RTC
SATA_TXP_0 SATA_PTX_DRX_P0 <36>
+RTC_CELL RH15 1 2 20K_0402_5%~D 18P_0402_50V8J~D SRTCRST# B9
SRTCRST# BC10 SATA_PRX_DTX_N1
SATA_RXN_1 SATA_PRX_DTX_N1 <29>
RH12 1 2 1M_0402_5%~D INTRUDER# A8 BE10 SATA_PRX_DTX_P1
INTRUDER# SATA_RXP_1 SATA_PRX_DTX_P1 <29>
NGFF SSD for Echo 15
PCH_INTVRMEN G10 AV10 SATA_PTX_DRX_N1
INTVRMEN SATA_TXN_1 AW10 SATA_PTX_DRX_N1 <29>
SATA_PTX_DRX_P1
SATA_TXP_1 SATA_PTX_DRX_P1 <29>
RH13 1 2 20K_0402_5%~D PCH_RTCRST# D9
RTCRST#
SATA
BB9
SATA_RXN_2 BD9
2 SATA_RXP_2
CMOS_CLR1 CMOS setting CH3 PCH_AZ_BITCLK B25
1U_0402_6.3V6K~D HDA_BCLK AY13
1 2 PCH_AZ_SYNC A22 SATA_TXN_2 AW13
Shunt Clear CMOS 1 2 1 HDA_SYNC SATA_TXP_2
Open Keep CMOS HDA_SPKR AL10 BC12 SATA_PRX_DTX_N3
<32> HDA_SPKR SPKR SATA_RXN_3 BE12 SATA_PRX_DTX_N3 <29>
SATA_PRX_DTX_P3
C24 SATA_RXP_3 SATA_PRX_DTX_P3 <29>
@ PCH_AZ_RST# NGFF SSD for Echo 17
CMOS1 SHORT PADS~D HDA_RST# AR13 SATA_PTX_DRX_N3
ME_CLR1 TPM setting 1 2 L22 SATA_TXN_3 AT13 SATA_PTX_DRX_N3 <29> Gen2 Only
AZALIA
PCH_AZ_CODEC_SDIN0 SATA_PTX_DRX_P3
1U_0402_6.3V6K~D <32> PCH_AZ_CODEC_SDIN0 HDA_SDI0 SATA_TXP_3 SATA_PTX_DRX_P3 <29>
Shunt Clear ME RTC Registers CH4
CMOS place near DIMM K22
HDA_SDI1 BD13 SATA_PRX_DTX_N4
Open Keep ME RTC Registers G22 SATA_RXN4/PERN1 BB13 SATA_PRX_DTX_P4
SATA_PRX_DTX_N4 <29>
HDA_SDI2 SATA_RXP4/PERP1 SATA_PRX_DTX_P4 <29>
F22 AV15 SATA_PTX_DRX_N4
HDA_SDI3 SATA_TXN4/PETN1 AW15 SATA_PTX_DRX_N4 <29>
SATA_PTX_DRX_P4
1 2 A24 SATA_TXP4/PETP1 SATA_PTX_DRX_P4 <29>
PCH_AZ_SDOUT
<43> ME_EN HDA_SDO BC14
RH16 1K_0402_1%~D SATA_PRX_DTX_N5
PCH_GPIO33 B17 SATA_RXN5/PERN2 BE14 SATA_PRX_DTX_P5 SATA_PRX_DTX_N5 <29>
DOCKEN#/GPIO33 SATA_RXP5/PERP2 SATA_PRX_DTX_P5 <29>
HDA_SYNC Isolation Circuit +5VS +3V_PCH PCH_GPIO13 C22
HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2
AP15
AR15
SATA_PTX_DRX_N5
SATA_PTX_DRX_P5
SATA_PTX_DRX_N5 <29>
SATA_TXP5/PETP2 SATA_PTX_DRX_P5 <29>
1
0_0603_5%~D
2
B B
G
RH17
AY5 SATA_COMP
@ SATA_RCOMP
PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC AP3 PCH_SATALED#
SATALED# PCH_SATALED# <38>
S
RH18 2 1 51_0402_1%~D PCH_JTAG_TCK AB3 AT1 PCH_GPIO21

QH1 JTAG_TCK SATA0GP/GPIO21
1M_0402_5%~D
SSM3K7002FU_SC70-3~D +3.3V_ALW_PCH_JTAG RH19 1 2 210_0402_1%~D PCH_JTAG_TMS AD1 AU2 PCH_GPIO19

JTAG_TMS SATA1GP/GPIO19
2
@
RH20
RH21 1 2 210_0402_1%~D PCH_JTAG_TDI AE2 BD4 SATA_IREF 2 1
JTAG
@ +1.5VS
@ JTAG_TDI SATA_IREF RH22 0_0402_5%
RH23 1 2 210_0402_1%~D PCH_JTAG_TDO AD3 BA2
@ JTAG_TDO TP9 PAD~D T64 @
1
2 @ 1 PCH_TP25 F8 BB2
TP25 TP8
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
RH24 0_0402_5% PAD~D T65 @

1
C26
TP22
RH25
RH26
RH27
@ T66 PAD~D
AB6
@ T67 PAD~D TP20
SATA Impedance Compensation
2
LYNXPOINT_BGA695 1 OF 11 +1.5VS
SATA_COMP 1 2
7.5K_0402_1%~D RH28
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
HDA for Codec and MDC routing next to clock pins.
RP2
1 8
2 7 PCH_AZ_SDOUT
<32> PCH_AZ_CODEC_SDOUT 3 6 PCH_AZ_SYNC_Q
<32> PCH_AZ_CODEC_SYNC 4 5 PCH_AZ_RST#
<32> PCH_AZ_CODEC_RST#
33_0804_8P4R_5%
1 2 PCH_AZ_BITCLK
<32> PCH_AZ_CODEC_BITCLK
RH29 33_0402_5%~D
27P_0402_50V8J~D
A A
@ CH5

PCH (1/9) RTC,HDA,SATA,XDP
5 4 3 2 1
5 4 3 2 1
+3VS
@ CH6
1 2
0.1U_0402_25V6K~D
5
PCH_PWROK 1
P
B 4 SYS_PWROK
IMVP_PWRGD 2 O +3VS
<65,8> IMVP_PWRGD A
G
UH2 1 2 PCH_DPC_CLK
3
TC7SH08FU_SSOP5~D RV528 2.2K_0402_5%~D
1 2 PCH_DPC_DAT
RV529 2.2K_0402_5%~D
D D
+3V_PCH
1 @ 2 SUS_STAT#
LPT_PCH_M_EV
RH30 10K_0402_5%~D UH1E 5
1 2 ME_SUS_PWR_ACK
RH31 10K_0402_5%~D T45 R40 PCH_DPB_HDMI_CLK
1 2 VGA_BLUE DDPB_CTRLCLK PCH_DPB_HDMI_CLK <27>
@ PCIE_WAKE#
RH35 10K_0402_5%~D U44
VGA_GREEN DDPB_CTRLDATA
R39 PCH_DPB_HDMI_DAT
PCH_DPB_HDMI_DAT <27>
HDMI
V45 R35 PCH_DPC_CLK
1 2 PCH_RI# VGA_RED DDPC_CTRLCLK PCH_DPC_CLK <26>
RH37 10K_0402_5%~D
1 2 SYS_RESET#
M43
VGA_DDC_CLK DDPC_CTRLDATA
R36 PCH_DPC_DAT
PCH_DPC_DAT <26>
mDP
@
<8> XDP_DBRESET# M45 N40
RH32 0_0402_5%
CRT
+3VS VGA_DDC_DATA DDPD_CTRLCLK
N42 N38
1 2 PM_CLKRUN# RH34 0_0402_5% VGA_HSYNC DDPD_CTRLDATA
RH33 8.2K_0402_5%~D ME_SUS_PWR_ACK_R 1 @ 2 SUSACK#_R N44
VGA_VSYNC H45
1 2 PCH_RSMRST# 1 2 U40 DDPB_AUXN
RH38 10K_0402_5%~D RH39 649_0402_1%~D DAC_IREF K43 PCH_DPC_AUX#
U39 DDPC_AUXN PCH_DPC_AUX# <26>
VGA_IRTN
DISPLAY
J42
DDPD_AUXN
PCH_INV_PWM N36 H43
LPT_PCH_M_EDS <10,25> PCH_INV_PWM EDP_BKLTCTL DDPB_AUXP
UH1B 5
LVDS
PANEL_BKLEN K36 K45 PCH_DPC_AUX
AW22 <43> PANEL_BKLEN EDP_BKLTEN DDPC_AUXP PCH_DPC_AUX <26>
DMI_CTX_PRX_N0
<7> DMI_CTX_PRX_N0 AR20 DMI_RXN_0 G36 J44
DMI_CTX_PRX_N1 PCH_ENVDD
<7> DMI_CTX_PRX_N1 DMI_RXN_1 AJ35 <25> PCH_ENVDD EDP_VDDEN DDPD_AUXP
DMI_CTX_PRX_N2 AP17 FDI_RXN_0 K40 PCH_HDMI_HPD
<7> DMI_CTX_PRX_N2 AV20 DMI_RXN_2 AL35 H20 DDPB_HPD PCH_HDMI_HPD <27>
DMI_CTX_PRX_N3 PCI_PIRQA#
<7> DMI_CTX_PRX_N3 DMI_RXN_3 FDI_RXN_1 PIRQA# K38 PCH_mDP_HPD
AY22 AJ36 L20 DDPC_HPD PCH_mDP_HPD <26>
DMI_CTX_PRX_P0 PCI_PIRQB#
<7> DMI_CTX_PRX_P0 AP20 DMI_RXP_0 FDI_RXP_0 PIRQB# H39
DMI_CTX_PRX_P1
<7> DMI_CTX_PRX_P1 DMI_RXP_1 FDI AL36 PCI_PIRQC# K17 DDPD_HPD
C DMI_CTX_PRX_P2 AR17 FDI_RXP_1 PIRQC# C
<7> DMI_CTX_PRX_P2 AW20 DMI_RXP_2 AV43 M20
DMI_CTX_PRX_P3 DMI PCI_PIRQD#
<7> DMI_CTX_PRX_P3 DMI_RXP_3 TP16 PIRQD# PCI
G17 BT_OFF#
BD21 AY45 PIRQE#/GPIO2 BT_OFF# <28>
DMI_CRX_PTX_N0 GPU_PWR_LEVEL A12
<7> DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 BE20 DMI_TXN_0 TP5 <43,46> GPU_PWR_LEVEL GPIO50 F17 DP_CBL_DET
<7> DMI_CRX_PTX_N1 DMI_TXN_1 AV45 B13 PIRQF#/GPIO3 DP_CBL_DET <26>
BD17 TP15 <25> TS_RST# GPIO52 L15
DMI_CRX_PTX_N2
<7> DMI_CRX_PTX_N2 BE18 DMI_TXN_2 AW44 PIRQG#/GPIO4
DMI_CRX_PTX_N3 DGPU_HOLD_RST# C12
<7> DMI_CRX_PTX_N3 DMI_TXN_3 TP10 <43,46> DGPU_HOLD_RST# GPIO54 M15 FFS_INT1
DMI_CRX_PTX_P0 BB21 AL39 FDI_CSYNC BBS_BIT1 C10 PIRQH#/GPIO5 FFS_INT1 <36>
<7> DMI_CRX_PTX_P0 BC20 DMI_TXP_0 FDI_CSYNC FDI_CSYNC <7> GPIO51 AD10
DMI_CRX_PTX_P1 @ T68 PAD~D
<7> DMI_CRX_PTX_P1 DMI_TXP_1 AL40 A10 PME#
FDI_INT WL_OFF#
BB17 FDI_INT FDI_INT <7> <28> WL_OFF# GPIO53 Y11 PCH_PLTRST#
DMI_CRX_PTX_P2
<7> DMI_CRX_PTX_P2 BC18 DMI_TXP_2 AT45 1 2 AL6 PLTRST# PCH_PLTRST# <41,46>
DMI_CRX_PTX_P3 FDI_IREF @ +1.5VS
<7> DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF <25> TS_INT# GPIO55
RH40 0_0402_5%
1 @ 2 DMI_IREF BE16 AU42 PAD~D T69 @
+1.5VS DMI_IREF TP17
RH144 0_0402_5% LYNXPOINT_BGA695 5 OF 11
AW17 AU44 PAD~D T71 @
@ T70 PAD~D TP12 TP13
AV17 AR44 FDI_RCOMP 2 1 +3VS +3VS
TP7 FDI_RCOMP +1.5VS
@ T72 PAD~D 7.5K_0402_1%~D RH41 @ CH7
1 2 DMI_RCOMP AY17 1 2
+1.5VS DMI_RCOMP
1
RH42 7.5K_0402_1%~D
0.1U_0402_25V6K~D RH43
R2458 10K_0402_5%~D
1 2 SUSACK#_R R6 C8 DSWODVREN RH46 0_0402_5% @
<43> SUSACK# SUSACK# DSWVRMEN
5
0_0402_5% 1 @ 2 PCH_RSMRST#_R
2
System Power
SYS_RESET# AM1 L13 PCH_DRWROK_R 1 2 PCH_PLTRST# 1
P
SYS_RESET# Management DPWROK @ PCH_DPWROK <43> B 4
RH45 0_0402_5% PLT_RST
1 2 SYS_PWROK_R AD7 K3 WAKE# 1 2 2 O PLT_RST# <28,30,31,43,44>
@
<12,43,8> SYS_PWROK SYS_PWROK WAKE# PCIE_WAKE# <30,43> A
G
RH47 0_0402_5% RH48 @ 0_0402_5%~D UH3
1
1 @ 2 PCH_PWROK_R F10 AN7 PM_CLKRUN# TC7SH08FU_SSOP5~D
3
<43> PCH_PWROK PWROK CLKRUN#
RH49 0_0402_5%
1 @ 2 PM_APWROK_R AB7 U7 SUS_STAT# T73 PAD~D@ RH51
RH50 0_0402_5% APWROK SUS_STAT#/GPIO61 100K_0402_5%~D
1 @ 2 PM_DRAM_PWRGD_R H3 Y6
2
<8> PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62 SUSCLK <28>
RH52 0_0402_5% @
1 2 J2 Y7 T74 PAD~D
@ PCH_RSMRST#_R PM_SLP_S5#
<43> PCH_RSMRST# RSMRST# SLP_S5#/GPIO63 PM_SLP_S5# <37,43> 1 2
RH53 0_0402_5% PCH_ENVDD
1 2 ME_SUS_PWR_ACK_R J4 C6 PM_SLP_S4# T75 PAD~D @
@ RH54 100K_0402_5%
B <43> ME_SUS_PWR_ACK SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PM_SLP_S4# <43> B
RH55 0_0402_5%
1 2 K1 H1 T76 PAD~D @
@ SIO_PWRBTN#_R PM_SLP_S3#
<43,8> PBTN_OUT# PWRBTN# SLP_S3# PM_SLP_S3# <37,43>
RH56 0_0402_5%
ACIN E6 F3
<37,43,59> ACIN ACPRESENT/GPIO31 SLP_A# 1 2 PCH_mDP_HPD +3VS
1 2 PCH_BATLOW# K7 F1 PM_SLP_SUS# T77 PAD~D @ RH57 100K_0402_5%
+PCH_VCCDSW3_3 BATLOW#/GPIO72 SLP_SUS# PM_SLP_SUS# <43>
RH58 8.2K_0402_5%~D PAD~D @
PCH_RI# N4 AY3 H_PM_SYNC T78
RI# PMSYNCH H_PM_SYNC <8> 2 1
BT_OFF#
@ T79 PAD~D AB10 G5 Mason: Follow Intel DG. HPD PL. 2014/1/21 8.2K_0402_5%~D RH59
TP21 SLP_LAN# WL_OFF# 2 1
D2 8.2K_0402_5%~D RH61
SLP_WLAN#/GPIO29 PCI_PIRQA# 2 1
+RTC_CELL 8.2K_0402_5%~D RH62
+PCH_VCCDSW3_3 LYNXPOINT_BGA695 4 OF 11 PCI_PIRQB# 2 1
330K_0402_1%
8.2K_0402_5%~D RH63
2
2 1 ACIN PCI_PIRQC# 2 1
RH65
RH152 10K_0402_5% 8.2K_0402_5%~D RH64

1 2 WAKE# PCI_PIRQD# 2 1
RH36 10K_0402_5%~D 8.2K_0402_5%~D RH66
1
1 2 PM_CLKRUN#
RH67 @ 10K_0402_5%~D
DSWODVREN
DSWODVREN - ON DIE DSW VR ENABLE A16 SWAP OVERRIDE STRAP
HIGH = ENABLED (DEFAULT)
330K_0402_1%
LOW = DISABLED STP_A16OVR LOW = A16 SWAP OVERRIDE

@ RH70
HIGH = DEFAULT
2
1
Boot BIOS Strap

SATA_SLPD
BBS_BIT1
BBS_BIT1 (BBS_BIT0) Boot BIOS Location
A A
1K_0402_1%
0 0 LPC
1
@ RH71
0 1 Reserved (NAND)
2
1 0 PCI
* 1 1 SPI
GPIO51 has internal pull up.
PCH (2/9) DMI,FDI,PM,DP,CRT
5 4 3 2 1
5 4 3 2 1
D D
LPT_PCH_M_EDS
UH1C 5
RH129 0_0402_5%
Y43 AB35 CLK_PEG_GPU#_R 1 @ 2 CLK_PEG_GPU#
CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PEG_GPU# <41,46>
RH128 0_0402_5% GPU
Y45 AB36 CLK_PEG_GPU_R 1 @ 2 CLK_PEG_GPU
CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PEG_GPU <41,46>
1 @ 2 AB1 AF6 CLKREQ#_GPU
+3V_PCH
RH73 10K_0402_5%~D PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 10K_0402_5% RH74 1
CLKREQ#_GPU
2 <41,46>
+3V_PCH
CLOCK TERMINATION for FCIM and need close to PCH
AA44 Y39 CLK_PCIE_DGPU#
AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B CLK_PCIE_DGPU# <41> RPH1
CLKOUT_PCIE_P_1 Y38 CLK_PCIE_DGPU CLK_BUF_DMI# 1 8
1 2 AF1 CLKOUT_PEG_B_P CLK_PCIE_DGPU <41> 2 7
+3V_PCH @ Caldera CLK_BUF_DMI
RH75 10K_0402_5%~D PCIECLKRQ1#/GPIO18 U4 CLKREQ#_DGPU CLK_BUF_BCLK 3 6
AB43 PEGB_CLKRQ#/GPIO56 CLKREQ#_DGPU <41,43>
CLK_PCIE_LAN# 10K_0402_5% RH76 1 2 +3V_PCH CLK_BUF_BCLK# 4 5
<30> CLK_PCIE_LAN# CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI#
10/100/1G LAN CLKOUT_DMI CLK_CPU_DMI# <8>
CLK_PCIE_LAN AB45 10K_0804_8P4R_5%~D
<30> CLK_PCIE_LAN CLKOUT_PCIE_P_2 AF40 CLK_CPU_DMI
AF3 CLKOUT_DMI_P CLK_CPU_DMI <8> RPH2
LANCLK_REQ#
<30> LANCLK_REQ# 1 2 PCIECLKRQ2#/GPIO20/SMI# AJ40 1 8
+3V_PCH CLK_CPU_SSC_DPLL#
CLK_PCIE_WLAN# AD43 CLKOUT_DP AJ39 CLK_CPU_SSC_DPLL CLK_CPU_SSC_DPLL# <8> 2 7
RH77 10K_0402_5%~D
<28> CLK_PCIE_WLAN# AD45 CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL <8> 3 6
C MiniWLAN CLK_PCIE_WLAN CLK_BUF_DOT96# C
<28> CLK_PCIE_WLAN T3 CLKOUT_PCIE_P_3 AF35 4 5
WLANCLK_REQ# CLK_CPU_DPLL# CLK_BUF_DOT96
<28> WLANCLK_REQ# 1 2 PCIECLKRQ3#/GPIO25 CLKOUT_DPNS AF36 CLK_CPU_DPLL# <8>
CLK_CPU_DPLL
+3VS CLKOUT_DPNS_P CLK_CPU_DPLL <8>
RH78 10K_0402_5%~D CLK_PCIE_CD# AF43 10K_0804_8P4R_5%~D
<31> CLK_PCIE_CD# AF45 CLKOUT_PCIE_N_4 AY24
CLK_PCIE_CD CLK_BUF_DMI# CLK_PCH_14M RH79 1 2 10K_0402_5%~D
<31> CLK_PCIE_CD V3 CLKOUT_PCIE_P_4 CLKIN_DMI AW24
Card Reader CDCLK_REQ# CLK_BUF_DMI
<31> CDCLK_REQ# 1 2 PCIECLKRQ4#/GPIO26 CLKIN_DMI_P
+3V_PCH CLK_BUF_CKSSCD# RH122 1 2 10K_0402_5%~D
RH80 10K_0402_5%~D AE44
AE42 CLKOUT_PCIE_N5
CLKOUT_PCIE_P_5
CLKIN_GND
CLKIN_GND_P
AR24
AT24
CLK_BUF_BCLK#
CLK_BUF_BCLK 距距距距，從 RP拆拆拆拆拆拆
CLK_BUF_CKSSCD RH155 1 2 10K_0402_5%~D
1 @ 2 AA2
+3V_PCH PCIECLKRQ5#/GPIO44
RH81 10K_0402_5%~D H33 CLK_BUF_DOT96#
AB40 CLKIN_DOT96N G33 CLK_BUF_DOT96
AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P
1 @ 2 AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD#
+3V_PCH PCIECLKRQ6#/GPIO45 CLKIN_SATA
RH82 10K_0402_5%~D BC6 CLK_BUF_CKSSCD
AJ44 CLKIN_SATA_P
CLKOUT_PCIE_N_7 F45 CLK_PCH_14M
AJ42 REFCLK14IN D17 CLK_PCI_LPBACK
CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
RH83 2 1 10K_0402_5%~D Y3 AL44 XTAL25_IN
+3V_PCH PCIECLKRQ7#/GPIO46 XTAL25_IN AM43 XTAL25_OUT 1 2
2 @ 1 CLK_BCLK_ITP# AH43 XTAL25_OUT RH84 1M_0402_5%
<8> CLK_CPU_ITP# CLKOUT_ITPXDP C40
RH85 0_0402_5%
CLKOUTFLEX0/GPIO64
2
2 @ 1 CLK_BCLK_ITP AH45 PAD~D T80 @
<8> CLK_CPU_ITP CLKOUT_ITPXDP_P F38 PCH_GPIO65
RH86 0_0402_5% RH88
CLK_PCI_LPBACK RH87 2 1 22_0402_5%~D CLK_PCI0 D44 CLKOUTFLEX1/GPIO65
CLKOUT_33MHZ0 F36 PCH_GPIO66 0_0402_5% YH2
CLK_PCI_LPC RH89 2 1 22_0402_5%~D CLK_PCI1 E44 CLKOUTFLEX2/GPIO66 25MHZ_10PF_Q22FA2380049900
1
<43> CLK_PCI_LPC CLKOUT_33MHZ1 F39 3 1
@ T96 PAD~D CLK_PCI2 B42 CLKOUTFLEX3/GPIO67 OUT IN
CLKOUT_33MHZ2
12P_0402_50V8J
12P_0402_50V8J
AM45 ICLK_IREF 2 @ 1 4 2
ICLK_IREF +1.5VS GND GND
CLK_PCI3 F41
10P_0402_50V8J
@ T95 PAD~D RH91 0_0402_5% 2 2

CLKOUT_33MHZ3
1
CH9
@RF@
AD39
CH8
A40 TP19 AD38
CH72
@ T83 PAD~D CLK_PCI4 PAD~D T82 @

CLKOUT_33MHZ4 TP18 PAD~D T84 @
2
AN44 PCH_CLK_BIASREF 1 2 1 1
DIFFCLK_BIASREF +1.05V_+1.5V_RUN
CLOCK SIGNAL 7.5K_0402_1% RH92
LYNXPOINT_BGA695 2 OF 11
B B
+3VS
RPH3
1 8
PCH_GPIO65 2 7
PCH_GPIO66 3 6
4 5
10K_0804_8P4R_5%
A A

PCH (3/9) CLK
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9201P
5 4 3 2 1
5 4 3 2 1
+3VS
+3VS
+3VS
2
SML1CLK 6 1
EC_SMB_CK2 <42,43,46>
1
RH93 RH94 DMN66D0LDW-7
QH3A
5
2
2.2K_0402_5% 2.2K_0402_5%
SML1DATA 3 4
2
6 1 EC_SMB_DA2 <42,43,46>
MEM_SMBCLK
PCH_SMBCLK <14,15,36,8>
@
QH4A QH3B
D DMN66D0LDW-7 D
DMN66D0LDW-7_SOT363-6
2 @ 1
RH95 0_0402_5%
5
MEM_SMBDATA 3 4
PCH_SMBDATA <14,15,36,8>
QH4B @
2 @ 1
RH96 0_0402_5%
+3V_PCH
+3VS MEM_SMBCLK 2 @ 1
2.2K_0402_5% RH97
1 2 SERIRQ MEM_SMBDATA 2 @ 1
RH98 10K_0402_5%~D 2.2K_0402_5% RH99
DDR_HVREF_RST_PCH 2 1
1K_0402_1% RH100
LPT_PCH_M_EDS
UH1D RH127 PCH_GPIO74 2 1
1 @ 2 0_0402_5% 10K_0402_5% RH101
EC_LID_OUT# <43>
RH102
N7 PCH_LID_SW_IN# 1 @ 2 0_0402_5%
A20 SMBALERT#/GPIO11 LID_SW_IN# <37,38,43>
LPC_AD0
<43> LPC_AD0 LAD_0 R10
SMBus MEM_SMBCLK
LPC_AD1 C20 SMBCLK
<43> LPC_AD1 LAD_1 U11 MEM_SMBDATA
LPC_AD2 A18 SMBDATA +3V_PCH
LPC
<43> LPC_AD2 LAD_2 N8 DDR_HVREF_RST_PCH
LPC_AD3 C18 SML0ALERT#/GPIO60 RPH4
<43> LPC_AD3 LAD_3 U8 SML0CLK SML1DATA 1 8
B21 SML0CLK SML0CLK <41> 2 7
LPC_FRAME# SML1CLK
<43> LPC_FRAME# LFRAME# R7 3 6
SML0DATA SML0DATA
D21 SML0DATA SML0DATA <41> 4 5
SML0CLK
LDRQ0# H6 PCH_GPIO74
G20 SML1ALERT#/PCHHOT#/GPIO74 2.2K_0804_8P4R_5%
C
LDRQ1#/GPIO23 K6 SML1CLK C
SERIRQ AL11 SML1CLK/GPIO58
<43> SERIRQ SERIRQ N11 SML1DATA
SML1DATA/GPIO75
AF11
PCH_SPI_CLK AJ11 CL_CLK
SPI
<44> PCH_SPI_CLK SPI_CLK AF10
PCH_SPI_CS0# AJ7 C-Link CL_DATA
SPI_CS0# AF7
PCH_SPI_CS1# AL7 CL_RST#
<44> PCH_SPI_CS1# SPI_CS1#
AJ10
SPI_CS2# BA45 PAD~D T85 @
PCH_SPI_SI AH1 TP1
15_0804_8P4R_5% <44> PCH_SPI_SI SPI_MOSI BC45 PAD~D T86 @
SPI_PCH_DO2_R 4 5 PCH_SPI_DO2 PCH_SPI_SO AH3 Thermal TP2
3 6 <44> PCH_SPI_SO SPI_MISO BE43
SPI_PCH_DO3_R PCH_SPI_DO3 PAD~D T87 @
PCH_SPI_SI_R 2 7 PCH_SPI_SI PCH_SPI_DO2 AJ4 TP4
PCH_SPI_S0_R 1 8 PCH_SPI_SO SPI_IO2 BE44 PAD~D T88 @
RPH5
To TPM PCH_SPI_DO3 AJ2
SPI_IO3
TP3
AY43 PCH_TD_IREF 1 2
TD_IREF RH103 8.2K_0402_1%
PCH_SPI_CLK_R 1 2 PCH_SPI_CLK
RH104 EMI@ 15_0402_1%
LYNXPOINT_BGA695 3 OF 11 5
+3V_PCH +3V_PCH
1 2 SPI_PCH_DO3_R +3V_PCH
200 MIL SO8
2
RH105 1K_0402_5%
1 2 SPI_PCH_DO2_R RH107
RH106 1K_0402_5% 3.3K_0402_5%~D 64Mb Flash ROM CH10
@ 1 2
1
UH4 0.1U_0402_25V6K~D
B B
PCH_SPI_CS0# 1 8 PCH_SPI_CLK_R
PCH_SPI_S0_R 2 /CS VCC 7 SPI_PCH_DO3_R
SPI_PCH_DO2_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_R
/WP(IO2) CLK
2
4 5 PCH_SPI_SI_R
GND DI(IO0) RH108 @
W25Q64FVSSIQ_SO8 33_0402_5%~D
1
UH14 to SA000039A30 IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
22P_0402_50V8J~D
UH14 to SA000046400 IC FL 64M EN25Q64-104HIP SOIC 8P SPI ROM 1
@
UH14 to SA00006N100 IC FL 64M MX25L647EM2I-10G SOIC 8P SPI ROM
CH11
2
UH14 to SA00005L100 IC FL 64M N25Q064A13ESEC0P SOIC 8P SPI ROM
Reserve for EMI please

close to UH14
A A

PCH (4/9) SPI, SMBUS,LPC
5 4 3 2 1
5 4 3 2 1
D D
LPT_PCH_M_EDS
UH1I
USB3RN3 AW31 B37 USB20_N0

<35> USB3RN3 AY31 PERN1/USB3RN3 USB2N0 D37 USB20_N0 <34>
USB3RP3 USB20_P0 JUSB1(Right Side)
<35> USB3RP3 PERP1/USB3RP3 USB2P0 A38 USB20_N1 USB20_P0 <34>
BE32 USB2N1 C38 USB20_N1 <35>
P3: JUSB4 Left USB3TN3 USB20_P1 JUSB3(Left Side) PowerShare
<35> USB3TN3 BC32 PETN1/USB3TN3 USB2P1 A36 USB20_P1 <35>
USB3TP3 USB20_N2
<35> USB3TP3 PETP1/USB3TP3 USB2N2 C36 USB20_N2 <41>
USB20_P2 Caldera
AT31 USB2P2 A34 USB20_P2 <41>
USB20_N3
AR31 PERN2/USB3RN4 USB2N3 C34 USB20_P3 USB20_N3 <37>
PERP2/USB3RP4 USB2P3 B33 USB20_N4
USB20_P3 <37> ELC LED
BD33 USB2N4 D33 USB20_N4 <28>
USB20_P4 BT
BB33 PETN2/USB3TN4 USB2P4 F31 USB20_P4 <28>
USB20_N5
PETP2/USB3TP4 USB2N5 G31 USB20_N5 <25>
USB20_P5 Thuch sereen
USB2P5 K31 USB20_N6 USB20_P5 <25>
AW33 USB2N6 L31 USB20_N6 <25>
PCIE_PRX_GLANTX_N3 USB20_P6 Camera
<30> PCIE_PRX_GLANTX_N3 AY33 PERN_3 USB2P6 G29 USB20_P6 <25>
PCIE_PRX_GLANTX_P3 USB20_N7
<30> PCIE_PRX_GLANTX_P3 PERP_3 USB2N7 H29 USB20_N7 <34>
10/100/1G LAN USB20_P7 JUSB1(Right Side)
1 2 0.1U_0402_25V6K BE34 USB2P7 A32 USB20_P7 <34>
CH12 PCIE_PTX_GLANRX_N3_C USB20_N8
<30> PCIE_PTX_GLANRX_N3 1 2 0.1U_0402_25V6K PCIE_PTX_GLANRX_P3_C BC34 PETN_3 USB2N8 C32 USB20_P8 USB20_N8 <35>
CH13 JUSB4(Left Side)
<30> PCIE_PTX_GLANRX_P3 PETP_3 USB2P8 A30 USB20_P8 <35>
USB20_N9
AT33 USB2N9 C30 USB20_N9 <69>
PCIE_PRX_WLANTX_N4 USB20_P9 Touch PAD
<28> PCIE_PRX_WLANTX_N4 AR33 PERN_4 USB2P9 B29 USB20_P9 <69>
PCIE_PRX_WLANTX_P4
<28> PCIE_PRX_WLANTX_P4 PERP_4 USB2N10 D29
WLAN USB2P10
CH14 1 2 0.1U_0402_25V6K PCIE_PTX_WLANRX_N4_C BE36 A28
<28> PCIE_PTX_WLANRX_N4 1 2 0.1U_0402_25V6K PETN_4 USB2N11
C CH15 PCIE_PTX_WLANRX_P4_C BC36 C28 C
<28> PCIE_PTX_WLANRX_P4 PETP_4 USB2P11 G26
PCIe
PCIE_PRX_CARDTX_N5 AW36 USB2N12 F26
USB
<31> PCIE_PRX_CARDTX_N5 AV36 PERN_5 USB2P12 F24
PCIE_PRX_CARDTX_P5
<31> PCIE_PRX_CARDTX_P5 PERP_5 USB2N13 G24
CARD READER USB2P13
CH16 1 2 0.1U_0402_25V6K PCIE_PTX_CARDRX_N5_C BD37
<31> PCIE_PTX_CARDRX_N5 1 2 0.1U_0402_25V6K PETN_5
CH17 PCIE_PTX_CARDRX_P5_C BB37
<31> PCIE_PTX_CARDRX_P5 PETP_5 AR26 USB3RN1 USBRBIAS
AY38 USB3RN1 AP26 USB3RN1 <34>
USB3RP1
PERN_6 USB3RP1 USB3RP1 <34>
22.6_0402_1%
AW38 BE24 USB3TN1 P1: JUSB1 Right
PERP_6 USB3TN1 USB3TN1 <34>
1
BD23 USB3TP1
USB3TP1 USB3TP1 <34>
RH109
BC38 AW26 USB3RN2 On MB
BE38 PETN_6 USB3RN2 AV26 USB3RN2 <34>
USB3RP2
PETP_6 USB3RP2 BD25 USB3RP2 <34>
USB3TN2 P2: JUSB2 Right
AT40 USB3TN2 BC24 USB3TP2 USB3TN2 <34>
2
AT39 PERN_7 USB3TP2 AW29 USB3TP2 <34>
USB3RN5
PERP_7 USB3RN5 AV29 USB3RN5 <41>
USB3RP5
BE40 USB3RP5 BE26 USB3RP5 <41>
USB3TN5 P5: Calder
BC40 PETN_7 USB3TN5 BC26 USB3TN5 <41>
USB3TP5
PETP_7 USB3TP5 AR29 USB3RN6 USB3TP5 <41>
USB3RN6 USB3RN6 <35> CAD NOTE:
AN38 AP29 USB3RP6 Route single-end 50-ohms and max 500-mils length.
AN39 PERN_8 USB3RP6 BD27 USB3RP6 <35>
USB3TN6 P6: JUSB3 Left Avoid routing next to clock pins or under stitching capacitors.
PERP_8 USB3TN6 BE28 USB3TN6 <35>
USB3TP6
BD42 USB3TP6 USB3TP6 <35> Recommended minimum spacing to other signal traces is 15 mils.
BD41 PETN_8 K24 USBRBIAS
PETP_8 USBRBIAS# K26
USBRBIAS
2 @ 1 PCH_PCIE_IREF BE30 M33 PAD~D T89 @
+1.5VS PCIE_IREF TP24
RH110 0_0402_5% L33 PAD~D T90 @
TP23 +3V_PCH
@ T91 PAD~D BC30 P3 USB_OC0#
TP11 OC0#/GPIO59 V1 USB_OC1# USB_OC0# <34>
RPH6
OC1#/GPIO40 U2 USB_OC2# USB_OC1# <34> 4 5
USB_OC4#
BB29 OC2#/GPIO41 P1 USB_OC3# USB_OC2# <32> 3 6
@ T92 PAD~D USB_OC7#
TP6 OC3#/GPIO42 M3 USB_OC4# USB_OC6# 2 7
OC4#/GPIO43 T1 USB_OC5# USB_OC4# <32> 1 8
USB_OC3#
1 2 PCH_PCIE_RCOMP BD29 OC5#/GPIO9 N2 USB_OC6#
+1.5VS PCIE_RCOMP OC6#/GPIO10
RH111 7.5K_0402_1% M1 USB_OC7# 10K_0804_8P4R_5%
OC7#/GPIO14
RPH7
B B
LYNXPOINT_BGA695 9 OF 11 5 USB_OC0# 4 5
USB_OC1# 3 6
USB_OC2# 2 7
USB_OC5# 1 8
採採採採
10K_0804_8P4R_5%
SD302100280 Chnage SD309100280 2/25
A A

PCH (5/9) PCIE,USB
5 4 3 2 1
5 4 3 2 1
+3VS
1 2 PCH_GPIO0
RH113 10K_0402_5%~D
1 2 PCH_GPIO1
RH115 10K_0402_5%~D
D D
1 2 PCH_GPIO6
RH116 10K_0402_5%~D +3VS
2 1 STP_PCI#
RH117 10K_0402_5%~D GATEA20 2 1
LPT_PCH_M_EDS
1 2 PCH_GPIO22 UH1F 10K_0402_5%~D RH112
RH118 10K_0402_5%~D KB_RST# 2 1
1 2 PCH_GPIO39 PCH_GPIO0 AT8 10K_0402_5%~D RH114
RH119 10K_0402_5%~D BMBUSY#/GPIO0
1 2 PCH_GPIO70 PCH_GPIO1 F13
RH120 10K_0402_5%~D TACH1/GPIO1
1 2 PCH_GPIO71 PCH_GPIO6 A14
RH121 10K_0402_5%~D TACH2/GPIO6
CPU/Misc
1 2 PCH_GPIO68 EC_SCI# G15
<43> EC_SCI# TACH3/GPIO7
RH151 10K_0402_5%~D
1 2 TPM_PIRQ# EC_SMI# Y1
<43> EC_SMI# GPIO8
RH154 for TPM 10K_0402_5%~D
K13
LAN_PHY_PWR_CTRL/GPIO12 AN10 GATEA20
GPU_GC6_FB_EN AB11 TP14
<43,46> GPU_GC6_FB_EN GPIO15 AY1 H_PECI_R
AN2 PECI T81
PCH_GPIO16
<29> PCH_GPIO16 SATA4GP/GPIO16 AT6 KB_RST#
C14 GPIO RCIN# KB_RST# <43>
TPM_PIRQ#
+3V_PCH To TPM <44> TPM_PIRQ# TACH0/GPIO17
PROCPWRGD
AV3 H_CPUPWRGD
H_CPUPWRGD <8>
PCH_GPIO22 BB4
2 1 HDD_DET# SCLOCK/GPIO22 AV1 PCH_THRMTRIP#_R_R 1 2
Y10 THRMTRIP# H_THERMTRIP# <8>
RH123 10K_0402_5% RH124 390_0402_5%
<46,49,63> DGPU_PWR_EN GPIO24 AU4 CPU_PLTRST#
2 1 PCH_GPIO35 WAKE_PCH# R11 PLTRST_PROC# CPU_PLTRST# <8>
<43> WAKE_PCH# GPIO27 N10
RH126 10K_0402_5%
GC6_EVENT# AD11 VSS
<43,46> GC6_EVENT# GPIO28
STP_PCI# AN6
GPIO34
PCH_GPIO35 AP1
GPIO35/NMI#
+PCH_VCCDSW3_3 PCH_GPIO36 AT3
SATA2GP/GPIO36
2 1 WAKE_PCH# PCH_GPIO37 AK1
C RH156 10K_0402_5%~D SATA3GP/GPIO37 C
DGPU_PRSNT# AT7
SLOAD/GPIO38
PCH_GPIO39 AM3 A2
SDATAOUT0/GPIO39 VSS A41
FFS_INT2 AN4 VSS A43
<36> FFS_INT2 SDATAOUT1/GPIO48 VSS A44
PCH_GPIO49 AK3 VSS B1
<29> PCH_GPIO49 SATA5GP/GPIO49 VSS B2
HDD_DET# U12 VSS B44
<36> HDD_DET# GPIO57 VSS B45
PCH_GPIO68 C16 VSS BA1
TACH4/GPIO68 VSS BC1
KB_DET# D13 VSS BD1
<39> KB_DET# TACH5/GPIO69 VSS BD2
PCH_GPIO70 G13 VSS BD44
TACH6/GPIO70 VSS BD45
PCH_GPIO71 H15 VSS BE2
TACH7/GPIO71 VSS BE3
VSS D1
BE41 VSS E1
BE5 VSS NCTF VSS E45
C45 VSS VSS A4
A5 VSS VSS
VSS
+3VS
1 2 PCH_GPIO49
RH157 10K_0402_5%~D
1 2 PCH_GPIO16
RH130 10K_0402_5%~D
2 1 KB_DET#
RH131 10K_0402_5%~D
For BIOS setting dGPU present
* LOW - dGPU exist
2 1 PCH_GPIO16
B B
@ RH132 10K_0402_5%~D +3VS
2 1 KB_DET# @
@ RH133 10K_0402_5%~D 1 2 DGPU_PRSNT#
2 1 PCH_GPIO49 RH134 10K_0402_5%~D
@ RH158 10K_0402_5%~D 1 2 DGPU_PRSNT#
RH135 10K_0402_5%~D
+3VS
Config GPIO16,49 2 1 PCH_GPIO36
RH136 1K_0402_1%~D
1 2 PCH_GPIO37
USB X4,PCIEX8,SATAX6 11 @ RH137 200K_0402_5%
2 1 PCH_GPIO36
USB X6,PCIEX8,SATAX4 01 @ RH138 10K_0402_5%~D
2 1 PCH_GPIO37
RH139 10K_0402_5%~D
SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.

WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.
A A
Same with 534345_PCH_LPT_9

PCH (6/9) GPIO,MISC,NTFC
5 4 3 2 1
5 4 3 2 1
D D
PCH Power Rail Table
Voltage Rail Voltage S0 Iccmax Current (A)
VCC 1.05V 1.29 A

LPT_PCH_M_EDS
UH1G
C +1.05V_+1.5V_RUN VCCIO 1.05V 3.629 A C
+1.05VS P45
VCCADAC1_5
10U_0603_6.3V6M~D
AA24 P43 VCCADAC1_5 1.5V 0.070 A
VCC CRT DAC VSS
10U_0603_6.3V6M~D
AA26 +1.05VS
VCC
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 AD20 M31 1
VCC VCCADACBG3_3
1U_0402_6.3V6K~D
@ CH23
AD22 VCCADAC3_3 3.3V 0.0133 A
VCC
CH18
CH21
CH19
CH20
AD24 1 @
AD26 VCC BB44
2 2 2 2 VCC VCCVRM +3VS 2
CH22
AD28 VCCCLK 1.05V 0.306 A
AE18 VCC FDI
AN34
AE20 VCC VCCIO 2
AE22 VCC AN35
VCC VCCIO VCCCLK3_3 3.3V 0.055 A
+3V_PCH
0.1U_0402_10V7K~D
AE24
AE26 VCC R30
VCC HVCMOS VCC3_3_R30 1
AG18 R32 VCCVRM 1.5V 0.179 A
VCC VCC3_3_R32
0.1U_0402_10V7K~D
CH24
AG20
AG22 VCC Y12
VCC DCPSUS1 1 2
AG24 VCC3_3 3.3V 0.133 A
VCC
CH25
Y26 AJ30
VCC VCCSUS3_3
Core
AJ32
VCCSUS3_3 2
VCCASW 1.05V 0.67 A
+1.05V AJ26 +1.05V_+1.5V_RUN
+PCH_VCCDSW U14 USB3 DCPSUS3 AJ28
AA18 DCPSUSBYP DCPSUS3 AK20
VCCASW VCCIO +1.05VS VCCSUSHDA 3.3V 0.01 A
U18 AK26
VCCASW VCCVRM
22U_0805_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+1.05V_+1.5V_RUN
10U_0603_6.3V6M~D
U20 AK28 1
VCCASW VCCVRM
@ CH29
1 1 1 U22 VCCSPI 3.3V 0.022 A
U24 VCCASW BE22
VCCASW VCCVRM
CH26
CH27
CH28
V18 PCIe/DMI
VCCASW +1.05V_+1.5V_RUN 2
10U_0603_6.3V6M~D
V20 AK18 1 VCCSUS3_3 3.3V 0.261 A
2 2 2 VCCASW VCCIO +1.05VS
@ CH30
V22
V24 VCCASW AN11
VCCASW VCCVRM
10U_0603_6.3V6M~D
Y18 VCCDSW3_3 3.3V 0.015 A
Y20 VCCASW SATA AK22 2
VCCASW VCCIO 1
@ CH31
Y22 +1.05VS
VCCASW AM18
VCCIO V_PROC_IO 1.05V 0.004 A
AM20
VCCIO AM22 2
VCCMPHY VCCIO AP22
B VCCIO B
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
AR22 1 1 1 1 1
VCCIO AT22
VCCIO
CH32
CH33
CH34
CH35
CH36
LYNXPOINT_BGA695 7 OF 11 5 2 2 2 2 2
1 2 +PCH_VCCDSW +1.5VS +1.05V_+1.5V_RUN

RH140 5.11_0402_1%~D
+PCH_VCCDSW_R
RH153 0_0402_5%
1 @ 2
1U_0402_6.3V6K~D
1
CH37
A A

PCH (7/9) Power
5 4 3 2 1
5 4 3 2 1
D D
+3V_PCH +PCH_VCCDSW3_3
0.1U_0402_10V7K~D
@
1 2 1
LPT_PCH_M_EDS +3V_PCH
CH41
UH1H 0_0402_5%~D RH145
0.1U_0402_10V7K~D
2 1
+3V_PCH +3VALW
0_0402_5%~D RH141
2
1
CH38
R24 R20
R26 VCCSUS3_3 VCCSUS3_3 R22
0.1U_0402_10V7K~D R28 VCCSUS3_3 VCCSUS3_3
+1.05VS U26 VCCSUS3_3 GPIO/LPC 2
1 VCCSUS3_3 A16 +PCH_VCCDSW3_3
VCCDSW3_3
CH39
M24 +3VS
VSS AA14 +PCH_VCCSST 1 2
2 DCPSST
0.1U_0402_10V7K~D
+3VS U35 CH42 0.1U_0402_10V7K~D
VCCUSBPLL AE14
1
USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3
CH40
0.1U_0402_10V7K~D
AG14
VCC3_3 +3V_PCH
0.1U_0402_10V7K~D
U30 1
2 +1.05VS V28 VCCIO
1 VCCIO
CH43
CH44
V30 U36
VCCIO VCCIO +1.05VS
Y30
VCCIO +3V_PCH 2
2
0.1U_0402_10V7K~D
+1.05V_+1.5V_RUN +PCH_USB_DCPSUS2 Y35 Azalia
DCPSUS2
1U_0402_6.3V6K~D
1 A26 1
AF34 VCCSUSHDA
VCCVRM
CH45
CH46
10U_0603_6.3V6M~D
+RTC_CELL
1U_0402_6.3V6K~D
1 +PCH_VCC AP45 K8 1
2 VCC VCCSUS3_3 2
CH47
CH48
+PCH_VCCCLK
Y32 A6
VCCCLK VCCRTC
2 RTC 2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
M29 P14 +PCH_DCPRTC CH49
+PCH_VCCCLK3_3 VCCCLK3_3 DCPRTC P16 1 2 1 1 1
L29 DCPRTC
VCCCLK3_3
CH50
CH51
CH52
0.1U_0402_10V7K~D
L26 AJ12 +PCH_VPROC
C M26 VCCCLK3_3 V_PROC_IO AJ14 +3V_PCH 2 2 2 C
CPU
VCCCLK3_3 V_PROC_IO
+1.05V U32
VCCCLK3_3
1U_0402_6.3V6K~D
ICC
V32 AD12
1 2 +PCH_USB_DCPSUS2 VCCCLK3_3 SPI VCCSPI
@ RH142 0_0402_5%~D AD34 1
+PCH_VCCCLK VCCCLK
1U_0402_6.3V6K~D
P18 +PCH_VCCCFUSE
VCC
CH54
1 AA30 P20
VCCCLK VCC
@ CH53
AA32
VCCCLK L17 2
Fuse VCCASW +1.05V
AD35
2 VCCCLK R18
AG30 VCCASW +1.05VS
AG32 VCCCLK RH146 0_0805_5%
VCCCLK AW40 +PCH_VPROC 1 @ 2
VCCVRM +1.5VS
AD36
VCCCLK +3VS
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
AK30
AE30 VCC3_3
Thermal 1 1 1
AE32 VCCCLK AK32
VCCCLK VCC3_3
0.1U_0402_10V7K~D
CH55
CH56
CH57
1 2 2 2
CH58
2
+1.05VS +PCH_VCCCLK
RH147
1 @ 2 0_0805_5% RH148
+PCH_VCCCFUSE 1 @ 2
+3VS
0_0805_5%
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2 1
+1.05VS
@ CH59
1 1 @ 1 1 1 1 1 0_0805_5%~D RH143 @
CH60
CH61
CH62
CH63
CH64
CH65
B 2 2 2 2 2 2 2 B
Place near pin AP45 Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36 Place near pin AG30,AG32,AE30,AE32
+3VS +PCH_VCCCLK3_3
RH149
1 @ 2
0_0805_5% +1.05VS +1.05VS_VCC

1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 LH1 RH150
CH66
CH67
CH68
CH69
1 2 1 @ 2 +PCH_VCC
4.7UH_LQM18FN4R7M00D_20%~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
0_0603_5%
2 2 2 2
1 1
CH70
CH71
2 2
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
Place near pin AP45
A A

PCH (8/9) Power
5 4 3 2 1
5 4 3 2 1
D D
UH1J LPT_PCH_M_EDS UH1K LPT_PCH_M_EDS
AL34 K39 AA16 B19

AL38 VSS VSS L2 AA20 VSS VSS B23
AL8 VSS VSS L44 AA22 VSS VSS B27
AM14 VSS VSS M17 AA28 VSS VSS B31
AM24 VSS VSS M22 AA4 VSS VSS B35
AM26 VSS VSS N12 AB12 VSS VSS B39
AM28 VSS VSS N35 AB34 VSS VSS B7
AM30 VSS VSS N39 AB38 VSS VSS BA40
AM32 VSS VSS N6 AB8 VSS VSS BD11
AM16 VSS VSS P22 AC2 VSS VSS BD15
AN36 VSS VSS P24 AC44 VSS VSS BD19
AN40 VSS VSS P26 AD14 VSS VSS AY36
AN42 VSS VSS P28 AD16 VSS VSS AT43
AN8 VSS VSS P30 AD18 VSS VSS BD31
AP13 VSS VSS P32 AD30 VSS VSS BD35
C AP24 VSS VSS R12 AD32 VSS VSS BD39 C
AP31 VSS VSS R14 AD40 VSS VSS BD7
AP43 VSS VSS R16 AD6 VSS VSS D25
AR2 VSS VSS R2 AD8 VSS VSS AV7
AK16 VSS VSS R34 AE16 VSS VSS F15
AT10 VSS VSS R38 AE28 VSS VSS F20
AT15 VSS VSS R44 AF38 VSS VSS F29
AT17 VSS VSS R8 AF8 VSS VSS F33
AT20 VSS VSS T43 AG16 VSS VSS BC16
AT26 VSS VSS U10 AG2 VSS VSS D4
AT29 VSS VSS U16 AG26 VSS VSS G2
D42 VSS VSS U38 AJ16 VSS VSS G8
AV13 VSS VSS U42 AJ18 VSS VSS H10
AV22 VSS VSS U6 AJ20 VSS VSS H13
AV24 VSS VSS V14 AJ22 VSS VSS H17
BB25 VSS VSS V43 AJ38 VSS VSS H26
AV40 VSS VSS W2 AJ6 VSS VSS H31
AV6 VSS VSS W44 AJ8 VSS VSS H36
AW2 VSS VSS Y14 AK14 VSS VSS H40
F43 VSS VSS Y16 AK24 VSS VSS H7
AY10 VSS VSS Y24 AK43 VSS VSS K10
AY15 VSS VSS Y28 AK45 VSS VSS K15
AY20 VSS VSS Y34 AL12 VSS VSS K20
AY26 VSS VSS Y36 AL2 VSS VSS K29
AY29 VSS VSS Y40 BC22 VSS VSS K33
AY7 VSS VSS Y8 BB42 VSS VSS BC28
B11 VSS VSS VSS VSS
B15 VSS
B VSS B
A A

PCH (9/9) Power
5 4 3 2 1
A B C D E
eDP connector
JEDP1
+3VS
LCD power control +LCDVDD +LCDVDD_CONN
<10>
<10>
CPU_EDP_TX0P
CPU_EDP_TX0N
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
1 CV1
1 CV2
EDP_TX0_C
EDP_TX0#_C
1
2
3
1
2 G1
41
42
0.1U_0402_16V7K 2 1 CV3 EDP_TX1_C 4 3 G2 43
<10> CPU_EDP_TX1P 2 1 CV4 EDP_TX1#_C 5 4 G3 44
UV17 0.1U_0402_16V7K
W=60mils 5
IN OUT
1 1 2 W=60mils <43> BKOFF#
2 1 DISPOFF# <10> CPU_EDP_TX1N 6 5
6
G4
FBMA-L11-201209-221LMA30T_0805 0.1U_0402_16V7K 2 1 CV8 EDP_TX2_C 7
<10> CPU_EDP_TX2P 7
1
1 2 LV8 DV1 0.1U_0402_16V7K 2 1 CV6 EDP_TX2#_C 8
GND <10> CPU_EDP_TX2N 8
0.1U_0402_10V7K
CV9
4.7U_0805_10V4Z
CV10
1 RB751V-40_SOD323-2 9 1
CV5 4 31 2 10K_0402_5% 0.1U_0402_16V7K 2 1 CV7 EDP_TX3_C 10 9
EN OC +3VS 1 1 <10> CPU_EDP_TX3P 10
4.7U_0805_10V4Z RV45 10K_0402_5% RV1 0.1U_0402_16V7K 2 1 CV11 EDP_TX3#_C 11
2 <10> CPU_EDP_TX3N 12 11
SY6288C20AAC_SOT23-5
2
0.1U_0402_16V7K 2 1 CV12 EDP_AUX_C 13 12
2 2 <10> CPU_EDP_AUX 2 1 CV13 EDP_AUX#_C 14 13
0.1U_0402_16V7K
<10> CPU_EDP_AUX# 15 14
CPU_EDP_HPD 16 15
<10> CPU_EDP_HPD 17 16
0_0402_5% +VDD_TOUCH
RV3 1 @ 2 ENVDD_R CE_EN_R 18 17
<17> PCH_ENVDD DBC_EN_R 19 18
RV5
2 1 0_0402_5% 20 19
<43> EC_ENVDD +3VS +LCDVDD_CONN WCM-2012HS-900T_4P TS_EN 1 2 TS_EN_R 21 20
RV4 @ 0_0402_5%
4 3 USB20_CAM_P6_R TS_INT# 22 21
<20> USB20_P6 4 3 <17> TS_INT# TS_RST# 23 22
<17> TS_RST# 23
10P_0402_50V8J
10P_0402_50V8J
RV13 24
W=60mils 24
1
@RF@
@RF@
1 2 USB20_CAM_N6_R 0_0402_5% 25
<20> USB20_N6 1 2 +LCDVDD_CONN 25
CV372
CV373
MIC_CLK 1 2 26
26
1
LV2
@RF@
EMI@ USB20_CAM_P6_R 27
2
EMI@ CV374 USB20_CAM_N6_R 28 27
10P_0402_50V8J 29 28
+3VS_CAM
2
1 2 MIC_CLK 30 29
<32> MIC_CLK MIC_GND 31 30
RV6 0_0402_5%
@EMI@ MIC_DATA 32 31
1 2 <32> MIC_DATA LCD_TEST 33 32
<43> LCD_TEST 33
RV7 0_0402_5% USB20_N5 34
@EMI@ USB20_P5 35 34
36 35
<10,17> PCH_INV_PWM 37 36
DISPOFF#
USB20_N5 38 37
<20> USB20_N5 W=60mils 38
1
39
+INV_PWR_SRC 39
USB20_P5 RV8 40
<20> USB20_P5 40
10P_0402_50V8J
2 100K_0402_5% 2
1
@RF@
ACES_50473-0400M-P01
CV375
CONN@
LCD backlight power control
2
@ESD@
DV2
Laverage Echo13
PESD5V0U2BT_SOT23-3
QV1
SI3457CDV-T1-GE3_TSOP6
W=60mils
1
B+ 6 +3VS +LCDVDD_CONN
+INV_PWR_SRC
5
2
W=60mils
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0805_10V6K
4 1
S
1 1 1 1
1000P_0402_50V7K
CV15
100K_0402_5%
RV9
CV16
CV17
CV18
1
CV14 +VDD_TOUCH
G
1
0.1U_0603_25V7K
3
2 2 2 2
RV10 1 2 100K_0402_5% TS_INT#
2
2
PWR_SRC_ON RV11 1 @ 2 100K_0402_5% TS_RST#

Place close to JEDP
1
RV12
100K_0402_5%
2
3 3
1
D
2 QV2
<43> EN_INVPWR
G 2N7002KW_SOT323-3
S
3
Touch screen panel power control

+3VS
+VDD_TOUCH
UV2
Webcam power control 5
IN OUT
1 1 2
FBMA-L11-201209-221LMA30T_0805
0.1U_0402_10V7K
CV19
4.7U_0805_10V4Z
CV20
1 2 LV1 CE_EN_R
GND
1 1
CV21 4 3 1 2 DBC_EN 1 @ 2 DBC_EN_R
+3VS +3VS_CAM EN OC +3VS <43> DBC_EN
4.7U_0805_10V4Z RV2 10K_0402_5%
2 RV46 0_0402_5%
1
SY6288C20AAC_SOT23-5 2 2
RV47 0_0603_5% @ @
1 @ 2 RV36 RV14
0_0402_5% 0_0402_5%
2
4 <43> TS_EN Change to 6288C ( High Enable) 4

LCD Conn/Cam, Touch
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B751P 0.1
A B C D E
A B C D E
1 1
+5VS
+5VS
+3VS
10P_0402_50V8J
1
@RF@
CV376
1 DISP_DAT_AUXN_CONN RV15 1 2 100K_0402_5%

2
@ CV23 DISP_CLK_AUXP_CONN RV16 1 2 100K_0402_5%

0.1U_0402_10V6K
2 UV3
16
Vcc 4 DISP_CLK_AUXP_CONN
0.1U_0402_10V7K 2 1 CV24 PCH_DP_AUXP_C 2 1A 7 DISP_DAT_AUXN_CONN
<17> PCH_DPC_AUX 3 1B1 2A 9
<17> PCH_DPC_CLK 2 1 CV25 PCH_DP_AUXN_C 5 1B2 3A 12
0.1U_0402_10V7K
<17> PCH_DPC_AUX# 6 2B1 4A
<17> PCH_DPC_DAT 11 2B2 15
10 3B1 OE# 1 DP_CBL_DET
14 3B2 S
13 4B1 8
4B2 GND
1
SN74CBT3257CPWR_TSSOP16 RV17
1M_0402_5%
2 2
2
1
GND
2
<17> PCH_mDP_HPD HPD
CV26 1 2 0.1U_0402_10V7K~D mDP_LANE_P0_C 3
<10> CPU_mDP_P0 DP_CBL_DET 4
LANE0_P
<17> DP_CBL_DET CONFIG1
CV27 1 2 0.1U_0402_10V7K~D mDP_LANE_N0_C 5
<10> CPU_mDP_N0 1 2 5.1M_0402_5% 6
LANE0_N
RV18 DISP_CEC
CONFIG2
7
GND
8
<10> CPU_mDP_P1
CV28
CV29
1
1
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
mDP_LANE_P1_C
mDP_LANE_P3_C
9
10
LANE1_P
GND
Same with ECHO13.
<10>
<10>
CPU_mDP_P3
CPU_mDP_N1
CV30
CV31
1
1
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
mDP_LANE_N1_C
mDP_LANE_N3_C
11
12
LANE1_N
LANE3_P
Symbol check OK. 2/25
<10> CPU_mDP_N3 13 LANE3_N
GND
14
GND
CV32 1 2 0.1U_0402_10V7K~D mDP_LANE_P2_C 15
<10> CPU_mDP_P2 16
LANE2_P
DISP_CLK_AUXP_CONN
AUX_CHP
+3VS_DP CV33 1 2 0.1U_0402_10V7K~D mDP_LANE_N2_C 17
UV18 <10> CPU_mDP_N2 DISP_DAT_AUXN_CONN 18
LANE2_N
AUX_CHN
19
RETURN
3 20
OUT DP_PWR
1 1
10U_0603_6.3V6M~D
CV34
0.1U_0402_16V7K~D
CV35
10P_0402_50V8J
1 21
+3VS IN
1
@RF@
22
CV377
2 23
GND
GND 2 2 24
2
AP2330W-7_SC59-3
JDP1
FOX_3V111T1-R24011-7H
3 3
CONN@
4 4

3D Camera
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B751P 0.1
A B C D E
5 4 3 2 1
+3VS
PU 10K.
RV43 10K_0402_5%
2 1 PCH_DPB_HDMI_DAT
2 1 PCH_DPB_HDMI_CLK
RV44 10K_0402_5%
+HDMI_5V_OUT
+3VS
+3VS
Place close to JHDMI

1 2
@EMI@
W=60mils
+3VS
0.1U_0402_16V7K
CV36
0.1U_0402_16V7K
CV40
1 1 RV19 0_0402_5%~D
1
D D
TMDS_TXCN 1 2 TMDS_L_TXCN RV20
1 2 10K_0402_5%
2 2
UV4 TMDS_TXCP 4 3 TMDS_L_TXCP JHDMI1
2
WCM-2012HS-900T_4P 4 3 HDMI_HPLUG 19
33 LV3 EMI@ 18 HP_DET
CV37 2 1 0.1U_0402_10V7K TMDS_TX2P_C 1 EPAD 32 PCH_DPB_HDMI_DAT 1 2 17 +5V
<10> CPU_HDMI_P2 IN_D2P SDA_SRC PCH_DPB_HDMI_DAT <17> DDC/CEC_GND
CV38 2 1 0.1U_0402_10V7K TMDS_TX2N_C 2 31 PCH_DPB_HDMI_CLK RV21 @EMI@ 0_0402_5%~D CPU_DPB_CTRLDAT_R 16
<10> CPU_HDMI_N2 3 IN_D2N SCL_SRC 30 PCH_DPB_HDMI_CLK <17> 15 SDA
HDMI_HPLUG_R CPU_DPB_CTRLCLK_R
CV39 2 1 0.1U_0402_10V7K TMDS_TX1P_C 4 HPD_SRC VDDIO 29 CPU_DPB_CTRLDAT_R 14 SCL
<10> CPU_HDMI_P1 2 1 TMDS_TX1N_C 5 IN_D1P SDA_SNK 28 CPU_DPB_CTRLCLK_R 1 2 13 Reserved
CV41 0.1U_0402_10V7K @EMI@
<10> CPU_HDMI_N1 2 1 TMDS_TX0P_C 6 IN_D1N SCL_SNK 27 TMDS_TX2P TMDS_L_TXCN 12 CEC 20
CV42 0.1U_0402_10V7K RV22 0_0402_5%~D
<10> CPU_HDMI_P0 2 1 7 IN_D0P OUT_D2P 26 11 CK- GND 21
CV43 0.1U_0402_10V7K TMDS_TX0N_C TMDS_TX2N
<10> CPU_HDMI_N0 8 IN_D0N OUT_D2N 25 HDMI_HPLUG TMDS_TX0N 1 2 TMDS_L_TX0N TMDS_L_TXCP 10 CK_shield GND 22
CV44 2 1 0.1U_0402_10V7K TMDS_TXCP_C 9 DCIN_EN HPD_SNK 24 TMDS_TX1P 1 2 TMDS_L_TX0N 9 CK+ GND 23
<10> CPU_HDMI_P3 IN_CKP OUT_D1P D0- GND
CV45 2 1 0.1U_0402_10V7K TMDS_TXCN_C 10 23 TMDS_TX1N 8
<10> CPU_HDMI_N3 11 IN_CKN OUT_D1N 22 TMDS_TX0P TMDS_TX0P 4 3 TMDS_L_TX0P TMDS_L_TX0P 7 D0_shield
HDMI_HPLUG_R RV539 1 @ 2 0_0402_5% PD# 12 VDD OUT_D0P 21 TMDS_TX0N WCM-2012HS-900T_4P 4 3 TMDS_L_TX1N 6 D0+
RV23 1 2 4.7K_0201_5% 13 PD# OUT_D0N 20 LV4 EMI@ 5 D1-
+3VS @
EQ CFG CFG Reserved D1_shield
14 19 TMDS_TXCP 1 2 TMDS_L_TX1P 4
RV25 1 @ 2 4.7K_0201_5% 15 GND OUT_CKP 18 TMDS_TXCN RV24 @EMI@ 0_0402_5%~D TMDS_L_TX2N 3 D1+
+3VS PRE OUT_CKN D2-
16 17 2
REXT CEXT TMDS_L_TX2P 1 D2_shield
D2+
2
0.1U_0402_16V7K
CV46
1 1 2
@EMI@
RV42 RV41 RV27 RV26 0_0402_5%~D FOX_QJ111A1-R240HA-8H
0_0402_5%~D
0_0402_5%~D
5.9K_0402_1%
@ @ PS8203TQFN32GTR-A3_TQFN32 CONN@
TMDS_TX1N 1 2 TMDS_L_TX1N
2 1 2
Change PN to DC232000B00 (ECHO13)
1
TMDS_TX1P 4 3 TMDS_L_TX1P
WCM-2012HS-900T_4P 4 3
C LV5 EMI@ C
1 2
RV28 @EMI@ 0_0402_5%~D
Pin13 EQ(Internal pull Low) 1 2

@EMI@
Pin15 PER(Internal pull Low) RV29 0_0402_5%~D +HDMI_5V_OUT
12.4dB L LV6 EMI@
0 dB, No pre-emphasis L(default) TMDS_TX2P 4 3 TMDS_L_TX2P UV5
4.3dB H 4 3 W=60mils
2.5 dB, pre-emphasis H 3
8.6dB M TMDS_TX2N 1 2 TMDS_L_TX2N W=60mils OUT
WCM-2012HS-900T_4P 1 2
+5VS
1
IN
0.1U_0402_16V7K
1 2 2 1
RV30 @EMI@ 0_0402_5%~D GND
CV47
AP2330W-7_SC59-3 2
PCH_DPB_HDMI_CLK to PS8203 +5VS

No need level shift.
B
+3VS
ROYALTY HDMI W/LOGO B
CPN:RO0000002HM
2
RV31 RV32
2.2K_0402_5% 2.2K_0402_5% 46@ ROYALTY HDMI W/LOGO
Part Number Description
QV3B
1
1
2
@ DMN66D0LDW-7_SOT363-6 RO0000002HM HDMI W/Logo:RO0000002HM

G
PCH_DPB_HDMI_CLK 1 6 CPU_DPB_CTRLCLK_R
S
D
5
@
G
PCH_DPB_HDMI_DAT 4 3 CPU_DPB_CTRLDAT_R
S
QV3A
+3VS
1
C
QV4 2 1 2 HDMI_HPLUG_R
MMBT3904_NL_SOT23-3 B
E RV33 1
3
150K_0402_5%
<17> PCH_HDMI_HPD
CV56
1
220P_0402_50V8J
2
RV34
100K_0402_5%
A A
2
HDMI LS & Conn.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B751P 0.1
5 4 3 2 1
5 4 3 2 1
+3VS +5VALW
D D
1
RN25 RN26 RN27
2
100K_0402_5% 100K_0402_5% 100K_0402_5%
G
2
2
WLAN_LED# 3 1 WLES ON/OFF LED#
WLES ON/OFF LED# <38>
D
QN5
2
2N7002K_SOT23-3
G
NGFF WL Con (E Key) BT_LED# 3 1
D
QN4
+3VS_WLAN_NGFF 2N7002K_SOT23-3
JWLAN1
1 2
USB20_P4 3 GND 3.3VAUX 4
<20> USB20_P4 5 USB_D+ 3.3VAUX 6
USB20_N4 BT_LED#
<20> USB20_N4 7 USB_D- LED1# 8
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16 WLAN_LED#
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21
23
SDO_DAT3
SDIO_WAKE#
SDIO_RESET#
UART_WAKE#
UART_RX
22
For EC to detect
C
debug card insert. C
32 1 2
33 UART_TX 34
35 GND UART_CTS 36 RM31
<20> PCIE_PTX_WLANRX_P4 37 PETP0 UART_RTS 38 100K_0402_5%
<20> PCIE_PTX_WLANRX_N4 39 PETN0 RESERVED 40 EC_TX <43> +3VS_WLAN_NGFF +3VS
41 GND RESERVED 42 EC_RX <43>
<20> PCIE_PRX_WLANTX_P4 43 PERP0 RESERVED 44
<20> PCIE_PRX_WLANTX_N4 PERN0 COEX3
1
45 46
CLK_PCIE_WLAN_R 47 GND COEX2 48 RN5
CLK_PCIE_WLAN#_R 49 REFCLKP0 COEX1 50 SUSCLK_R RM32 1 2 0_0402_5% 10K_0402_5%~D QN2
REFCLKN0 SUSCLK SUSCLK <17>
2
51 52 PLT_RST#_R RM33 1 2 0_0402_5% DII-DMN65D8LW-7~D
G
53 GND PERST0# 54 PLT_RST# <17,30,31,43,44>
WLANCLK_REQ# BT_OFF#
<18> WLANCLK_REQ# BT_OFF# <17>
2
WLAN_WAKE# 55 CLKEQ0# W_DISABLE2# 56 WL_OFF#_R 1 3
<43> WLAN_WAKE# PEWAKE0# W_DISABLE1# WL_OFF# <17>
57 58
S
59 GND I2C_DATA 60
61 RSRVD/PETP1 I2C_CLK 62
63 RSRVD/PETN1 ALERT 64
65 GND RESERVED 66
RM390_0402_5% 67 RSRVD/PERP1 RESERVED 68
1 2 69 RSRVD/PERN1 RESERVED 70
RF@ 71 GND RESERVED 72
73 RESERVED 3.3VAUX 74
75 RESERVED 3.3VAUX
LM2 @RF@ GND
1 2 CLK_PCIE_WLAN_R
<18> CLK_PCIE_WLAN 77 76
MTG77 MTG76
4 3 CLK_PCIE_WLAN#_R
<18> CLK_PCIE_WLAN#
LOTES_APCI0019-P009A
DLW21SN670HQ2L_4P CONN@
RM400_0402_5%
1 2
B RF@ B
+3VS_WLAN_NGFF
+3VALW
closed to pin 2, 4 closed to pin 64, 66
+3VS_WLAN_NGFF +3VS_WLAN_NGFF
2
2
2 AOAC@ @RF@
2
@RF@ AOAC@ CM10 CM25

CM24 CM11 100U_1206_6.3V6M 10P_0402_50V8J
1
1
22U_0603_6.3V6M~D
0.1U_0402_10V7K~D
22U_0603_6.3V6M~D
0.1U_0402_10V7K~D
1 1 1 1 10P_0402_50V8J 1U_0402_6.3V6K UM1

1
1
@RF@ @RF@ 1 5 1
IN OUT +3VALW
CM12
CM13
CM14
CM15
CM26 CM27
10P_0402_50V8J 10P_0402_50V8J 2
2
2 2 2 2 GND
4 3 2 1
<43> AOAC_WLAN EN OC
2
SY6288C20AAC_SOT23-5 AOAC@ @RF@
AOAC@ RM34 CM28
10K_0402_5% 10P_0402_50V8J
1
A A

WLAN
0.1
5 4 3 2 1
5 4 3 2 1
D
Port1,Gen3 +3VS
+3VS Port5,Gen3 +3VS +3VS
D
JSSD2
JSSD1 1 2
1 2 3 CONFIG_3 3.3VAUX 4
3 CONFIG_3 3.3VAUX 4 5 GND 3.3VAUX 6
GND 3.3VAUX NC NC
10U_0805_25V6K~D
1U_0402_6.3V6K~D
0.1U_0402_25V6K~D
1000P_0402_50V7K~D
10U_0805_25V6K~D
1U_0402_6.3V6K~D
0.1U_0402_25V6K~D
1000P_0402_50V7K~D
5 6 7 8
7 NC NC 8 9 NC NC 10
NC NC 1 1 1 1 NC DAS# 1 1 1 1
9 10 11
NC DAS# NC
CN19
CN20
CN21
CN22
CN23
CN24
CN25
CN26
11
NC
2 2 2 2 2 2 2 2
+3VS
+3VS 13 12
13 12 15 (P21)CONFIG_0 NC(P20) 14
15 (P21)CONFIG_0 NC(P20) 14 17 (P23)NC NC(P22) 16
(P23)NC NC(P22) (P25)NC NC(P24)
2
17 16 19 18
(P25)NC NC(P24) (P27)GND NC(P26)
2
19 18 21 20 RN29
21 (P27)GND NC(P26) 20 RN28 23 (P29)NC NC(P28) 22 10K_0402_5%
23 (P29)NC NC(P28) 22 10K_0402_5% 25 (P31)NC NC(P30) 24
25 (P31)NC NC(P30) 24 27 (P33)GND NC(P32) 26
1
27 (P33)GND NC(P32) 26 29 (P35)NC NC(P34) 28
1
29 (P35)NC NC(P34) 28 31 (P37)NC NC(P36) 30
31 (P37)NC NC(P36) 30 CN28 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P5_C 33 (P39)GND DEVSLP(P38) 32
(P39)GND DEVSLP(P38) <16> SATA_PRX_DTX_P5 (P41)PETn0/SATA-B+ NC(P40)
CN27 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P1_C 33 32 CN30 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N5_C 35 34
<16> SATA_PRX_DTX_P1 (P41)PETn0/SATA-B+ NC(P40) <16> SATA_PRX_DTX_N5 (P43)PETp0/SATA-B- NC(P42)
2
CN29 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N1_C 35 34 37 36
<16> SATA_PRX_DTX_N1 (P43)PETp0/SATA-B- NC(P42) (P45)GND NC(P44)
2
37 36 CN32 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N5_C 39 38 RN30 @
(P45)GND NC(P44) <16> SATA_PTX_DRX_N5 (P47)PERn0/SATA-A- NC(P46)
CN31 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N1_C 39 38 RN31 @ CN34 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P5_C 41 40 10K_0402_5%
<16> SATA_PTX_DRX_N1 (P47)PERn0/SATA-A- NC(P46) <16> SATA_PTX_DRX_P5 (P49)PERp0/SATA-A+ NC(P48)
CN33 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P1_C 41 40 10K_0402_5% 43 42
<16> SATA_PTX_DRX_P1 43 (P49)PERp0/SATA-A+ NC(P48) 42 45 (P51)GND NC(P50) 44
1
45 (P51)GND NC(P50) 44 47 (P53)NC NC(P52) 46
1
47 (P53)NC NC(P52) 46 49 (P55)NC NC(P54) 48
49 (P55)NC NC(P54) 48 51 (P57)GND MFG1(P56) 50
51 (P57)GND MFG1(P56) 50 53 (P59)KEY MFG2(P58) 52
53 (P59)KEY MFG2(P58) 52 55 (P61)KEY KEY(P60) 54
55 (P61)KEY KEY(P60) 54 57 (P63)KEY KEY(P62) 56
57 (P63)KEY KEY(P62) 56 SATA Port5 / PCIe Port2 59 (P65)KEY KEY(P64) 58 +3VS
59 (P65)KEY KEY(P64) 58 +3VS PCH_GPIO49 61 (P67)NC KEY(P66) 60
61 (P67)NC KEY(P66) 60 <21> PCH_GPIO49 63 (P69)CONFIG_1 SUSCLK(P68) 62
C (P69)CONFIG_1 SUSCLK(P68) (P71)GND 3.3VAUX(P70) C
63 62 65 64
65 (P71)GND 3.3VAUX(P70) 64 67 (P73)GND 3.3VAUX(P72) 66
67 (P73)GND 3.3VAUX(P72) 66 69 (P75)CONFIG_2 3.3VAUX(P74) 68
69 (P75)CONFIG_2 3.3VAUX(P74) 68 GND GND
GND GND
CONN@ FOX_AS0BC21-S85BB-7H
CONN@ FOX_AS0BC21-S85BB-7H
Port4,Gen3 Port3,Gen2
+3VS
+3VS +3VS
+3VS
JSSD3 JSSD4
1 2 1 2
3 CONFIG_3 3.3VAUX 4 3 CONFIG_3 3.3VAUX 4
GND 3.3VAUX 10U_0805_25V6K~D GND 3.3VAUX
1U_0402_6.3V6K~D
0.1U_0402_25V6K~D
1000P_0402_50V7K~D
5 6 5 6
7 NC NC 8 7 NC NC 8
B NC NC 1 1 1 1 NC NC B
10U_0805_25V6K~D
1U_0402_6.3V6K~D
0.1U_0402_25V6K~D
1000P_0402_50V7K~D
9 10 9 10
NC DAS# NC DAS#
CN37
CN38
CN35
CN36
11 11 1 1 1 1
NC NC
2 2 2 2
CN39
CN40
CN41
CN42
+3VS +3VS 2 2 2 2
13 12 13 12
15 (P21)CONFIG_0 NC(P20) 14 15 (P21)CONFIG_0 NC(P20) 14
17 (P23)NC NC(P22) 16 17 (P23)NC NC(P22) 16
(P25)NC NC(P24) (P25)NC NC(P24)
2
2
19 18 19 18
21 (P27)GND NC(P26) 20 RN33 21 (P27)GND NC(P26) 20 RN32
23 (P29)NC NC(P28) 22 10K_0402_5% 23 (P29)NC NC(P28) 22 10K_0402_5%
25 (P31)NC NC(P30) 24 25 (P31)NC NC(P30) 24
27 (P33)GND NC(P32) 26 27 (P33)GND NC(P32) 26
1
1
29 (P35)NC NC(P34) 28 29 (P35)NC NC(P34) 28
31 (P37)NC NC(P36) 30 31 (P37)NC NC(P36) 30
CN44 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P4_C 33 (P39)GND DEVSLP(P38) 32 CN43 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P3_C 33 (P39)GND DEVSLP(P38) 32
<16> SATA_PRX_DTX_P4 (P41)PETn0/SATA-B+ NC(P40) <16> SATA_PRX_DTX_P3 (P41)PETn0/SATA-B+ NC(P40)
CN46 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N4_C 35 34 CN45 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N3_C 35 34
<16> SATA_PRX_DTX_N4 (P43)PETp0/SATA-B- NC(P42) <16> SATA_PRX_DTX_N3 (P43)PETp0/SATA-B- NC(P42)
2
2
37 36 37 36
CN48 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N4_C 39 (P45)GND NC(P44) 38 RN35 @ CN47 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N3_C 39 (P45)GND NC(P44) 38 RN34 @
<16> SATA_PTX_DRX_N4 (P47)PERn0/SATA-A- NC(P46) <16> SATA_PTX_DRX_N3 (P47)PERn0/SATA-A- NC(P46)
CN50 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P4_C 41 40 10K_0402_5% CN49 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P3_C 41 40 10K_0402_5%
<16> SATA_PTX_DRX_P4 43 (P49)PERp0/SATA-A+ NC(P48) 42 <16> SATA_PTX_DRX_P3 43 (P49)PERp0/SATA-A+ NC(P48) 42
45 (P51)GND NC(P50) 44 45 (P51)GND NC(P50) 44
1
1
47 (P53)NC NC(P52) 46 47 (P53)NC NC(P52) 46
49 (P55)NC NC(P54) 48 49 (P55)NC NC(P54) 48
51 (P57)GND MFG1(P56) 50 51 (P57)GND MFG1(P56) 50
53 (P59)KEY MFG2(P58) 52 53 (P59)KEY MFG2(P58) 52
SATA Port4 / PCIe Port1 59 (P65)KEY KEY(P64) 58 +3VS 59 (P65)KEY KEY(P64) 58 +3VS
PCH_GPIO16 61 (P67)NC KEY(P66) 60 61 (P67)NC KEY(P66) 60
<21> PCH_GPIO16 63 (P69)CONFIG_1 SUSCLK(P68) 62 63 (P69)CONFIG_1 SUSCLK(P68) 62
69 (P75)CONFIG_2 3.3VAUX(P74) 68 69 (P75)CONFIG_2 3.3VAUX(P74) 68
GND GND GND GND
A A
CONN@ FOX_AS0BC21-S85BB-7H CONN@ FOX_AS0BC21-S85BB-7H

Mini Card/LED
0.1
5 4 3 2 1
5 4 3 2 1
UL1
<20> PCIE_PRX_GLANTX_P3
2 1 PCIE_PRX_LANTX_P3_C 30
TX_P VDD33
1 W=40mils +LAN_IO
CL1 0.1U_0402_16V7K~D 16
2 1 PCIE_PRX_LANTX_N3_C 29 AVDD33
<20> PCIE_PRX_GLANTX_N3 CL2 0.1U_0402_16V7K~D TX_N
PCIE_PTX_LANRX_P3 35 13 +AVDDL
+LAN_IO <20> PCIE_PTX_GLANRX_P3 RX_P AVDDL 19
<20> PCIE_PTX_GLANRX_N3
PCIE_PTX_LANRX_N3 36
RX_N
AVDDL
AVDDL
31 +DVDDL W=20mils
34
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
CLK_PCIE_LAN 33 AVDDL 6
<18> CLK_PCIE_LAN REFCLK_P AVDDL_REG
1
1 1
RL1 CLK_PCIE_LAN# 32
<18> CLK_PCIE_LAN# REFCLK_N 22
D 4.7K_0402_5%~D +AVDDH CL3 CL4 D
LANCLK_REQ# 4 AVDDH 9
<18> LANCLK_REQ# CLKREQ# AVDDH_REG 2 2
2
PLT_RST# 2
<17,28,31,43,44> PLT_RST# PERST# 37 +DVDDL
PCIE_WAKE# 3 DVDDL_REG
<17,43> PCIE_WAKE# WAKE#
11 LAN_MDIP0
25 TRXP0 12 LAN_MDIN0
26 SMCLK TRXN0 14 LAN_MDIP1 close to UL1 pin37
The pull-up resisters might not be 28
27
SMDATA
NC
TRXP1
TRXN1
TRXP2
15
17
18
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
necessory due to existence 41 TESTMODE
GND
TRXN2
TRXP3
20
21
LAN_MDIP3
LAN_MDIN3
TRXN3 W=20mils
on PCH side. XTLI
XTLO
8
7 XTLI
+AVDDH
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
XTLO 40
25MHZ_10PF_7V25000014
1 2 5 LX
+LAN_IO ISOLAT# 1 1 1
RL2 30K_0402_5% 24
PPS
4
CL5 CL6 CL7
LAN_ACTIVITY# 38 10 +RBIAS 1 2
GND
GND
LAN_LINK#_R 39 LED_0 RBIAS 2 2 2
LAN_LED2#_R 23 LED_1 RL3
LED_2
2
2.37K_0402_1%~D
OSC
OSC
RL4
YL1 5.1K_0402_1%~D S IC E2201-BL3A-R QFN 40P E-LAN CTRL
3
15P_0402_50V8J~D
15P_0402_50V8J~D
1
2 2
close to UL1 pin9 close to UL1 pin22
CL8 CL9
1 1
+3VALW
C C
1 1
CL40 CL41
4.7U_0805_10V4Z 0.1U_0402_16V7K
2 2
+LAN_IO 1A
UL2 +AVDDL W=20mils
1 W=40mils
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
4.7U_0603_6.3V6K~D
5 OUT
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1000P_0402_50V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
IN 2 1 1 1 1 1 1 1 1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4 GND
CL22
EN_WOL#
<43> EN_WOL# EN 3 1 2 CL18 CL19 CL20 CL21 CL23 CL24 CL25
OCB +3VS 1 1 1 1 1 1 1
1 RL5
CL42 10K_0402_5% CL11 CL12 CL13 CL14 CL15 CL16 CL17 2 2 2 2 2 2 2 2
SY6288D20AAC_SOT23-5
2 2 2 2 2 2 2
0.1U_0402_16V7K
close to UL1 pin1 close to UL1 pin16 close to UL1 pin6 close to UL1 pin34 close to UL1 pin31 close to UL1 pin13 close to UL1 pin19
JLAN
B @EMI@ B
2 1 LAN_ACTIVITY# 10
CL27 470P_0402_50V7K Yellow LED-
TIMAG: S X'FORM_ IH-160 LAN,SP050006F00 +LAN_IO

2
RL8
1
330_0402_5%
RJ45_MDI3-
9
8
Yellow LED+
BOTHHAND: S X'FORM_ GST5009-D LF LAN,SP050006B00 RJ45_MDI3+ 7

PR4-
TL1
RL9 RJ45_MDI1- 6
PR4+
Same with ECHO13.
+VDDCT_L
LAN_MDIN3
1
2 TCT1 MCT1
24
23
RJ45_CT3
RJ45_MDI3-
1 2 RJ45_CT
75_0402_1%~D RJ45_MDI2- 5
PR2-
LAN_MDIP3 3 TD1+ MX1+ 22 RJ45_MDI3+ PR3-
TD1- MX1- RL10 RJ45_MDI2+ 4
4 21 RJ45_CT2 1 2 PR3+ 17
LAN_MDIN2 5 TCT2 MCT2 20 RJ45_MDI2- 75_0402_1%~D RJ45_MDI1+ 3 GND
LAN_MDIP2 6 TD2+ MX2+ 19 RJ45_MDI2+ PR2+ 16
TD2- MX2- RL11 RJ45_MDI0- 2 GND
7 18 RJ45_CT1 1 2 PR1- 15
LAN_MDIN1 8 TCT3 MCT3 17 RJ45_MDI1- 75_0402_1%~D RJ45_MDI0+ 1 GND
LAN_MDIP1 9 TD3+ MX3+ 16 RJ45_MDI1+ PR1+ 14
TD3- MX3- RL12 2 1 LAN_LINK# 11 GND
10 15 RJ45_CT0 1 2 @EMI@ CL28 470P_0402_50V7K Green LED-
LAN_MDIN0 11 TCT4 MCT4 14 RJ45_MDI0- 75_0402_1%~D 2 1 LAN_LED2# 13
LAN_MDIP0 12 TD4+ MX4+ 13 RJ45_MDI0+ @EMI@ CL29 470P_0402_50V7K Orange LED-
TD4- MX4- 1 2 12
QL3 +LAN_IO Green-Orange LED+
LL1
2N7002_SOT23 BLM15AG121SN1D_L0402_2P
2
350UH_GST5009-CLF SANTA_130456-511
D
CL30 3 1 2 1 CONN@
150P_1808_3KV7K~D RL13 130_0402_1%~D
2
1 LAN_LED2#_R 2 1 1
RL15 130_0402_5%~D @EMI@
G
2
LAN_LINK#_R RL14 CL31
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1K_0402_1%~D 470P_0402_50V7K
A 2 A
CL32
CL33
CL34
CL35
CL36
CL37
CL38
CL39
2 1 2 1 2 1 2 1
1
+LAN_IO
1 2 1 2 1 2 1 2

LAN E2201
5 4 3 2 1
5 4 3 2 1
+3VS_CARD UR1
+3VS_CARD
11 30 SD_CD#
3V3_IN SD_CD#
1 2
20 mils 18
+DV33_18 31 MS_INS#
DV33_18 MS_INS#
0.1U_0402_16V7K
4.7U_0603_6.3V6K
1U_0402_6.3V6K CR3
CR6
1
CR7
1
2 1
20 mils 10
+AV12_DV12_S 32 CR_WAKE#
0.1U_0402_16V7K CR4 AV12 WAKE#
2 1
20 mils 14
D 2 2 4.7U_0603_6.3V6K CR5 DV12S D
2 1
0.1U_0402_16V7K CR8 15 SD_D1_R
+Vcc_3in1 SP1
40 mils 12 16 SD_D0 MS_D1_R
Card_3V3 SP2 @EMI@
Close to Pin 27 +3VS_CARD 17 SD_CLK MS_D0 RR1 1 2 0_0402_5% SD_CLK MS_D0_R 1 2
20 mils 375mA 27 SP3 EMI@
3V3aux 19 SD_CMD MS_D2_R CR9
12 mils SP4 5P_0402_50V8C
6.2K_0402_1% 1 2 RR2 RREF 9 20 SD_D3 MS_D3_R
RREF SP5
Close pin < 200mil
21 SD_D2 MS_CLK RR3 1 2 0_0402_5% SD_D2 MS_CLK_R
SP6
PCIE_PTX_CARDRX_P5 3 29 SD_WP MS_BS EMI@
<20> PCIE_PTX_CARDRX_P5 HSIP SP7
PCIE_PTX_CARDRX_N5 4
<20> PCIE_PTX_CARDRX_N5 HSIN for project which need fine tune SD signal can change to R
PCIE_PRX_CARDTX_P5 1 2 PCIE_PRX_C_DTX_P1 7
<20> PCIE_PRX_CARDTX_P5 CR10 0.1U_0402_16V7K HSOP
PCIE_PRX_CARDTX_N5 1 2 PCIE_PRX_C_DTX_N1 8 13
<20> PCIE_PRX_CARDTX_N5 CR11 0.1U_0402_16V7K HSON NC 40 mils
22
NC +Vcc_3in1
C C
CLK_PCIE_CD 5 23
<18> CLK_PCIE_CD REFCLKP NC
CLK_PCIE_CD# 6 24
<18> CLK_PCIE_CD# REFCLKN NC
10U_0603_6.3V6M
CR12
0.1U_0402_16V7K
CR13
+3VS_CARD 25
NC 1 1
Close to JCR Pin 12
PLT_RST# 1 26
<17,28,30,43,44> PLT_RST# PERST# NC
1 8 CR_GPIO 2 2
2 7 CR_WAKE# CDCLK_REQ# 2
3 6 <18> CDCLK_REQ# CLK_REQ#
4 5
CR_GPIO 28 33
RR4 10K_8P4R_5% GPIO GND
JCR
SD_D2 MS_CLK_R 1
RTS5227-GR_QFN32_4X4 SD-DAT2
pin28: 2
SD_CD# 3 MS-VSS1
If GPIO NO use for LED function and 4 SD-CD/DAT3 MMC-RSV
GPIO must pull high SD_D2 MS_CLK_R 5 MS-VCC
SD_CMD MS_D2_R 6 MS-SCLK
Internal Pull status SD-CMD MMC-CMD
SD_D3 MS_D3_R 7
MS_INS# 8 MS-DATA3
NO Card SD Insert MS Insert MS-INS
B 9 B
SD_CMD MS_D2_R 10 SD-VSS MMC-VSS1
15_SP1 PD80 SD_D1_PU80 PD80 MS-DATA2
11
SD_D0 MS_D1_R 12 SD-VDD MMC-VDD
16_SP2 PD80 SD_D0_PU80 MS_D1_PD80 MS-DATA0
SD_D0 MS_D1_R 13
SD_CLK MS_D0_R 14 MS-DATA1
60mil 60mil 1.5A 17_SP3 PD80 SD_CLK_PD80 MS_D0_PD80 SD-CLK MMC-CLK
SD_WP MS_BS 15
+3VS +3VS_CARD 16 MS-BS
19_SP4 PD80 SD_CMD_PU80 MS_D2_PD80 MS-VSS2
LR1 17
MMZ1608R301AT_2P~D SD_D0 MS_D1_R 18 SD-VSS MMC-VSS2
20_SP5 PD80 SD_D3_PU80 MS_D3_PD80 SD-DAT0 MMC-DAT
1 2 SD_D1_R 19
SD_CD# 20 SD-DAT1
21_SP6 PD80 SD_D2_PU80 MS_CLK_PD80 SD-CD
10U_0603_6.3V6M
CR1
0.1U_0402_16V7K
CR2
21 23
SD_WP MS_BS 22 SD-GND GND1 24
1 1 29_SP7 PD200 SD_WP_PD200 MS_BS_PD200 SD-WP(SW) GND2
30_SD_CD# PU200 PU200 PU200 T-SOL_143-2300302602_RV
2 2
31_MS_CD# PU200 PU200 PU200
Close to Pin 11
A A

Card Reader RTS5179
5 4 3 2 1
5 4 3 2 1
+3.3V_DVDD
BLM15AG121SN1D_L0402_2P +3.3V_DVDD
+3VS
LA10
1 2 VDDQ_PLL BLM15AG121SN1D_L0402_2P
LA9 1 2 VDD_SW
+3.3V_DVDD +3.3V_DVDD
1
+3VS +3.3V_DVDD
2 1
+1.2VS +3.3V_AVDD +5VS
20 mil 500mA
closed to Pin 16,19 CA3 2 UA5 RT9041E-15GQW_WDFN8_2X2
0.1U_0402_25V6K~D CA4 CA5 2 1
2
20 mil
0.1U_0402_25V6K~D 10U_0603_6.3V6M~D CA1 RA95 0_0603_5% 8 1 +1.2VS
+3VS UA1 1 2 VIN VOUT
0.1U_0402_25V6K~D
9 38 1 7 2 FB_1.2V
DVDD_1 AVDD NC ADJ
2
20 mil
20 29 closed to Pin 10, 11 closed to Pin 54 QA1
DVDD_2 PORTA_VDD
40 mil 700mA
RA51 1 2 0_0402_5% 2 DVDD_HDAIO 48 34 LP2301ALT1G_SOT23-3 6 3 RA127
+3.3V_DVDD DVDD_3 PORTD_VDD VDD PGOOD
5.1K_0402_1%
4.7U_0603_6.3V6K~D
+1.2VS
40 mil 700mA
15 10 3 1 +3VS 2 1 5 4
D
0.1U_0402_25V6K~D CA14 VDD_SW EN_1.2V
FBDC VDD_SW_1 EN GND
0.1U_0402_16V7K
2
11 1 1 9
150_0402_1%
1
VDD_SW_2 1U_0402_10V6K PGND
1
1
20 mil
54 16 VDDQ_PLL @ @ 12K_0402_1%
DVDD_HDAIO 6 DVDD_IO VDDQ_SW CA70 @ @ RA128 CA112
G
2
DVDD_HDAIO +3VS +3.3V_AVDD
20 mil
12 +1.2VS_SWout 1 2 RA82
2
SWOUT
2
VDDQ_PLL 19 LA1 4.7UH_CBC2012T4R7M_20%~D 2 2
CA69
1 1
10P_0402_50V8J~D RA96 0_0402_5% VDDQ_PLL RA92 RA129
D 2 D
@
CA30 2 1 2 1 28 HPOUT-L 1 2 1 10K_0402_5%
510K_0402_5%
PORTA_L
0.01U_0402_16V7K
@ @ 5 26 HPOUT-R @ CA12
RA83
<16> PCH_AZ_CODEC_BITCLK HDA_BCLK PORTA_R 1 2 2
1 2PCH_AZ_CODEC_SDIN0_R 7 24 0_0805_5%~D CA71
<16> PCH_AZ_CODEC_SDIN0 47U_0805_6.3V6M~D FB=0.8V
1
RA40 33_0402_5%~D 4 HDA_SDI PORTA_S 27 1 CA6 CA7 CA8 @ @
<16> PCH_AZ_CODEC_SDOUT 3 HDA_SDO PORTA_VCOM 10U_0603_6.3V6M~D 2
0.1U_0402_25V6K~D 0.1U_0402_25V6K~D
2
<16> PCH_AZ_CODEC_SYNC 2 HDA_SYNC 44 MIC_LINE_IN_L 2 1 1
<16> PCH_AZ_CODEC_RST# HDA_RSTN PORTB_L
PORTB_R
43 MIC_LINE_IN_R Vo=0.8(1+Rt/Rb)=1.2V
SENSE A# 47 45 MIC1_C_L CA13 1 2 2.2U_0603_10V6K MIC1
RA64 1 2 10K_0402_1%~D 37 SENSE_A PORTC_L 46 AGND
RA42 1 2 20K_0402_1%~D 36 SENSE_B PORTC_R RA97 +3.3V_DVDD
AGND SENSE_I 33 HP2_D_L1 2 1 10K_0402_1%~D
PORTD_L 31 HP2_D_R1
CA15 1 2 2200P_0402_25V7K~D MIC_BIAS_B 42 PORTD_R 35
AGND MIC_BIASB PORTD_S +1.2VS
AGND CA24 1 2 100P_0402_50V8J~D MIC_BIAS_C 41 32 AGND
MIC_BIASC PORTD_VCOM
MIC_BIAS_C 2
23 AMP_LEFT CA89 220U_B2_2.5VM_R35M~D
MIC_CLK_C 55 PORTG_L 22 AMP_RIGHT HP2_D_L1 1 2 HP2_D_L2 CA16
+
1 2 51 DMIC_MCLK / MPIO1 PORTG_R UA6
<25> MIC_DATA DMIC_DATA0 / MPIO3 2 2 2 0.1U_0402_25V6K~D
RA45 0_0805_5%~D 56 MPIO_2 CA90 220U_B2_2.5VM_R35M~D MIC_BIAS_B 1
MPIO_4_PB#_PD 50 SPDIF OUT0 / MPIO2 CA9 CA10 CA11 HP2_D_R1 1 2 HP2_D_R2 HP_MIC_LINE_IN_L 4 1
+
SPDIF IN / MPIO4 L 5V_SUPPLY
RA102
RA100
40 MIC_BIAS_B HP_MIC_LINE_IN_R 5 16
2.2K_0402_5%~D
2.2K_0402_5%~D
VREF_FILT 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D R VDD
1
PC_BEEP_1 53 1 1 1
PCBEEP / MPIO5 1 2 RA101
1
13
VSS_SW_1
100_0402_1%
100_0402_1%
EAPD 1 2EAPD_R 52 14 CA17 CA18 MIC_LINE_IN_L2 14 2 AC/DC 1 8
EAPD / MPIO0 VSS_SW_2 L1 AC/DC
RA107
RA108
RA66 0_0805_5%~D 17 47U_0805_6.3V6M~D 0.1U_0402_25V6K~D HP2_D_L2 13 8 DIR_SEL 2 7
1 VSSQ_SW 2 1 L2 DIR_SEL 3 6
2
8 DVSS_1 39 MIC_LINE_IN_R2 12 6 MPIO_4_PB#_PD 4 5
When the external amplifier is to be powered down,
2
21 DVSS_2 AVSS 25 HP2_D_R2 11 R1 SEL 3 MPIO_2
this pin output a logic ‘1’ 49 DVSS_3 PORTA_VSS 30 R2 MUTE
18 DVSS_4 PORTD_VSS 10K_0804_8P4R_5%~D AGND
VSSQ_PLL 57 AGND AGND AGND 10 15
1 2 Thermal PAD 9 GND CAP_SS
GND 2
RA53 0_0805_5%~D 2.2U_0603_10V6K 7
1 2 MALCOLM-EX_QFN56_7X7~D RA103 GND CA19
RA55 0_0805_5%~D MIC_LINE_IN_L CA76 1 2MIC_LINE_IN_L1 1 2 MIC_LINE_IN_L2 0.1U_0402_25V6K~D
1 2 +3.3V_AVDD ISL54405IVZ-T_TSSOP16 1
RA57 0_0805_5%~D 7.5K_0402_1%~D
AGND AGND AGND
2
MIC_LINE_IN_R CA77 1 2 MIC_LINE_IN_R1 1 RA104 2 MIC_LINE_IN_R2
RA41 7.5K_0402_1%~D
10K_0402_5%~D 2.2U_0603_10V6K Intersil SA00007TP00
3 EC_MUTE# <43>
AGND EC_MUTE#
ISL54405IVZ-T TSSOP16P
1
GND RA106
1
C C
SPK_MUTE# 1 RA105
LA2 EMI@ 10K_0402_1%~D 10K_0402_1%~D
@ MIC_CLK_C 1 2 MIC_CLK 2 EAPD
MIC_CLK <25>
0.1U_0402_16V7K BLM15BB221SN1D_2P
PC BEEP
2
CA65 2 1 PC_BEEP_1 AC/DC 0 0 0
+3.3V_AVDD DA15
CA67 RA81 0.1U_0402_16V7K BAT54AW_SOT323-3~D DIR X X X
1 2 1 2 PC_BEEP CA66 2 1 PC_BEEP_L
<43> BEEP#
2
MUTE 0 0 1
1U_0402_6.3V6K~D 560_0402_5% 0.1U_0402_16V7K
CA72 2 1 PC_BEEP_R
RA52
10K_0402_5%~D
SENSE pin Close to chip side
SEL 0 1 X
3 DEPOP#_EC
DEPOP#_EC <43> 1 2
CA68 JACK1_PLUG SENSE A# L1,R1 ON OFF OFF
1
1 2 1 RA84 2 HP_MUTE# 1 RA46 39.2K_0402_1%
<16> HDA_SPKR
JACK2_PLUG# 1 2 L2,R2 OFF ON OFF
1
1U_0402_6.3V6K~D 560_0402_5% 2 EAPD RA47 20K_0402_1%~D

MIC_C_PLUG 1 2 L, R OFF OFF OFF
RA80 @ RA48 10K_0402_1%~D
10K_0402_5%~D DA16 JACK2_PLUG# 1 2
C/P shunts
+RTC_CELL BAT54AW_SOT323-3~D RA49 5.11K_0402_1%~D L1, R1 OFF OFF OFF
2
C/P shunts
L2, R2 OFF OFF OFF
1
MIC_IN
RA123
C/P shunts
470K_0402_5%
UNDER WIN8 WLP (FSOP >= 1Vrms), AVDD=3.5 to 3.57Vrms AND MOUNT RA44(5K1).
2
UNDER WIN8.1 WLP (FSOP >= 0.707Vrms). AVDD=3.3 +/- 0.3Vrms AND UNMOUNT RA44
3
5
D
G QA7A
QA7B S DMN66D0LDW-7_SOT363-6
4
6
1 2 2
D
PCH_AZ_CODEC_RST# G
RA124 10K_0402_5% S
CONN@
1
1 2 I-PEX_20455-040E-12
+3VS
RA125 @ 10K_0402_5%
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R- AMP_LEFT 40 44
LA7
Speaker 4 ohm : 40mil AMP_RIGHT
MIC_IN
39
38
40
39
G5
G4
43
B
FBMA-L11-160808-121LMA30T_0805
1 2
40mil +PVDD
Speaker 8 ohm : 20mil Int. Speaker Connector RING2
HPOUT-L
37
36
38
37 B
B+_BIAS 36
HPOUT-R 35
close to Codec JSPK +3VS +5VALW B+_BIAS JACK1_PLUG 34 35
CA92
CA91
CA95
CA97
CA94
CA96
1 1
10U_1206_25V6M
1U_0603_25V6K
1U_0603_25V6K
1U_0603_25V6K
1U_0603_25V6K
0.1U_0402_25V6
34
1
SPKR- EMI@ LA3 1 2 NBQ160808T-800Y-N 0603 SPK_R1-_CONN 1 JACK2_PLUG# 33

SPKR+ EMI@ LA4 1 2 NBQ160808T-800Y-N 0603 SPK_R2+_CONN 2 1 HP_MIC_LINE_IN_L 32 33
Close to LA7 2 32
SPKL- EMI@ LA5 1 2 NBQ160808T-800Y-N 0603 SPK_L1-_CONN 3 HP_MIC_LINE_IN_R 31
2
2 2 SPKL+ EMI@ LA6 1 2 NBQ160808T-800Y-N 0603 SPK_L2+_CONN 4 3 30 31

+GVDD 5 4 SPK_MUTE# 29 30
6 G1 HP_MUTE# 28 29
G2 27 28
Close to UA1 1
27
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
Pin12,13,14,27,28 1 1 1 1 26
26
3
RA113 25
EMI@ CA29
EMI@ CA33
EMI@ CA31
EMI@ CA32
10K_0402_1% 24 25
24
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
UA4 23
2 2 2 2 <43> CTL1 23
ESD@ ESD@ ACES_50278-00401-001 22
<35> USB20_N1_CONN
2
B+_BIAS 1 2 +PAVDD 12 1 PLIMIT DA13 DA14 CONN@ 21 22

AVCC PLIMIT <35> USB20_P1_CONN 21
10U_0805_25V6K
RA109 10_0402_1% 20
<20> USB_OC4# 20
1
PC_BEEP_R 19
<35> USB3RN6_R
2 RA91 19
1
1U_0603_25V6K
24.9K_0402_1% CA98 +PVDD 13 3 1 18

RA120 PVCC GAIN/SLV <35> USB3RP6_R 18
1
CA99
PC_BEEP_L 14 100K_0402_1% RA112 17

2
1
1 2 27 PVCC 10K_0402_1% 16 17
RA114 <35> USB3TN6_R
CA105 28 PVCC 11 1 2 1 RA111 2 15 16
<35> USB3TP6_R
2
PVCC SYNC 15
0.1U_0402_10V7K
2.2U_0603_10V6K 20K_0402_5% 14
47K_0402_5% <43> CTL2
2
RA118 0.027U_0402_16V6K 13 14
RA115 <35> USB20_N8_CONN 13
AMP_LEFT 1 2 AMP_LEFT-1 1 2 CA1031 2 AMP_LEFT_C 6 29 2 1 +PVDD 1 12
INPL /SDZ <35> USB20_P8_CONN 12
CE52
13.3K_0402_1% 1 2 1 2 CA101 5 100K_0402_1% 11

RA117 5.9K_0402_5% 0.027U_0402_16V6K INNL 10 11
<35> USB3RN3_R
CA106 RA119 0.027U_0402_16V6K 30 2 RA110 1 +PVDD +3.3V_AVDD 9 10
/FAULTZ 2 <35> USB3RP3_R 9
AMP_RIGHT 1 2 AMP_RIGHT-1 1 2 CA1041 2 AMP_RIGHT_C 31 100K_0402_1% 8
2 1 1 2 CA102 32 INPR 7 8
12.4K_0402_1% +GVDD INNR <35> USB3TN3_R 7
2.2U_0603_10V6K RA116 5.76K_0402_5% 0.027U_0402_16V6K 25 SPKR+ AGND 6
OUTPR <35> USB3TP3_R 6
23 SPKR- 5
RA122 OUTNR MIC_BIAS_C <20> USB_OC2# 5
2 4
GVDD <43> PWRSHARE_EN_EC# 4
1U_0603_25V6K
1 2 16 SPKL+ 3
OUTPL <34,43> USB_PWR_EN# 3
1
CA107 0.22U_0603_25V7K 18 SPKL- 2 42

OUTNL <35> USBCHG_DET# 2 G2
CA100
2.2K_0402_5%~D
RA126
SPKL+ 2 1 BSPL 15 UA3 1 41

24.9K_0402_1% BSPL <43> USB_IN_STATUS# 1 G1
1
SPKL- 2 1 BSNL 19 13 9 HPOUT-L

W=20mil
2
CA108 0.22U_0603_25V7K BSNL 7 SPK_MUTE# 16 VDD TIP_SENSE 5 JACK1_PLUG

CA109 0.22U_0603_25V7K MUTE VDD DET_TRIGGER JIO
SPKR+ 2 1 BSPR 26 1 14 RING2
SPKR- 2 1 BSNR 22 BSPR 4 2 SCL RING2_SENSE 7 SP01001DR00
2
CA110 0.22U_0603_25V7K BSNR GND 17 4 SDA RING2

GND 20 ADDR_SEL 15 MIC_IN
+PVDD AM0 10 GND 21 MIC_C_PLUG 8 SLEEVE_SENSE 6
AM0 GND MIC_PRESENT SLEEVE 1
AM1 9 24 MIC1 11 17 AGND
AM1 GND MIC_P GND
2
A A
AM2 8 12 3 CA81
AM2 33 MIC_N GND 10 10U_0603_6.3V6M~D
RA85 RA86 RA87 GND GND 2
100K_0402_1% 100K_0402_1% 100K_0402_1% TPA3131D2DAPR_QFN32_5X5 TS3A225ERTER_PWQFN16_3X3
1
AM0 AM1 AM2

AGND AGND
Combo JACK Mic. switch
2
RA88 RA89 RA90

100K_0402_1% 100K_0402_1%~D 100K_0402_1%
@ @ @
TI SA000074E00
1
2011/06/02 2012/06/02 Title

Issued Date Deciphered Date
AGND AGND AGND TPA3131D2DAPR QFN 32P Codec Malcolm-EX
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Reserved Page
0.1
5 4 3 2 1
5 4 3 2 1
+5VALW
1 1
CI1 CI2
4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +USB3_VCCA
UI2
1 80mil
D
5 OUT D
IN 2
USB_PWR_EN# 4 GND
<32,43> USB_PWR_EN# EN 3 @EMI@
OCB USB_OC0# <20> RI1 1 2 0_0402_5%~D
1
CI4 1 On MB (Right Side)
SY6288D20AAC_SOT23-5 CI5 LI1 EMI@
0.1U_0402_16V7K
USB20_N0 4 3 USB20_N0_CONN +USB3_VCCA
2 <20> USB20_N0 4 3 +USB3_VCCA
0.1U_0402_16V7K
2
USB20_P0 1 2 USB20_P0_CONN JUSB1
<20> USB20_P0 1 2
10U_0603_6.3V6M~D
1
DLW21SN900SQ2L_0805_4P~D USB20_N0_CONN 2 VBUS
D- 1
CI11
USB20_P0_CONN 3
RI4 1 2 0_0402_5%~D 4 D+ CI10
Change AP2301 to SY6228D @EMI@ USB3RN1_R 5 GND 47U_0805_6.3V6M~D
2
USB3RP1_R 6 StdA-SSRX- 2
7 StdA-SSRX+
@EMI@ USB3TN1_R 8 GND-DRAIN
RI5 1 2 0_0402_5%~D USB3TP1_R 9 StdA-SSTX-
StdA-SSRX+
DLW21SN900HQ2L_0805_4P~D 10
USB3RN1 3 4 USB3RN1_R 11 GND
<20> USB3RN1 3 4 GND
2
12
L30ESDL5V0C3-2_SOT23-3
13 GND
USB3RP1 2 1 USB3RP1_R GND
<20> USB3RP1 2 1 +USB3_VCCA
DI2
EMI@ ESD@
LI2 CONN@
RI8 1 2 0_0402_5%~D
10P_0402_50V8J
1
@RF@
@EMI@
CI40
1
2
@EMI@
RI11 1 2 0_0402_5%~D
DLW21SN900HQ2L_0805_4P~D
C USB3TN1_L 3 4 USB3TN1_R DI3 ESD@ C
USB3TN1 CI30 1 2 0.1U_0402_10V6K~D USB3TN1_L 3 4 USB3RN1_R 1 9 USB3RN1_R
<20> USB3TN1
USB3TP1 CI31 1 2 0.1U_0402_10V6K~D USB3TP1_L
<20> USB3TP1 2 1 2 8
USB3TP1_L USB3TP1_R USB3RP1_R USB3RP1_R
2 1
EMI@ USB3TN1_R 4 7 USB3TN1_R
LI3
RI13 1 2 0_0402_5%~D USB3TP1_R 5 6 USB3TP1_R
@EMI@
TVWDF1004AD0_DFN9
@EMI@ On MB (Right Side)

RI56 1 2 0_0402_5%~D
+5VALW
LI4 +USB3_VCCB
EMI@
USB20_P7 4 3 USB20_P7_CONN
B <20> USB20_P7 4 3 +USB3_VCCB B
1 1 JUSB2
CI26 CI27 USB20_N7 1 2 USB20_N7_CONN
<20> USB20_N7 1 2 1
2.0A VBUS
10U_0603_6.3V6M~D
4.7U_0805_10V4Z 0.1U_0402_16V7K USB20_N7_CONN 2
2 2 +USB3_VCCB DLW21SN900HQ2L_0805_4P~D USB20_P7_CONN 3 D-
D+ 1
CI25
RI58 1 2 0_0402_5%~D 4
UI3 @EMI@ USB3RN2_R 5 GND CI24
1 USB3RP2_R 6 StdA-SSRX- 47U_0805_6.3V6M~D
80mil
2
5 OUT 7 StdA-SSRX+ 2
IN 2 @EMI@ USB3TN2_R 8 GND-DRAIN
USB_PWR_EN# 4 GND RI61 1 2 0_0402_5%~D USB3TP2_R 9 StdA-SSTX-
EN 3 StdA-SSRX+
OCB USB_OC1# <20> LI6 10
EMI@
L30ESDL5V0C3-2_SOT23-3
1 GND
2
CI28 1 USB3RP2 2 1 USB3RP2_R 11
<20> USB3RP2 2 1 12 GND
SY6288D20AAC_SOT23-5 CI29 DI4
GND
0.1U_0402_16V7K
13
2 0.1U_0402_16V7K USB3RN2 3 4 USB3RN2_R ESD@ GND
2 <20> USB3RN2 3 4 +USB3_VCCB
DLW21SN900HQ2L_0805_4P~D CONN@
1 2 0_0402_5%~D
10P_0402_50V8J
RI62
1
@RF@
@EMI@
Change AP2301 to SY6228D
CI41
2
@EMI@ ESD@
RI59 1 2 0_0402_5%~D DI5
USB3RN2_R 1 9 USB3RN2_R
LI5
EMI@
USB3TP2_L 2 1 USB3TP2_R USB3RP2_R 2 8 USB3RP2_R
USB3TN2 CI32 1 2 0.1U_0402_10V6K~D USB3TN2_L 2 1
<20> USB3TN2
USB3TP2 CI33 1 2 0.1U_0402_10V6K~D USB3TP2_L USB3TN2_R 4 7 USB3TN2_R
<20> USB3TP2 3 4
USB3TN2_L USB3TN2_R
3 4 USB3TP2_R 5 6 USB3TP2_R
A A
RI60 1 2 0_0402_5%~D
@EMI@ 3
TVWDF1004AD0_DFN9

USB 3.0/2.0 x2 (left side)
5 4 3 2 1
5 4 3 2 1
@EMI@
RI63 1 2 0_0402_5%~D
+3VLP +3VLP +3VLP +3VLP
LI7 EMI@
SDMK0340L-7-F_SOD323-2
USB20_N1 4 3 USB20_N1_CONN
<20> USB20_N1 4 3 USB20_N1_CONN <32>
1
D D
220K_0402_5%
<20> USB20_P1
USB20_P1 1
1
DLW21SN900SQ2L_0805_4P~D
2
2 USB20_P1_CONN
USB20_P1_CONN <32>
RU4
100K_0402_5% RU5 DU8 1
CU26
USB charge for DC S5
0.1U_0402_16V7K
2
RI64 1 2 0_0402_5%~D
@EMI@
2
5
CU27 1
P
RI65 1 2 0_0402_5%~D
@EMI@ 2 1 2 NC 4
A Y USBCHG_DET_D <60>
LI8
G
EMI@ 2.2U_0603_6.3V6K
1
USB3RN6 2 1 USB3RN6_R UU5
3
<20> USB3RN6 2 1 USB3RN6_R <32>
TC7SZ14FU_SSOP5~D RU6
1M_0402_5%
USB3RP6 3 4 USB3RP6_R
<20> USB3RP6 3 4 USB3RP6_R <32>
2
DLW21SN900HQ2L_0805_4P~D DU9
RI66 1 2 0_0402_5%~D
@EMI@ USBCHG_DET# 2 1
<32> USBCHG_DET# USBCHG_DET_EC# <43>
1 SDMK0340L-7-F_SOD323-2 1
CU28 CU29
0.1U_0402_16V7K 0.1U_0402_16V7K
2 2
RI67 1 2 0_0402_5%~D
@EMI@
LI9
EMI@
USB3TN6_L 2 1 USB3TN6_R To PowerShare Port (On DB)
2 1 USB3TN6_R <32>
USB3TN6 CI34 1 2 0.1U_0402_10V6K~D USB3TN6_L
<20> USB3TN6
USB3TP6 CI35 1 2 0.1U_0402_10V6K~D USB3TP6_L
<20> USB3TP6 USB3TP6_L 3 4 USB3TP6_R
3 4 USB3TP6_R <32>
RI68 1 2 0_0402_5%~D
@EMI@
C C
RI69 1 2 0_0402_5%~D
@EMI@
LI10 EMI@
USB20_N8 4 3 USB20_N8_CONN
<20> USB20_N8 4 3 USB20_N8_CONN <32>
USB20_P8 1 2 USB20_P8_CONN
<20> USB20_P8 1 2 USB20_P8_CONN <32>
B B
DLW21SN900SQ2L_0805_4P~D
RI70 1 2 0_0402_5%~D
@EMI@
RI71 1 2 0_0402_5%~D
@EMI@
LI11
EMI@
USB3RN3 2 1 USB3RN3_R
<20> USB3RN3 2 1 USB3RN3_R <32>
USB3RP3 3 4 USB3RP3_R
<20> USB3RP3 3 4 USB3RP3_R <32>
RI72 1 @EMI@2 0_0402_5%~D
RI73 1 2 0_0402_5%~D
@EMI@
LI12
EMI@
USB3TN3_L 2 1 USB3TN3_R
1 2 0.1U_0402_10V6K~D USB3TN3_L 2 1 USB3TN3_R <32>
USB3TN3 CI36
<20> USB3TN3 USB3TP3 CI37 1 2 0.1U_0402_10V6K~D USB3TP3_L
<20> USB3TP3 3 4
USB3TP3_L USB3TP3_R
3 4 USB3TP3_R <32>
RI74 1 @EMI@2 0_0402_5%~D
A A

USB 3.0/2.0 x2 (left side)
5 4 3 2 1
A B C D E F G H
+3VS
1 1
1
4.7K_0402_5%
RN6
4.7K_0402_5%
RN7
0.01U_0402_16V7K
CN7
0.1U_0402_25V6K
CN8
0_0402_5%
RN8
0_0402_5%
RN9
0_0402_5%
RN10
0_0402_5%
RN11
@ @ 2 2 @ @
Change to TI SA00003ZX00
2
+3VS
1 1
UN1
RN12 1 2 0_0402_5% 7 6 DEW2
EN VDD 16 DEW1
CN9 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P0_C 1 VDD
<16> SATA_PTX_DRX_P0 A_INp
CN10 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N0_C 2 10
<16> SATA_PTX_DRX_N0 A_INn NC 20 HDD_REXT_SATA0
CN11 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P0_C 5 REXT
<16> SATA_PRX_DTX_P0 B_OUTp
CN12 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N0_C 4 9 HDD_A0_PRE0
<16> SATA_PRX_DTX_N0 B_OUTn A_PRE0 8 HDD_B0_PRE0
RN13 1 @ 2 0_0402_5% HDD_B0_PRE1 17 B_PRE0
+3VS B_PRE1
RN14 1 @ 2 0_0402_5% HDD_A0_PRE1 19 15 SATA_PTX_DRX_P0_RC CN13 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P0_R
A_PRE1 A_OUTp 14 SATA_PTX_DRX_N0_RC CN14 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N0_R
RN15 1 @ 2 0_0402_5% 18 A_OUTn
3 TEST 11 SATA_PRX_DTX_P0_RC CN15 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P0_R
RN16 1 @ 2 0_0402_5% 13 GND B_INp 12 SATA_PRX_DTX_N0_RC CN16 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N0_R
21 GND B_INn
EPAD
PS8520BTQFN20GTR2_TQFN20_4X4
SATA Redriver
DEW2 RN17 1 @ 2 4.7K_0402_5%
Pin 20: Pin 9: DEW1
HDD_B0_PRE0
RN18 1
RN19 1
@
@
2 4.7K_0402_5%
2 0_0402_5%
PARADE PS8250B PARADE PS8250B HDD_B0_PRE1 RN20 1 2 0_0402_5%
Depop RS26 Depop RS24 HDD_A0_PRE1 RN21 1 @ 2 0_0402_5%
2
PERICOM PI3EQX6741ST PERICOM PI3EQX6741ST HDD_A0_PRE0
HDD_REXT_SATA0
RN22 1
RN23 1 @
2 2K_0402_5%
2 5.1K_0402_1%
2
Pop RS26 Depop RS24

ASMEDIA ASM1466 ASMEDIA ASM1466
Pop RS26 Pop RS24 to pull down
+3VS +5VS
+3VS
Free Fall Sensor Close to JHDD1
0.1U_0402_16V4Z~D
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
1U_0402_6.3V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
4.7U_0603_10V
4.7U_0603_10V
1 1 1 1 1 1 1
CN4
CN1
CN2
CN3
CN51
CN52
1 1 CN6
CN17
CN18
47P_0402_50V8J~D
2 2 2 2 2 2 2
@ @ @
2 2
UN2
LNG3DM 10
1 RES 13
14 VDD_IO RES 15
VDD RES
RES
16 High Limit, 10U change to 4.7U*2
FFS_INT1 11
<17> FFS_INT1 9 INT 1 5
FFS_INT2
<21> FFS_INT2 INT 2 GND 12
7 GND
3 SDO/SA0 3
PCH_SMBDATA 6
<14,15,19,8> PCH_SMBDATA 4 SDA / SDI / SDO
PCH_SMBCLK
<14,15,19,8> PCH_SMBCLK SCL/SPC 2 JHDD1
8 NC 3 1
CS NC SATA_PTX_DRX_P0_R 2 1
LNG3DMTR_LGA16_3X3~D SATA_PTX_DRX_N0_R 3 2
FFS_INT1 connect to PCH GPIO & EC 4 3
discuss with BIOS to use which pin SATA_PRX_DTX_N0_R 5 4
SATA_PRX_DTX_P0_R 6 5
7 6
8 7
+3VS 9 8
10 9
+5VS 11 10
12 11
<21> HDD_DET# 13 12
13
1
+3VS 14
+5VS 15 14
@
RN24 16 15
100K_0402_5%~D 17 16
17
2
G
FFS_INT2_CONN 18
2
19 18
FFS_INT2 3 1 1 2 FFS_INT2_CONN 20 19
21 20
S
22 G1
QN3
SSM3K7002FU_SC70-3~D
DN1
SDM10U45-7_SOD523-2~D
PCH no support DEVSLP 23
24
G2
G3
G4
STARC_111H20-100000-G2-R
CONN@
4 4

HDD/ODD
0.1
A B C D E F G H
5 4 3 2 1
+3.3V_F347
D D
0.1U_0402_16V4Z~D
22P_0402_50V8J~D
1U_0805_10V7
0.1U_0402_16V4Z~D
1 2
CE3
CE4
10P_0402_50V8J
1 1
CE1
CE2
@RF@
+3.3V_F347
CE59
@
2 1 place RE5 as close as UE1 I2C_DAT 4.7K_0402_5% 2 1 RE1
2
2 2
RE3 I2C_CLK 4.7K_0402_5% 2 1 RE2
UE1 0_0603_5%
6 2 SPI_MOCLK 1 2 SPI_MOCLK_R
VDD P0.0 1 SPI_MOSO
USB20_P3 4 P0.1 32 SPI_MOSI
<20> USB20_P3 USB20_N3 5 D+ P0.2 31 SPI_MOCS# I2C_CLK
1 2 0_0603_5%~D <20> USB20_N3 D- P0.3 30
RE4 I2C_DAT
+5VALW P0.4 I2C_DAT <38,40,41>
7 29 I2C_CLK SPI_MOCLK_R
1 2 0_0603_5%~D W=40mils +3.3V_F347
8 REGIN P0.5 28 CALDERA_PRSNT#
I2C_CLK <38,40,41>
10P_0402_50V8J
+5VS RE5 @
VBUS P0.6 27 CALDERA_PRSNT# <41,43>
RE6 1 2 1K_0402_5% +3.3V_F347
10P_0402_50V8J
P0.7
1
1 2 9
@RF@
@RF@
+3.3V_F347 RST#/C2CK
CE57
CE58
RE7 10 26 SLP_S3
P3.0/C2D P1.0
1U_0805_10V7
0.1U_0402_16V4Z~D
25 BATT_CHG_LED 10K_0402_5% 2 1 RE8
10P_0402_50V8J
1 1 1K_0402_1%~D +3.3V_F347
2
P1.1
1
CE6
CE7
@RF@
18 24 ACIN#
P2.0 P1.2
CE60
17 23 LID_SW_IN#_D 2 1 LID_SW_IN#
16 P2.1 P1.3 22 BATT_LOW_LED LID_SW_IN# <19,38,43>
@ DE1
2
2 2 15 P2.2 P1.4 21 SLP_S5 SDMK0340L-7-F_SOD323-2~D

14 P2.3 P1.5 20 CE8 @ 1 2 0.1U_0402_16V4Z~D
13 P2.4 P1.6 19 CE9 @ 1 2 0.1U_0402_16V4Z~D
12 P2.5 P1.7
+3.3V_F347 11 P2.6 3
P2.7 GND
JELC1 C8051F383-GQ_LQFP32_7X7
@
+3.3V_F347 1
1
CE11
CE12
CE13
CE14
CE15
CE16
CE17
CE18
2
2
0.1U_0402_16V4Z
3
1
3
4
4 CPN change to SA00007JF00
CE10
5 1 1 1 1 1 1 1 1 UE2
5 6 SPI_MOSI 15_0402_5% 2 1 RE9 5 2 RE10 1 2 15_0402_5% SPI_MOSO
@ 6 +3.3V_F347 DI SO
2 7 SPI_MOCLK_R 15_0402_5% 2 1 RE11 6
C
GND1 8 2 2 2 2 2 2 2 2 CLK C
GND2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2 SPI_MOCS# 1
AMPHE_G846A06201EU RE12 10K_0402_5%~D CS DEVICE SMBUS ADDRESS
CONN@ 1 2 7
Cloase to JP1 RE13 10K_0402_5%~D HOLD MAXIM - LED 0100 000b
1 2 3
RE14 10K_0402_5%~D WP MAXIM - GPIO 0100 001b
8 4
+3.3V_F347 VCC VSS I2C EEPROM 1010 000b
0.1U_0402_16V4Z~D
22P_0402_50V8J~D
1 EN25Q80A-100HIP_SO8
CE19
1
CE20
2
2
+3.3V_F347
1
RE15
100K_0402_5%
2
SLP_S3
1
D
QE1 +3.3V_F347
2 SSM3K7002F_SC59-3~D
<17,43> PM_SLP_S3# G
1
S RE16
SIO_SLP_S3# change to PM_SLP_S3# 3 100K_0402_5%
+3VALW +3.3V_F347
+3.3V_F347 behavior
2
SLP_S5
J2 @
+3.3V_F347 D
1
2 1 S0 S3 S4 S5
B
QE3 2 1 B
2 SSM3K7002F_SC59-3~D JUMP_43X118
AC IN ON ON ON ON
<17,43> PM_SLP_S5#
1
G
RE17 BATT only ON ON OFF OFF
100K_0402_5% S UE9
SIO_SLP_S5# change to PM_SLP_S5# 3 5 1 AC mode battery full in S5:turn off ELC controller
IN OUT
2
ACIN# 1 2
GND
1
D CE22 4 3 1 2
EN OC +3VS
QE4 4.7U_0805_10V4Z RE20 10K_0402_5%
2 SSM3K7002F_SC59-3~D +3.3V_F347 2 SY6288C20AAC_SOT23-5
<17,43,59> ACIN G
1
S
3 RE21
100K_0402_5%
<43> 3V_F347_ON
2
+3.3V_F347 BATT_LOW_LED
1
D
1
QE6
RE23 2 SSM3K7002F_SC59-3~D
<43> BATT_LOW_LED# G
100K_0402_5%
S
2
BATT_CHG_LED 3
1
D
QE7
2 SSM3K7002F_SC59-3~D
<43> BATT_CHG_LED# G
S
3
A A

ELC (1)
5 4 3 2 1
5 4 3 2 1
MAX7313 change to TI TLC59116F PWM expander

Power LED W=20mils
+5VS
0.1U_0402_16V4Z
+3.3V_F347
AD3 AD2 AD1 AD1
+5VALW
+3.3V_F347 0 0 1 1 +3.3V_F347 1
CE23
+5VALW +5VALW
1
+5VALW
0.1U_0402_16V4Z
100K_0402_5%
RE25 1 JLOGO1 1
1
2
CE26
4.7K_0402_1% CE24 1
1
RE28
UE3 0.1U_0402_16V4Z 2
2
1
1
D D
LID_SW 3
2
RE40 RE43 24 27 2 LOGO_LED_R_DRV# 4 3 2
RESET Vcc 4
3
S
4.7K_0402_1%~D 4.7K_0402_1%~D QE8 LOGO_LED_G_DRV# 5
2
3 ALIEN_LED_R_DRV# Power_LED 2
G
LOGO_LED_B_DRV# 6 5
I2C_CLK 25 OUT0 4 ALIEN_LED_G_DRV# 7 6
2
<37,38,40,41> I2C_CLK 26 SCL OUT1 5 8 7

I2C_DAT ALIEN_LED_B_DRV# 1 ALIEN_LED_R_DRV#
<37,38,40,41> I2C_DAT SDA OUT2 6 9 8
LOGO_LED_R_DRV# D LP2301ALT1G 1P SOT-23-3 ALIEN_LED_G_DRV#
AD0_2 31 OUT3 8 LOGO_LED_G_DRV#
D
ALIEN_LED_B_DRV# 10 9
1
AD1_2 32 A0 OUT4 9 LOGO_LED_B_DRV# 2 QE9 11 10
1 A1 OUT5 10 <43> PWR_LED# 12 11
AD2_2 LED_R_7313#_A# G SSM3K7002F_SC59-3
AD3_2 2 A2 OUT6 11 LED_G_7313#_A# +5VALW_LED 13 12
A3 OUT7 14 LED_B_7313#_A# S 14 GND
OUT8 GND
1
12 15 PWR_R_7313# 3
13 N.C. OUT9 16 PWR_G_7313# ACES_50208-01201-P01_12P
RE42 RE44 28 N.C. OUT10 17 PWR_B_7313#
N.C. OUT11 CONN@
4.7K_0402_1%~D 4.7K_0402_1%~D 29 19 HDD_R_7313#
30 N.C. OUT12 20 HDD_G_7313#
2
N.C. OUT13 21 HDD_B_7313# +5VALW

OUT14
1
22
RE31 OUT15
Logic up LED board
1
10K_0402_5%~D 7 23
18 GND GND 33
GND GND RE38
2
100K_0402_5%
TLC59116FIRHBR_VQFN32_5X5
2
1 LID_SW
D
LID_SW_IN# 2 QE10
G SSM3K7002F_SC59-3
S
3
+3.3V_F347
For IND/TP/HDD/PWR
+3.3V_F347 AD3 AD2 AD1 AD0 +3.3V_F347
0 1 0 0
1
C C
1
RE45 1
RE35 4.7K_0402_1% CE53
4.7K_0402_1% UE8 0.1U_0402_16V4Z
2
24 27 2
2
RESET Vcc
3 TP_LED_R#
I2C_CLK 25 OUT0 4 TP_LED_G#
<37,38,40,41> I2C_CLK I2C_DAT 26 SCL OUT1 5 TP_LED_B#
<37,38,40,41> I2C_DAT SDA OUT2 6 LTRON_LED_R_DRV#
31 OUT3 8 LTRON_LED_R_DRV# <39>
AD0 LTRON_LED_G_DRV#
32 A0 OUT4 9 LTRON_LED_G_DRV# <39>
AD1 LTRON_LED_B_DRV#
1 A1 OUT5 10 LTRON_LED_B_DRV# <39>
AD2 RTRON_LED_R_DRV#
AD3 2 A2 OUT6 11 RTRON_LED_G_DRV# RTRON_LED_R_DRV# <39>
A3 OUT7 14 RTRON_LED_G_DRV# <39>
RTRON_LED_B_DRV#
OUT8 RTRON_LED_B_DRV# <39>
1
1
4.7K_0402_1% RE34
12 15 KB_LED_R5_DRV#
13 N.C. OUT9 16 KB_LED_R5_DRV# <39>
RE33 KB_LED_G5_DRV#
28 N.C. OUT10 17 KB_LED_G5_DRV# <39>
4.7K_0402_1% RE36 KB_LED_B5_DRV#
29 N.C. OUT11 19 KB_LED_B5_DRV# <39>
4.7K_0402_1%
30 N.C. OUT12 20
To Hot Key
2
N.C. OUT13 21
OUT14
1
22 RT4
RE41 OUT15 0_0603_5%
10K_0402_5%~D 7 23 1 2
GND GND +3VALW
18 33
GND GND +V_TP +3VS_TOUCH
2
RT5
TLC59116FIRHBR_VQFN32_5X5 0_0603_5% UT1
1 2 5 1
+3VS IN OUT
@
2
0.1U_0402_10V6K
GND 1
1 RT11
CT3
4 3 2
2200P_0402_25V7K
<43> TP_EN EN OC +5VS 1
CT2
10K_0402_5% 2
SY6288C20AAC_SOT23-5
2
HDD_B +3VALW +3VS_TOUCH
B Power ON Circuit C17
0.1U_0402_16V4Z
B
3
2
1 2
2 RT17 JPWR1
5
QE13B
DMN66D0LDW-7_SOT363-6~D +3VLP
@
CT4 For TouchPAD 100K_0402_5% +5VS_TP_LED
1
2
3
1
2
ON/OFF switch 1U_0402_6.3V6K +3VS_TOUCH
1
1 4 3
+5VS
4
+5VS 5 4
+5VALW_LED 5
2
HDD_B_7313# 6
+3VALW 6
100K_0402_5%
TOP Side RE63 TP_INT# TP_INT# 7

<43> TP_INT# 7
1
HDD_R 100K_0402_5% TP_LED_R# 8

8
RE39
TP_LED_G# 9
SW2 TP_LED_B# 10 9
1
SMT1-05-A_4P LED_R_7313#_A# 11 10
11
6
1 3 LED_G_7313#_A# 12
2
ON/OFFBTN# <43> 13 12
LED_B_7313#_A#
QE13A 2 4 HDD_R 14 13
1 14
SATA_LED_ACT 2 DMN66D0LDW-7_SOT363-6~D B+_BIAS +5VS Q2409 +5VS_TP_LED HDD_G 15
CE27 SI3456DDV-T1-GE3_TSOP6~D HDD_B 16 15
6
5
16
D
0.1U_0402_16V7K 6 PWR_R_7313# 17
S
1
17
6
300K_0402_5%~D
5 4 PWR_G_7313# 18
18
2
0.1U_0402_16V4Z
HDD_R_7313# 2 PWR_B_7313# 19
DMN66D0LDW-7_SOT363-6~D
19
R2456
1U_0603_10V4Z~D
QE12A
1 1 20
20
C29
2 HDD_G 1 TP_+ 21
G
<16> PCH_SATALED# <69> TP_+ 21
C2508
TP_- 22
3
<69> TP_- 23 22
Bottom Side
1
2 PTP_DISABLE# 24 23
<43> PTP_DISABLE# 24
3
2 PTP_KBBL# 25 31
<43> PTP_KBBL# 26 25 GND1 32
SW1 EN_TPLED LID_SW_IN#
<19,37,43> LID_SW_IN# 26 GND2
SSM3K7002FU_SC70-3~D
QE12B SMT1-05-A_4P ON/OFFBTN# 27 33

27 GND3
1.5M_0402_5%~D
0.1U_0402_25V6K~D
5 DMN66D0LDW-7_SOT363-6~D 1 3 1 CAPS_LED# 28 34
<43> CAPS_LED# 28 GND4
1
1
D
R2457
WLES ON/OFF LED# 29 35
<28> WLES ON/OFF LED# 29 GND5
C2509
2 4 2 @ NumLock LED_A# 30 36
4
<43> TP_LED_EN <43> NumLock LED_A# 30 GND6

G
HDD_G_7313# Q2410 S 2 STARC_107K30-000001-G2
6
5
2 CONN@
1
D
A
Change Symbol OK A
LID_SW 2
G
QE14
SSM3K7002F_SC59-3~D Touchpad LED circuit 2/18 -Tarry
S
3
ON/OFF switch power button
Bottom Side pop only before MP
ELC (2)/TP/PWR SW
5 4 3 2 1
A B C D E
INT_KBD Conn.
KSI[0..7]
KSI[0..7] <43>
KSO[0..17]
KSO[0..17] <43>
ACES_50552-03001-001
KB_DET# 30 31
<21> KB_DET# 29 30 GND 32
KSO7
1 KSO0 28 29 GND 1
KSI1 27 28
KSI7 26 27 +3VS
KSO9 25 26
KSI6 24 25 +3VS
24
1
KSI5 23
KSO3 22 23 R149 KB_LED_R5_DRV#_A#
22
1
KSI4 21 100K_0402_5%
KSI2 20 21 R148
20
6
KSO1 19 100K_0402_5%
Net follow Ranger.
2
KSI3 18 19 KB_LED_R5_DRV 2 G
D
KSI0 17 18 Q2411B
Only Pin26 add KSO16
S
2
KSO13 16 17 DMN66D0LDW-7_SOT363-6
1
16
3
KSO5 15
KSO2 14 15 KB_LED_R5_DRV# 5 G
D
13 14 <38> KB_LED_R5_DRV#
KSO4 S Q2411A
KSO8 12 13 DMN66D0LDW-7_SOT363-6
4
KSO6 11 12
KSO11 10 11
KSO10 9 10
KSO12 8 9
KSO14 7 8 +3VS
KSO15 6 7
KSO16 5 6 +3VS
5
1
KSO17 4
3 4 R153 KB_LED_G5_DRV#_A#
3
1
2 100K_0402_5%
GND 1 2 R152
1
6
100K_0402_5%
2
JKB1 CONN@ KB_LED_G5_DRV 2 G
D
S Q2412B
2
1
3
2 2
+5VS 5
D
KB_LED_G5_DRV# G
<38> KB_LED_G5_DRV#
0.1U_0402_16V4Z
S Q2412A
4
1
Symbol Leverage Echo13
C27
2 1
JTRONF 2/18 -Tarry +3VS
2 1
RTRON_LED_R_DRV# 3 2 +3VS
<38> RTRON_LED_R_DRV# 3
1
RTRON_LED_G_DRV# 4
<38> RTRON_LED_G_DRV# 5 4
RTRON_LED_B_DRV# R173 KB_LED_B5_DRV#_A#
<38> RTRON_LED_B_DRV# 5
1
LTRON_LED_R_DRV# 6 100K_0402_5%
<38> LTRON_LED_R_DRV# LTRON_LED_G_DRV# 7 6 R172
<38> LTRON_LED_G_DRV# 7
6
LTRON_LED_B_DRV# 8 100K_0402_5%
<38> LTRON_LED_B_DRV#
2
9 8 KB_LED_B5_DRV 2 G
D
10 9 S Q2413B
2
11 10 DMN66D0LDW-7_SOT363-6
1
11
3
12
13 12 KB_LED_B5_DRV# 5 G
D
14 GND <38> KB_LED_B5_DRV# S Q2413A

GND DMN66D0LDW-7_SOT363-6
4
ACES_50208-01201-P01
CONN@
TRON LED Board (F) CONN
Hot Key Conn. 3
+5VS +5VS
Hot Key Conn. Key Pad
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 PWM
C30
C31
JKB2 CONN@
JKB3 CONN@ KP_DET# 1 2 KP_DET#
2
JTRONL
2
JTRONR
Change Symbol OK 10
G4 9
<43> KP_DET#
KSO16 3 1
3
2 4
4 6
KSO16
KSI0 5 KSI0
1
LTRON_LED_R_DRV# 2 1 RTRON_LED_R_DRV#2
1
1
2/18 -Tarry G3 8
G2 7
KSI5
KSI1
7
9
5
7
6 8
8 10
KSI5
KSI1
LTRON_LED_G_DRV# 3 2 RTRON_LED_G_DRV#3 2 G1 KSI4 11 9 10 12 KSI4
LTRON_LED_B_DRV# 4 3 RTRON_LED_B_DRV# 4 3 6 KSI2 13 11 12 14 KSI2
4 4 +5VS 6 6 13 14 16
5 5 5 KSI3 15 KSI3
6 5 6 5 KB_LED_R5_DRV#_A# 4 5 GND 17 15 16 18 GND
7 6 7 6 KB_LED_G5_DRV#_A# 3 4 4 GND 19 17 18 20 GND
8 GND 8 GND KB_LED_B5_DRV#_A# 2 3 19 20
GND GND 1 2 2 ACES_50611-0100N-001_10P
ACES_50208-00601-P01 ACES_50208-00601-P01 1
ACES_87153-06411
CONN@ CONN@
TRON LED Board (L) CONN TRON LED Board (R) CONN
4 4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
KB/HotKey conn
Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
0.1
LA-B751P
A B C D E
5 4 3 2 1
+3VS +3VS
+3VS
1
+3VS
R144 KB_LED_R1_DRV#_A# R145 KB_LED_R3_DRV#_A#
1
100K_0402_5% 100K_0402_5%
1
R146
6
100K_0402_5% R147
2
2 2
D D
KB_LED_R1_DRV G
100K_0402_5% KB_LED_R3_DRV G
S Q28B S Q34B
2
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
1
3
3
D
K/B Backlight D
D D
KB_LED_R1_DRV# 5 G KB_LED_R3_DRV# 5 G
S Q28A S Q34A
4
+3.3V_F347
AD3 AD2 AD1 AD0
+3.3V_F347 0 0 1 0 +3.3V_F347
+3VS +3VS
1
RE32
4.7K_0402_1% +3VS
1
1
CE25 +3VS
UE4 0.1U_0402_16V4Z R150 KB_LED_G1_DRV#_A# R151 KB_LED_G3_DRV#_A#
1
100K_0402_5% 100K_0402_5%
2
1
RE26 24 27 2
RESET Vcc
6
4.7K_0402_1%~D R154 R155
2
3 2 2
D D
KB_LED_R1_DRV# 100K_0402_5% KB_LED_G1_DRV G
100K_0402_5% KB_LED_G3_DRV G
I2C_CLK 25 OUT0 4 KB_LED_G1_DRV# S Q29B S Q35B

<37,38,41> I2C_CLK
2
I2C_DAT 26 SCL OUT1 5 KB_LED_B1_DRV# DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6

<37,38,41> I2C_DAT
1
SDA OUT2
3
6 KB_LED_R2_DRV#
AD0_1 31 OUT3 8 KB_LED_G2_DRV# KB_LED_G1_DRV# 5 G
D
KB_LED_G3_DRV# 5 G
D
AD1_1 32 A0 OUT4 9 KB_LED_B2_DRV# S Q29A S Q35A

AD2_1 1 A1 OUT5 10 KB_LED_R3_DRV# DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
4
AD3_1 2 A2 OUT6 11 KB_LED_G3_DRV#
A3 OUT7 14 KB_LED_B3_DRV#
OUT8
1
12 15 KB_LED_R4_DRV#
13 N.C. OUT9 16 KB_LED_G4_DRV# +3VS +3VS
4.7K_0402_1% RE30
4.7K_0402_1% RE27
RE29 28 N.C. OUT10 17 KB_LED_B4_DRV#

4.7K_0402_1%~D 29 N.C. OUT11 19
N.C. OUT12
1
30 20 +3VS +3VS
2
N.C. OUT13 21 R156 KB_LED_B1_DRV#_A# R157 KB_LED_B3_DRV#_A#

OUT14
1
RE37 22 100K_0402_5% 100K_0402_5%

OUT15
1
10K_0402_5%
6
7 23 R158 R159
2
C 18 GND GND 33 100K_0402_5% KB_LED_B1_DRV 2 G
D
100K_0402_5% KB_LED_B3_DRV 2 G
D
C
GND GND S Q30B S Q36B
2
1
3
3
TLC59116FIRHBR_VQFN32_5X5
5 5
D D
KB_LED_B1_DRV# G KB_LED_B3_DRV# G
S Q30A S Q36A
4
+3VS +3VS
1
+3VS +3VS
R160 KB_LED_R2_DRV#_A# R161 KB_LED_R4_DRV#_A#
100K_0402_5% 100K_0402_5%
1
6
6
R162 R163
2
D D
100K_0402_5% KB_LED_R2_DRV 2 100K_0402_5% KB_LED_R4_DRV 2
Check Pin define

G G
S Q31B S Q37B
1
3
3
+5VS KB_LED_R2_DRV# 5 G
D
KB_LED_R4_DRV# 5 G
D
JKBBL1 S Q31A S Q37A

1 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
4
2 1
3 2
4 3
KB_LED_R1_DRV#_A# 5 4
KB_LED_G1_DRV#_A# 6 5 +3VS +3VS
KB_LED_B1_DRV#_A# 7 6
KB_LED_R2_DRV#_A# 8 7
8
1
B KB_LED_G2_DRV#_A# 9 +3VS +3VS B
KB_LED_B2_DRV#_A# 10 9 R164 KB_LED_G2_DRV#_A# R165 KB_LED_G4_DRV#_A#
KB_LED_R3_DRV#_A# 11 10 100K_0402_5% 100K_0402_5%
11
1
1
KB_LED_G3_DRV#_A# 12
12
6
KB_LED_B3_DRV#_A# 13 R166 2 R167
2
KB_LED_R4_DRV#_A# 14 13 100K_0402_5% KB_LED_G2_DRV 2 G
D
100K_0402_5% KB_LED_G4_DRV 2 G
D
KB_LED_G4_DRV#_A# 15 14 S Q32B S Q38B

KB_LED_B4_DRV#_A# 16 15 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
2
1
16
3
3
17
18 17 KB_LED_G2_DRV# 5 G
D
KB_LED_G4_DRV# 5 G
D
19 18 21 S Q32A S Q38A
20 19 GND 22 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
4
4
20 GND
ACES_50552-02001-001
CONN@
+3VS +3VS
（ KB BL LED ）
1
1
+3VS +3VS
R168 KB_LED_B2_DRV#_A# R169 KB_LED_B4_DRV#_A#
Symbol OK Leverage Echo13 100K_0402_5% 100K_0402_5%
1
1
2/18 -Tarry
6
6
R170 R171
2
2
2 2
D D
100K_0402_5% KB_LED_B2_DRV G 100K_0402_5% KB_LED_B4_DRV G
S Q33B S Q39B
2
1
3
3
5 5
D D
KB_LED_B2_DRV# G KB_LED_B4_DRV# G
S Q33A S Q39A
4
4
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
ELC(3)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
0.1
LA-B751P
5 4 3 2 1
5 4 3 2 1
D D
PCIE_CLK_BUFFER
+3VS
+3VS
2 1
0.1U_0402_10V7K
0.1U_0402_10V7K
CM16
CM17
1 1
1
RM18 CM19
控控
1
2.2_0402_1% 22U_0603_6.3V6M
@
2
1
RM19 2 2
EC PIN RM21
1K_0402_1%
4.7K_0402_5%
2
UM4
PCI_SMCLK 1 20
2
RM22 1 2 0_0402_5% BUF_CLK+ 2 PLL_BW_SEL VDDA 19
<18> CLK_PCIE_DGPU SRCIN GNDA
PCI_SMDAT <18> CLK_PCIE_DGPU#
<18,46> CLKREQ#_GPU 2
RM24 1
CLKREQ#_GPU
1 CLKREQ#_DGPU +3VS
2 0_0402_5% BUF_CLK1 3
4
5
SRCIN#
OE_0#
IRef
OE_1#
18
17
16
RM25 2
CLKREQ#_DGPU
1 475_0402_1%
+3VS
CLKREQ#_DGPU <18,43>
USB_PWR_EN# <18,46> CLK_PEG_GPU

DK4
CLK_PEG_GPU
CLK_PEG_GPU#
RB751V-40_SOD323-2
RM43 1
RM44 1
2 0_0402_5%
2 0_0402_5%
CLK_PEG_GPU_UM4
CLK_PEG_GPU#_UM4
6
7
8
VDD
GND
CLK0
VDD
GND
CLK1
15
14
13
2
2 RM27
1
1 33_0402_1%
CLK_PCIE_DGPU_C
CLK_PCIE_DGPU#_C
DOCKING_LED ON# <18,46> CLK_PEG_GPU# 9
10
CLK0#
VDD
CLK1#
VDD
12
11
RM28 33_0402_1%
0.1U_0402_10V7K
0.1U_0402_10V7K
SDATA SCLK
1
1
49.9_0402_1%
RM29
49.9_0402_1%
RM38
CM18
CM20
DOCKING_LED OFF# 1 1
1U_0402_6.3V
CM21
1
PI6CEQ20200LIEX
DOCK_PSID 2 2
2
2
DOCK_ACIN
C
DOCK_EN +3VS
C
PRSNT#_R
2
2
@ @
RM30 RM35
2.2K_0402_5% 2.2K_0402_5%
1
<19> SML0DATA RM37 1 2 0_0402_5% BUF_SM_DAT
<19> SML0CLK RM36 1 2 0_0402_5% BUF_SM_CLK
+3VALW
Caldera connector
1
@
RM41
1K_0402_1%
JCDRA
2
1
Caldera_ON 2 CALDERA_ ON <43> PEG_HTX_C_GRX_N[8..11] <7>
Caldera_PWRGD
T0+
3 PEG_HTX_C_GRX_P8
CALDERA_ PWRGD <43>
PEG_GTX_HRX_P[8..11] <7>
Caldera
1
4 PEG_HTX_C_GRX_N8
T0- 5 PEG_GTX_HRX_N[8..11] <7>
@
GND 6 PEG_HTX_C_GRX_P9 RM42
T1+ 7 PEG_HTX_C_GRX_N9 10M_0402_5%
T1- 8
2
GND 9 PEG_HTX_C_GRX_P10
B T2+ B
10 PEG_HTX_C_GRX_N10
T2- 11
GND 12 PEG_HTX_C_GRX_P11 0_0402_5% 2 1 RI75
T3+
T3-
13 PEG_HTX_C_GRX_N11 +3VALW
LI13
Follow Echo 13 design.
14 @EMI@
GND 15 PEG_GTX_HRX_P8 USB3RP5_R 1 2 USB3RP5_L
R0+ 1 2
1
16 PEG_GTX_HRX_N8 USB3RN5_L 0.1U_0402_10V6K 2 1 CI38 USB3RN5

R0- 17 2 1 CI39 USB3RP5 USB3RN5 <20>
RM5 USB3RP5_L 0.1U_0402_10V6K
GND 18 4 3 USB3RP5 <20>
PEG_GTX_HRX_P9 10K_0402_5% USB3RN5_R USB3RN5_L
R1+ 19 PEG_GTX_HRX_N9 4 3
R1- 20
2
GND 21 DLW21SN900HQ2L_0805_4P
CALDERA_PRSNT# 22 CALDERA_PRSNT# <37,43> 2 1
CDRA_RST# 0_0402_5% RI76
PLTRST# 23
GND 24 PEG_GTX_HRX_P10
R2+ 25 PEG_GTX_HRX_N10
R2- 26 BUTTON#
BUTTON# 27 BUTTON# <43>
CDRA_LED WHITE
LED_WHITE CDRA_LED WHITE <43>
2
28 CDRA_LED RED +3VALW
0.1U_0402_10V7K
LED_RED 29 CDRA_LED RED <43> 2 1
RM17 0_0402_5% RI77
GND 30 PEG_GTX_HRX_P11 10K_0402_5%
R3+ LI14 1
CM23
31 PEG_GTX_HRX_N11 @EMI@ 2 1
R3- 32 USB3TP5_R 1 2 USB3TP5
USB3TP5 <20>
1
GND 33 CLK_PCIE_DGPU_C 1 2 RM6

REFCLK+ 34 CLK_PCIE_DGPU#_C @ 2 10K_0402_5%
REFCLK- 35 USB3TN5_R 4 3 USB3TN5
GND 4 3 USB3TN5 <20>
5
36 USB3RN5_R
SSTX+ 37 USB3RP5_R 1
P
SSTX- 38 DLW21SN900HQ2L_0805_4P 4 B CALDERA_RST# <43>
CDRA_RST#
GND 39 USB20_P2_CONN 0_0402_5% 2 1 RI78 O 2
USBD+ A PCH_PLTRST# <17,46>
G
40 USB20_N2_CONN
USBD- 41 UM3
3
GND 42 USB3TN5_R TC7SH08FU_SSOP5
SSRX+ 43 USB3TP5_R
SSRX- 44 EMI@
GND 45 CDRA_CLK RM15 1 2 0_0402_5% LM1
I2C_CLK 46 I2C_CLK <37,38,40>
A CDRA_DAT RM16 1 2 0_0402_5% USB20_P2_CONN 3 4 USB20_P2 A
I2C_DATA 47 I2C_DAT <37,38,40> 3 4 USB20_P2 <20>
GND 48
GND 49 USB20_N2_CONN 2 1 USB20_N2
GND 50 2 1 USB20_N2 <20>
GND WCM-2012HS-900T_4P
（）
TE_2260531-1
CONN@
Symbol OK Leverage Echo13 Security Classification Compal Secret Data Compal Electronics, Inc.
2014/2/11 2014/2/11 Title
2/18 -Tarry Issued Date Deciphered Date
USB3.0
0.1
5 4 3 2 1
5 4 3 2 1
+3VS +3VS
+VGA_CORE thermal sensor
1
+3VS +5VS
R2449
REMOTE1+_2 U2409 10K_0402_5%
22U_0805_6.3VAM
1 1 @
1
C 1
CF4
@ CF2 2 CF3 1 10 EC_SMB_CK1_R
VDD SMCLK
10K_0402_5%
10K_0402_5%
10K_0402_5%
2200P_0402_25V7K B 2200P_0402_25V7K
2
2 E QF1 2 REMOTE1+_2 2 9 EC_SMB_DA1_R
3
DP1 SMDATA 2
RF1
RF2
RF3
MMBT3904WT1G_SC70-3 REMOTE1-_2 1
C2499 REMOTE1-_2 3 8
0.1U_0402_10V6K DN1 ALERT#
REMOTE2+_2 4 7
Diode circuit s used for +VGA_CORE sensor
1
D 2 DP2/DN3 THERM# D
REMOTE2-_2 5 6 JFAN1
DN2/DP3 GND 1
2 1
<43> CPU_FAN_PWM 2 1 3 2
F75303M_MSOP10
<43> CPU_FAN_FB 3
DF1 4
Address 1001_101xb SDMK0340L-7-F_SOD323-2 5 4
6 G5
2nd source G6
SKIN SA000029210-->EMC1403-2-AIZL-TR
CPU FAN Control circuit
ACES_50273-00401-001
CONN@
Diode circuit s used for skin temp sensor

(placed around DIMM).
Place C43 close to Q19as possible.
REMOTE2+_2 +3VS
1
1
C +3VS +5VS
1
2 CF8
@ CF7 B 2200P_0402_25V7K
2.2K_0402_5%~D
2
22U_0805_6.3VAM
2200P_0402_25V7K E QF2
2.2K_0402_5%~D
3
1
2 MMBT3904WT1G_SC70-3~D REMOTE2-_2 1
CF5
RF7 RF8
10K_0402_5%
10K_0402_5%
10K_0402_5%
+3VS
2
2
2
RF4
RF5
RF6
2
2
EC_SMB_CK1_R 1 6
EC_SMB_CK1 <43,58,59>
1
DMN66D0LDW-7
5
QF3A JFAN2
1
EC_SMB_DA1_R 4 3 2 1
EC_SMB_DA1 <43,58,59> <43> GPU_FAN_PWM 2 1 3 2
<43> GPU_FAN_FB 3
DF2 4
QF3B SDMK0340L-7-F_SOD323-2 5 4
DMN66D0LDW-7 6 G5
G6
ACES_50273-00401-001
GPU FAN Control circuit CONN@
C C
Fintek thermal sensor-> CPU core, DIMM

+3VS +3VS
1
R2448
U2407 10K_0402_5%
@
2
1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 <19,43,46>
REMOTE1+ 2 9 EC_SMB_DA2
DP1 SMDATA EC_SMB_DA2 <19,43,46>
1
C2498 REMOTE1- 3 8
0.1U_0402_10V6K DN1 ALERT#
REMOTE2+ 4 7
2 DP2/DN3 THERM#
REMOTE2- 5 6
DN2/DP3 GND
F75303M_MSOP10
Address 1001_101xb
2nd source
SA000029210-->EMC1403-2-AIZL-TR
REMOTE1,2 (+/-) :
REMOTE1+ BOTTOM DDR3 Trace width/space:10/10 mil
Close U2407
Trace length:<8"
1
REMOTE1+ C
1 @ C2500 2 Q2407
2200P_0402_25V7K B MMST3904-7-F_SOT323-3
2
C2502 E
3
2200P_0402_25V7K REMOTE1-
2 REMOTE1-
B B
REMOTE2+
1
REMOTE2+ BOTTOM CPU
C2504
1
2200P_0402_25V7K C
2 REMOTE2- @ C2505 2 Q2408
2200P_0402_25V7K B MMST3904-7-F_SOT323-3
2
E
3
REMOTE2-
A A
Security Classification
2014/2/11
Compal Secret Data
2014/2/11 Title
FAN/TP/PWR SW
5 4 3 2 1
5 4 3 2 1
SD028000080 0_0402_5%
+3VALW SD034120280 12K_0402_1%
Board ID
NV: 0 AMD:10 SD034100300 27K_0402_1%
2
RE64 SD034430280 43K_0402_1%
Ra 100K_0402_1%
SD034560280 56K_0402_1%
EMI@
SD034750280 75K_0402_1%
1
LE1 +EC_VCCA RE66 AMD@ AD_BID0
+3VALW FBMA-L11-160808-800LMT_0603
1
SD034100380 100K_0402_1%
2
+3VALW_EC 1 2 +EC_VCCA
1 1 2 2 Rb RE66 CE28 SD034130380 130K_0402_1%
CE29 CE30 @EMI@ @EMI@ 0_0402_5% 0.1U_0402_10V7K
D 0.1U_0402_10V7K 0.1U_0402_10V7K CE31 CE32 +3VLP
1
CE33 130K_0402_1% NV@ 2 SD034160380 160K_0402_1% D
1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_10V7K
SD034200380 200K_0402_1%
1
2 2 1 1 SD034130380
2
ECAGND SD000001B80 240K_0402_1%
ECAGND <58>
PLT_RST# SD00000G280 270K_0402_1%
1 SD034330380 330K_0402_1%
111
125
CE34 ESD@ +3VS +5VALW
22
33
96
67
9
UE5
0.047U_0402_16V4Z SD028430380 430K_0402_1%
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
2
Place CC30
1
100K_0402_5%~D
RE87
100K_0402_5%~D
RE88
1 21 CDRA_LED WHITE_R
close to RC51.1 GATEA20/GPIO00 GPIO0F
1
100K_0402_5%~D
RE85
100K_0402_5%~D
RE86
KB_RST# 2 23 BEEP#
<21> KB_RST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# <32>
SERIRQ CPU_FAN_PWM
<19> SERIRQ 4 SERIRQ GPIO12 27 CPU_FAN_PWM <42>
LPC_FRAME# GPU_FAN_PWM
<19> LPC_FRAME# 5 LPC_FRAME# ACOFF/GPIO13 GPU_FAN_PWM <42>
LPC_AD3
<19> LPC_AD3
2
@EMI@ @EMI@ LPC_AD2 7 LPC_AD3 CE35 2 1 100P_0402_50V8J ECAGND
<19> LPC_AD2 PWM Output
2
LPC_AD2
2
CE36 RE89 LPC_AD1 8 63 BATT_TEMP
<19> LPC_AD1 10 LPC_AD1 BATT_TEMP/GPIO38 64 BATT_TEMP <58>
0.1U_0402_10V7K 0_0402_5% LPC_AD0 LPC & MISC PCIE_WAKE#
2 1 1 2 <19> LPC_AD0 LPC_AD0 GPIO39 65 PCIE_WAKE# <17,30> 1 6
ADP_I CDRA_LED WHITE_R
12 ADP_I/GPIO3A 66 ADP_I <58,59> CDRA_LED WHITE <41>
CLK_PCI_LPC AD Input AD_BID0
<18> CLK_PCI_LPC 13 CLK_PCI_EC GPIO3B 75
PLT_RST# USBCHG_DET_EC# USBCHG_DET_EC# <35> QE15A
<17,28,30,31,44> PLT_RST# PCIRST#/GPIO05 GPIO42
+3VALW RE68 2 1 47K_0402_5% EC_RST# 37 76 PANEL_BKLEN PANEL_BKLEN <17> DMN66D0LDW-7_SOT363-6~D
EC_RST# IMON/GPIO43
5
EC_SCI# 20
2 1 <21> EC_SCI# 38 EC_SCII#/GPIO0E
CE37 0.1U_0402_10V7K PM_SLP_SUS#
<17> PM_SLP_SUS# GPIO1D 68 4 3
EN_INVPWR CDRA_LED RED_R
DAC_BRIG/GPIO3C 70 EN_INVPWR <25> CDRA_LED RED <41>
"TOUCH_RST" for OAK 15 only M_THERMAL#
EN_DFAN1/GPIO3D 71 M_THERMAL# <14,15>
DA Output EC_ENVDD QE15B
+3VALW 55 IREF/GPIO3E 72 EC_ENVDD <25>
KSI0 LCD_TEST DMN66D0LDW-7_SOT363-6~D
56 KSI0/GPIO30 CHGVADJ/GPIO3F LCD_TEST <25>
KSI1
KSI[0..7] KSI2 57 KSI1/GPIO31
<39> KSI[0..7] 58 KSI2/GPIO32 83
KSI3 EC_MUTE#
KSO[0..17] 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 EC_MUTE# <32>
KSI4 PM_SLP_S4# IMVP_VR_ON
<39> KSO[0..17] 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 PM_SLP_S4# <17>
KSI5 AOAC_WLAN 1 IMVP_VR_ON
2 1 USB_IN_STATUS# 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 AOAC_WLAN <28>
C KSI6 PS2 Interface SYS_PWROK CE38 ESD@ C
62 KSI6/GPIO36 EAPD/GPIO4D 87 SYS_PWROK <12,17,8>
RE99 100K_0402_5% KSI7
1 2 EN_WOL# KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 0.1U_0402_10V7K
RE79 10K_0402_5% KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F 2
1 2 LID_SW_IN# KSO2 41 KSO1/GPIO21
KSO2/GPIO22
2
RE70 10K_0402_5% KSO3 42 97 SUSACK# Place CE34 +3VS
43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 SUSACK# <17>
KSO4 EN_WOL#
2
KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_EN
EN_WOL# <30> between DE1 and RE12
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH
ME_EN <16>
PTP_DISABLE# 2 1
+3VALW_EC KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <58>
DE2 4.7K_0402_5% RE69
KSO7/GPIO27 SPI Device Interface
KSO8 47 PTP_KBBL# 2 1
KSO9 48 KSO8/GPIO28 119 PWRSHARE_EN_EC# @ESD@ 4.7K_0402_5% RE67
KSO9/GPIO29 SPIDI/GPIO5B PWRSHARE_EN_EC# <32>
1
1 2 EC_ESB_CLK KSO10 49 120 1 @ 2 TP_INT# M_THERMAL# 2 1
50 KSO10/GPIO2A SPIDO/GPIO5C 126 TP_INT# <38>
RE93 4.7K_0402_5% KSO11 SPI Flash ROM CDRA_LED RED_R RE73 0_0402_5% 10K_0402_5% RE77
1
1 2 EC_ESB_DAT KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 3V_F347_ON L03ESDL5V0CG3-2_SOT-523-3
52 KSO12/GPIO2C SPICS#/GPIO5A 3V_F347_ON <37>
RE94 4.7K_0402_5% KSO13
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73 TS_EN
KSO15/GPIO2F ENBKL/GPIO40 TS_EN <25>
KSO16 81 74 WAKE_PCH# Place DE1 close to UE1
KSO16/GPIO48 PECI_KB930/GPIO41 WAKE_PCH# <21>
KSO17 82 89 DBC_EN CE40 EMI@
+3VALW_EC KSO17/GPIO49 FSTCHG/GPIO50 90 DBC_EN <25> 2 1 100P_0402_50V8J
BATT_CHG_LED# ACIN
BATT_CHG_LED#/GPIO52 91 BATT_CHG_LED# <37>
CAPS_LED#
+3VS 77 CAPS_LED#/GPIO53 92 CAPS_LED# <38>
RE90 EC_SMB_CK1 GPIO PWR_LED#
5 4 <42,58,59> EC_SMB_CK1 78 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 93 PWR_LED# <38>
EC_SMB_CK1 EC_SMB_DA1 BATT_LOW_LED# BATT_LOW_LED# <37>
6 3 <42,58,59> EC_SMB_DA1 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95
EC_SMB_DA1 EC_SMB_CK2 SM Bus SYSON
7 2 <19,42,46> EC_SMB_CK2 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 1 2 IMVP_VR_ON SYSON <61,62,64>
EC_SMB_CK2 EC_SMB_DA2 VR_ON_R
8 1 <19,42,46> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 IMVP_VR_ON <65>
EC_SMB_DA2 PCH_DPWROK RE71 0_0402_5% 1
PM_SLP_S4#/GPIO59 PCH_DPWROK <17>
ESD@
2
2.2K_0804_8P4R_5% @ CE42 LID_SW_IN# 1 2
PM_SLP_S3# 6 100 PCH_RSMRST# RE72 0.1U_0402_10V7K CE43 0.1U_0402_10V7K
<17,37> PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 PCH_RSMRST# <17> 2
PM_SLP_S5# EC_LID_OUT# 10K_0402_5% ESD@
<17,37> PM_SLP_S5# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 EC_LID_OUT# <19> 1 2
EC_SMI# VCIN1_PH PCH_PWROK
<21> EC_SMI# 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 VCIN1_PH <58>
PS_ID VCOUT1_PH CE44 0.1U_0402_10V7K
<58> PS_ID
1
2 1 PCH_PWROK EC_ESB_CLK 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 VCOUT0_PH# ESD@
18 GPIO0B VCOUT0_PH/GPXIOA07 105 VCOUT0_PH# <60> 1 2
RE75 10K_0402_5% EC_ESB_DAT GPO BKOFF# SYS_PWROK
2 1 EN_INVPWR 19 GPIO0C BKOFF#/GPXIOA08 106 BKOFF# <25>
CLKREQ#_DGPU GPIO PBTN_OUT# CE46 0.1U_0402_10V7K
<18,41> CLKREQ#_DGPU 25 GPIO0D PBTN_OUT#/GPXIOA09 107 2 1 PBTN_OUT# <17,8>
RE80 10K_0402_5%
2 1 3V_F347_ON <38> TP_LED_EN 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 PCH_PWR_EN <45>
B CPU_FAN_FB CALDERA_ ON RE74 43_0402_1% B
<42> CPU_FAN_FB 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 CALDERA_ ON <41>
RE83 10K_0402_5% GPU_FAN_FB
<42> GPU_FAN_FB EC_TX 30 EC_PME#/GPIO15
<28> EC_TX EC_TX/GPIO16
EC_RX 31 110 ACIN
<28> EC_RX 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 ACIN <17,37,59>
PCH_PWROK EC_ON
<17> PCH_PWROK 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <60>
ON/OFFBTN# Place CE30,CE31,CE32,CE33 close to UE1
<17> ME_SUS_PWR_ACK 36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 115 ON/OFFBTN# <38>
GPI LID_SW_IN#
<38> NumLock LED_A# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 LID_SW_IN# <19,37,38>
SUSP#
SUSP#/GPXIOD05 117 SUSP# <45,61,62>
USB_PWR_EN#
GPXIOD06 118 1 USB_PWR_EN#
2 <32,34>
Reserve for ESD PECI_KB9012
122 PECI_KB9012/GPXIOD07 H_PECI <8>
AGND/AGND
SIO_SLP_S3# change to PM_SLP_S3# <62> +1.05V_PGOOD 123 XCLKI/GPIO5D 124 +V18R RE76
GND/GND
GND/GND
GND/GND
GND/GND
<39> KP_DET# XCLKO/GPIO5E V18R

1 43_0402_1%
GND0
2 1 PM_SLP_S3# CE48 UE6

EC_ESB_CLK 1 13
CE41 ESD@ 4.7U_0805_10V4Z ESB_CLK TEST_EN#
0.1U_0402_10V7K KB9012QF-A4_LQFP128_14X14 2 DEPOP#_EC 2 14 TP_EN
<32> DEPOP#_EC TP_EN <38>
11
24
35
94
113
69
SIO_SLP_S5# change to PM_SLP_S5# GPIO00 GPIO08/CAS_DAT
CE45
2 1
ESD@
PM_SLP_S5#
KB9012A3 change to ECAGND 2
LE2
1
FBMA-L11-160808-800LMT_0603
RST#
EC_ESB_DAT
3
4
RST# GPIO09
15
16
CALDERA_ PWRGD <41>
0.1U_0402_10V7K
Please close to EC KB9012A4 SA00004OB30 20mil +3VALW_EC <37,41> CALDERA_PRSNT#
5
ESB_DAT
GPIO01
GPIO0A
GPIO0B
17
CALDERA_RST#
PTP_KBBL# <38>
<41>
+3VS
0.1U_0402_10V7K
RE95 1 @ 2 0_0402_5% 6 18
<21,46> GC6_EVENT# GPIO02 GPIO0C/PWM0 USB_IN_STATUS# <32>
47K_0402_5%
1
VR_HOT# 1 7 19 RE96 1 @ 2 0_0402_5%

<65> VR_HOT# <32> CTL1 GPIO03 GPIO0D/PWM1 GPU_GC6_FB_EN <21,46>
CE50
ME_FWP PCH has internal 20K PD.

RE91
2
8 20
<32> CTL2 GPIO04 GPIO0E/PWM2 BUTTON# <41>
RE78
0_0402_5% @ 2
(suspend power rail) <17,46> GPU_PWR_LEVEL
RE97 1 @ 2 0_0402_5% 9 21 RE92 1 2 10K_0402_5%
+3VS_WLAN_NGFF
2
GPIO05 GPIO0F/PWM3
5
RST# RE98 1 @ 2 0_0402_5% 10 22

<17,46> DGPU_HOLD_RST# WLAN_WAKE# <28>
1
UE7 GPIO06 GPIO10/ESB_RUN#

P
.1U_0402_16V7K~D
<58,59,8> H_PROCHOT# H_PROCHOT# 4 2 VCOUT1_PH 11 23

Y A <38> PTP_DISABLE# GPIO07/CAS_CLK GPIO11/BaseAddOpt
NC
2
W=60mils
G
12 24
GND
GND VCC +3VALW_EC
CE55
A 1 RE82 A
1
0.1U_0402_16V4Z
100K_0402_5% 1
1
CE56
CE51 KC3810_QFN24_4X4
25
47P_0402_50V8J ME_EN
1
2
1
@ 2
RE81
SN74LVC1G06DCKR_SC70-5 1K_0402_5%
2

EC ENE-KB9012
0.1
5 4 3 2 1
5 4 3 2 1
02/18 Add TPM Function (Follow ZAM60)

+3VALW
0.1U_0402_25V6
4700P_0402_25V7K
2200P_0402_50V7K
2200P_0402_50V7K
D D
1
CT6
CZ6
CT7
CT5
UT2 TPM@
2
TPM@
TPM@
TPM@
@
3 12
10 VCC V_BAT
19 VCC
24 VCC 1
VCC GPIO_1 2
GPIO_2 17
GPIO_3 6
TPM@ RT12 1 2 33_0402_5% PCH_SPI_SI_T 26 GPIO-Express-00 7
<19> PCH_SPI_SI 1 2 23 MISO PP/GPIO
TPM@ RT13 33_0402_5% PCH_SPI_SO_T
<19> PCH_SPI_SO 1 2 21 MOSI
TPM@ RT14 33_0402_5% PCH_SPI_CLK_T
<19> PCH_SPI_CLK 1 2 22 SPI_CLK 9
TPM@ RT15 0_0402_5% PCH_SPI_CS1#_T
<19> PCH_SPI_CS1# 16 SPI_CS# TESTBI 8
PLT_RST#
<17,28,30,31,43> PLT_RST# 20 SPI_RST# TESTI
TPM_PIRQ#
<21> TPM_PIRQ# PIRQ#
5
NBO_1 13
25 NBO_2 14
PCH_SPI_CLK_T 18 GND NBO_3 15
11 GND NBO_4 27
GND NBO_5
33_0402_5%
4 28
GND NBO_6
@EMI@
RT16
AT97SC3205_TSSOP28~D
1
0.1U_0402_25V6
TPM
@EMI@
CT8
2
C C
Screw Hole
H2
H1 H3 H_3P5X3P8 H4 H6 H5 H7 H8
H_3P5X3P8 H_2P8 @ H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H16 H17 H18 H19 H20 H21 H24
@ @ @ @ @ @ @ H15 H_3P8 H_3P8 H_3P8 H_3P8 H_3P8 H_3P8 H_3P2
1
H_3P5 @ @ @ @ @ @ @
1
1
B B
1
H9 H10 H11 H12 H13 H14 H22 H23
NC H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_3P8 H_3P8
@ @ @ @ @ @ @ @
1
1
FD1 FD2 FD3 FD4
@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
1
FIDUCIAL MARK
A A

Screw Hole
0.1
5 4 3 2 1
A B C D E
+5VS and +3VS switch

1 1
+5VALW +5VS
SHORT DEFAULT
U17 J4
1 14 5VS 2 1
2 VIN1 VOUT1 13 2 1
VIN1 VOUT1
C256
10U_0603_6.3V6M
C257
10U_0603_6.3V6M
R2454 0_0402_5% C2506 @ JUMP_43X79
1 @ 2 5VS_GATE 3 12 1 2 1 1
<43,61,62> SUSP# ON1 CT1 220P_0402_50V8J
4 11
R174 10K_0402_5% VBIAS GND C2507 @
1 2 3VS_GATE 5 10 1 2 2 2
10mil ON2 CT2 470P_0402_50V7K
1 6 9 3VS
C258 +3VALW 7 VIN2 VOUT2 8
0.1U_0402_16V7K VIN2 VOUT2
15 +3VS
2 GPAD
TPS22966DPUR_SON14_2X3 J5
2 1
2 1
C260
10U_0603_6.3V6M
C261
10U_0603_6.3V6M
@ JUMP_43X79
+3VALW +5VALW
1 1
SHORT DEFAULT @
+5VALW 2 2
C262
10U_0603_6.3V6M
C263
10U_0603_6.3V6M
C264
10U_0603_6.3V6M
C265
10U_0603_6.3V6M
1 1 1 1
1
R175 2 2 2 2
2 2
100K_0402_5%
2
SUSP
1
D
SUSP# 2 Q40
G 2N7002K_SOT23-3
S
1
R176
100K_0402_5%
2
+3VALW_PCH switch
3 3
+5VALW +3VALW +3V_PCH

SHORT DEFAULT
U18 J6
1 14 3VALW_PCH 2 1
2 VIN1 VOUT1 13 2 1
VIN1 VOUT1
C266
10U_0603_6.3V6M
C267
10U_0603_6.3V6M
@ JUMP_43X79
PCH_PWR_EN 2 1 +3VALW_PCH_GATE 3 12 1 1
<43> PCH_PWR_EN ON1 CT1
RE62 4 11
0_0402_5% VBIAS GND @
5 10 2 2
10mil ON2 CT2
6 9
VIN2 VOUT2
1
C268 7 8
VIN2 VOUT2
0.01U_0603_25V7K
15
2
GPAD
TPS22966DPUR_SON14_2X3
+3VALW
+0.675VS
1
C269
10U_0603_6.3V6M
C270
10U_0603_6.3V6M
R177
1 1 22_0603_5%
1 2
2 2
D
4
2 SUSP 4
G
S Q41
2N7002K_SOT23-3
3

For Intel S3 Power Reduction DC/DC Interface
0.1
A B C D E
5 4 3 2 1
+3.3V_GFX_AON
GC6_EVENT#_D 1 2
RV50 10K_0402_5%
GPIO3_OC_WARN# 1 @ 2
RV53 10K_0402_5%
GPIO8_THERM_SHDWN# 1 2
RV527 10K_0402_5%
GPIO9_THERMAL_ALERT# 1 2
RV526 10K_0402_5%
UV1A DGPU_HOLD_RST# 2 1
RV530 10K_0402_5%~D
Part 1 of 12 GPU_PEX_RST_HOLD# 1 2
BH21 AT9 NVVDD PWM_VID RV63 10K_0402_5%
<7> PEG_HTX_C_GRX_P0 PEX_RX0 GPIO0 NVVDD PWM_VID <63>
BG21 AT7 GPU_GC6_FB_EN 3V3_MAIN_EN 1 2
<7> PEG_HTX_C_GRX_N0 PEX_RX0_N GPIO1 GPU_GC6_FB_EN <21,43>
BG23 AV1 GC6_EVENT#_D RV55 10K_0402_1%
<7> PEG_HTX_C_GRX_P1 PEX_RX1 GPIO2
BH23 AW4 GPIO3_OC_WARN# NVVDD PSI 1 2
<7> PEG_HTX_C_GRX_N1 PEX_RX1_N GPIO3 GPIO3_OC_WARN# <49>
BJ23 AW1 3V3_MAIN_EN RV35 10K_0402_1%
<7> PEG_HTX_C_GRX_P2 PEX_RX2 GPIO4 3V3_MAIN_EN <49,63>
BJ24 AT4
<7> PEG_HTX_C_GRX_N2 PEX_RX2_N GPIO5
BH24 AT1 NVVDD PSI
<7> PEG_HTX_C_GRX_P3 PEX_RX3 GPIO6 NVVDD PSI <63>
BG24 AT10 GPU_PWR_LEVEL 2 1
D BG26 AV7 RV61 100K_0402_5%~D D
<7> PEG_HTX_C_GRX_P4 PEX_RX4 GPIO8 GPIO8_THERM_SHDWN# <49>
BH26 AW7 GPIO9_THERMAL_ALERT#
BJ26 AT6 MEM_VREF
<7> PEG_HTX_C_GRX_P5 PEX_RX5 GPIO10 MEM_VREF <51,52,53,54>
BJ27 AV2
BH27 AV4 GPU_PWR_LEVEL
GPIO
<7> PEG_HTX_C_GRX_P6 PEX_RX6 GPIO12 GPU_PWR_LEVEL <17,43>
BG27 AT5
BG29 AW5
<7> PEG_HTX_C_GRX_P7 PEX_RX7 GPIO14
BH29 AV6
BJ29 AW2 RV546 1 N16@ 2 SYS_PEX_RST_MON#
BJ30 PEX_RX8 GPIO16 AW6 0_0402_5% +3.3V_GFX_AON
BH30 PEX_RX8_N GPIO17 AW3
BG30 PEX_RX9 GPIO18 AT8
BG32 PEX_RX9_N GPIO19 AV5
BH32 PEX_RX10 GPIO20 AT3 VGA_SMB_CK2 1 2
BJ32 PEX_RX10_N GPIO21 AR9 RV191 1.8K_0402_5%
BJ33 PEX_RX11 GPIO22 AV3 GPU_PEX_RST_HOLD# SYS_PEX_RST_MON# VGA_SMB_DA2 1 2
BH33 PEX_RX11_N GPIO23 AT2 RV192 1.8K_0402_5%
BG33 PEX_RX12 GPIO24
PEX_RX12_N
5
BG35 AV9
BH35 PEX_RX13 PGOOD QV13B GPU_GC6_FB_EN 1 2
BJ35 PEX_RX13_N VGA_SMB_CK2 4 3 RV37 10K_0402_5%
PEX_RX14 EC_SMB_CK2 <19,42,43>
BJ36 AY21 MEM_VREF 2 1
PEX_RX14_N DACA_RED
2
BH36 BA21 2N7002DW-T/R7_SOT363-6 RV38 100K_0402_5%~D
BG36 PEX_RX15 DACA_GREEN AW21 QV13A DGPU_PEX_RST# 1 2
PEX_RX15_N DACA_BLUE VGA_SMB_DA2 1 6 RV59 10K_0402_5%
EC_SMB_DA2 <19,42,43>
DACs
BA20
DACA_HSYNC @
CV57 1 2 0.22U_0402_10V6K PEG_GTX_HRX_P0_C BC21 AY18 2N7002DW-T/R7_SOT363-6
<7> PEG_GTX_HRX_P0 PEX_TX0 DACA_VSYNC
CV62 1 2 0.22U_0402_10V6K PEG_GTX_HRX_N0_C BD21
<7> PEG_GTX_HRX_N0 PEX_TX0_N
CV59 1 2 0.22U_0402_10V6K PEG_GTX_HRX_P1_C BE22
<7> PEG_GTX_HRX_P1 PEX_TX1 +3VS
CV60 1 2 0.22U_0402_10V6K PEG_GTX_HRX_N1_C BE23 AW18
<7> PEG_GTX_HRX_N1 PEX_TX1_N DACA_VDD
CV58 1 2 0.22U_0402_10V6K PEG_GTX_HRX_P2_C BD23 AW20
<7> PEG_GTX_HRX_P2 PEX_TX2 DACA_VREF
CV63 1 2 0.22U_0402_10V6K PEG_GTX_HRX_N2_C BC23 AY20
PCI EXPRESS
<7> PEG_GTX_HRX_N2 PEX_TX2_N DACA_RSET
CV64 1 2 0.22U_0402_10V6K PEG_GTX_HRX_P3_C BC24
<7>
<7>
<7>
PEG_GTX_HRX_P3
PEG_GTX_HRX_N3
PEG_GTX_HRX_P4
CV61
CV67
CV71
1
1
1
2
2
2
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_N3_C
PEG_GTX_HRX_P4_C
PEG_GTX_HRX_N4_C
BD24
BE26
BE25
PEX_TX3
PEX_TX3_N
PEX_TX4
PU AT EC SIDE, +3VS AND 4.7K CLKREQ#_GPU
PCH side has PU.
10K_0402_5%~D
2
@
1
RV531
CV69 1 2 0.22U_0402_10V6K PEG_GTX_HRX_P5_C BD26
<7> PEG_GTX_HRX_P5 PEX_TX5
CV68 1 2 0.22U_0402_10V6K PEG_GTX_HRX_N5_C BC26
CV65 1 2 0.22U_0402_10V6K PEG_GTX_HRX_P6_C BC27 BD4 1 2
<7> PEG_GTX_HRX_P6 PEX_TX6 I2CA_SCL
CV70 1 2 0.22U_0402_10V6K PEG_GTX_HRX_N6_C BD27 BD3 RV510 1 2 1.8K_0402_5%
<7> PEG_GTX_HRX_N6 PEX_TX6_N I2CA_SDA
CV72 1 2 0.22U_0402_10V6K PEG_GTX_HRX_P7_C BE28 RV511 1.8K_0402_5%
<7> PEG_GTX_HRX_P7 PEX_TX7
CV66 1 2 0.22U_0402_10V6K PEG_GTX_HRX_N7_C BE29 BB5 1 2
<7> PEG_GTX_HRX_N7 PEX_TX7_N I2CB_SCL
BD29 BB4 RV512 1 2 1.8K_0402_5%
BC29 PEX_TX8 I2CB_SDA RV513 1.8K_0402_5%
BC30 PEX_TX8_N BD2 I2CC_SCL_R +3.3V_GFX_AON
BD30 PEX_TX9 I2CC_SCL BD1 I2CC_SDA_R SYS_PEX_RST_MON#
PEX_TX9_N I2CC_SDA
I2C
BE31
BE32 PEX_TX10 BF3 VGA_SMB_CK2
BD32 PEX_TX10_N I2CS_SCL BE3 VGA_SMB_DA2
BC32 PEX_TX11 I2CS_SDA
C BC33 PEX_TX11_N C
1.8K_0402_1%
PEX_TX12
Address:0x9Eh and 0x9Ch
1
BD33
1.8K_0402_1%
BE34 PEX_TX12_N
RV547
RV548
+3.3V_GFX_AON BE35 PEX_TX13
<64> +1.35VS_VGA_PGOOD PEX_TX13_N
BD35
BC35 PEX_TX14 GPU_PLLVDD
2
PEX_TX14_N
2
BC36 Y39 GPU_PLLVDD

PEX_TX15 GPCPLL_AVDD0
2
5
RV56 BD36 AD11
10K_0402_5% RV62 PEX_TX15_N GPCPLL_AVDD1 AT11 QV89B
10K_0402_5% BJ21 LXS_PLLVDD I2CC_SCL_R 4 3
PEX_WAKE_N I2CC_SCL <49>
1 2
AW27 VID_PLLVDD
G
SP_PLLVDD
2
QV12 BD20 2N7002DW-T/R7_SOT363-6
<18,41> CLK_PEG_GPU
1
1 3 CLK_REQ# BC20 PEX_REFCLK AW28 QV89A

<18,41> CLKREQ#_GPU <18,41> CLK_PEG_GPU# PEX_REFCLK_N VID_PLLVDD
CLK_REQ# BB20 GC6_EVENT#_D 2 1 GC6_EVENT# I2CC_SDA_R 1 6
D
PEX_CLKREQ_N GC6_EVENT# <21,43> I2CC_SDA <49>

BB2 XTALIN
CLK
2N7002H 1N_SOT23-3 1 @ 2 PEX_TSTCLK_OUT BH38 XTALIN BA1 XTAL_OUT DV9 2N7002DW-T/R7_SOT363-6
RV54 200_0402_1% PEX_TSTCLK_OUT# BG38 PEX_TSTCLK_OUT XTALOUT 10K_0402_5% RB751S40T1G_SOD523-2
PEX_TSTCLK_OUT_N BB1 XTALOUT 1 2 RV51
XTALOUTBUFF BB3 XTALSSIN 1 2
DGPU_PEX_RST# 1 2 DGPU_PEX_RST#_R BE20 XTALSSIN RV49
RV40 1 2 0_0402_5% PEX_TERMP BJ38 PEX_RST_N 10K_0402_5%
RV57 2.49K_0402_1% PEX_TERMP +3VS
10K_0402_5%
N15E-GX-A2_BGA1745~D
RV105
GPU_GC6_FB_EN GC6@
1
D
2
RV106 UV19 2
10K_0402_5% AO3413_SOT23-3 G
1
GC6@ GC6@ S D GC6@
3
2 DGPU_PWR_EN
DGPU_PWR_EN <21,49,63>
2
GC6_EN G
S QV19
3
2N7002H 1N_SOT23-3
1 2
RV52 10M_0402_5%
YV1 DV4
GC6@ DAN202UT106_SC70-3
XTALIN 1 3XTAL_OUT GPU_GC6_FB_EN RV127 1 2 GC6_EN 2
1 3 0_0402_1% 1
GND GND FBVDD_EN <64>
+3VALW 3
0.1U_0402_10V7K
CV74 CV73 1 2
<49,63> GPU_PGOOD
1
22P_0402_50V8J 2 4 22P_0402_50V8J RV128 0_0402_5% GC6@
1
1 2 GC6@ RV125
CV212
RV58 10K_0402_5% 1K_0402_5%

2@ 27MHZ 16PF +-30PPM 7M27070004F50Q5 GC6@
2
B B
330ohms
5
DGPU_HOLD_RST# 1
(ESR=) Bead
P
<17,43> DGPU_HOLD_RST# B 4 SYS_PEX_RST_MON#

PCH_PLTRST# 2 O N16@
<17,41> PCH_PLTRST# A
G
N16@ 1 2 +1.05VS_VGA
UV14 RV187 LV15
3
TC7SH08FU_SSOP5~D 10K_0402_5% BLM18PG331SN1D_2P
LV7 N15@
2
BLM18PG181SN1D_2P
150mA
1
0_0402_5%
+3.3V_GFX_AON VID_PLLVDD 1 2 +1.05VS_VGA

RV208
10U_0603_6.3V6M
22U_0805_6.3V6M
4.7U_0402_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
47U_0805_6.3V6M~D
N15@
CV77
CV79
CV80
CV76
CV397
2 1 1 1 1
1
CV398
1
10K_0402_5%
180ohms
2
RV39
N16@
2
1 2 2 2 2
N16@ (ESR=0.2) Bead
DV8
2
SYS_PEX_RST_MON# 2 N16@ N16@ N15@ N15@
1 DGPU_PEX_RST# Under GPU

GPU_PEX_RST_HOLD# 3 (below 150mils)
BAT54A-7-F_SOT23-3
ES sample : Depop DV8,RV29 , Pop RV208 GPU_PLLVDD 1 2

+1.05VS_VGA
QS sample : pop DV8,RV29 , depop RV208

22U_0805_6.3V6M
0.1U_0402_10V7K
1 1 LV9
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
BLM18PG181SN1D_2P
CV109
CV108
1 1 1 1
CV396
CV394
CV149
CV147
2 2 2 2
2 2 30 ohms @100MHz (ESR=0.05)
A A

2014/2/11 2014/2/11 Title
N15P-GX (1/5) PEG & DAC
Custom 0.1
5 4 3 2 1
5 4 3 2 1
UV1B
UV1C
Part 2 of 12
AJ7 Part 3 of 12 AK5
BC18 AW14 AJ2 MIOAD0 MIOA_CTL3 AJ1
BD18 IFPA_TXC 3V3AUX_NC BE15 AJ6 MIOAD1 MIOA_HSYNC AK8
BH14 IFPA_TXC_N NC BF12 AJ5 MIOAD2 MIOA_VSYNC AM4
IFPA_TXD0 NC trace width: 16mils MIOAD3 MIOA_DE
BG14 BF18 AK4
BD15 IFPA_TXD0_N NC AK10 differential voltage sensing. AJ4 MIOAD4 AK1
BC15 IFPA_TXD1 NC AM10 differential 50ohm signal routing. AK9 MIOAD5 MIOA_CLKOUT AK2
D BF17 IFPA_TXD1_N NC AN10 AK3 MIOAD6 MIOA_CLKOUT_N AJ3 D
BE17 IFPA_TXD2 NC AR10 AM3 MIOAD7 MIOA_CLKIN
BD17 IFPA_TXD2_N NC AY14 AK7 MIOAD8
NC
BC17 IFPA_TXD3 NC BC11 +VGA_CORE AM2 MIOAD9 AR8
IFPA_TXD3_N NC BF15 AK6 MIOAD10 MIOB_CTL3 AM7
BH18 NC BG5 MIOAD11 MIOB_HSYNC AN7
BG18 IFPB_TXC NC BJ5 MIOB_VSYNC AR3
IFPB_TXC_N NC MIOB_DE
2
BJ15 AM8
BJ14 IFPB_TXD4 RV532 AM6 MIOBD0 AN3
BG15 IFPB_TXD4_N DIS@ 100_0402_1% AM9 MIOBD1 MIOB_CLKOUT AN2
BH15 IFPB_TXD5 AN9 MIOBD2 MIOB_CLKOUT_N AM5
BH17 IFPB_TXD5_N AN5 MIOBD3 MIOB_CLKIN
1
BG17 IFPB_TXD6 AN8 MIOBD4
BJ17 IFPB_TXD6_N AY23 VCCSENSE_VGA AR7 MIOBD5
BJ18 IFPB_TXD7 NVVDD_SENSE VCCSENSE_VGA <63> AN4 MIOBD6
IFPB_TXD7_N AN1 MIOBD7
BC14 AR6 MIOBD8
BD14 IFPC_L0 AW23 VSSSENSE_VGA AN6 MIOBD9
IFPC_L0_N GND_SENSE VSSSENSE_VGA <63> MIOBD10
BF14 AR2
BE14 IFPC_L1 MIOBD11
BD12 IFPC_L1_N
BC12 IFPC_L2 2 DIS@ 1 AJ9
BD11 IFPC_L2_N RV533 100_0402_1% AJ8 MIOACAL_PD_VDDQ
BE11 IFPC_L3 MIOACAL_PU_GND
C IFPC_L3_N C
AM1
BG12 MIOA_VREF
BH12 IFPD_L0 TEST 10K_0402_5% AR5
BJ12 IFPD_L0_N BA23 1 2 AR4 MIOBCAL_PD_VDDQ
BJ11 IFPD_L1 TESTMODE RV67 MIOBCAL_PU_GND
BH11 IFPD_L1_N AR1
BG11 IFPD_L2 BJ20 GPU_JTAG_TCK PAD~D T100 @ MIOB_VREF
BG9 IFPD_L2_N JTAG_TCK BG20 GPU_JTAG_TDI PAD~D T97 @
BH9 IFPD_L3 JTAG_TDI BH20 GPU_JTAG_TDO PAD~D T98 @
IFPD_L3_N JTAG_TDO BF20 GPU_JTAG_TMS PAD~D T99 @
BE8 JTAG_TMS BF21 GPU_JTAG_TRST# 1 2 N15E-GX-A2_BGA1745~D
BF8 IFPE_L0 JTAG_TRST_N
LVDS/TMDS
BF6 IFPE_L0_N RV69

BG6 IFPE_L1 10K_0402_5%
BD6 IFPE_L1_N
BE6 IFPE_L2
BD5 IFPE_L2_N SERIAL
BE5 IFPE_L3 BA3 ROM_CS +3VS_VGA +3VS_VGA +3VS_VGA
IFPE_L3_N ROM_CS_N
10K_0402_5%
0.1U_0402_16V4Z~D
BA2 ROM_SCLK
ROM_SCLK ROM_SCLK <55>
1
BF9 BA5 ROM_SI
BE9 IFPF_L0 ROM_SI BA4 ROM_SI <55>
ROM_SO
IFPF_L0_N ROM_SO ROM_SO <55>
RV167
BJ9 1
IFPF_L1
CV195
BJ8
BH8 IFPF_L1_N
B B
2
BG8 IFPF_L2
IFPF_L2_N not find @CRB 2
BJ6 UV10
BH6 IFPF_L3 ROM_CS 1 8
IFPF_L3_N GENERAL ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 RV169 33_0402_5%~D
BG2 AW9 2 1 RV168 33_0402_5%~D 3 SO HOLD# 6 ROM_SCLK_R 1 2 ROM_SCLK
BF2 IFPC_AUX BUFRST RV68 10K_0402_5% 4 WP# SCK 5 ROM_SI_R 1 2 ROM_SI
IFPC_AUX_N BB7 1 2 GND SI RV170 33_0402_5%~D
MULTI_STRAP_REF0_GND @
BG4 RV66 40.2K_0402_1% W25X20CLSNIG SOIC 8P
BF4 IFPD_AUX BA6 STRAP0
IFPD_AUX_N STRAP0 AW8 STRAP0 <55>
STRAP1
STRAP1 STRAP1 <55>
BG3 BA7 STRAP2
BH3 IFPE_AUX STRAP2 BA8 STRAP2 <55>
STRAP3
IFPE_AUX_N STRAP3 STRAP3 <55>
BB6 STRAP4
BJ4
BH4 IFPF_AUX
IFPF_AUX_N
STRAP4
BF1
STRAP4 <55>
W25X20CL 2M-Bit/256K-byte
THERMDP
THERMDN
BE1
SA00003GM30
+3VS_VGA
AV8 2 @ 1
CEC RV65 10K_0402_5%
A A

B 0.1
5 4 3 2 1
5 4 3 2 1
UV1D
Part 4 of 12
FBA_D0 V43 U47 FBA_CAS#_L
FBA_D0 FBA_CMD0 FBA_CAS#_L <51>
FBA_D1 V41 U48 FBA_CKE_L
FBA_D1 FBA_CMD1 FBA_CKE_L <51>
FBA_D2 V44 U49 FBA_RST#_L UV1E
FBA_D2 FBA_CMD2 FBA_RST#_L <51>
FBA_D3 V42 V48 FBA_RAS#_L
FBA_D3 FBA_CMD3 FBA_RAS#_L <51>
FBA_D4 U43 V49 FBA_MA1_MA9_L
FBA_D4 FBA_CMD4 FBA_MA1_MA9_L <51>
FBA_D5 U44 V47 FBA_MA0_MA10_L FBB_D0 D30 Part 5 of 12 C29 FBB_CAS#_L
FBA_D5 FBA_CMD5 FBA_MA0_MA10_L <51> FBB_D0 FBB_CMD0 FBB_CAS#_L <52>
FBA_D6 U41 AA49 FBA_MA12_RFU_L FBB_D1 G30 B29 FBB_CKE_L UV1F
FBA_D6 FBA_CMD6 FBA_MA12_RFU_L <51> FBB_D1 FBB_CMD1 FBB_CKE_L <52>
FBA_D7 U42 AA48 FBA_ABI#_L FBB_D2 E30 A29 FBB_RST#_L
FBA_D7 FBA_CMD7 FBA_ABI#_L <51> FBB_D2 FBB_CMD2 FBB_RST#_L <52>
FBA_D8 AA46 AC48 FBA_MA6_MA11_L FBB_D3 F30 A30 FBB_RAS#_L Part 6 of 12 UV1G
FBA_D8 FBA_CMD8 FBA_MA6_MA11_L <51> FBB_D3 FBB_CMD3 FBB_RAS#_L <52>
FBA_D9 AC46 AC49 FBA_MA7_MA8_L FBB_D4 G29 B30 FBB_MA1_MA9_L FBC_D0 A8 B3 FBC_CAS#_L
FBA_D9 FBA_CMD9 FBA_MA7_MA8_L <51> FBB_D4 FBB_CMD4 FBB_MA1_MA9_L <52> FBC_D0 FBC_CMD0 FBC_CAS#_L <53>
FBA_D10 AA45 AC47 FBA_WE#_L FBB_D5 F29 B32 FBB_MA0_MA10_L FBC_D1 D8 A4 FBC_CKE_L Part 7 of 12
FBA_D10 FBA_CMD10 FBA_WE#_L <51> FBB_D5 FBB_CMD5 FBB_MA0_MA10_L <52> FBC_D1 FBC_CMD1 FBC_CKE_L <53>
FBA_D11 AA47 AD49 FBA_MA5_BA1_L FBB_D6 J29 A32 FBB_MA12_RFU_L FBC_D2 B8 B4 FBC_RST#_L FBD_D0 AF7 AG3 FBD_CAS#_L
FBA_D11 FBA_CMD11 FBA_MA5_BA1_L <51> FBB_D6 FBB_CMD6 FBB_MA12_RFU_L <52> FBC_D2 FBC_CMD2 FBC_RST#_L <53> FBD_D0 FBD_CMD0 FBD_CAS#_L <54>
FBA_D12 Y46 AD48 FBA_MA4_BA2_L FBB_D7 H29 C32 FBB_ABI#_L FBC_D3 C8 A5 FBC_RAS#_L FBD_D1 AF9 AG2 FBD_CKE_L
FBA_D12 FBA_CMD12 FBA_MA4_BA2_L <51> FBB_D7 FBB_CMD7 FBB_ABI#_L <52> FBC_D3 FBC_CMD3 FBC_RAS#_L <53> FBD_D1 FBD_CMD1 FBD_CKE_L <54>
FBA_D13 Y49 AD47 FBA_MA2_BA0_L FBB_D8 C33 A33 FBB_MA6_MA11_L FBC_D4 C5 A6 FBC_MA1_MA9_L FBD_D2 AF6 AG1 FBD_RST#_L
FBA_D13 FBA_CMD13 FBA_MA2_BA0_L <51> FBB_D8 FBB_CMD8 FBB_MA6_MA11_L <52> FBC_D4 FBC_CMD4 FBC_MA1_MA9_L <53> FBD_D2 FBD_CMD2 FBD_RST#_L <54>
FBA_D14 Y45 AF47 FBA_MA3_BA3_L FBB_D9 E33 B33 FBB_MA7_MA8_L FBC_D5 B5 B6 FBC_MA0_MA10_L FBD_D3 AF8 AF3 FBD_RAS#_L
D FBA_D14 FBA_CMD14 FBA_MA3_BA3_L <51> FBB_D9 FBB_CMD9 FBB_MA7_MA8_L <52> FBC_D5 FBC_CMD5 FBC_MA0_MA10_L <53> FBD_D3 FBD_CMD3 FBD_RAS#_L <54> D
FBA_D15 Y48 AF48 FBA_CS#_L FBB_D10 F33 B35 FBB_WE#_L FBC_D6 D5 B11 FBC_MA12_RFU_L FBD_D4 AG7 AF1 FBD_MA1_MA9_L
FBA_D15 FBA_CMD15 FBA_CS#_L <51> FBB_D10 FBB_CMD10 FBB_WE#_L <52> FBC_D6 FBC_CMD6 FBC_MA12_RFU_L <53> FBD_D4 FBD_CMD4 FBD_MA1_MA9_L <54>
FBA_D16 AJ46 BB49 FBA_CAS#_H FBB_D11 D33 A35 FBB_MA5_BA1_L FBC_D7 C4 A11 FBC_ABI#_L FBD_D5 AG6 AF2 FBD_MA0_MA10_L
FBA_D16 FBA_CMD16 FBA_CAS#_H <51> FBB_D11 FBB_CMD11 FBB_MA5_BA1_L <52> FBC_D7 FBC_CMD7 FBC_ABI#_L <53> FBD_D5 FBD_CMD5 FBD_MA0_MA10_L <54>
FBA_D17 AG47 BA48 FBA_CKE_H FBB_D12 C30 C35 FBB_MA4_BA2_L FBC_D8 B9 C12 FBC_MA6_MA11_L FBD_D6 AG9 AC1 FBD_MA12_RFU_L
FBA_D17 FBA_CMD17 FBA_CKE_H <51> FBB_D12 FBB_CMD12 FBB_MA4_BA2_L <52> FBC_D8 FBC_CMD8 FBC_MA6_MA11_L <53> FBD_D6 FBD_CMD6 FBD_MA12_RFU_L <54>
FBA_D18 AG46 BA49 FBA_RST#_H FBB_D13 K33 A36 FBB_MA2_BA0_L FBC_D9 E11 A12 FBC_MA7_MA8_L FBD_D7 AG8 AC2 FBD_ABI#_L
FBA_D18 FBA_CMD18 FBA_RST#_H <51> FBB_D13 FBB_CMD13 FBB_MA2_BA0_L <52> FBC_D9 FBC_CMD9 FBC_MA7_MA8_L <53> FBD_D7 FBD_CMD7 FBD_ABI#_L <54>
FBA_D19 AG45 AW49 FBA_RAS#_H FBB_D14 E32 B36 FBB_MA3_BA3_L FBC_D10 D9 B12 FBC_WE#_L FBD_D8 AC5 AA2 FBD_MA6_MA11_L
FBA_D19 FBA_CMD19 FBA_RAS#_H <51> FBB_D14 FBB_CMD14 FBB_MA3_BA3_L <52> FBC_D10 FBC_CMD10 FBC_WE#_L <53> FBD_D8 FBD_CMD8 FBD_MA6_MA11_L <54>
FBA_D20 AF44 AV48 FBA_MA1_MA9_H FBB_D15 D32 B38 FBB_CS#_L FBC_D11 A9 C15 FBC_MA5_BA1_L FBD_D9 AA4 AA1 FBD_MA7_MA8_L
FBA_D20 FBA_CMD20 FBA_MA1_MA9_H <51> FBB_D15 FBB_CMD15 FBB_CS#_L <52> FBC_D11 FBC_CMD11 FBC_MA5_BA1_L <53> FBD_D9 FBD_CMD9 FBD_MA7_MA8_L <54>
FBA_D21 AF45 AV49 FBA_MA0_MA10_H FBB_D16 H39 D49 FBB_CAS#_H FBC_D12 H11 A15 FBC_MA4_BA2_L FBD_D10 AC4 AA3 FBD_WE#_L
FBA_D21 FBA_CMD21 FBA_MA0_MA10_H <51> FBB_D16 FBB_CMD16 FBB_CAS#_H <52> FBC_D12 FBC_CMD12 FBC_MA4_BA2_L <53> FBD_D10 FBD_CMD10 FBD_WE#_L <54>
FBA_D22 AD46 AN48 FBA_MA12_RFU_H FBB_D17 G39 C48 FBB_CKE_H FBC_D13 F9 B15 FBC_MA2_BA0_L FBD_D11 AC3 Y1 FBD_MA5_BA1_L
FBA_D22 FBA_CMD22 FBA_MA12_RFU_H <51> FBB_D17 FBB_CMD17 FBB_CKE_H <52> FBC_D13 FBC_CMD13 FBC_MA2_BA0_L <53> FBD_D11 FBD_CMD11 FBD_MA5_BA1_L <54>
FBA_D23 AD45 AN49 FBA_ABI#_H FBB_D18 F39 B46 FBB_RST#_H FBC_D14 J11 B17 FBC_MA3_BA3_L FBD_D12 AD4 Y2 FBD_MA4_BA2_L
FBA_D23 FBA_CMD23 FBA_ABI#_H <51> FBB_D18 FBB_CMD18 FBB_RST#_H <52> FBC_D14 FBC_CMD14 FBC_MA3_BA3_L <53> FBD_D12 FBD_CMD12 FBD_MA4_BA2_L <54>
FBA_D24 AD44 AM47 FBA_MA6_MA11_H FBB_D19 D41 A46 FBB_RAS#_H FBC_D15 E8 A17 FBC_CS#_L FBD_D13 AD2 Y3 FBD_MA2_BA0_L
FBA_D24 FBA_CMD24 FBA_MA6_MA11_H <51> FBB_D19 FBB_CMD19 FBB_RAS#_H <52> FBC_D15 FBC_CMD15 FBC_CS#_L <53> FBD_D13 FBD_CMD13 FBD_MA2_BA0_L <54>
FBA_D25 AD43 AM49 FBA_MA7_MA8_H FBB_D20 F38 A45 FBB_MA1_MA9_H FBC_D16 K17 C27 FBC_CAS#_H FBD_D14 AD5 V3 FBD_MA3_BA3_L
FBA_D25 FBA_CMD25 FBA_MA7_MA8_H <51> FBB_D20 FBB_CMD20 FBB_MA1_MA9_H <52> FBC_D16 FBC_CMD16 FBC_CAS#_H <53> FBD_D14 FBD_CMD14 FBD_MA3_BA3_L <54>
FBA_D26 AD42 AM48 FBA_WE#_H FBB_D21 G38 C44 FBB_MA0_MA10_H FBC_D17 G17 B27 FBC_CKE_H FBD_D15 AD1 V2 FBD_CS#_L
FBA_D26 FBA_CMD26 FBA_WE#_H <51> FBB_D21 FBB_CMD21 FBB_MA0_MA10_H <52> FBC_D17 FBC_CMD17 FBC_CKE_H <53> FBD_D15 FBD_CMD15 FBD_CS#_L <54>
FBA_D27 AC42 AJ47 FBA_MA5_BA1_H FBB_D22 D38 A44 FBB_MA12_RFU_H FBC_D18 J17 A27 FBC_RST#_H FBD_D16 R4 C2 FBD_CAS#_H
FBA_D27 FBA_CMD27 FBA_MA5_BA1_H <51> FBB_D22 FBB_CMD22 FBB_MA12_RFU_H <52> FBC_D18 FBC_CMD18 FBC_RST#_H <53> FBD_D16 FBD_CMD16 FBD_CAS#_H <54>
FBA_D28 AA44 AJ49 FBA_MA4_BA2_H FBB_D23 E38 B44 FBB_ABI#_H FBC_D19 G15 C26 FBC_RAS#_H FBD_D17 U3 D1 FBD_CKE_H
FBA_D28 FBA_CMD28 FBA_MA4_BA2_H <51> FBB_D23 FBB_CMD23 FBB_ABI#_H <52> FBC_D19 FBC_CMD19 FBC_RAS#_H <53> FBD_D17 FBD_CMD17 FBD_CKE_H <54>
FBA_D29 AA43 AJ48 FBA_MA2_BA0_H FBB_D24 F36 C42 FBB_MA6_MA11_H FBC_D20 K15 A26 FBC_MA1_MA9_H FBD_D18 U4 D2 FBD_RST#_H
FBA_D29 FBA_CMD29 FBA_MA2_BA0_H <51> FBB_D24 FBB_CMD24 FBB_MA6_MA11_H <52> FBC_D20 FBC_CMD20 FBC_MA1_MA9_H <53> FBD_D18 FBD_CMD18 FBD_RST#_H <54>
FBA_D30 AA42 AG48 FBA_MA3_BA3_H FBB_D25 K35 B42 FBB_MA7_MA8_H FBC_D21 K14 B26 FBC_MA0_MA10_H FBD_D19 U5 E1 FBD_RAS#_H
FBA_D30 FBA_CMD30 FBA_MA3_BA3_H <51> FBB_D25 FBB_CMD25 FBB_MA7_MA8_H <52> FBC_D21 FBC_CMD21 FBC_MA0_MA10_H <53> FBD_D19 FBD_CMD19 FBD_RAS#_H <54>
FBA_D31 AA40 AG49 FBA_CS#_H FBB_D26 E36 A42 FBB_WE#_H FBC_D22 H14 A23 FBC_MA12_RFU_H FBD_D20 V6 F2 FBD_MA1_MA9_H
FBA_D31 FBA_CMD31 FBA_CS#_H <51> FBB_D26 FBB_CMD26 FBB_WE#_H <52> FBC_D22 FBC_CMD22 FBC_MA12_RFU_H <53> FBD_D20 FBD_CMD20 FBD_MA1_MA9_H <54>
FBA_D32 AT48 AF49 FBB_D27 D36 A41 FBB_MA5_BA1_H FBC_D23 J14 B23 FBC_ABI#_H FBD_D21 V5 F1 FBD_MA0_MA10_H
FBA_D32 FBA_CMD32 FBB_D27 FBB_CMD27 FBB_MA5_BA1_H <52> FBC_D23 FBC_CMD23 FBC_ABI#_H <53> FBD_D21 FBD_CMD21 FBD_MA0_MA10_H <54>
FBA_D33 AT46 AF46 FBB_D28 G35 B41 FBB_MA4_BA2_H FBC_D24 E14 B21 FBC_MA6_MA11_H FBD_D22 Y4 L2 FBD_MA12_RFU_H
FBA_D33 FBA_CMD33 FBB_D28 FBB_CMD28 FBB_MA4_BA2_H <52> FBC_D24 FBC_CMD24 FBC_MA6_MA11_H <53> FBD_D22 FBD_CMD22 FBD_MA12_RFU_H <54>
FBA_D34 AT49 FBB_D29 F35 C39 FBB_MA2_BA0_H FBC_D25 F14 A21 FBC_MA7_MA8_H FBD_D23 Y5 L1 FBD_ABI#_H
INTERFACE A
FBA_D34 FBB_D29 FBB_CMD29 FBB_MA2_BA0_H <52> FBC_D25 FBC_CMD25 FBC_MA7_MA8_H <53> FBD_D23 FBD_CMD23 FBD_ABI#_H <54>
FBA_D35 AT47 FBB_D30 D35 B39 FBB_MA3_BA3_H FBC_D26 A14 C21 FBC_WE#_H FBD_D24 Y6 M3 FBD_MA6_MA11_H
FBA_D35 FBB_D30 FBB_CMD30 FBB_MA3_BA3_H <52> FBC_D26 FBC_CMD26 FBC_WE#_H <53> FBD_D24 FBD_CMD24 FBD_MA6_MA11_H <54>
FBA_D36 AW47 Y47 FBB_D31 E35 A39 FBB_CS#_H FBC_D27 B14 A20 FBC_MA5_BA1_H FBD_D25 Y7 M1 FBD_MA7_MA8_H
FBA_D36 FBA_DEBUG0 FBB_D31 FBB_CMD31 FBB_CS#_H <52> FBC_D27 FBC_CMD27 FBC_MA5_BA1_H <53> FBD_D25 FBD_CMD25 FBD_MA7_MA8_H <54>
FBA_D37 AW48 AR47 FBB_D32 M44 A38 FBC_D28 E12 B20 FBC_MA4_BA2_H FBD_D26 Y8 M2 FBD_WE#_H
FBA_D37 FBA_DEBUG1 FBB_D32 FBB_CMD32 FBC_D28 FBC_CMD28 FBC_MA4_BA2_H <53> FBD_D26 FBD_CMD26 FBD_WE#_H <54>
MEMORY
FBA_D38 BA47 FBB_D33 P42 C38 FBC_D29 F12 C20 FBC_MA2_BA0_H FBD_D27 AC9 R3 FBD_MA5_BA1_H
FBA_D38 FBB_D33 FBB_CMD33 FBC_D29 FBC_CMD29 FBC_MA2_BA0_H <53> FBD_D27 FBD_CMD27 FBD_MA5_BA1_H <54>
FBA_D39 AW46 FBB_D34 M43 FBC_D30 G12 C18 FBC_MA3_BA3_H FBD_D28 AC7 R1 FBD_MA4_BA2_H
INTERFACE B
FBA_D39 FBB_D34 FBC_D30 FBC_CMD30 FBC_MA3_BA3_H <53> FBD_D28 FBD_CMD28 FBD_MA4_BA2_H <54>
FBA_D40 AR46 FBB_D35 P43 FBC_D31 G14 B18 FBC_CS#_H FBD_D29 AC6 R2 FBD_MA2_BA0_H
FBA_D40 FBB_D35 FBC_D31 FBC_CMD31 FBC_CS#_H <53> FBD_D29 FBD_CMD29 FBD_MA2_BA0_H <54>
FBA_D41 AN45 FBB_D36 R45 FBC_D32 G26 D18 FBD_D30 AC8 U2 FBD_MA3_BA3_H
FBA_D41 FBB_D36 FBC_D32 FBC_CMD32 FBD_D30 FBD_CMD30 FBD_MA3_BA3_H <54>
FBA_D42 AR49 FBB_D37 R46 FBC_D33 J26 A18 FBD_D31 AC10 U1 FBD_CS#_H
FBA_D42 FBB_D37 FBC_D33 FBC_CMD33 FBD_D31 FBD_CMD31 FBD_CS#_H <54>
MEMORY
FBA_D43 AR48 FBB_D38 R43 D29 FBC_D34 F26 FBD_D32 H2 V1
INTERFACE C
FBA_D44 AT45 FBA_D43 AF41 FBA_CLK0 FBB_D39 R44 FBB_D38 FBB_DEBUG0 C41 FBC_D35 H26 FBC_D34 FBD_D33 H4 FBD_D32 FBD_CMD32 V4
FBA_D44 FBA_CLK0 FBA_CLK0 <51> FBB_D39 FBB_DEBUG1 FBC_D35 FBD_D33 FBD_CMD33
FBA_D45 AR44 AF40 FBA_CLK0# FBB_D40 M47 FBC_D36 G27 FBD_D34 H1
INTERFACE D
FBA_D45 FBA_CLK0_N FBA_CLK0# <51> FBB_D40 FBC_D36 FBD_D34
FBA_D46 AN41 AJ44 FBA_CLK1 FBB_D41 P44 FBC_D37 F27 FBD_D35 H3
FBA_D46 FBA_CLK1 FBA_CLK1 <51> FBB_D41 FBC_D37 FBD_D35
MEMORY
FBA_D47 AN42 AJ45 FBA_CLK1# FBB_D42 M46 FBC_D38 J27 FBD_D36 F5 AD3
FBA_D47 FBA_CLK1_N FBA_CLK1# <51> FBB_D42 FBC_D38 FBD_D36 FBD_DEBUG0
FBA_D48 AG40 FBB_D43 M45 FBC_D39 H27 C9 FBD_D37 E2 J3
FBA_D48 FBB_D43 FBC_D39 FBC_DEBUG0 FBD_D37 FBD_DEBUG1
MEMORY
FBA_D49 AG43 FBB_D44 P47 FBC_D40 E23 C24 FBD_D38 E4
FBA_D50 AG41 FBA_D49 FBB_D45 P49 FBB_D44 E41 FBB_CLK0 FBC_D41 D21 FBC_D40 FBC_DEBUG1 FBD_D39 D3 FBD_D38
FBA_D50 FBB_D45 FBB_CLK0 FBB_CLK0 <52> FBC_D41 FBD_D39
FBA_D51 AJ43 V46 FBA_WCK0 FBB_D46 P45 F41 FBB_CLK0# FBC_D42 D23 FBD_D40 J4
FBA_D51 FBA_WCK01 FBA_WCK0 <51> FBB_D46 FBB_CLK0_N FBB_CLK0# <52> FBC_D42 FBD_D40
FBA_D52 AJ40 V45 FBA_WCK0_N FBB_D47 P46 E42 FBB_CLK1 FBC_D43 C23 FBD_D41 L5
FBA_D52 FBA_WCK01_N FBA_WCK0_N <51> FBB_D47 FBB_CLK1 FBB_CLK1 <52> FBC_D43 FBD_D41
FBA_D53 AK40 Y42 FBB_D48 F46 D42 FBB_CLK1# FBC_D44 A24 FBD_D42 J2
FBA_D53 FBA_WCKB01 FBB_D48 FBB_CLK1_N FBB_CLK1# <52> FBC_D44 FBD_D42
FBA_D54 AK42 Y41 FBB_D49 E47 FBC_D45 B24 F15 FBC_CLK0 FBD_D43 J1 V9 FBD_CLK0
FBA_D54 FBA_WCKB01_N FBB_D49 FBC_D45 FBC_CLK0 FBC_CLK0 <53> FBD_D43 FBD_CLK0 FBD_CLK0 <54>
FBA_D55 AK41 AD41 FBA_WCK1 FBB_D50 D47 FBC_D46 E24 E15 FBC_CLK0# FBD_D44 J6 V10 FBD_CLK0#
FBA_D55 FBA_WCK23 FBA_WCK1 <51> FBB_D50 FBC_D46 FBC_CLK0_N FBC_CLK0# <53> FBD_D44 FBD_CLK0_N FBD_CLK0# <54>
FBA_D56 AK45 AD40 FBA_WCK1_N FBB_D51 D48 FBC_D47 D24 J18 FBC_CLK1 FBD_D45 H5 R6 FBD_CLK1
FBA_D56 FBA_WCK23_N FBA_WCK1_N <51> FBB_D51 FBC_D47 FBC_CLK1 FBC_CLK1 <53> FBD_D45 FBD_CLK1 FBD_CLK1 <54>
FBA_D57 AK43 AC41 FBB_D52 F48 FBC_D48 D15 K18 FBC_CLK1# FBD_D46 L9 R5 FBD_CLK1#
FBA_D57 FBA_WCKB23 FBB_D52 FBC_D48 FBC_CLK1_N FBC_CLK1# <53> FBD_D46 FBD_CLK1_N FBD_CLK1# <54>
FBA_D58 AK48 AC40 FBB_D53 H46 F32 FBB_WCK0 FBC_D49 C17 FBD_D47 L8
FBA_D58 FBA_WCKB23_N FBB_D53 FBB_WCK01 FBB_WCK0 <52> FBC_D49 FBD_D47
FBA_D59 AK49 AT44 FBA_WCK2 FBB_D54 H47 G32 FBB_WCK0_N FBC_D50 D17 FBD_D48 U10
FBA_D59 FBA_WCK45 FBA_WCK2 <51> FBB_D54 FBB_WCK01_N FBB_WCK0_N <52> FBC_D50 FBD_D48
FBA_D60 AM45 AT43 FBA_WCK2_N FBB_D55 H48 H32 FBC_D51 E17 FBD_D49 U7
FBA_D60 FBA_WCK45_N FBA_WCK2_N <51> FBB_D55 FBB_WCKB01 FBC_D51 FBD_D49
FBA_D61 AM44 AR43 FBB_D56 L45 J32 FBC_D52 F18 FBD_D50 U9
FBA_D62 AK44 FBA_D61 FBA_WCKB45 AR42 FBB_D57 L44 FBB_D56 FBB_WCKB01_N G36 FBB_WCK1 FBC_D53 E18 FBC_D52 FBD_D51 R7 FBD_D50 AF4 FBD_WCK0
FBA_D[0..63] FBA_D62 FBA_WCKB45_N FBB_D57 FBB_WCK23 FBB_WCK1 <52> FBC_D53 FBD_D51 FBD_WCK01 FBD_WCK0 <54>
FBA_D63 AM43 AM42 FBA_WCK3 FBB_D58 J46 H36 FBB_WCK1_N FBC_D54 D20 F8 FBC_WCK0 FBD_D52 R10 AF5 FBD_WCK0_N
<51> FBA_D[0..63] FBA_D63 FBA_WCK67 FBA_WCK3 <51> FBB_D58 FBB_WCK23_N FBB_WCK1_N <52> FBC_D54 FBC_WCK01 FBC_WCK0 <53> FBD_D52 FBD_WCK01_N FBD_WCK0_N <54>
C AM41 FBA_WCK3_N FBB_D59 H49 K36 FBC_D55 E20 G8 FBC_WCK0_N FBD_D53 P10 AD8 C
FBA_WCK67_N FBA_WCK3_N <51> FBB_D59 FBB_WCKB23 FBC_D55 FBC_WCK01_N FBC_WCK0_N <53> FBD_D53 FBD_WCKB01
FBA_DBI0# U40 AN47 FBB_D60 L47 J36 FBC_D56 G20 H9 FBD_D54 P8 AD9
<51> FBA_DBI0# FBA_DQM0 FBA_WCKB67 FBB_D60 FBB_WCKB23_N FBC_D56 FBC_WCKB01 FBD_D54 FBD_WCKB01_N
FBA_DBI1# AC45 AN46 FBB_D61 J49 M42 FBB_WCK2 FBC_D57 H20 G9 FBD_D55 P9 Y9 FBD_WCK1
<51> FBA_DBI1# FBA_DQM1 FBA_WCKB67_N +3VS_VGA FBB_D61 FBB_WCK45 FBB_WCK2 <52> FBC_D57 FBC_WCKB01_N FBD_D55 FBD_WCK23 FBD_WCK1 <54>
FBA_DBI2# AG44 FBB_D62 L48 M41 FBB_WCK2_N FBC_D58 F20 H12 FBC_WCK1 FBD_D56 P5 Y10 FBD_WCK1_N
<51> FBA_DBI2# FBA_DQM2 FBB_D[0..63] FBB_D62 FBB_WCK45_N FBB_WCK2_N <52> FBC_D58 FBC_WCK23 FBC_WCK1 <53> FBD_D56 FBD_WCK23_N FBD_WCK1_N <54>
FBA_DBI3# AA41 FBB_D63 L49 L42 FBC_D59 H21 J12 FBC_WCK1_N FBD_D57 P6 AA9
<51> FBA_DBI3# FBA_DQM3 LV14 <52> FBB_D[0..63] FBB_D63 FBA_WCKB45 FBC_D59 FBC_WCK23_N FBC_WCK1_N <53> FBD_D57 FBD_WCKB23
FBA_DBI4# AV45 L43 FBC_D60 F23 C11 FBD_D58 P2 AA10
<51> FBA_DBI4# FBA_DQM4 FBB_WCKB45_N FBC_D60 FBC_WCKB23 FBD_D58 FBD_WCKB23_N
FBA_DBI5# AR45 AJ39 +FB_PLLAVDD 1 2 FBB_DBI0# E29 H45 FBB_WCK3 FBC_D61 G23 D11 FBD_D59 P1 H6 FBD_WCK2
<51> FBA_DBI5# FBA_DQM5 FBA_PLL_AVDD <52> FBB_DBI0# FBB_DQM0 FBB_WCK67 FBB_WCK3 <52> FBC_D61 FBC_WCKB23_N FBD_D59 FBD_WCK45 FBD_WCK2 <54>
FBA_DBI6# AG42 FBB_DBI1# G33 H44 FBB_WCK3_N FBC_D62 H23 D26 FBC_WCK2 FBD_D60 M5 H7 FBD_WCK2_N
<51> FBA_DBI6# <52> FBB_DBI1# FBB_WCK3_N <52> FBC_WCK2 <53> FBD_WCK2_N <54>
22U_0805_6.3V6M
0.1U_0402_16V7K
FBA_DBI7# AM46 FBA_DQM6 PBY160808T-300Y-N_2P FBB_DBI2# H38 FBB_DQM1 FBB_WCK67_N J45 FBC_D[0..63] FBC_D63 K23 FBC_D62 FBC_WCK45 E26 FBC_WCK2_N FBD_D61 M6 FBD_D60 FBD_WCK45_N J8
CV148
<51> FBA_DBI7# FBA_DQM7 1 1 <52> FBB_DBI2# FBB_DQM2 FBB_WCKB67 <53> FBC_D[0..63] FBC_D63 FBC_WCK45_N FBC_WCK2_N <53> FBD_D61 FBD_WCKB45
FBB_DBI3# C36 J44 H24 FBD_D62 M7 J7
CV364
<52> FBB_DBI3# FBB_DQM3 FBB_WCKB67_N FBC_WCKB45 FBD_D[0..63] FBD_D62 FBD_WCKB45_N

FBA_EDC0 U45 DIS@ FBB_DBI4# P41 FBC_DBI0# E6 J24 FBD_D63 P7 M8 FBD_WCK3
<51> FBA_EDC[7..0] FBA_DQS_WP0 <52> FBB_DBI4# FBB_DQM4 <53> FBC_DBI0# FBC_DQM0 FBC_WCKB45_N <54> FBD_D[0..63] FBD_D63 FBD_WCK67 FBD_WCK3 <54>
FBA_EDC1 Y43 FBB_DBI5# P48 FBC_DBI1# E9 J20 FBC_WCK3 M9 FBD_WCK3_N
FBA_DQS_WP1 2 2 <52> FBB_DBI5# FBB_DQM5 <53> FBC_DBI1# FBC_DQM1 FBC_WCK67 FBC_WCK3 <53> FBD_WCK67_N FBD_WCK3_N <54>
FBA_EDC2 AF42 FBB_DBI6# F47 FBC_DBI2# H17 K20 FBC_WCK3_N FBD_DBI0# AG10 L3
FBA_DQS_WP2 <52> FBB_DBI6# FBB_DQM6 <53> FBC_DBI2# FBC_DQM2 FBC_WCK67_N FBC_WCK3_N <53> <54> FBD_DBI0# FBD_DQM0 FBD_WCKB67
FBA_EDC3 AC44 BB48 FBB_DBI7# L46 FBC_DBI3# D12 J21 FBD_DBI1# AA5 L4
FBA_DQS_WP3 FB_CLAMP <52> FBB_DBI7# FBB_DQM7 <53> FBC_DBI3# FBC_DQM3 FBC_WCKB67 <54> FBD_DBI1# FBD_DQM1 FBD_WCKB67_N
FBA_EDC4 AV47 R39 FBC_DBI4# K27 K21 FBD_DBI2# U6
FBA_DQS_WP4 FB_VREF <53> FBC_DBI4# FBC_DQM4 FBC_WCKB67_N <54> FBD_DBI2# FBD_DQM2
FBA_EDC5 AN43 FBB_EDC0 J30 FBC_DBI5# E21 FBD_DBI3# AA8
FBA_DQS_WP5 FBB_DQS_WP0 <53> FBC_DBI5# FBC_DQM5 <54> FBD_DBI3# FBD_DQM3
FBA_EDC6 AJ42 FBB_EDC1 H33 FBC_DBI6# F17 FBD_DBI4# E3
FBA_DQS_WP6 FBB_DQS_WP1 <53> FBC_DBI6# FBC_DQM6 <54> FBD_DBI4# FBD_DQM4
FBA_EDC7 AK47 FBB_EDC2 D39 FBC_DBI7# J23 FBD_DBI5# J5
FBA_DQS_WP7 <52> FBB_EDC[7..0] <53> FBC_DBI7# <54> FBD_DBI5#
1
FBB_EDC3 J35 FBB_DQS_WP2 FBC_DQM7 FBD_DBI6# U8 FBD_DQM5

FBB_DQS_WP3 <54> FBD_DBI6# FBD_DQM6
U46 RV153 FBB_EDC4 R42 FBC_EDC0 D6 FBD_DBI7# M4
FBA_DQS_RN0 FBB_DQS_WP4 FBC_DQS_WP0 <54> FBD_DBI7# FBD_DQM7
Y44 10K_0402_5% FBB_EDC5 M48 FBC_EDC1 F11
AF43 FBA_DQS_RN1 FBB_EDC6 F49 FBB_DQS_WP5 L36 +FB_PLLAVDD FBC_EDC2 H15 FBC_DQS_WP1 FBD_EDC0 AG5
FBA_DQS_RN2 FBB_DQS_WP6 FBB_PLL_AVDD <53> FBC_EDC[7..0] FBC_DQS_WP2 FBD_DQS_WP0
AC43 FBB_EDC7 J47 100mA FBC_EDC3 C14 FBD_EDC1 AD7
<54> FBD_EDC[7..0]
2
AV46 FBA_DQS_RN3 FBB_DQS_WP7 FBC_EDC4 E27 FBC_DQS_WP3 FBD_EDC2 V8 FBD_DQS_WP1

AN44 FBA_DQS_RN4 H30 FBC_EDC5 F24 FBC_DQS_WP4 FBD_EDC3 AA7 FBD_DQS_WP2
0.1U_0402_16V7K
AJ41 FBA_DQS_RN5 J33 FBB_DQS_RN0 FBC_EDC6 H18 FBC_DQS_WP5 FBD_EDC4 F4 FBD_DQS_WP3
FBA_DQS_RN6 FBB_DQS_RN1 1 FBC_DQS_WP6 FBD_DQS_WP4
AK46 E39 FBC_EDC7 G21 FBD_EDC5 L7
CV365
FBA_DQS_RN7 H35 FBB_DQS_RN2 DIS@ FBC_DQS_WP7 L26 +FB_PLLAVDD FBD_EDC6 R8 FBD_DQS_WP5
GPU_PLLVDD R41 FBB_DQS_RN3 C6 FBC_PLL_AVDD FBD_EDC7 P3 FBD_DQS_WP6
FBB_DQS_RN4 2 FBC_DQS_RN0 100mA FBD_DQS_WP7
AC39 M49 G11 AA11 +FB_PLLAVDD
L21 FB_REFPLL_DLL_AVDD0 E49 FBB_DQS_RN5 J15 FBC_DQS_RN1 AG4 FBD_PLL_AVDD
FB_REFPLL_DLL_AVDD1 FBB_DQS_RN6 FBC_DQS_RN2 FBD_DQS_RN0 100mA
0.1U_0402_10V7K
0.1U_0402_16V7K
1 J48 D14 1 AD6
FBB_DQS_RN7 FBC_DQS_RN3 FBD_DQS_RN1
0.1U_0402_10V7K
Under GPU D27 V7

CV75
CV366
1
0.1U_0402_16V7K
G24 FBC_DQS_RN4 DIS@ AA6 FBD_DQS_RN2
CV131
close to ball : L36 G18 FBC_DQS_RN5 F3 FBD_DQS_RN3 1
CV367
2 N15E-GX-A2_BGA1745~D F21 FBC_DQS_RN6 2 L6 FBD_DQS_RN4 DIS@
2 FBC_DQS_RN7 R9 FBD_DQS_RN5
P4 FBD_DQS_RN6 2
FBD_DQS_RN7
+1.35VS_VGA
Under GPU
+1.35VS_VGA N15E-GX-A2_BGA1745~D
close to ball : L26 +1.35VS_VGA
Under GPU
close to ball : AA11
1
+1.35VS_VGA
1
1
RV114 RV113 N15E-GX-A2_BGA1745~D
RV110 RV109 10K_0402_5% 10K_0402_5% RV150 RV152
10K_0402_5% 10K_0402_5% N15E-GX-A2_BGA1745~D 10K_0402_5% 10K_0402_5%
1
2
2
FBB_CKE_L RV147 RV148
2
2
FBA_CKE_L FBB_CKE_H 10K_0402_5% 10K_0402_5% FBD_CKE_L
B B
FBA_CKE_H FBD_CKE_H
FBB_RST#_L
2
FBA_RST#_L FBB_RST#_H FBC_CKE_L FBD_RST#_L
FBA_RST#_H FBC_CKE_H FBD_RST#_H
1
FBC_RST#_L
1
1
RV112 RV111 FBC_RST#_H
RV107 RV108 10K_0402_5% 10K_0402_5% RV149 RV151
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
1
2
2
RV115 RV146
2
2
10K_0402_5% 10K_0402_5%
2
Package Supported CMD Mapping
GB2B-64 H RST signal pull down resister

should be at the end of the
GB4B-128 H daisy-chain of this trace.
GB3-256 F
Mode H Mode H Mode F Mode F

Address 0..31 Address 32..63 Address 0..31 Address 32..63
CMD0 CS* CMD16 CS* CMD0 CAS* CMD16 CAS*
CMD1 A3_BA3 CMD17 A3_BA3 CMD1 CK1* CMD17 CK1*
CMD2 A2_BA0 CMD18 A2_BA0 CMD2 RST* CMD18 RST*
CMD3 A4_BA2 CMD19 A4_BA2 CMD3 RAS* CMD19 RAS*
CMD4 A5_BA1 CMD20 A5_BA1 CMD4 A1_A9 CMD20 A1_A9
CMD5 WE* CMD21 WE* CMD5 A0_A10 CMD21 A0_A10
CMD6 A7_A8 CMD22 A7_A8 CMD6 A12_RFU CMD22 A12_RFU
CMD7 A6_A11 CMD23 A6_A11 CMD7 ABI* CMD23 ABI*
CMD8 ABI* CMD24 ABI* CMD8 A6_A11 CMD24 A6_A11
A CMD9 A12_RFU CMD25 A12_RFU CMD9 A7_A8 CMD25 A7_A8 A
CMD10 A0_A10 CMD26 A0_A10 CMD10 WE* CMD26 WE*

CMD11 A1_A9 CMD27 A1_A9 CMD11 A5_BA1 CMD27 A5_BA1
CMD12 RAS* CMD28 RAS* CMD12 A4_BA2 CMD28 A4_BA2
CMD13 RST* CMD29 RST* CMD13 A2_BA0 CMD29 A2_BA0
CMD14 CK1* CMD30 CK1* CMD14 A3_BA3 CMD30 A3_BA3
CMD15 CAS* CMD31 CAS* CMD15 CS* CMD31 CS*
CMD32 NO USED CMD32 NO USED
CMD33 NO USED CMD33 NO USED Security Classification Compal Secret Data
CMD34 Debug0 CMD34 Debug0 Issued Date 2014/2/11 Deciphered Date 2014/2/11 Title
CMD35 Debug1 CMD35 Debug1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (5/5) POWER/ GND
5 4 3 2 1
5 4 3 2 1
UV1H +3VS_VGA
+3VS_VGA
For GDDR5 setting. Near GPU 3500mA Under GPU Near GPU +1.05VS_VGA
100P_0402_50V8J~D
Part 8 of 12 1
+1.35VS_VGA
CV408
AA39 AW33
AC11 FBVDDQ PEX_IOVDD AY32
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CV137
CV138
CV85
CV86
CV88
CV87
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
AD10 FBVDDQ PEX_IOVDD AY33 2
CV81
CV93
CV89
CV90
CV139
CV140
CV117
CV118
CV96
CV114
CV119
CV95
CV99
CV94
CV98
CV111
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 2 2 2 2 1 1 1 1 1 1 FBVDDQ PEX_IOVDD 1 1 1 1 1 1 2 2 2 2
10K_0402_1%
10K_0402_1%
1.8K_0402_1%
AD39 AY35
FBVDDQ PEX_IOVDD
1
1.8K_0402_1%
AF11 BA33
FBVDDQ PEX_IOVDD
RV551
RV552
RV243
RV242
AF39 BA35
1 1 1 1 1 1 2 2 2 2 2 2 AG39 FBVDDQ PEX_IOVDD BB33 2 2 2 2 2 2 1 1 1 1 UV20
AK39 FBVDDQ PEX_IOVDD 4 16
AM39 FBVDDQ AY24 VS VPU
2
AM40 FBVDDQ PEX_IOVDDQ AY26
AN40 FBVDDQ PEX_IOVDDQ AY27 +1.05VS_VGA VIN1N 11 13
B47 FBVDDQ PEX_IOVDDQ AY29 VIN1P 12 IN-1 TC
+1.35VS_VGA C45 FBVDDQ PEX_IOVDDQ AY30 IN+1 10
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
D FBVDDQ PEX_IOVDDQ PV D
CV144
CV146
CV143
CV145
CV110
CV116
CV120
CV115
C46 BA24 14
CV83
CV91
CV82
CV84
CV92
CV97
VIN2N 0_0402_5%
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 1 1 1 1 1 1 FBVDDQ PEX_IOVDDQ 1 1 1 1 IN-2
C47 BA26 VIN2P 15 9 RV553 1 @ 2
FBVDDQ PEX_IOVDDQ IN+2 Critical GPIO8_THERM_SHDWN# <46>
D44 BA27
D45 FBVDDQ PEX_IOVDDQ BA29 1 8 RV554 1 2 0_0402_5%
2 2 2 2 2 2 2 2 2 2 D46 FBVDDQ PEX_IOVDDQ BA30 2 2 2 2 +3VS_VGA +3.3V_GFX_AON 2 IN-3 Warning GPIO3_OC_WARN# <46>
E44 FBVDDQ PEX_IOVDDQ BA32 IN+3 5 RV241 2 1 10K_0402_1%
FBVDDQ PEX_IOVDDQ A0
1
E45 BB24 I2CC_SCL 6
FBVDDQ PEX_IOVDDQ <46> I2CC_SCL SCL
F42 BB27 RV534 RV535 I2CC_SDA 7 3
Near GPU
POWER
F44 FBVDDQ PEX_IOVDDQ BB30 <46> I2CC_SDA SDA GND
FBVDDQ PEX_IOVDDQ 0_0402_5% 0_0402_5%
F45
+1.35VS_VGA Under GPU(below 150mils) G41 FBVDDQ N15@ N16@
INA3221AIRGVR_VQFN16_4X4
2
G42 FBVDDQ
H41
H42
FBVDDQ
FBVDDQ PEX_PLL_HVDD
AW30
AW32
PEX_PLL_HVDD 210mA
CV141
CV142
CV100
CV101
CV102
CV103
CV112
CV113
CV105
CV107
CV104
CV106
CV136
CV135
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 FBVDDQ PEX_SVDD_3V3
H43 AW26
CV122
CV123
CV121
PEX_PLLVDD 1 1 1
J38 FBVDDQ PEX_PLLVDD
J39 FBVDDQ +3VS_VGA
2 2 2 2 2 2 2 2 2 2 2 2 2 2 J42
J43
FBVDDQ
FBVDDQ VDD33
AW15
AY15
Under GPU 2 2 2 CSSP_B+1 2 VIN1P
FBVDDQ VDD33 <63> CSSP_B+
1U_0603_10V6K
K24 AJ10
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0805_25V6-K
RV540 10_0402_1%
FBVDDQ VDD33
CV127
CV128
CV129
CV130
CV409
K26 AJ11 1 1 1 1 2
K29 FBVDDQ VDD33 AK11
K30 FBVDDQ VDD33 AM11
K32 FBVDDQ VDD33 AN11 +1.05VS_VGA
+1.35VS_VGA L14
L15
FBVDDQ
FBVDDQ
VDD33
VDD33
AR11 2 2 2 2 Under GPU 1
FBVDDQ
1U_0603_10V6K
L17 AW17
4.7U_0805_25V6-K
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CSSN_B+ VIN1N
FBVDDQ 3V3_MISC <63> CSSN_B+
CV209
CV206
CV207
CV208
CV205
CV215
CV203
CV204
CV126
CV124
CV125
1 1 1 1 1 1 1 1 L18 AY17 1 1 1 RV542 10_0402_1%
L20 FBVDDQ 3V3_MISC
L23 FBVDDQ BB15
L24 FBVDDQ IFPAB_PLLVDD BE18
2 2 2 2 2 2 2 2 L27 FBVDDQ IFPAB_RSET 2 2 2 CSSP_VGA1 2 VIN2P
FBVDDQ <63> CSSP_VGA
10U_0603_6.3V6M
L29 BB17 RV543 10_0402_1%
L30 FBVDDQ IFPA_IOVDD BA17
CV410
FBVDDQ IFPA_IOVDD 2
L32
L33 FBVDDQ BA18
L35 FBVDDQ IFPB_IOVDD BB18
C L41 FBVDDQ IFPB_IOVDD 1 C
P11 FBVDDQ BB12
P39 FBVDDQ IFPC_PLLVDD BB14 CSSN_VGA1 2 VIN2N
FBVDDQ IFPC_RSET <63> CSSN_VGA
R11 RV544 10_0402_1%
R40 FBVDDQ BA11
FBVDD/FBVDDQ U11 FBVDDQ IFPC_IOVDD BA12
(+1.35VS_VGA) 22uF 10uF 4.7uF 1uF 0.1uF U39 FBVDDQ IFPC_IOVDD
V11 FBVDDQ BB11
V39 FBVDDQ IFPD_PLLVDD BE12
V40 FBVDDQ IFPD_RSET
GPU 6 6 10 14 8 Y11 FBVDDQ BA14
Y40 FBVDDQ IFPD_IOVDD BA15
FBVDDQ IFPD_IOVDD
BB9
Memory 2X8 4X8 10X8 IFPEF_PLVDD BF11
IFPEF_RSET +3VS_VGA +3.3V_GFX_AON
AG11 BC8 N15@
AF10 PROBE_FBVDDQ IFPE_IOVDD BD8 RV536 1 2 0_0402_5%
PROBE_FB_GND IFPE_IOVDD
IFPF_IOVDD
IFPF_IOVDD
BC9
BD9
3V3_MISC RV537 1 2 0_0402_5%
+3.3V_GFX_AON
1U_0603_10V6K
0.1U_0402_10V7K
4.7U_0805_25V6-K
N16@
+3.3V_GFX_AON
CV132
CV133
CV134
1 1 1
+5VALW +3VS
22uF 10uF 4.7uF 1uF 0.1uF R49 +3VS
<64> FB_VDDQ_SENSE FB_VDDQ_SENSE QV86
1
2 2 2
100K_0402_5%
LP2301ALT1G_SOT23-3
FBx_PLL_DLL_AVDD
RV210
0.1U_0402_25V6
1
+1.35VS_VGA
+GPU_PLLVDD(1.05)
10K_0402_5%
3
D
1
CV363
FBx_PLL_AVDD
2
1 2 P40 RV538
G
1 1X4
2
FB_CAL_PD_VDDQ
+FB_PLLAVDD(3.3) RV771 2 40.2_0402_1% R48 DGPU_PWR_EN#
2
RV781 2 40.2_0402_1% R47 FB_CAL_PU_GND
FB_CALTERM_GND
L2N7002WT1G_SC-70-3
RV79 60.4_0402_1%
1
D
QV87
2 RV549
B 22uF 10uF 4.7uF 1uF 0.1uF Place near balls <21,46,63> DGPU_PWR_EN
G 470_0603_5% B
S @
3
12
PEX_IOVDD/Q(1.05) 4 4 2 4 D RV550 @
2 1 2 DGPU_PWR_EN#
QV90 G 10K_0402_5%
CV78
0.1U_0402_10V7K
2N7002K_SOT23-3 S
PEX_PLLVDD(1.05) 1 1 1 @ 1
3
PEX_SVDD_3V3 @
2 1
+3.3V_GFX_AON +3VS_VGA / +1.05VS_VGA 2
+3.3V_GFX_AON
1
10K_0402_5%
22uF 10uF 4.7uF 1uF 0.1uF RV541 +3.3V_GFX_AON
3V3_Main +3VS_VGA
1 1 2
2
+3VS_VGA 1
UV11
14
60 mil
2 VIN1 VOUT1 13
3V3_AON VIN1 VOUT1 CV368
+3.3V_GFX_AON 1 1 1 3V3_MAIN_EN 3 12 1 2 220P_0402_50V8J
<46,63> 3V3_MAIN_EN ON1 CT1 @
4 11
VBIAS GND CV369
GPU_PGOOD 5 10 1 2 220P_0402_50V8J +1.05VS_VGA
<46,63> GPU_PGOOD ON2 CT2 @
+1.05VS 6 9
7 VIN2 VOUT2 8
VIN2 VOUT2 60 mil
15
1.05V 22uF 10uF 4.7uF 1uF 0.1uF GPAD
A AOZ1331_SON14_2X3 A
SP_PLLVDD
VID_PLLVDD 1 1 1X2
GPU_PLLAVDD
1 5

5 4 3 2 1
5 4 3 2 1
UV1K UV1L
+VGA_CORE +VGA_CORE
+VGA_CORE +VGA_CORE UV1J Part 11 of 12 BB32 Part 12 of 12 K2
Part 10 of 12 A2 AJ25 BB34 GND GND K4
UV1I BA39 BH48 A3 GND GND AJ27 BB35 GND GND K42
AA14 AH31 BA42 VDD VDD BH49 A47 GND GND AJ29 BB36 GND GND K45
AA16 VDD Part 9 of 12 VDD AJ14 BA43 VDD VDD BJ39 A48 GND GND AJ31 BB8 GND GND K46
AA18 VDD VDD AJ16 BA44 VDD VDD BJ41 AA15 GND GND AK14 BC2 GND GND K48
AA24 VDD VDD AJ22 BB37 VDD VDD BJ45 AA21 GND GND AK20 BC5 GND GND L13
AA26 VDD VDD AJ24 BB38 VDD VDD BJ46 AA23 GND GND AK22 BE10 GND GND L16
AA28 VDD VDD AJ26 BB39 VDD VDD BJ47 AA25 GND GND AK24 BE13 GND GND L19
D
AA30 VDD VDD AJ28 BB40 VDD VDD BJ48 AA27 GND GND AK26 BE16 GND GND L22 D
AA32 VDD VDD AJ30 BB41 VDD VDD P15 AA29 GND GND AK28 BE19 GND GND L25
AB15 VDD VDD AJ32 BB42 VDD VDD P17 AA31 GND GND AK30 BE2 GND GND L28
AB17 VDD VDD AK15 BB43 VDD VDD P19 AB11 GND GND AK32 BE21 GND GND L31
AB19 VDD VDD AK17 BB44 VDD VDD P21 AB14 GND GND AL11 BE24 GND GND L34
AB21 VDD VDD AK19 BB45 VDD VDD P23 AB16 GND GND AL15 BE27 GND GND L37
AB23 VDD VDD AK21 BB46 VDD VDD P25 AB18 GND GND AL17 BE30 GND GND N11
AB25 VDD VDD AK23 BB47 VDD VDD P27 AB2 GND GND AL19 BE33 GND GND N2
AB27 VDD VDD AK25 BC38 VDD VDD P29 AB20 GND GND AL2 BE36 GND GND N39
AB29 VDD VDD AK27 BC39 VDD VDD P31 AB22 GND GND AL21 BE37 GND GND N4
AB31 VDD VDD AK29 BC41 VDD VDD R14 AB24 GND GND AL23 BE4 GND GND N41
AC14 VDD VDD AK31 BC42 VDD VDD R16 AB26 GND GND AL25 BE7 GND GND N42
AC16 VDD VDD AL14 BC45 VDD VDD R18 AB28 GND GND AL27 BF10 GND GND N45
AC18 VDD VDD AL16 BC46 VDD VDD R20 AB30 GND GND AL29 BF13 GND GND N46
AC20 VDD VDD AL18 BD38 VDD VDD R22 AB32 GND GND AL31 BF16 GND GND N48
AC28 VDD VDD AL26 BD44 VDD VDD R30 AB42 GND GND AL42 BF24 GND GND P14
AC30 VDD VDD AL28 BD45 VDD VDD R32 AB45 GND GND AL45 BF25 GND GND P16
AC32 VDD VDD AL30 BD46 VDD VDD T15 AB46 GND GND AL46 BF26 GND GND P18
AD15 VDD VDD AL32 BD47 VDD VDD T17 AB48 GND GND AL48 BF27 GND GND P20
AD17 VDD VDD AM15 BD48 VDD VDD T19 AB5 GND GND AL5 BF28 GND GND P22
AD19 VDD VDD AM17 BD49 VDD VDD T21 AB8 GND GND AL8 BF29 GND GND P24
AD21 VDD VDD AM19 BE38 VDD VDD T23 AB9 GND GND AL9 BF30 GND GND P26
AD23 VDD VDD AM21 BE39 VDD VDD T25 AC15 GND GND AM14 BF31 GND GND P28
AD29 VDD VDD AM27 BE42 VDD VDD T31 AC21 GND GND AM20 BF34 GND GND R15
AD31 VDD VDD AM29 BE43 VDD VDD U14 AC23 GND GND AM22 BF35 GND GND R17
AE14 VDD VDD AM31 BE44 VDD VDD U16 AC25 GND GND AM24 BF36 GND GND R19
AE16 VDD VDD AM32 BE45 VDD VDD U18 AC27 GND GND AM26 BF37 GND GND R21
AE18 VDD VDD AN39 BE46 VDD VDD U20 AC29 GND GND AM28 BF5 GND GND R23
AE20 VDD VDD AP39 BE47 VDD VDD U22 AC31 GND GND AM30 BF7 GND GND R25
AE22 VDD VDD AR39 BE48 VDD VDD U24 AD14 GND GND AP11 BG1 GND GND R27
AE24 VDD VDD AR40 BE49 VDD VDD U26 AD16 GND GND AP2 BH1 GND GND R29
AE26 VDD VDD AR41 BF38 VDD VDD U28 AD18 GND GND AP4 BH10 GND GND R31
AE28 VDD VDD AT39 BF39 VDD VDD U30 AD20 GND GND AP41 BH13 GND GND T11
C C
AE30 VDD VDD AT40 BF40 VDD VDD U32 AD22 GND GND AP42 BH16 GND GND T14
AE32 VDD VDD AT41 BF41 VDD VDD V15 AD24 GND GND AP45 BH19 GND GND T16
AF15 VDD VDD AU39 BF42 VDD VDD V17 AD26 GND GND AP46 BH2 GND GND T18
AF21 VDD VDD AV41 BF45 VDD VDD V23 AD32 GND GND AP8 BH28 GND GND T22
AF23 VDD VDD AV42 BF46 VDD VDD V25 AE11 GND GND AP9 BH31 GND GND T24
AF25 VDD VDD AV43 BF47 VDD VDD V27 AE15 GND GND AT42 BH34 GND GND T26
AF27 VDD VDD AV44 BF48 VDD VDD V29 AE17 GND GND AU11 BH37 GND GND T28
AF29 VDD VDD AW35 BF49 VDD VDD V31 AE19 GND GND AU2 BH5 GND GND T30
AF31 VDD VDD AW36 BG39 VDD VDD W14 AE2 GND GND AU4 BH7 GND GND T32
AG14 VDD VDD AW37 BG41 VDD VDD W16 AE21 GND GND AU45 BJ2 GND GND T39
AG16 VDD VDD AW41 BG42 VDD VDD W18 AE23 GND GND AU46 BJ3 GND GND T4
AG18 VDD VDD AW42 BG44 VDD VDD W20 AE25 GND GND AU48 C1 GND GND T41
AG24 VDD VDD AW45 BG47 VDD VDD W26 AE31 GND GND AU9 D10 GND GND T46
AG26 VDD VDD AY36 BG48 VDD VDD W28 AE39 GND GND AW13 D13 GND GND T48
AG28 VDD VDD AY42 BG49 VDD VDD W30 AE4 GND GND AW16 D16 GND GND T5
AG30 VDD VDD AY45 BH39 VDD VDD W32 AE41 GND GND AW19 D19 GND GND T8
AG32 VDD VDD BA36 BH40 VDD VDD Y15 AE42 GND GND AW22 D22 GND GND T9
AH15 VDD VDD BA37 BH41 VDD VDD Y17 AE45 GND GND AW25 D25 GND GND U15
AH17 VDD VDD BA38 BH42 VDD VDD Y19 AE46 GND GND AW29 D28 GND GND U17
AH19 VDD VDD Y31 BH43 VDD VDD Y21 AE48 GND GND AW31 D31 GND GND U19
AH21 VDD VDD BH44 VDD VDD Y23 AE5 GND GND AW34 D34 GND GND U21
AH23 VDD BH45 VDD VDD Y25 AE8 GND GND AY2 D37 GND GND U23
AH25 VDD BH46 VDD VDD Y27 AE9 GND GND AY4 D4 GND GND U25
AH27 VDD BH47 VDD VDD Y29 AF14 GND GND AY46 D40 GND GND U27
AH29 VDD VDD VDD AF16 GND GND AY48 D43 GND GND U29
VDD AF18 GND GND AY5 D7 GND GND U31
N15E-GX-A2_BGA1745~D AF20 GND GND AY8 E10 GND GND V14
N15E-GX-A2_BGA1745~D GND GND GND GND
AF22 B1 E13 V16
AF24 GND GND B10 E16 GND GND V18
B NVVDD 22uF 10uF 4.7uF 0.1uF AG15 GND GND B22 E31 GND GND V28 B
AG17 GND GND B25 E34 GND GND V30
AG19 GND GND B28 E37 GND GND V32
AG21 GND GND B31 E40 GND GND W11
+VGA_CORE 11 4 40 20 AG23 GND GND B34 E43 GND GND W15
AH11 GND GND B48 F6 GND GND W23
AH14 GND GND B49 G2 GND GND W25
+VGA_CORE AH16 GND GND B7 G4 GND GND W27
AH18 GND GND BA13 G45 GND GND W29
CV159
CV325
CV323
CV319
CV317
CV324
CV318
CV322
CV320
CV321
1 1 1 1 1 1 1 1 1 1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K

AH24 GND GND BA25 H10 GND GND W41
2 2 2 2 2 2 2 2 2 2 AH28 GND GND BA31 H16 GND GND W45
AH32 GND GND BB10 H22 GND GND W48
+VGA_CORE AH4 GND GND BB16 H28 GND GND W8
AH42 GND GND BB22 H34 GND GND Y14
CV326
CV335
CV332
CV329
CV328
CV334
CV327
CV333
CV331
CV330
1 1 1 1 1 1 1 1 1 1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K

AH5 GND GND BB28 J13 GND GND Y22
2 2 2 2 2 2 2 2 2 2 AH8 GND GND BB29 J16 GND GND Y24
AH9 GND GND BB31 J19 GND GND Y26
AJ15 GND GND Y32 J22 GND GND Y28
AJ17 GND GND J25 GND GND Y30
AJ19 GND J28 GND GND J34
AJ21 GND AW24 J31 GND GND J37
AJ23 GND GND BB21 GND GND
GND GND
A +VGA_CORE A
0.1U_0402_10V7K
0.1U_0402_10V7K
CV379
CV380
1 1 1 1 1 1 1 N15E-GX-A2_BGA1745~D
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
CV411
CV412
CV413
CV414
CV415
2 2 2 2 2 2 2

5 4 3 2 1
5 4 3 2 1
Memory Partition A - Lower 32 bits MF=0 MF=1

UV6 UV7
FBA_D[0..63] MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

<48> FBA_D[0..63]
FBA_EDC[7..0] A4 FBA_D0 A4 FBA_D56
<48> FBA_EDC[7..0] DQ24 DQ0 DQ24 DQ0
FBA_EDC0 C2 A2 FBA_D1 FBA_EDC7 C2 A2 FBA_D57
FBA_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 FBA_EDC6 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D58
FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D3 FBA_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D59
R2 EDC2 EDC1 DQ27 DQ3 E4 R2 EDC2 EDC1 DQ27 DQ3 E4
FBA_EDC3
EDC3 EDC0 DQ28 DQ4
FBA_D4 BYTE0 FBA_EDC4
EDC3 EDC0 DQ28 DQ4
FBA_D60 BYTE7
E2 FBA_D5 E2 FBA_D61
DQ29 DQ5 F4 FBA_D6 DQ29 DQ5 F4 FBA_D62
FBA_DBI0# D2 DQ30 DQ6 F2 FBA_D7 FBA_DBI7# D2 DQ30 DQ6 F2 FBA_D63
D <48> FBA_DBI0# DBI0# DBI3# DQ31 DQ7 <48> FBA_DBI7# DBI0# DBI3# DQ31 DQ7 D
FBA_DBI1# D13 A11 FBA_D8 FBA_DBI6# D13 A11 FBA_D48
<48> FBA_DBI1# DBI1# DBI2# DQ16 DQ8 <48> FBA_DBI6# DBI1# DBI2# DQ16 DQ8
FBA_DBI2# P13 A13 FBA_D9 FBA_DBI5# P13 A13 FBA_D49
FBA_DBI3# P2 B11 FBA_D10 FBA_DBI4# P2 B11 FBA_D50
B13 FBA_D11 BYTE1 B13 FBA_D51
J12 DQ19 DQ11 E11 J12 DQ19 DQ11 E11
<48> FBA_CLK0
FBA_CLK0
CK DQ20 DQ12
FBA_D12
<48> FBA_CLK1
FBA_CLK1
CK DQ20 DQ12
FBA_D52 BYTE6
FBA_CLK0# J11 E13 FBA_D13 FBA_CLK1# J11 E13 FBA_D53
<48> FBA_CLK0# CK# DQ21 DQ13 <48> FBA_CLK1# CK# DQ21 DQ13
FBA_CKE_L J3 F11 FBA_D14 FBA_CKE_H J3 F11 FBA_D54
<48> FBA_CKE_L CKE# DQ22 DQ14 <48> FBA_CKE_H CKE# DQ22 DQ14
F13 FBA_D15 F13 FBA_D55
DQ23 DQ15 U11 FBA_D16 DQ23 DQ15 U11 FBA_D40
FBA_MA2_BA0_L H11 DQ8 DQ16 U13 FBA_D17 FBA_MA4_BA2_H H11 DQ8 DQ16 U13 FBA_D41
<48> FBA_MA2_BA0_L BA0/A2 BA2/A4 DQ9 DQ17 <48> FBA_MA4_BA2_H BA0/A2 BA2/A4 DQ9 DQ17
FBA_MA5_BA1_L K10 T11 FBA_D18 FBA_MA3_BA3_H K10 T11 FBA_D42
FBA_MA4_BA2_L K11 T13 FBA_D19 BYTE2 FBA_MA2_BA0_H K11 T13 FBA_D43
FBA_MA3_BA3_L H10 N11 FBA_D20 FBA_MA5_BA1_H H10 N11 FBA_D44 BYTE5
N13 FBA_D21 N13 FBA_D45
DQ13 DQ21 M11 FBA_D22 DQ13 DQ21 M11 FBA_D46
FBA_MA7_MA8_L K4 DQ14 DQ22 M13 FBA_D23 FBA_MA0_MA10_H K4 DQ14 DQ22 M13 FBA_D47
<48> FBA_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 <48> FBA_MA0_MA10_H A8/A7 A10/A0 DQ15 DQ23
FBA_MA1_MA9_L H5 U4 FBA_D24 FBA_MA6_MA11_H H5 U4 FBA_D32
FBA_MA0_MA10_L H4 U2 FBA_D25 FBA_MA7_MA8_H H4 U2 FBA_D33
FBA_MA6_MA11_L K5 T4 FBA_D26 FBA_MA1_MA9_H K5 T4 FBA_D34
FBA_MA12_RFU_L J5 T2 FBA_D27 BYTE3 FBA_MA12_RFU_H J5 T2 FBA_D35 BYTE4
<48> FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 <48> FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27
N4 FBA_D28 N4 FBA_D36
A5 DQ4 DQ28 N2 FBA_D29 A5 DQ4 DQ28 N2 FBA_D37
U5 VPP/NC DQ5 DQ29 M4 FBA_D30 +1.35VS_VGA U5 VPP/NC DQ5 DQ29 M4 FBA_D38
2 RV116 1 VPP/NC DQ6 DQ30 M2 FBA_D31 2 RV117 1 VPP/NC DQ6 DQ30 M2 FBA_D39
1K_0402_1% DQ7 DQ31 1K_0402_1% DQ7 DQ31
J1 +1.35VS_VGA J1 +1.35VS_VGA
2 RV118 1 J10 MF 2 RV119 1 J10 MF
2 RV120 1 1K_0402_1% J13 SEN B1 2 RV121 1 1K_0402_1% J13 SEN B1
121_0402_1% ZQ VDDQ D1 121_0402_1% ZQ VDDQ D1
VDDQ F1 VDDQ F1
FBA_ABI#_L J4 VDDQ M1 FBA_ABI#_H J4 VDDQ M1
<48> FBA_ABI#_L ABI# VDDQ <48> FBA_ABI#_H ABI# VDDQ
FBA_RAS#_L G3 P1 FBA_CAS#_H G3 P1
<48> FBA_RAS#_L RAS# CAS# VDDQ <48> FBA_CAS#_H RAS# CAS# VDDQ
FBA_CS#_L G12 T1 FBA_WE#_H G12 T1
<48> FBA_CS#_L CS# WE# VDDQ <48> FBA_WE#_H CS# WE# VDDQ
FBA_CLK0 FBA_CAS#_L L3 G2 FBA_RAS#_H L3 G2
<48> FBA_CAS#_L CAS# RAS# VDDQ <48> FBA_RAS#_H CAS# RAS# VDDQ
FBA_WE#_L L12 L2 FBA_CS#_H L12 L2
<48> FBA_WE#_L WE# CS# VDDQ <48> FBA_CS#_H WE# CS# VDDQ
B3 B3
VDDQ VDDQ
1
C D3 D3 C
RV123 VDDQ F3 VDDQ F3
80.6_0402_1% FBA_WCK0_N D5 VDDQ H3 FBA_WCK3_N D5 VDDQ H3
<48> FBA_WCK0_N WCK01# WCK23# VDDQ <48> FBA_WCK3_N WCK01# WCK23# VDDQ
FBA_WCK0 D4 K3 FBA_CLK1 FBA_WCK3 D4 K3
<48> FBA_WCK0 WCK01 WCK23 VDDQ <48> FBA_WCK3 WCK01 WCK23 VDDQ
M3 M3
2
FBA_CLK0# FBA_WCK1_N P5 VDDQ P3 FBA_WCK2_N P5 VDDQ P3

<48> FBA_WCK1_N WCK23# WCK01# VDDQ <48> FBA_WCK2_N WCK23# WCK01# VDDQ
1
FBA_WCK1 P4 T3 FBA_WCK2 P4 T3
<48> FBA_WCK1 WCK23 WCK01 VDDQ <48> FBA_WCK2 WCK23 WCK01 VDDQ
E5 RV175 E5
VDDQ N5 80.6_0402_1% VDDQ N5
+FBA_VREFD A10 VDDQ E10 +FBA_VREFD A10 VDDQ E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
2
+FBA_VREFC J14 VREFD VDDQ B12 FBA_CLK1# +FBA_VREFC J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
FBA_RST#_L J2 VDDQ K12 FBA_RST#_H J2 VDDQ K12
<48> FBA_RST#_L RESET# VDDQ <48> FBA_RST#_H RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
K1 VSS VDDQ B14 K1 VSS VDDQ B14
B5 VSS VDDQ D14 B5 VSS VDDQ D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
+1.35VS_VGA L5 VSS VDDQ M14 L5 VSS VDDQ M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
B10 VSS VDDQ T14 B10 VSS VDDQ T14
1
D10 VSS VDDQ D10 VSS VDDQ

RV195 G10 VSS G10 VSS
549_0402_1% L10 VSS A1 L10 VSS A1
RV193
W=16mils P10 VSS
VSS
VSSQ
VSSQ
C1 P10 VSS
VSS
VSSQ
VSSQ
C1
T10 E1 T10 E1
2
1 2 +FBA_VREFD H14 VSS VSSQ N1 H14 VSS VSSQ N1

931_0402_1% K14 VSS VSSQ R1 K14 VSS VSSQ R1
820P_0402_25V7
820P_0402_25V7
VSS VSSQ VSS VSSQ

1
+1.35VS_VGA U1 +1.35VS_VGA U1
CV304
CV302
@ 1 1
RV190 VSSQ H2 VSSQ H2
@ 1.33K_0402_1% G1 VSSQ K2 G1 VSSQ K2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
B VDD VSSQ VDD VSSQ B
2 2 G4 C3 G4 C3
2
L4 VDD VSSQ E3 L4 VDD VSSQ E3

C5 VDD VSSQ N3 C5 VDD VSSQ N3
@ R5 VDD VSSQ R3 R5 VDD VSSQ R3
one Close to UV8 C10 VDD VSSQ U3 C10 VDD VSSQ U3
one Close to UV9 R10 VDD VSSQ C4 R10 VDD VSSQ C4
@ @ VDD VSSQ VDD VSSQ
D11 R4 D11 R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
+1.35VS_VGA L11 VDD VSSQ M5 L11 VDD VSSQ M5
P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
VDD VSSQ VDD VSSQ
1
L14 C11 L14 C11

RV189 VDD VSSQ R11 VDD VSSQ R11
549_0402_1% VSSQ A12 VSSQ A12
VSSQ C12 VSSQ C12
RV194
W=16mils VSSQ E12 VSSQ E12
2
1 2 +FBA_VREFC VSSQ N12 VSSQ N12

931_0402_1% VSSQ R12 VSSQ R12
820P_0402_25V7
820P_0402_25V7
VSSQ VSSQ
1
U12 U12
CV301
CV303
1 1 170-BALL 170-BALL
RV196 VSSQ H13 VSSQ H13
1.33K_0402_1% SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ VSSQ
1
D A14 A14
2 2 2 VSSQ C14 VSSQ C14
<46,52,53,54> MEM_VREF
2
G VSSQ E14 VSSQ E14

QV23 VSSQ N14 VSSQ N14
S
3
2N7002W-T/R7_SOT323-3 VSSQ R14 VSSQ R14

one Close to UV8 VSSQ U14 VSSQ U14
one Close to UV9 VSSQ VSSQ
2GS@ 2GS@
H5GQ1H24BFR-T2C_BGA170 H5GQ1H24BFR-T2C_BGA170
+1.35VS_VGA +1.35VS_VGA
A A
CV225
CV224
CV227
CV170
CV169
CV173
CV223
CV228
CV226
CV171
CV172
CV168
CV154
CV167
CV201
CV229
CV218
CV217
CV220
CV163
CV162
CV166
CV216
CV221
CV219
CV165
CV164
CV161
CV153
CV160
CV200
CV222
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
N15P_GDDR5_A Lower
0.1
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Lower 32 bits UV8 MF=0 UV9 MF=1

MF=0 MF=1 MF=1 MF=0
FBB_D[0..63] MF=0 MF=1 MF=1 MF=0
<48> FBB_D[0..63]
A4 FBB_D56
FBB_EDC[7..0] A4 FBB_D0 FBB_EDC7 C2 DQ24 DQ0 A2 FBB_D57
<48> FBB_EDC[7..0] DQ24 DQ0 EDC0 EDC3 DQ25 DQ1
FBB_EDC0 C2 A2 FBB_D1 FBB_EDC6 C13 B4 FBB_D58
FBB_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBB_D2 FBB_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBB_D59
R13 EDC1 EDC2 DQ26 DQ2 B2 R2 EDC2 EDC1 DQ27 DQ3 E4
FBB_EDC2
EDC2 EDC1 DQ27 DQ3
FBB_D3 BYTE0 FBB_EDC4
EDC3 EDC0 DQ28 DQ4
FBB_D60 BYTE7
FBB_EDC3 R2 E4 FBB_D4 E2 FBB_D61
EDC3 EDC0 DQ28 DQ4 E2 FBB_D5 DQ29 DQ5 F4 FBB_D62
DQ29 DQ5 F4 FBB_D6 FBB_DBI7# D2 DQ30 DQ6 F2 FBB_D63
D DQ30 DQ6 <48> FBB_DBI7# DBI0# DBI3# DQ31 DQ7 D
FBB_DBI0# D2 F2 FBB_D7 FBB_DBI6# D13 A11 FBB_D48
<48> FBB_DBI0# DBI0# DBI3# DQ31 DQ7 <48> FBB_DBI6# DBI1# DBI2# DQ16 DQ8
FBB_DBI1# D13 A11 FBB_D8 FBB_DBI5# P13 A13 FBB_D49
FBB_DBI2# P13 A13 FBB_D9 FBB_DBI4# P2 B11 FBB_D50
FBB_DBI3# P2 B11 FBB_D10 B13 FBB_D51
<48> FBB_DBI3# DBI3# DBI0# DQ18 DQ10 DQ19 DQ11
FBB_CLK0 B13 FBB_D11 BYTE1 FBB_CLK1 J12 E11 FBB_D52 BYTE6
DQ19 DQ11 <48> FBB_CLK1 CK DQ20 DQ12
FBB_CLK0 J12 E11 FBB_D12 FBB_CLK1# J11 E13 FBB_D53
<48> FBB_CLK0 CK DQ20 DQ12 <48> FBB_CLK1# CK# DQ21 DQ13
FBB_CLK0# J11 E13 FBB_D13 FBB_CKE_H J3 F11 FBB_D54
<48> FBB_CLK0# CK# DQ21 DQ13 <48> FBB_CKE_H CKE# DQ22 DQ14
1
FBB_CKE_L J3 F11 FBB_D14 F13 FBB_D55

<48> FBB_CKE_L CKE# DQ22 DQ14 DQ23 DQ15
RV178 F13 FBB_D15 U11 FBB_D40
80.6_0402_1% DQ23 DQ15 U11 FBB_D16 FBB_MA4_BA2_H H11 DQ8 DQ16 U13 FBB_D41
DQ8 DQ16 <48> FBB_MA4_BA2_H BA0/A2 BA2/A4 DQ9 DQ17
FBB_MA2_BA0_L H11 U13 FBB_D17 FBB_MA3_BA3_H K10 T11 FBB_D42
<48> FBB_MA2_BA0_L BA0/A2 BA2/A4 DQ9 DQ17 <48> FBB_MA3_BA3_H BA1/A5 BA3/A3 DQ10 DQ18
FBB_MA5_BA1_L K10 T11 FBB_D18 FBB_MA2_BA0_H K11 T13 FBB_D43
<48> FBB_MA5_BA1_L <48> FBB_MA2_BA0_H
2
K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11
FBB_CLK0#
<48> FBB_MA4_BA2_L
FBB_MA4_BA2_L
BA2/A4 BA0/A2 DQ11 DQ19
FBB_D19
<48> FBB_MA5_BA1_H
FBB_MA5_BA1_H
FBB_D44 BYTE5
FBB_MA3_BA3_L H10 N11 FBB_D20 BYTE2 N13 FBB_D45
<48> FBB_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 DQ13 DQ21
N13 FBB_D21 M11 FBB_D46
DQ13 DQ21 M11 FBB_D22 FBB_MA0_MA10_H K4 DQ14 DQ22 M13 FBB_D47
DQ14 DQ22 <48> FBB_MA0_MA10_H A8/A7 A10/A0 DQ15 DQ23
FBB_MA7_MA8_L K4 M13 FBB_D23 FBB_MA6_MA11_H H5 U4 FBB_D32
<48> FBB_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 <48> FBB_MA6_MA11_H A9/A1 A11/A6 DQ0 DQ24
FBB_MA1_MA9_L H5 U4 FBB_D24 FBB_MA7_MA8_H H4 U2 FBB_D33
FBB_MA0_MA10_L H4 U2 FBB_D25 FBB_MA1_MA9_H K5 T4 FBB_D34
FBB_MA6_MA11_L K5 T4 FBB_D26 FBB_MA12_RFU_H J5 T2 FBB_D35 BYTE4
<48> FBB_MA6_MA11_L A11/A6 A9/A1 DQ2 DQ26 <48> FBB_MA12_RFU_H A12/RFU/NC DQ3 DQ27
FBB_MA12_RFU_L J5 T2 FBB_D27 BYTE3 N4 FBB_D36
<48> FBB_MA12_RFU_L A12/RFU/NC DQ3 DQ27 DQ4 DQ28
N4 FBB_D28 A5 N2 FBB_D37
A5 DQ4 DQ28 N2 FBB_D29 +1.35VS_VGA U5 VPP/NC DQ5 DQ29 M4 FBB_D38
U5 VPP/NC DQ5 DQ29 M4 FBB_D30 2 RV131 1 VPP/NC DQ6 DQ30 M2 FBB_D39
2 RV132 1 VPP/NC DQ6 DQ30 M2 FBB_D31 1K_0402_1% DQ7 DQ31
1K_0402_1% DQ7 DQ31 J1 +1.35VS_VGA
J1 +1.35VS_VGA 2 RV133 1 J10 MF
2 RV134 1 J10 MF 2 RV135 1 1K_0402_1% J13 SEN B1
2 RV136 1 1K_0402_1% J13 SEN B1 121_0402_1% ZQ VDDQ D1
121_0402_1% ZQ VDDQ D1 VDDQ F1
VDDQ F1 FBB_ABI#_H J4 VDDQ M1
VDDQ <48> FBB_ABI#_H ABI# VDDQ
FBB_ABI#_L J4 M1 FBB_CAS#_H G3 P1
<48> FBB_ABI#_L ABI# VDDQ <48> FBB_CAS#_H RAS# CAS# VDDQ
FBB_RAS#_L G3 P1 FBB_WE#_H G12 T1
<48> FBB_RAS#_L RAS# CAS# VDDQ <48> FBB_WE#_H CS# WE# VDDQ
FBB_CS#_L G12 T1 FBB_RAS#_H L3 G2
<48> FBB_CS#_L CS# WE# VDDQ <48> FBB_RAS#_H CAS# RAS# VDDQ
FBB_CAS#_L L3 G2 FBB_CLK1 FBB_CS#_H L12 L2
<48> FBB_CAS#_L CAS# RAS# VDDQ <48> FBB_CS#_H WE# CS# VDDQ
FBB_WE#_L L12 L2 B3
<48> FBB_WE#_L WE# CS# VDDQ VDDQ
C B3 D3 C
VDDQ VDDQ
1
D3 F3
VDDQ F3 RV138 FBB_WCK3_N D5 VDDQ H3
VDDQ <48> FBB_WCK3_N WCK01# WCK23# VDDQ
FBB_WCK0_N D5 H3 80.6_0402_1% FBB_WCK3 D4 K3
<48> FBB_WCK0_N WCK01# WCK23# VDDQ <48> FBB_WCK3 WCK01 WCK23 VDDQ
FBB_WCK0 D4 K3 M3
<48> FBB_WCK0 WCK01 WCK23 VDDQ VDDQ
M3 FBB_WCK2_N P5 P3
<48> FBB_WCK2_N
2
FBB_WCK1_N P5 VDDQ P3 FBB_CLK1# FBB_WCK2 P4 WCK23# WCK01# VDDQ T3
<48> FBB_WCK1_N WCK23# WCK01# VDDQ <48> FBB_WCK2 WCK23 WCK01 VDDQ
FBB_WCK1 P4 T3 E5
<48> FBB_WCK1 WCK23 WCK01 VDDQ VDDQ
E5 N5
VDDQ N5 +FBB_VREFD A10 VDDQ E10
+FBB_VREFD A10 VDDQ E10 U10 VREFD VDDQ N10
U10 VREFD VDDQ N10 +FBB_VREFC J14 VREFD VDDQ B12
+FBB_VREFC J14 VREFD VDDQ B12 VREFC VDDQ D12
VREFC VDDQ D12 VDDQ F12
VDDQ F12 VDDQ H12
VDDQ H12 FBB_RST#_H J2 VDDQ K12
VDDQ <48> FBB_RST#_H RESET# VDDQ
FBB_RST#_L J2 K12 M12
<48> FBB_RST#_L RESET# VDDQ VDDQ
M12 P12
VDDQ P12 VDDQ T12
VDDQ T12 VDDQ G13
VDDQ G13 H1 VDDQ L13
H1 VDDQ L13 K1 VSS VDDQ B14
K1 VSS VDDQ B14 B5 VSS VDDQ D14
+1.35VS_VGA B5 VSS VDDQ D14 G5 VSS VDDQ F14
G5 VSS VDDQ F14 L5 VSS VDDQ M14
L5 VSS VDDQ M14 T5 VSS VDDQ P14
VSS VDDQ VSS VDDQ
1
T5 P14 B10 T14

RV201 B10 VSS VDDQ T14 D10 VSS VDDQ
549_0402_1% D10 VSS VDDQ G10 VSS
RV199
W=16mils G10 VSS
VSS
L10 VSS
VSS VSSQ
A1
L10 A1 P10 C1
2
1 2 +FBB_VREFD P10 VSS VSSQ C1 T10 VSS VSSQ E1

931_0402_1% T10 VSS VSSQ E1 H14 VSS VSSQ N1
820P_0402_25V7
820P_0402_25V7
VSS VSSQ VSS VSSQ

1
H14 N1 K14 R1
CV308
CV306
@ 1 1
RV198 K14 VSS VSSQ R1 +1.35VS_VGA VSS VSSQ U1
@ 1.33K_0402_1% +1.35VS_VGA VSS VSSQ U1 VSSQ H2
VSSQ H2 G1 VSSQ K2
2 2 G1 VSSQ K2 L1 VDD VSSQ A3
B B
2
L1 VDD VSSQ A3 G4 VDD VSSQ C3

G4 VDD VSSQ C3 L4 VDD VSSQ E3
@ L4 VDD VSSQ E3 C5 VDD VSSQ N3
one Close to UV8 C5 VDD VSSQ N3 R5 VDD VSSQ R3
one Close to UV9 R5 VDD VSSQ R3 C10 VDD VSSQ U3
C10 U3 R10 C4
R10 VDD VSSQ C4 D11 VDD VSSQ R4
+1.35VS_VGA D11 VDD VSSQ R4 G11 VDD VSSQ F5
G11 VDD VSSQ F5 L11 VDD VSSQ M5
L11 VDD VSSQ M5 P11 VDD VSSQ F10
VDD VSSQ VDD VSSQ
1
P11 F10 G14 M10

RV197 G14 VDD VSSQ M10 L14 VDD VSSQ C11
549_0402_1% L14 VDD VSSQ C11 VDD VSSQ R11
VDD VSSQ R11 VSSQ A12
RV200
W=16mils VSSQ A12 VSSQ C12
2
1 2 +FBB_VREFC VSSQ C12 VSSQ E12

931_0402_1% VSSQ E12 VSSQ N12
820P_0402_25V7
820P_0402_25V7
VSSQ VSSQ
1
N12 R12
CV305
CV307
1 1 VSSQ VSSQ
RV202 R12 170-BALL U12
1.33K_0402_1% 170-BALL VSSQ U12 VSSQ H13
VSSQ VSSQ
1
D H13 SGRAM GDDR5 K13

2 2 2 SGRAM GDDR5 VSSQ K13 VSSQ A14
<46,51,53,54> MEM_VREF
2
G VSSQ A14 VSSQ C14

QV24 VSSQ C14 VSSQ E14
S
3
2N7002W-T/R7_SOT323-3 VSSQ E14 VSSQ N14

one Close to UV8 VSSQ N14 VSSQ R14
one Close to UV9 VSSQ R14 VSSQ U14
VSSQ U14 VSSQ
VSSQ 2GS@
2GS@
H5GQ1H24AFR-T2L_BGA170
A A
CV238
CV239
CV248
CV243
CV242
CV247
CV237
CV249
CV246
CV244
CV245
CV241
CV156
CV240
CV214
CV250
CV232
CV231
CV234
CV199
CV198
CV213
CV230
CV235
CV233
CV210
CV211
CV175
CV155
CV174
CV202
CV236
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
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N15P_GDDR5_A Upper
0.1
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Lower 32 bits UV13 MF=0 UV12 MF=1

MF=0 MF=1 MF=1 MF=0
FBC_D[0..63] MF=0 MF=1 MF=1 MF=0
<48> FBC_D[0..63]
A4 FBC_D56
FBC_EDC[7..0] A4 FBC_D0 FBC_EDC7 C2 DQ24 DQ0 A2 FBC_D57
<48> FBC_EDC[7..0] DQ24 DQ0 EDC0 EDC3 DQ25 DQ1
FBC_EDC0 C2 A2 FBC_D1 FBC_EDC6 C13 B4 FBC_D58
FBC_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D2 FBC_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D59
FBC_EDC2
EDC2 EDC1 DQ27 DQ3
FBC_D3 BYTE0 FBC_EDC4
EDC3 EDC0 DQ28 DQ4
FBC_D60 BYTE7
FBC_EDC3 R2 E4 FBC_D4 E2 FBC_D61
EDC3 EDC0 DQ28 DQ4 E2 FBC_D5 DQ29 DQ5 F4 FBC_D62
DQ29 DQ5 F4 FBC_D6 FBC_DBI7# D2 DQ30 DQ6 F2 FBC_D63
DQ30 DQ6 <48> FBC_DBI7# DBI0# DBI3# DQ31 DQ7
D FBC_DBI0# D2 F2 FBC_D7 FBC_DBI6# D13 A11 FBC_D48 D
<48> FBC_DBI0# DBI0# DBI3# DQ31 DQ7 <48> FBC_DBI6# DBI1# DBI2# DQ16 DQ8
FBC_DBI1# D13 A11 FBC_D8 FBC_DBI5# P13 A13 FBC_D49
FBC_DBI2# P13 A13 FBC_D9 FBC_DBI4# P2 B11 FBC_D50
FBC_DBI3# P2 B11 FBC_D10 B13 FBC_D51
<48> FBC_DBI3# DBI3# DBI0# DQ18 DQ10 DQ19 DQ11
FBC_CLK0 B13 FBC_D11 BYTE1 FBC_CLK1 J12 E11 FBC_D52 BYTE6
DQ19 DQ11 <48> FBC_CLK1 CK DQ20 DQ12
FBC_CLK0 J12 E11 FBC_D12 FBC_CLK1# J11 E13 FBC_D53
<48> FBC_CLK0 CK DQ20 DQ12 <48> FBC_CLK1# CK# DQ21 DQ13
FBC_CLK0# J11 E13 FBC_D13 FBC_CKE_H J3 F11 FBC_D54
<48> FBC_CLK0# CK# DQ21 DQ13 <48> FBC_CKE_H CKE# DQ22 DQ14
1
FBC_CKE_L J3 F11 FBC_D14 F13 FBC_D55
<48> FBC_CKE_L CKE# DQ22 DQ14 DQ23 DQ15
RV179 F13 FBC_D15 U11 FBC_D40
80.6_0402_1% DQ23 DQ15 U11 FBC_D16 FBC_MA4_BA2_H H11 DQ8 DQ16 U13 FBC_D41
DQ8 DQ16 <48> FBC_MA4_BA2_H BA0/A2 BA2/A4 DQ9 DQ17
FBC_MA2_BA0_L H11 U13 FBC_D17 FBC_MA3_BA3_H K10 T11 FBC_D42
<48> FBC_MA2_BA0_L BA0/A2 BA2/A4 DQ9 DQ17 <48> FBC_MA3_BA3_H BA1/A5 BA3/A3 DQ10 DQ18
FBC_MA5_BA1_L K10 T11 FBC_D18 FBC_MA2_BA0_H K11 T13 FBC_D43
<48> FBC_MA5_BA1_L <48> FBC_MA2_BA0_H
2
FBC_CLK0#
<48> FBC_MA4_BA2_L
FBC_MA4_BA2_L
FBC_D19
<48> FBC_MA5_BA1_H
FBC_MA5_BA1_H
FBC_D44 BYTE5
FBC_MA3_BA3_L H10 N11 FBC_D20 BYTE2 N13 FBC_D45
<48> FBC_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 DQ13 DQ21
N13 FBC_D21 M11 FBC_D46
DQ13 DQ21 M11 FBC_D22 FBC_MA0_MA10_H K4 DQ14 DQ22 M13 FBC_D47
DQ14 DQ22 <48> FBC_MA0_MA10_H A8/A7 A10/A0 DQ15 DQ23
FBC_MA7_MA8_L K4 M13 FBC_D23 FBC_MA6_MA11_H H5 U4 FBC_D32
<48> FBC_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 <48> FBC_MA6_MA11_H A9/A1 A11/A6 DQ0 DQ24
FBC_MA1_MA9_L H5 U4 FBC_D24 FBC_MA7_MA8_H H4 U2 FBC_D33
FBC_MA0_MA10_L H4 U2 FBC_D25 FBC_MA1_MA9_H K5 T4 FBC_D34
FBC_MA6_MA11_L K5 T4 FBC_D26 FBC_MA12_RFU_H J5 T2 FBC_D35 BYTE4
<48> FBC_MA6_MA11_L A11/A6 A9/A1 DQ2 DQ26 <48> FBC_MA12_RFU_H A12/RFU/NC DQ3 DQ27
FBC_MA12_RFU_L J5 T2 FBC_D27 BYTE3 N4 FBC_D36
<48> FBC_MA12_RFU_L A12/RFU/NC DQ3 DQ27 DQ4 DQ28
N4 FBC_D28 A5 N2 FBC_D37
A5 DQ4 DQ28 N2 FBC_D29 +1.35VS_VGA U5 VPP/NC DQ5 DQ29 M4 FBC_D38
U5 VPP/NC DQ5 DQ29 M4 FBC_D30 2 RV165 1 VPP/NC DQ6 DQ30 M2 FBC_D39
2 RV161 1 VPP/NC DQ6 DQ30 M2 FBC_D31 1K_0402_1% DQ7 DQ31
1K_0402_1% DQ7 DQ31 J1 +1.35VS_VGA
J1 +1.35VS_VGA 2 RV140 1 J10 MF
2 RV159 1 J10 MF 2 RV160 1 1K_0402_1% J13 SEN B1
VDDQ F1 FBC_ABI#_H J4 VDDQ M1
VDDQ <48> FBC_ABI#_H ABI# VDDQ
FBC_ABI#_L J4 M1 FBC_CAS#_H G3 P1
<48> FBC_ABI#_L ABI# VDDQ <48> FBC_CAS#_H RAS# CAS# VDDQ
FBC_RAS#_L G3 P1 FBC_WE#_H G12 T1
<48> FBC_RAS#_L RAS# CAS# VDDQ <48> FBC_WE#_H CS# WE# VDDQ
FBC_CS#_L G12 T1 FBC_RAS#_H L3 G2
<48> FBC_CS#_L CS# WE# VDDQ <48> FBC_RAS#_H CAS# RAS# VDDQ
FBC_CAS#_L L3 G2 FBC_CLK1 FBC_CS#_H L12 L2
<48> FBC_CAS#_L CAS# RAS# VDDQ <48> FBC_CS#_H WE# CS# VDDQ
FBC_WE#_L L12 L2 B3
<48> FBC_WE#_L WE# CS# VDDQ VDDQ
B3 D3
VDDQ VDDQ
1
C D3 F3 C
VDDQ F3 RV141 FBC_WCK3_N D5 VDDQ H3
VDDQ <48> FBC_WCK3_N WCK01# WCK23# VDDQ
FBC_WCK0_N D5 H3 80.6_0402_1% FBC_WCK3 D4 K3
<48> FBC_WCK0_N WCK01# WCK23# VDDQ <48> FBC_WCK3 WCK01 WCK23 VDDQ
FBC_WCK0 D4 K3 M3
<48> FBC_WCK0 WCK01 WCK23 VDDQ VDDQ
M3 FBC_WCK2_N P5 P3
<48> FBC_WCK2_N
2
FBC_WCK1_N P5 VDDQ P3 FBC_CLK1# FBC_WCK2 P4 WCK23# WCK01# VDDQ T3
<48> FBC_WCK1_N WCK23# WCK01# VDDQ <48> FBC_WCK2 WCK23 WCK01 VDDQ
FBC_WCK1 P4 T3 E5
<48> FBC_WCK1 WCK23 WCK01 VDDQ VDDQ
E5 N5
VDDQ N5 +FBC_VREFD A10 VDDQ E10
+FBC_VREFD A10 VDDQ E10 U10 VREFD VDDQ N10
U10 VREFD VDDQ N10 +FBC_VREFC J14 VREFD VDDQ B12
+FBC_VREFC J14 VREFD VDDQ B12 VREFC VDDQ D12
VDDQ F12 VDDQ H12
VDDQ H12 FBC_RST#_H J2 VDDQ K12
VDDQ <48> FBC_RST#_H RESET# VDDQ
FBC_RST#_L J2 K12 M12
<48> FBC_RST#_L RESET# VDDQ VDDQ
M12 P12
VDDQ P12 VDDQ T12
VDDQ T12 VDDQ G13
+1.35VS_VGA K1 VSS VDDQ B14 B5 VSS VDDQ D14
B5 VSS VDDQ D14 G5 VSS VDDQ F14
VSS VDDQ VSS VDDQ
1
L5 M14 T5 P14
RV142 T5 VSS VDDQ P14 B10 VSS VDDQ T14
549_0402_1% B10 VSS VDDQ T14 D10 VSS VDDQ
RV144
W=16mils D10 VSS
VSS
VDDQ G10 VSS
VSS
G10 L10 A1
2
1 2 +FBC_VREFD L10 VSS A1 P10 VSS VSSQ C1

931_0402_1% P10 VSS VSSQ C1 T10 VSS VSSQ E1
820P_0402_25V7
820P_0402_25V7
VSS VSSQ VSS VSSQ

1
T10 E1 H14 N1
CV178
CV299
@ 1 1
RV158 H14 VSS VSSQ N1 K14 VSS VSSQ R1
@ 1.33K_0402_1% +1.35VS_VGA K14 VSS VSSQ R1 +1.35VS_VGA VSS VSSQ U1
VSS VSSQ U1 VSSQ H2
2 2 VSSQ H2 G1 VSSQ K2
2
G1 VSSQ K2 L1 VDD VSSQ A3

B VDD VSSQ VDD VSSQ B
@ G4 C3 L4 E3
one Close to UV8 L4 VDD VSSQ E3 C5 VDD VSSQ N3
R5 R3 C10 U3
C10 VDD VSSQ U3 R10 VDD VSSQ C4
+1.35VS_VGA R10 VDD VSSQ C4 D11 VDD VSSQ R4
D11 VDD VSSQ R4 G11 VDD VSSQ F5
VDD VSSQ VDD VSSQ
1
L11 M5 P11 F10

RV143 P11 VDD VSSQ F10 G14 VDD VSSQ M10
549_0402_1% G14 VDD VSSQ M10 L14 VDD VSSQ C11
L14 VDD VSSQ C11 VDD VSSQ R11
RV164
W=16mils VDD VSSQ R11 VSSQ A12
2
1 2 +FBC_VREFC VSSQ A12 VSSQ C12

931_0402_1% VSSQ C12 VSSQ E12
820P_0402_25V7
820P_0402_25V7
VSSQ VSSQ
1
E12 N12
CV179
CV300
1 1 VSSQ VSSQ
RV145 N12 R12
1.33K_0402_1% VSSQ R12 170-BALL VSSQ U12
VSSQ VSSQ
1
D 170-BALL U12 H13

2 2 2 VSSQ H13 SGRAM GDDR5 VSSQ K13
<46,51,52,54> MEM_VREF
2
G SGRAM GDDR5 VSSQ K13 VSSQ A14

QV21 VSSQ A14 VSSQ C14
S
3
2N7002W-T/R7_SOT323-3 VSSQ C14 VSSQ E14

one Close to UV8 VSSQ E14 VSSQ N14
VSSQ R14 VSSQ U14
VSSQ U14 VSSQ
VSSQ 2GS@
2GS@
A A
CV268
CV269
CV280
CV275
CV274
CV279
CV267
CV281
CV278
CV276
CV277
CV273
CV271
CV272
CV270
CV282
CV253
CV257
CV264
CV259
CV258
CV263
CV252
CV265
CV262
CV260
CV261
CV283
CV255
CV256
CV254
CV266
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

N15P_GDDR5_A Upper
0.1
5 4 3 2 1
5 4 3 2 1
Memory Partition D UV15 MF=0 UV16 MF=1

MF=0 MF=1 MF=1 MF=0
FBD_D[0..63] MF=0 MF=1 MF=1 MF=0
<48> FBD_D[0..63]
A4 FBD_D56
FBD_EDC[7..0] A4 FBD_D0 FBD_EDC7 C2 DQ24 DQ0 A2 FBD_D57
<48> FBD_EDC[7..0] DQ24 DQ0 EDC0 EDC3 DQ25 DQ1
FBD_EDC0 C2 A2 FBD_D1 FBD_EDC6 C13 B4 FBD_D58
FBD_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBD_D2 FBD_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBD_D59
FBD_EDC2
EDC2 EDC1 DQ27 DQ3
FBD_D3 BYTE0 FBD_EDC4
EDC3 EDC0 DQ28 DQ4
FBD_D60 BYTE7
FBD_EDC3 R2 E4 FBD_D4 E2 FBD_D61
EDC3 EDC0 DQ28 DQ4 E2 FBD_D5 DQ29 DQ5 F4 FBD_D62
DQ29 DQ5 F4 FBD_D6 FBD_DBI7# D2 DQ30 DQ6 F2 FBD_D63
D DQ30 DQ6 <48> FBD_DBI7# DBI0# DBI3# DQ31 DQ7 D
FBD_DBI0# D2 F2 FBD_D7 FBD_DBI6# D13 A11 FBD_D48
<48> FBD_DBI0# DBI0# DBI3# DQ31 DQ7 <48> FBD_DBI6# DBI1# DBI2# DQ16 DQ8
FBD_DBI1# D13 A11 FBD_D8 FBD_DBI5# P13 A13 FBD_D49
FBD_DBI2# P13 A13 FBD_D9 FBD_DBI4# P2 B11 FBD_D50
FBD_DBI3# P2 B11 FBD_D10 B13 FBD_D51
<48> FBD_DBI3# DBI3# DBI0# DQ18 DQ10 DQ19 DQ11
FBD_CLK0 B13 FBD_D11 BYTE1 FBD_CLK1 J12 E11 FBD_D52 BYTE6
DQ19 DQ11 <48> FBD_CLK1 CK DQ20 DQ12
FBD_CLK0 J12 E11 FBD_D12 FBD_CLK1# J11 E13 FBD_D53
<48> FBD_CLK0 CK DQ20 DQ12 <48> FBD_CLK1# CK# DQ21 DQ13
FBD_CLK0# J11 E13 FBD_D13 FBD_CKE_H J3 F11 FBD_D54
<48> FBD_CLK0# CK# DQ21 DQ13 <48> FBD_CKE_H CKE# DQ22 DQ14
1
FBD_CKE_L J3 F11 FBD_D14 F13 FBD_D55
<48> FBD_CKE_L CKE# DQ22 DQ14 DQ23 DQ15
RV182 F13 FBD_D15 U11 FBD_D40
80.6_0402_1% DQ23 DQ15 U11 FBD_D16 FBD_MA4_BA2_H H11 DQ8 DQ16 U13 FBD_D41
DQ8 DQ16 <48> FBD_MA4_BA2_H BA0/A2 BA2/A4 DQ9 DQ17
FBD_MA2_BA0_L H11 U13 FBD_D17 FBD_MA3_BA3_H K10 T11 FBD_D42
<48> FBD_MA2_BA0_L BA0/A2 BA2/A4 DQ9 DQ17 <48> FBD_MA3_BA3_H BA1/A5 BA3/A3 DQ10 DQ18
FBD_MA5_BA1_L K10 T11 FBD_D18 FBD_MA2_BA0_H K11 T13 FBD_D43
<48> FBD_MA5_BA1_L <48> FBD_MA2_BA0_H
2
FBD_CLK0#
<48> FBD_MA4_BA2_L
FBD_MA4_BA2_L
FBD_D19
<48> FBD_MA5_BA1_H
FBD_MA5_BA1_H
FBD_D44 BYTE5
FBD_MA3_BA3_L H10 N11 FBD_D20 BYTE2 N13 FBD_D45
<48> FBD_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 DQ13 DQ21
N13 FBD_D21 M11 FBD_D46
DQ13 DQ21 M11 FBD_D22 FBD_MA0_MA10_H K4 DQ14 DQ22 M13 FBD_D47
DQ14 DQ22 <48> FBD_MA0_MA10_H A8/A7 A10/A0 DQ15 DQ23
FBD_MA7_MA8_L K4 M13 FBD_D23 FBD_MA6_MA11_H H5 U4 FBD_D32
<48> FBD_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 <48> FBD_MA6_MA11_H A9/A1 A11/A6 DQ0 DQ24
FBD_MA1_MA9_L H5 U4 FBD_D24 FBD_MA7_MA8_H H4 U2 FBD_D33
FBD_MA0_MA10_L H4 U2 FBD_D25 FBD_MA1_MA9_H K5 T4 FBD_D34
FBD_MA6_MA11_L K5 T4 FBD_D26 FBD_MA12_RFU_H J5 T2 FBD_D35 BYTE4
<48> FBD_MA6_MA11_L A11/A6 A9/A1 DQ2 DQ26 <48> FBD_MA12_RFU_H A12/RFU/NC DQ3 DQ27
FBD_MA12_RFU_L J5 T2 FBD_D27 BYTE3 N4 FBD_D36
<48> FBD_MA12_RFU_L A12/RFU/NC DQ3 DQ27 DQ4 DQ28
N4 FBD_D28 A5 N2 FBD_D37
A5 DQ4 DQ28 N2 FBD_D29 +1.35VS_VGA U5 VPP/NC DQ5 DQ29 M4 FBD_D38
U5 VPP/NC DQ5 DQ29 M4 FBD_D30 2 RV172 1 VPP/NC DQ6 DQ30 M2 FBD_D39
2 RV204 1 VPP/NC DQ6 DQ30 M2 FBD_D31 1K_0402_1% DQ7 DQ31
1K_0402_1% DQ7 DQ31 J1 +1.35VS_VGA
J1 +1.35VS_VGA 2 RV188 1 J10 MF
2 RV185 1 J10 MF 2 RV166 1 1K_0402_1% J13 SEN B1
VDDQ F1 FBD_ABI#_H J4 VDDQ M1
VDDQ <48> FBD_ABI#_H ABI# VDDQ
FBD_ABI#_L J4 M1 FBD_CAS#_H G3 P1
<48> FBD_ABI#_L ABI# VDDQ <48> FBD_CAS#_H RAS# CAS# VDDQ
FBD_RAS#_L G3 P1 FBD_WE#_H G12 T1
<48> FBD_RAS#_L RAS# CAS# VDDQ <48> FBD_WE#_H CS# WE# VDDQ
FBD_CS#_L G12 T1 FBD_RAS#_H L3 G2
<48> FBD_CS#_L CS# WE# VDDQ <48> FBD_RAS#_H CAS# RAS# VDDQ
FBD_CAS#_L L3 G2 FBD_CLK1 FBD_CS#_H L12 L2
<48> FBD_CAS#_L CAS# RAS# VDDQ <48> FBD_CS#_H WE# CS# VDDQ
FBD_WE#_L L12 L2 B3
<48> FBD_WE#_L WE# CS# VDDQ VDDQ
C B3 D3 C
VDDQ VDDQ
1
D3 F3
VDDQ F3 RV212 FBD_WCK3_N D5 VDDQ H3
VDDQ <48> FBD_WCK3_N WCK01# WCK23# VDDQ
FBD_WCK0_N D5 H3 80.6_0402_1% FBD_WCK3 D4 K3
<48> FBD_WCK0_N WCK01# WCK23# VDDQ <48> FBD_WCK3 WCK01 WCK23 VDDQ
FBD_WCK0 D4 K3 M3
<48> FBD_WCK0 WCK01 WCK23 VDDQ VDDQ
M3 FBD_WCK2_N P5 P3
<48> FBD_WCK2_N
2
FBD_WCK1_N P5 VDDQ P3 FBD_CLK1# FBD_WCK2 P4 WCK23# WCK01# VDDQ T3
<48> FBD_WCK1_N WCK23# WCK01# VDDQ <48> FBD_WCK2 WCK23 WCK01 VDDQ
FBD_WCK1 P4 T3 E5
<48> FBD_WCK1 WCK23 WCK01 VDDQ VDDQ
E5 N5
VDDQ N5 +FBD_VREFD A10 VDDQ E10
+FBD_VREFD A10 VDDQ E10 U10 VREFD VDDQ N10
U10 VREFD VDDQ N10 +FBD_VREFC J14 VREFD VDDQ B12
+FBD_VREFC J14 VREFD VDDQ B12 VREFC VDDQ D12
VDDQ F12 VDDQ H12
VDDQ H12 FBD_RST#_H J2 VDDQ K12
VDDQ <48> FBD_RST#_H RESET# VDDQ
FBD_RST#_L J2 K12 M12
<48> FBD_RST#_L RESET# VDDQ VDDQ
M12 P12
VDDQ P12 VDDQ T12
VDDQ T12 VDDQ G13
K1 VSS VDDQ B14 B5 VSS VDDQ D14
+1.35VS_VGA B5 VSS VDDQ D14 G5 VSS VDDQ F14
L5 VSS VDDQ M14 T5 VSS VDDQ P14
VSS VDDQ VSS VDDQ
1
T5 P14 B10 T14

RV207 B10 VSS VDDQ T14 D10 VSS VDDQ
549_0402_1% D10 VSS VDDQ G10 VSS
RV205
W=16mils G10 VSS
VSS
L10 VSS
VSS VSSQ
A1
L10 A1 P10 C1
2
1 2 +FBD_VREFD P10 VSS VSSQ C1 T10 VSS VSSQ E1

931_0402_1% T10 VSS VSSQ E1 H14 VSS VSSQ N1
820P_0402_25V7
820P_0402_25V7
VSS VSSQ VSS VSSQ

1
H14 N1 K14 R1
CV312
CV310
@ 1 1
RV213 K14 VSS VSSQ R1 +1.35VS_VGA VSS VSSQ U1
@ 1.33K_0402_1% +1.35VS_VGA VSS VSSQ U1 VSSQ H2
VSSQ H2 G1 VSSQ K2
2 2 G1 VSSQ K2 L1 VDD VSSQ A3
B B
2

G4 VDD VSSQ C3 L4 VDD VSSQ E3
@ L4 VDD VSSQ E3 C5 VDD VSSQ N3
one Close to UV9 R5 VDD VSSQ R3 C10 VDD VSSQ U3
C10 U3 R10 C4
R10 VDD VSSQ C4 D11 VDD VSSQ R4
+1.35VS_VGA D11 VDD VSSQ R4 G11 VDD VSSQ F5
L11 VDD VSSQ M5 P11 VDD VSSQ F10
VDD VSSQ VDD VSSQ
1
P11 F10 G14 M10

RV203 G14 VDD VSSQ M10 L14 VDD VSSQ C11
549_0402_1% L14 VDD VSSQ C11 VDD VSSQ R11
VDD VSSQ R11 VSSQ A12
RV206
W=16mils VSSQ A12 VSSQ C12
2
1 2 +FBD_VREFC VSSQ C12 VSSQ E12

931_0402_1% VSSQ E12 VSSQ N12
820P_0402_25V7
820P_0402_25V7
VSSQ VSSQ
1
N12 R12
CV309
CV311
1 1 VSSQ VSSQ
RV209 R12 170-BALL U12
1.33K_0402_1% 170-BALL VSSQ U12 VSSQ H13
VSSQ VSSQ
1
D H13 SGRAM GDDR5 K13

2 2 2 SGRAM GDDR5 VSSQ K13 VSSQ A14
<46,51,52,53> MEM_VREF
2
G VSSQ A14 VSSQ C14

QV25 VSSQ C14 VSSQ E14
S
3
2N7002W-T/R7_SOT323-3 VSSQ E14 VSSQ N14

one Close to UV9 VSSQ R14 VSSQ U14
VSSQ U14 VSSQ
VSSQ 2GS@
2GS@
A A
CV292
CV293
CV296
CV191
CV190
CV194
CV313
CV297
CV295
CV314
CV193
CV189
CV188
CV192
CV294
CV298
CV286
CV285
CV288
CV187
CV182
CV186
CV284
CV289
CV287
CV184
CV185
CV181
CV315
CV180
CV291
CV290
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
N15P_GDDR5_A Upper
0.1
5 4 3 2 1
5 4 3 2 1
RV217
+3.3V_GFX_AON
15K_0402_1%
N15P@
SD034150280
2
RV230 RV218 RV217 RV214 RV219
45.3K_0402_1% 34.8K_0402_1% 4.99K_0402_1% 15K_0402_1% 20K_0402_1%
@ N15E@ @ @
1
STRAP0
<47> STRAP0
STRAP1
D <47> STRAP1 D
STRAP2
<47> STRAP2
STRAP3
<47> STRAP3
STRAP4
<47> STRAP4
2
@ RV228 RV216 RV232 RV221 RV224
45.3K_0402_1% 4.99K_0402_1% 15K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
@
1
+3.3V_GFX_AON
2
2
RV229 RV231 RV233
4.99K_0402_1% 4.99K_0402_1% 24.9K_0402_1%
@
ROM_SI
<47> ROM_SI
1
1
ROM_SO
<47> ROM_SO
ROM_SCLK
<47> ROM_SCLK
2
2
RV215
15K_0402_1% RV223 RV226
Hyn@ 10K_0402_1% 15K_0402_1%
@ @
1
C C
1
Physical Logical Logical Logical Logical

Strapping pin Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
R_pu
PCI_DEVID[4] SUB_VENDER PCI_DEVID[5] PEX_PLL_EN_TERM
RV215 VRAM Strap ROM-SI ROM_SCLK
Hynix H5GC4H24MFR-T2C 0x2 PL 15K RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO
Samsung K4G41325FC-HC04 0x3 PL 20K
20K_0402_1% ROM_SI FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
Sam@
SD034200280 STRAP0 USER[3] USER[2] USER[1] USER[0]
STRAP1 3GIO_CFG[3] 3GIO_CFG[2] 3GIO_CFG[1] 3GIO_CFG[0]
STRAP2 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

STRAP3 SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
RESERVED PCIE_SPEED PCIE_MAX_SPEED DP_PLL_VDD33V
STRAP4 _CHNAGE_GEN3
PU to 3V3 PD to GND PCI_DEVID

4.99K 1000 0000
SUB_VENDER
B
10K 1001 0001 0- w/o dGPU ROM B
15K 1010 0010 1-w/ dGPU ROM

20K 1011 0011 FB[1:0]
0-Reserved
24.9K 1100 0100 1-Reserved
30.1K 1101 0101 2-256M
3-Reserved
34.8K 1110 0110
45.3K 1111 0111 VGA_DEVICE
0- Non-permary 3D
1-
SMB_ALT_ADDR
0-0x9E
1-0x9C(Multi-GPU)
PEX_PLL_EN_TERM
0-Disable
1-Enable
3GIO_PADCFG
0110-GEN1/GEN2
0000-GEN3
PCIE_MAX_SPEED
0-booting to PCIE Gen1
1-booting to PCIE Gen2/Gen3
A PCIE_SPEED_CHNAGE_GEN3 A
0-Disable PCIE Gen3
1-Enable PCIE Gen3

5 4 3 2 1
5 4 3 2 1
Timing Diagram for G3 or S4-5/M-off (Suspend Well Off) to S0/M0 [non Deep S4/S5 Platform]
+3VLP
T1=NA
EC_ON
D D
T2>100 ms
ON_OFF
T5=110ms T6=100ms
PBTN_OUT#
EC_RSMRST#
T4=110ms
PM_SLP_S5#
PM_SLP_S4#
SYSON T7=0ms
C C
PM_SLP_S3#
T8=20ms
SUSP#
KB_RST# T9=20ms
EC_SCI
VR_ON
T10=100ms
12/11/20
VGATE
B B
PCH_PWROK T11=20ms
SYS_PWROK T12=40ms
H_CPUPWRGD
PM_DRAM_PWRGD
PLT_RST#
A A
Color Command
Signal Names Timing of these signals is set by PCH or processor
Signal Names Timing of these signals should be met by the platform (EC)
Signal Names Timing of these signals is set by IntelR MVP

Voltage rails or chip-to-chip buses Security Classification Compal Secret Data Compal Electronics, Inc.
Signal Names Issued Date 2014/2/11 Deciphered Date 2014/2/11 Title
Power Sequence
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 34 Card Reader 2012/04/27 HW The Card reader USB signal is incorrect. SWAP UR1 USB signal P/N 0.2
D D
3
10
11
12
13
14
C 15 C
16
17
18
19
20
21
22
23
24
25
26
27
B B
28
29
30
31
32
33
34
35
36
37
38
A A
39
40
41

HW-PIR Page.1
0.1
5 4 3 2 1
A B C D
EMI@ PL1
SMB3025500YA_2P
VIN +3VALW
1 2
ADPIN EMI@ PL3
SMB3025500YA_2P
PJPDC1 @ 1 2
1
1000P_0402_50V7K
1000P_0402_50V7K
1 2
2.2K_0402_5%
100P_0402_50V8J
100P_0402_50V8J
2 3
1
3 4
2
EMI@ PC1
EMI@ PC2
PC3
EMI@ PC4
4 5
2
5 6
PR3
EMI@
6 7 PR4
7 8 33_0402_5%
1
8 9 1 3 PSID-3 1 2 PS_ID <43>
S
1
9 10 PQ7
1
10 11 FDV301N_G 1N SOT23-3
11
G
2
ACES_50293-0117N-001
100K_0402_1%
2
EMI@ PL2
PR8
PR6
BLM15HG601SN1D_2P
PSID 2 1 PSID-2 2 1
Adapter 240W +5VALW
240W/19.5V=12.3A Adapter connector:
1
10K_0402_1%
1
C
1.X PSID-1 2 PQ2
2.ADPIN B
15K_0402_1%
MMST3904-7-F_SOT323~D
2
3.ADPIN E
3
B+
PR9
4.ADPIN @
.1U_0402_16V7K
.1U_0402_16V7K
1
5.ADPIN
1
BATT+ PD1
6.GND
EMI@ PC15
EMI@ PC16
SM24_SOT23
1
7.GND
2
BATT++
BATT+
EMI@ PL4
SMB3025500YA_2P 8.GND
1 2 9.GND
10.PSID
EMI@ PL5
SMB3025500YA_2P 11.X
1 2 BATT++
放放DRAM下下下B+兩兩
100P_0402_50V8J
PQ3
1
1
1000P_0402_50V7K
0.022U_0402_25V7K
0.01U_0402_25V7K
1
EMI@ PC8
EMI@ PC9
SI3457CDV-T1-GE3_TSOP6
EMI@ PC6
EMI@ PC7
6
2
1
5
2
PD2 PD3 2 2
4 1
B+_BIAS
D
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMI@ EMI@ B+
100K_0402_1%
0.1U_0402_25V6
0.22U_0603_25V7K
1
G
2
1
PR12
PC10
PC11
3
2
2
2
PBATT1
@
1
+5VALW PR13
1
2
2 BATT_TEMP <43,58> 100K_0402_1%
3 1 2 VSB_N_001
3
1VSB_N_003
4
4 5 CLK_SMB PR15 PR16 PR14
5 6 DAT_SMB 100_0402_5% 10K_0402_1% 100K_0402_1%
6 7 BATT_PRS 1 2 1 2
7 8 SYS_PRES +3VALW PR17
1
8 9 BAT_ALERT 0_0402_5% D
9 10 1 2 VSB_N_002 2 PQ4
10 11 PR18 <60> POK G 2N7002KW _SOT323-3
11 12 100_0402_5%
.1U_0402_16V7K
S
3
12
1
13 1 2
PC12
13 EC_SMB_CK1 <42,43,59>
PR20 @
2
ACES_51481-01371-P01 100_0402_5%
Battery 92W 1 2
Battery connector: 92W/12V=7.7A EC_SMB_DA1 <42,43,59>
1.BATT++
2.BATT++
3.BATT++
3
4.BATT++ 3
5.CLK_SMB <43,59> ADP_I

6.DAT_SMB
7.BATT_PRS
8.SYS_PRES For PROCHOT CPU thermal protection at 93 +/- 3 degree C
9.BAT_ALERT PR2
10.GND @
240W
1K_0402_1%
11.GND JRTC1 PD5 VCIN1_PH= 1V
12.GND 1 2 1 JRTC1 2
13.GND 1 2 1 reset = 0.84V +3VALW +3VLP
2 +RTC_CELL
2
G1
3
4 +3VLP
3 180W PR23
VCIN0_PH = 1.2V
G2 VCIN1_PH=0.77V
2
BAS40CW _SOT323-3 110K_0402_1%
reset = 0.63V PR24 PR25 @
ACES_50271-00201-001 12.1K_0402_1% 12.1K_0402_1%
1
<43> VCIN0_PH
<43,59,8> H_PROCHOT# <43> VCIN1_PH
1
2
PR26 PC13 @
PH1
2
PC14 100K_0402_1% .1U_0402_16V7K 100K_0402_1%_TSM0B104F4251RZ
1
1U_0603_25V6K
1
1
D
4
1 2 2 PQ8 <43> ECAGND 4
<43,58> BATT_TEMP G DMN65D8LW -7_SOT323-3

100K_0402_1%
S
3
2
PR28

1
PWR-DCIN / BATT CONN / OTP
Date: W ednesday, March 26, 2014 Sheet 58 of 69
A B C D
A B C D
CC = 3A
1
D
PQ700 2
VIN DMN65D8LW-7_SOT323-3
S
G
PR701 PR700 CV = 17.7V
3
3M_0402_5% 1M_0402_5%
PQ707
MDU1516URH_POWERDFN56-8-5
P1 2 1 2 1
P2
1 Iada=0~12.3A(240W)
2
5 3 Iada=0~9.23A(180W)
1000P_0402_50V7K
PR726
1 2 ADP_I = 40*Iadapter*Rsense
4
4.7_0402_5% PQ702 PQ703
PC722
1 1
1 2 MDU1516URH_POWERDFN56-8-5
PR702
B+ MDU1516URH_POWERDFN56-8-5
1 1 0.004_1206_1% 1
2 2 2
5 3 3 5 1 4 5 3
0.1U_0402_25V6
2 3
1 CSSN_1
1 CSSP_1
PC701
4
4
PQ701
BATSRC_CHG
1
MDU1516URH_POWERDFN56-8-5 CHG_B+
2
BATDRV_CHG
EMI@ PL701
4.7_0402_5% PD700
1UH_6.6A_20%_5X5X3_M
0_0402_5%
0_0402_5%
PR725 2 1 2
PC723 BATT++
PR703
PR704
10U_0805_25V6K
10U_0805_25V6K
2
1 2 1
1
2200P_0402_50V7K
PC702
PC705
PC706
0.1U_0402_25V6
1
1
3 0.047U_0402_25V7K
@EMI@ PC703
VIN
EMI@ PC704
2
2
1000P_0402_50V7K PC707 PC708 PC709 1 2
2
1U_0603_25V6K 0.1U_0402_25V6 0.1U_0402_25V6
2
4.12K_0603_1%
4.12K_0603_1% BAT54CW_SOT323-3
1
1 2 1 2 1 2
10_1206_1%
2.2_0603_1%
PR706
PR705
1
PR707
PR708
2
+3VALW
2
PC710 PQ704
2.2U_0603_16V6K
REGN_CHG 1
5
1 2
BTST_CHG
20K_0402_1%
1
DH_CHG
DL_CHG
LX_CHG
AON6552 1N DFN5X6
PC711 PR710
PR709
1U_0603_25V6K 6.65K_0402_1%
DH_CHG 4
1 2
PU700 PQ705
28
27
26
25
24
23
22
1
D 2N7002W-T/R7_SOT323-3
2TB_STAT#_CHG
VCC
REGN
GND
BTST
PHASE
HIDRV
LODRV
G PR712
3
2
1
29 S PL700 0.01_1206_1%
CSSP_2
CSSN_2
2 2
3
PWPD 5.6UH_PCMB104T-5R6MS_8A_20%
PR711 LX_CHG 1 2CHG1 4 BATT+
1 21 1 2
ACN ILIM 2 3
1
1.13K_0402_1% PQ706
5
2 20
SBR3U40P1-7_POWERDI123-2
PR713
CSON_1
CSOP_1
ACP SRP 4.7_1206_5%
@EMI@
MDV1525URH 1N
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
1
CMSRC_CHG 3 19
PD701
2
CMSRC SRN
1
SNUB_CHG
PC712
PC713
PC714
DL_CHG 4
1
ACDRV_CHG 4 18 BATDRV_CHG PC715
2
ACDRV BQ24780RUYR_WQFN28_4X4 BATDRV 680P_0402_50V7K
2
@EMI@
2
<17,37,43> ACIN 5 17 BATSRC_CHG
3
2
1
ACOK BATSRC
PR714
REGN_CHG 1 2
VIN ACDET_CHG 6 16 TB_STAT#_CHG
120K_0402_5%
100K_0402_5% ACDET TB_STAT#

324K_0402_1%
1
PC716 PC717 PC721

1
1 2 7 15 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6

PR715
IADP BATPRES#
1
<43,58> ADP_I 1 2 1 2 1 2
PR716
PROCHOT#
PR717 PR718
CMPOUT
0_0402_5% 10K_0402_5%
CMPIN
100P_0402_50V8J
IDCHG
2
PMON
SDA
2
SCL
2
PR722
PC718
AC Det
2
10_0402_5%
Max:18.16V 1 2
1
10
11
12
13
14
Typ :17.98V
Min :17.8V +3VALW PR723
1
10_0402_5%
1
1 2 1 2
PR719
49.9K_0402_1%
PC719
0.1U_0402_25V4Z~D PC720
2
2
100P_0402_50V8J
2
0_0402_5% PR724
0_0402_5% PR720
0_0402_5% PR721
3 3
1
1
ADPI = 0.004*40*IADP = 0.16 * IADP
Adapter = 240W
CP = 240W/19.5V*0.9 = 11.07A
ADPI = 1.77V
IPCC= 240W/19.5V*0.95 = 11.69A
<42,43,58>
<42,43,58>
EC_SMB_DA1
EC_SMB_CK1
ADPI = 1.86V
<43,58,8>
H_PROCHOT#
IPCC(hybrid)= 240W/19.5V = 12.3A

ADPI = 1.97V
PROCHOT = 240W/19.5V+(1*0.95) = 13.25A
ADPI = 2.12V
Adapter = 180W
CP = 180W/19.5V*0.9 = 8.30A
APDI = 1.33V
IPCC = 180W/19.5V*(1*0.95) = 8.77A
ADPI = 1.40V
IPCC(hybrid)= 180W/19.5V = 9.23A
ADPI = 1.48V
PROCHOT = 180W/19.5V+(1*0.95) = 10.18A
ADPI = 1.62V
4 4

PWR-Charger
0.1
A B C D
A B C D E
+3VLP
PC101
4.7U_0603_6.3V6K
1 2
1 1
Output capacitor ESR need follow
below equation to make sure feed back
3.3V*8.7A=28.71W loop stability
ESR=20mV*L*fsw/2V
28.71/0.85/11=3.07A PR101 PR102
6.49K_0402_1% 15K_0402_1%
1 2 1 2
5V*7.8A=39W VFB=2V VFB=2V
39/0.85/11=4.17A
PR103 PR104
10K_0402_1% 10K_0402_1%
3.07A+4.17A=7.24A 1 2 1 2
POK need pull high, it
will pull high on VS
transfer circuit
1
3/5V_B+
PR105 PR106
8.87K_0402_1% 8.06K_0402_1%
EMI@ PL100
1UH_6.6A_20%_5X5X3_M
B+
10U_0805_25V6K
10U_0805_25V6K
1 2 3/5V_B+
FB_3V
FB_5V
1
CS2
CS1
PC114
PC102
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2
1
5
@EMI@ PC100
EMI@ PC103
PC104
PC113
MDV1525URH 1N PDFN33-8
5
<58> POK
2
@ PU100 21
CS2
VFB2
VREG3
VFB1
CS1
TP
PQ100
2 2
4
PQ102
3V_EN 6 20 5V_EN
EN2 EN1 PR107 4
200_0402_1%
7 19 1 2
DCR = 18mohm
1
2
3
PGOOD VCLK
DCR = 21mohm
3
2
1
PL101 LX_3V 8 18 LX_5V
PC105 PR108 SW2 TPS51285BRUKR_QFN20_3X3 SW1 PR109 PC106 PL102
1 2 LX_3V 0.1U_0402_25V6 0_0603_5% 0_0603_5% 0.1U_0402_25V6 3.3UH_PCMB064T-3R3MS_7A_20%
+3VALWP 1 2 1 2 BST_3V 9 17 BST_5V 1 2 1 2 LX_5V 1 2
VBST2 VBST1 +5VALWP
S COIL 2.2UH +-20% 7.8A 7X7X3
1
5
4.7_1206_5%
680P_0603_50V8J 4.7_1206_5%
UG_3V 10 16 UG_5V
DRVH2 DRVH1
1
@EMI@ PR110
@EMI@ PR111
VREG5
MDU1512RH 1N POWERDFN56-8
DRVL2
DRVL1
ESR = 18mohm
MDU1512RH 1N POWERDFN56-8
VO1
VIN
ESR = 18mohm
PQ101
1 1
2
PQ103
4
11
12
13
14
15
2
+ PC107 4 + PC108
680P_0603_50V8J
220U_6.3V_M LG_3V LG_5V 220U_6.3V_M

1
1
2 2
@EMI@ PC109
@EMI@ PC110
1
2
3
3
2
1
+5VALWP
2
2
3/5V_B+
3.3VALWP VL
TDC=8.7A
Peak Current 12.4A
1
3
OCP current 14.8A PC111
3
FSW=475kHz 4.7U_0603_6.3V6K 5VALWP
2
TYP MAX OVP=Vout*(112.5%~117.5%) TDC=7.8A
H/S Rds(on) : 11.5mohm 14mohm Peak Current 11.2A
L/S Rds(on) : 4.2mohm 5mohm OCP=Vtrip/Rdson+Iripple/2 OCP current 13.4A
Vtrip=Ics(min)*Rcs/8+1mV FSW=400kHz
EN Vcs=Ics*vcs should be in the range of 0.2~2V TYP MAX
Rising=1.6~0.3V H/S Rds(on) : 11.5mohm 14mohm
Vout=VFB*(1+Rtop/Rbot) L/S Rds(on) : 4.2mohm 5mohm
PR100 0_0402_5% VFB=2V
3V_EN 1 2
PR112 0_0402_5%
5V_EN 1 2 PJP100 PJP102
+5VALWP 1 2 +5VALW +3VALWP 1 2 +3VALW
1 2 1 2
PD100 PR113 JUMP_43X118 @ JUMP_43X118 @
2 2.2K_0402_5%
<43> EC_ON 1 1 2
3
<35> USBCHG_DET_D
BAS40CW_SOT323-3
PR114 0_0402_5%
1 2
4 <43> VCOUT0_PH# 4
@ PD101 @ PR115
LL4148_LL34-2 1M_0402_1%
2 1 1 2
VIN
200K_0402_1%
4.7U_0603_6.3V6K
1
PR116
PC112

2
PWR-3.3VALWP/5VALWP
2
Size
0.1
A B C D E
5 4 3 2 1
D D
1.35V*(7.64A+1A)=11.66W
11.66/0.85/11=1.24A
Pin19 need pull separate from +1.35VP.

If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
you can change from +1.35VP to +1.35VS. TDC 0.7A
PJP203@
B+ 1 2 1.35V_B+ PR200 Peak Current 1A
1 2 2.2_0603_5%
JUMP_43X39 BST_1.35V 1 2 BOOT_1.35V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1
1
@EMI@ PC200
EMI@ PC201
PC202
PC203
DH_1.35V +0.675VSP
2
2
1.35VP
SW _1.35V
TDC=7.64A
10U_0805_6.3V6K
10U_0805_6.3V6K
1
Ipeak=10.92A
1
PC204
PC205
PC206
5
OCP=13.1A
0.1U_0603_25V7K
16
17
18
19
20
2
PQ200
C
Switching Frequency: 285kHz PU200 C
2
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PAD
4 DL_1.35V 15 1
LGATE VTTGND
14 2
PL201 PR201 PGND VTTSNS
1
2
3
1UH_11A_20%_7X7X3_M 6.49K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP PC207 CS RT8207MZQW _W QFN20_3X3 GND
1
1U_0603_10V6K
5
1 2 12 4 VTTREF_1.35V
220U_B2_2.5VM_R15M
VDDP VTTREF
PQ201
1 @EMI@ PR202 PR203

4.7_1206_5% 5.1_0603_5%
+ 1 2 VDD_1.35V 11 5
PC209
+5VALW +1.35VP
1 2
VDD VDDQ
1
PGOOD
OVP: 110%~120%
4 PC210
2.2_0603_5%
VFB=0.75V, Vout=1.35V
TON
1
2
2 @EMI@ PC211 0.033U_0402_16V7K
FB
S5
S3
2
TYP MAX 680P_0402_50V7K PC212
PR204
2
H/S Rds(on) : 23.2mohm 27.8mohm 1U_0603_10V6K
10
6
L/S Rds(on) : 13.7mohm 16.4mohm
1
2
3
FB_1.35V
EN_0.675VSP
TON_1.35V
EN_1.35V
PR205
8.06K_0402_1%
PR206 1 2 +1.35VP
887K_0402_1%
B 1.35V_B+ 1 2 B
1
PR208 PR207
0_0402_5% 10K_0402_1%
1 2
<43,62,64> SYSON
2
Mode Level +0.675VSP VTTREF_1.35V
S5 L off off
1
@ PC213
S3 L off on 0.1U_0402_10V7K
S0 H on on @ PJP200
2
+1.35VP 1 2 +1.35V
1 2
Note: S3 - sleep ; S5 - power off PR209 JUMP_43X118
0_0402_5%
1 2 1
330U_D2_2V_Y
<43,45,62> SUSP#
+
PC208
1
@ PC214
0.1U_0402_10V7K 2
2
PJP202@
1 2
+0.675VSP 1 2 +0.675VS
A
JUMP_43X39 A

PWR-1.35VP/0.675VSP
5 4 3 2 1
5 4 3 2 1
PJP301@
+1.05VSP_B+ 1 2
1 2 B+
JUMP_43X39
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1.05V*6.5A=6.82W
1
@EMI@ PC301
EMI@ PC302
PC303
PC304
+3VS 6.82/0.85/11=0.73A
2
@
5
1
PQ300
D PR301
1.05VSP D
100K_0402_5% TDC 6.5A
4
Peak Current 9.3A
2
<43> +1.05V_PGOOD
PU300
PR302
2.2_0603_5%
PC305
0.1U_0603_25V7K
OCP current 11.1A
PR303 1 10 BST_+1.05VSP 1 2 1 2 MDV1528URH 1N PDFN33-8 FSW=290kHz
3
2
1
137K_0402_1% PGOOD VBST
PR300 1 2 TRIP_+1.05VSP 2 9 UG_+1.05VSP PL300
0_0402_5% TRIP DRVH 1UH_6.6A_20%_5X5X3_M
<43,45,61> SUSP# 1 2 EN_+1.05VSP 3 8 SW _+1.05VSP 1 2
EN SW
+1.05VSP
@ PR304 FB_+1.05VSP 4 7
VFB V5IN
+5VALW
1
0_0402_5%
0.1U_0402_16V7K
1 2 RF_+1.05VSP 5 6 LG_+1.05VSP
220U_B2_2.5VM_R15M
<43,61,64> SYSON TST DRVL
1
PR305 @EMI@
@ PC300
1
1
11 4.7_1206_5%
TP
1
+
PQ301
PC306
2
2
PR306 TPS51212DSCR_SON10_3X3 PC308 4
470K_0402_1% 1U_0603_6.3V6M
1
PC309 @EMI@ 2
2
680P_0402_50V7K
3
2
1
2
Switching Frequency: 290kHz
C PR307 C
4.99K_0402_1%
OVP: 120%-130%
1 2 VFB=0.7V
TYP MAX
H/S Rds(on) : 23.2mohm 27.8mohm
1
L/S Rds(on) : 13.7mohm 16.4mohm

PR308
10K_0402_1%
2
@ PJP300
+1.05VSP 1 2 +1.05VS
1 2
JUMP_43X118
+3VS
B +5VS 4.7U_0603_10V6K PU401 RT9041E-15GQW _W DFN8_2X2

PJP403 B
1 2
2 1 8 1 +1.5VSP
+1.5VSP 1 2 +1.5VS
VIN VOUT @ JUMP_43X39
PC405 7 2 FB_1.5V
NC ADJ 2.2U_0603_10V6K
1
1
6 3 PC406
VDD PGOOD
2
+3VS 2 1 EN_1.5V 5 4 4.99K_0402_1%
EN GND
1
9 PR405
1U_0402_10V6K PGND
1
12K_0402_1%
2
1U_0402_10V6K PR407 PC409

2
PC408
5.62K_0402_1%
PR406
FB=0.8V
2
Vo=0.8(1+Rt/Rb)=1.51V
A A

PWR-1.05VSP/1.5VSP
5 4 3 2 1
PR603 PR604
0.95V*86.2=81.7W B+ @ PJP600 0.001_1206_LE_1% 0.001_1206_LE_1%
81.7/0.85/11=8.7A 1
1 2
2 4 1 GPU_B+_VRAM 4 1 GPU_B+
JUMP_43X118 3 2 3 2
<64> GPU_B+_VRAM
CSSN_B+
CSSN_VGA
CSSP_VGA
CSSP_B+
+3VS
<49> CSSP_B+ <49> CSSN_B+ <49> CSSP_VGA <49> CSSN_VGA
1
PR600
0_0402_5%~D
10U_0805_25V6K
2200P_0402_50V7K~D
@ PR610
4.7U 25V K X5R 0805
4.7U 25V K X5R 0805

0_0402_5%
1
1 2
PC600
PC603
PC606
@EMI@ PC634
NVVDD PWM_VID <46>
2
AON6970_DFN5X6D-8-7
AON6970_DFN5X6D-8-7
PR602
0_0402_5%~D
1U2_UGATE1
1U2_UGATE1
@
PQ606
PQ605
2
2
+VGA_CORE
D1
G1
D1
G1
PL601
0.22UH_PCME064T-R22MS0R985_28A_20%
PR607 7 7 U2_PHASE1 2 1
D2/S1 D2/S1
1U_0402_6.3V6K
0_0402_5%
VBOOT=0.875V
1
1 2 NVVDD PSI <46>

1
PC613
G2
G2
S2
S2
S2
S2
S2
S2
47P_0402_50V8J~D
1
PR606
PC614
4.7_1206_5%
2
1
39.2K_0402_1%
@EMI@ PR608
3
U2_LGATE16
+3VS
@
VGA_CORE
680P_0603_50V7K
2
2
TDC 86A
12
49,63> 3V3_MAIN_EN
@EMI@ PC615
Peak Current 140A
1
PR611 PR613 PR614
1.5K_0402_1% 39.2K_0402_1% @ OCP=168A
2
GPU_REFIN 1 2 1 2 10K_0402_1%~D U2_LGATE1
@ PR615 TYP MAX
1
2
@ 0_0402_5% L/S Rds(on):6.7mohm ,8.5mohm
PR623
3K_0402_1%
30.1K_0402_1%
1500P_0402_50V7K
1500P_0402_50V7K
2
2
@ 1 2 PR649
DGPU_PWR_EN <21,46,49>
47P_0402_50V8J~D
1
PR620 11.8K_0402_1%
PR616
PC616
PC617
PC618
1
@ 0_0402_5%~D
@ PR621
2
1
0_0402_5%
1
2
1 2
3V3_MAIN_EN <46,49,63>
2N7002KW_SOT323-3
2
@ D
1
2 GPU_B+
GPU_REFADJ
U2_BOOT1
10U_0805_25V6K
1
@ PR618
PQ610
G
0.01U_0402_16V7K
1
4.7U 25V K X5R 0805
4.7U 25V K X5R 0805

AON6970_DFN5X6D-8-7
AON6970_DFN5X6D-8-7
U2_UGATE1
GPU_VID
PR631 @
GPU_PSI
S
GPU_EN
1.5K_0402_1%
3
1
10K_0402_1%~D PR601
PC626
PC601
PC604
PC607
1U2_UGATE2
1U2_UGATE2
2.2 +-5% 0603
2
U2_BOOT1 1 2
2
2
1
PQ608
PQ607
PR650
.1U_0603_25V7K
6
2
340K_0402_1% PU600
PC612
2
GPU_B+ 2 1
UGATE1
BOOT1
D1
G1
D1
G1
VID
PSI
EN
REFADJ
PL602
<47> VSSSENSE_VGA PR622 0.22UH_PCME064T-R22MS0R985_28A_20%
0_0402_5% GPU_REFIN 7 24 U2_PHASE1 7 7 U2_PHASE2 2 1
1 2 REFIN PHASE1 D2/S1 D2/S1
PR624 GPU_VREF 8 23 U2_LGATE1
100_0402_1% VREF LGATE1
G2
G2
S2
S2
S2
S2
S2
S2
1
1 2 GPU_TON 9 22 U2_PWM3 PR625 +5VS
4.7_1206_5%
TON GND/PWM3 2.2 +-5% 0603
@EMI@ PR626
2200P_0402_50V7K~D
U2_LGATE2 6
U2_LGATE2 6
PR627 10 21 1 2
0_0402_5% RGND PVCC
7> VCCSENSE_VGA
680P_0603_50V7K
1
1 2 11 20 U2_LGATE2
TALERT/ISEN2
@EMI@ PC635
12
VSNS LAGTE2
TSNS/ISEN3
@EMI@ PC621
VCC/ISNE1
12 19 U2_PHASE2
1U_0603_6.3V6M
2
SS PHASE2
UGATE2
1 2
PGOOD
PR617
BOOT2
+VGA_CORE
2
1
2.2 +-5% 0603

PC622
GND
PR629 U2_BOOT2 1 2 1 2
100_0402_1% PC619
2
RT8813AGQW_WQFN24_4X4 .1U_0603_25V7K
25
13
GPU_TALERT/ISEN2 14
15
16
17
18
GPU_TSNS/ISEN3
GPU_DSBL/ISEN1
GPU_PGOOD1
U2_UGATE2
+5VS GPU_B+
U2_BOOT2
10U_0805_25V6K
AON6970_DFN5X6D-8-7
AON6970_DFN5X6D-8-7
4.7U 25V K X5R 0805
4.7U 25V K X5R 0805

U2_UGATE3
U2_UGATE3
1
PC602
PC605
PC608
2
2
1
PQ611
PQ609
PR643
2
1
2.2 +-5% 0603
D1
G1
D1
G1
<46,49> GPU_PGOOD PL603
2
+3VS 0.22UH_PCME064T-R22MS0R985_28A_20%
2
PR638 7 7 U2_PHASE3 2 1
10K_0402_1%~D
D2/S1 D2/S1
1
PR640 @EMI@
PC629
1
.1U_0603_25V7K
PR639
10K_0402_1%
G2
G2
S2
S2
S2
S2
S2
S2
2
1
4.7_1206_5%
1
PR619
3
U2_LGATE36
U2_LGATE36
0_0402_5%
2
1 2 PR641 8 3 U2_UGATE3
680P_0603_50V7K
0_0402_1% VCC UGATE
0.01U_0402_16V7K
12
1
PC627 2
DGPU_PWR_EN 1 1 4 U2_BOOT3
@EMI@ PC628
U2_PHASE3 @ EN BOOT
U2_PWM3 1 2 5 2 U2_PHASE3
2
2
PR642 PWM PHASE
0_0402_5% 6 7 U2_LGATE3 PC625
GND LGATE PR633
2.2 +-5% 0603
TP
1
U2_BOOT3 2 1 2
9
.1U_0603_25V7K
2
PR646 PU601
RT9610BZQW WDFN8 MOSFET DRIVER ET88
10K_0402_1%
PR648
1
10K_0402_1%
U2_PHASE2

U2_PHASE1
PWR-VGA_CORE
5 4 3 2 1
1.35V*18.6A=25.11W
33.42/0.85/11=2.68A
D PJP303@ D
+1.35VS_VGAP_B+ 1 2 GPU_B+_VRAM <63>
1 2
JUMP_43X39
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VDGPUP
1
@EMI@ PC314
EMI@ PC316
PC307
PC310
TDC 18.6A
Peak Current 26.57A
2
+3VS
MDU1516URH_POWERDFN56-8-5
@
OCP current 31.88A
5
FSW=290kHz
1
<46> +1.35VS_VGA_PGOOD
PQ303
PR318 4
100K_0402_5%
PR309 PC315
2
PU301 2.2_0603_5% 0.1U_0603_25V7K
PR312 1 10 1
BST_+1.35VS_VGAP 2 1 2
3
2
1
162K_0402_1% PGOOD VBST
PR313 1 2 TRIP_+1.35VS_VGAP
2 9 UG_+1.35VS_VGAP PL301
0_0402_5% TRIP DRVH 1UH_PCMB104T-1R0MH_18A_20%
<46> FBVDD_EN 1 2 3
EN_+1.35VS_VGAP 8 SW _+1.35VS_VGAP 1 2
EN SW
+1.35VS_VGAP
@ PR315 4
FB_+1.35VS_VGAP 7
VFB V5IN +5VALW
1
MDU1511RH_POWERDFN56-8-5
0_0402_5%
0.1U_0402_16V7K
220U_B2_2.5VM_R15M
220U_B2_2.5VM_R15M
<43,61,62> SYSON 1 2 5
RF_+1.35VS_VGAP 6 LG_+1.35VS_VGAP 1 1
TST DRVL
1
PR314 @EMI@
@ PC312
C 11 4.7_1206_5% + + C
PC311
PC318
TP
PQ302
2
2
PR311 TPS51212DSCR_SON10_3X3 PC313 4
470K_0402_1% 1U_0603_6.3V6M 2 2
1
PC317 @EMI@
2
680P_0402_50V7K
3
2
1
2
Switching Frequency: 290kHz
PR316
9.31K_0402_1%
OVP: 120%-130%
1 2 VFB=0.7V
TYP MAX
H/S Rds(on) : 11.4mohm 14mohm
1
PR317
10_0402_1% L/S Rds(on) : 2.7mohm 3.3mohm
PR310 2 1
10K_0402_1% <49> FB_VDDQ_SENSE
2
@ PJP302
B 1 2 B
+1.35VS_VGAP 1 2 +1.35VS_VGA
JUMP_43X118
PJP304@
1 2
1 2
JUMP_43X39
PJP305@
1 2
1 2
JUMP_43X39
A A
Title
<Title>

A3 LA-B751P 0.1

5 4 3 2 1
5 4 3 2 1
+5VS CPU_B+
PC504 @EMI@
PC507 @EMI@
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
PC501
1U_0603_10V6K
0.22U_0603_16V7K @
1
1
2
1
PC502
PC503
PC505
PC506
AON6970_DFN5X6D-8-7
AON6970_DFN5X6D-8-7
1
PR501
2
+VCCIO_OUT PR500 130_0402_1%~D PR502
UGATE3
UGATE3
0_0402_5%
2
2 1 2.2_0603_5%
1
@ PR503 75_0402_5%
PQ505
PQ506
2 1
D PU501 D
1
PR504 54.9_0402_1% 6 1 UGATE3 PL501
2 1 VCC UGATE 0.22UH_PCME064T-R22MS_28A_20%
D1
G1
D1
G1
7 2 BOOT3
FCCM BOOT
PR505 0_0402_5% PWM3 3
PWM PHASE
8 PHASE3
D2/S1
7
D2/S1
7 PHASE3 4 1 +VCC_CORE
680P_0603_50V7K
1 2 PR507
<12> VIDSOUT PR506 0_0402_5% 21K_0402_1% 4 5 LGATE3 P3_SW 3 2 V3N
GND LGATE
PC508
1 2 1 2 9
G2
G2
S2
S2
S2
S2
S2
S2
<12> VIDALERT_N PR508 0_0402_5% TP PR510
1 2 PR509 ISL6208BCRZ-T_QFN8_2X2 10K_0603_1%
<12> VIDSCLK
2
3.24K_0402_1% 2 1
1 2 SNB_CPU_P3
LGATE3
LGATE3
4.7_1206_5%
3.65K_0603_1%
ISEN3
PR512
10_0402_1%
PR511
21K_0402_1%
PR513
PR514
PR515
0_0402_5% @ PR516
1 2 1 2 10K_0402_1%
<43> IMVP_VR_ON V1N 1 2
+5VS
1
BOOT2 @ PR518
UGATE2 10K_0402_1%
ISUMP
PR519 1.91K_0402_1% PHASE2 V2N 1 2
ISUMN
2 1 SDA PR520
+3VS ALERT# 0_0402_5%
PC509
<17,8> IMVP_PWRGD
1U_0603_10V6K
32
31
30
29
28
27
26
25
VCORE_VDDP 1
1 2
PC500
VCC_core (Base on PDDG rev 0.8)
SDA
ALERT#
SLOPE/PROG1
PROG3
PROG2
BOOT2
UGATE2
PHASE2
1 2 TDC 33A
1000P_0402_50V7K Peak Current 95A 1.8V*33A=59.4W
PR522 SCLK 1
SCLK LGATE2
24 LGATE2 @
PR523 DC Load line -1.5mV/A 59.4/0.85/11=6.35A
PR521 0_0402_5% VR_ON 2 23
100K_0402_1% 1 2 VCC_PGOOD 3 VR_ON
PGOOD
VDDP
PWM3
22 PWM3 2 1 Icc_Dyn_VID1 60A
C
2 1 PR524
0_0402_5%
IMON 4
5 IMON LGATE1
21
20
LGATE1
PHASE1
0_0402_5%~D OCP current 114A C
1 2 VR_HOT#1 6 VR_HOT#
NTC
PHASE1
UGATE1
19 UGATE1 TYP MAX
COMP 7 18 BOOT1
2 1 1
PR525
2
NTC
FB 8 COMP BOOT1 17 L/S Rds(on):6.7mohm ,8.5mohm
<43> VR_HOT# FB VIN
PH500 3.83K_0402_1% PR526 DCR 0.82m ohm
FB2/VSEN
470K_0402_5%_ TSM0B474J4702RE 0_0402_5%
B+
ISUMN
ISUMP
ISEN3
ISEN2
ISEN1
33 1 2CPU_B+ EMI@ PL504
VDD
RTN
+1.05VS @ PR527 PR528 PAD FBMA-L11-453215-800LMA90T_1812
0.22U_0603_25V7K
1 2 27.4K_0402_1% CPU_B+ 1 2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PC515@EMI@
PC516@EMI@
0.1U_0402_25V6K~D
AON6970_DFN5X6D-8-7
AON6970_DFN5X6D-8-7
2 1 9 PU500
10
11
12
13
14
15
16
1
47P_0402_50V8J
0_0402_5% PR529 ISL95812HRZ-T_QFN32_4x4

@
PC510
1 2
UGATE2
UGATE2
1
1
PC511
PC512
PC513
PC514
2
6.04K_0402_1%
2
2
PQ504
PQ503
PR530
1
1_0603_1%~D
1 2
+5VS
D1
G1
D1
G1
PL502
4700P_0402_50V7K~D
0.22UH_PCME064T-R22MS_28A_20%
1
PC520 7 7 PHASE2 4 1
D2/S1 D2/S1 +VCC_CORE
680P_0603_50V7K
PR533 470P_0402_50V7K PC518
2 1 2 1 1U_0603_10V6K PR536 3 2
2
1
1
PC521
PC524
3.65K_0603_1% P2_SW
G2
G2
V2N
S2
S2
S2
S2
S2
S2
499_0402_1% 1 2
549_0402_1%
PR538
2
2
1
PR537 SNB_CPU_P2 10K_0603_1%

PR535
2 1 1 2
LGATE2
LGATE2
1
4.7_1206_5%
2
1
6800P_0402_25V7K 909_0402_1%
ISUMP
PR541
2.87K_0402_1% ISEN2
2
PR539
@ PR546 PR544
2
2
1.5K_0402_1%
PR543 10K_0402_1% 10_0402_1%

2
PR545
2K_0402_1% PR534 V1N 2 1
2
B PC525 BOOT2 2 1 1 2 B
2 1
2
47P_0402_50V8J 2.2_0603_5% @ PR547
1
2 1
PC522 10K_0402_1%
1
ISUMN
PC526
0.22U_0603_16V7K V3N 2 1
PC527
1
330P_0402_50V7K~D
1
PC528
PC536 @EMI@
PC537 @EMI@
0.15U_0402_10V6K~D CPU_B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
AON6970_DFN5X6D-8-7
AON6970_DFN5X6D-8-7
1 2 1 1
100U_25V_M
100U_25V_M
PC530
+
PC531
ISEN3 +
UGATE1
UGATE1
1
PC533
PC534
PC535
PC529
0.1U_0603_25V7K~D
ISEN2 PR548 1 2 2 2
2
PQ502
PQ501
0_0402_5%
1 2
1
ISEN1 PC538 PL503
0.068U_0603_50V7K 0.22UH_PCME064T-R22MS_28A_20%
D1
G1
D1
G1
PC539 1 2
0.22U_0402_6.3V6K
2 1 <12> VCCSENSE 7 7 PHASE1 4 1
D2/S1 D2/S1 +VCC_CORE
680P_0603_50V7K
PR549
PC540 11K_0402_1% 3 2
PC543
0.22U_0402_6.3V6K @ PC541 1 2 P1_SW
G2
G2
V1N
S2
S2
S2
S2
S2
S2
2 1 ISUMN 1 2
0.082U_0402_16V7K
PR551 PR552 PR553

3
2
PC545
PC544 330P_0402_50V7K PH501 SNB_CPU_P1 3.65K_0603_1% 10K_0603_1%

1
0.22U_0402_6.3V6K 10KB_0402_5%_ERTJ0ER103J 2.61K_0402_1% 1 2 1 2
LGATE1
LGATE1
1
4.7_1206_5%
2 1 1 2 1 2
PR554
ISEN1
2
1
ISUMP
PC546 @
@
1 2 PR558 @ PR555 PR556
.1U_0402_16V7K
5.1M_0402_5% V2N 2 1 10_0402_1%
2
1
A A
0.01U_0402_50V7K 1 2 BOOT1 2 1 1 2 10K_0402_1%
PC547
PR550
ISUMN 2
ISUMN ISUMP 2.2_0603_5% PC542 @ PR557
2
0.22U_0603_16V7K V3N 2 1
<12> VSSSENSE 10K_0402_1%
Local sense put on HW site

PWR-CPU_CORE
5 4 3 2 1
5 4 3 2 1
+VGA_CORE
+VCC_CORE
1 1
+ PC906 + PC905
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
10U_0603_4VAM
10U_0603_4VAM
10U_0603_4VAM
10U_0603_4VAM
330U_D2_2.5VM_R9M 330U_D2_2.5VM_R9M @ @ @ @ 1 1 1 1
1
2 2
PC904
PC907
PC908
PC909
PC927
PC928
PC929
PC930
PC931
PC932
PC933
PC934
PC999
PC1000
PC1001
PC1002
PC1003
PC1004
PC1005
PC1006
PC1007
PC1008
D D
2
2 2 2 2
+VCC_CORE +VGA_CORE
22U_0805_6.3VAM
22U_0805_6.3VAM
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
@
PC944
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
PC946
PC947
PC948
PC949
PC950
PC951
PC952
PC953
PC1009
PC1010
PC1011
PC1012
PC1013
PC1014
PC1015
PC1016
PC1017
PC945
PC900 PC901 PC902 PC903
10U_0603_4VAM 10U_0603_4VAM 10U_0603_4VAM 10U_0603_4VAM
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+VCC_CORE
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
@ @ @ @ 1 1 1 1
330U_D2_2VM_R6M
330U_D2_2VM_R6M
330U_D2_2VM_R6M
330U_D2_2VM_R6M
1
1
PC954
PC955
PC956
PC957
PC958
PC959
PC960
PC961
PC962
PC963
PC964
PC965
+ + + +
PC966
PC967
PC969
PC970
C 1 1 1 1 1 C
2
PC917 PC918 PC919 PC920 PC921 2 2 2 2
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2
1 1 1 1 1
PC922 PC923 PC924 PC925 PC926
2 2 2 2 2
+VCC_CORE
1
1 1 1 1 1 PC990 PC988 PC987 PC998 PC982
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
PC935 PC936 PC937 PC938 PC939
2
2 2 2 2 2
B B
1
1
1 1 1 1 1 PC992 PC980 PC993 PC983 PC981
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
PC940 PC941 PC942 PC943 PC975
2
2
2 2 2 2 2
1 1 1 1 1
1
1
PC985 PC996 PC995 PC989 PC991
PC977 PC973 PC972 PC976 PC971 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2
2
2 2 2 2 2
1 1
1
1
PC984 PC986 PC997 PC994 PC979
PC974 PC978 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
22U_0805_6.3VAM 22U_0805_6.3VAM
2
2
2 2
A A

PWR-PROCESSOR DECOUPLING
5 4 3 2 1
5 4 3 2 1
Power block
CPU OTP
Page 45
D Turn Off D
Input B+
DC IN +3VALWP: TDC:6.2A
Switch +5VALWP: TDC:9.8A Always
Page 46
TPS51285BRUKR Page 47
CHARGER +1.35VP/+0.675VSP: TDC:8.4A/0.7A

CC:A SYSON
RT8207MZQW
CV: Page 48
BQ24780
Page 46
C C
+1.05VSP: TDC:7A SUSP#
Battery TPS51212DSCR
Page 49
+VGA_CORE
DGPU_PWR_EN TDC:40.6A
B RT8813AGQW B
Page 50
+VCC_CORE
VR_ON TDC: 10A
TPS51624
Page 51
A A

PWR_POWER BLOCK DIAGRAM
Size
0.1
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
C C
B B
A A

PWR-PIR
Size
0.1
5 4 3 2 1
5 4 3 2 1
+3VS +3VS_MCU
MCU@
D R76 D
1 2
0_0402_5%
1 1 1 1 1 1
C49 C50 C51 C52 C53 C54
.001U_0402_50V7-M
.001U_0402_50V7-M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 2 2 2 2 2
MCU@ MCU@ MCU@ MCU@

MCU@ MCU@
+3VS_MCU +3VS_MCU
C57 1 1 C58
MCU@ MCU@
10U_0402_6.3V6M
0.01U_0402_16V7K
2 2
24
36
48
9
1
U7 STM32F103C8T7TR_LQFP48_7X7
VBAT
VDD_1
VDD_2
VDD_3
VDDA
10 18
PA0-WKUP PB0 19
11 PB1 20 1 2
12 PA1 PB2 39 R81 MCU@ 10K_0402_5%
13 PA2 PB3 40 MCU@
14 PA3 PB4 41 R2654 0_0402_5%
15 PA4 PB5 42 TP_CLK_I2C 1 2 TP_-
16 PA5 PB6 43 1 2 TP_- <38,69>
TP_DATA_I2C TP_+
17 PA6 PB7 45 TP_+ <38,69>
R2655 0_0402_5%
C PA7 PB8 46 C
PB9 MCU@
1 MCU@ 2 29 21
R82 1.5K_0402_5% 30 PA8 PB10 22 USBTP@ USBTP@
31 PA9 PB11 25 R2662 0_0402_5% R2660 0_0402_5%
USB20_N9 R83 1 MCU@ 2 22_0402_5% USB20_N9_TP 32 PA10 PB12 26 USB20_N9 1 2 USB20_N9_R 1 2 TP_-
<20> USB20_N9 PA11 PB13 TP_- <38,69>
USB20_P9 R84 1 MCU@ 2 22_0402_5% USB20_P9_TP 33 27 USB20_P9 1 2 USB20_P9_R 1 2 TP_+
<20> USB20_P9 34 PA12 PB14 28 TP_+ <38,69>
SWDIO R2663 0_0402_5% R2661 0_0402_5%
SWCLK 37 PA13 PB15
PA14 USBTP@ USBTP@
38
PA15
1
@ R85 2
OSC_IN 5 PC13-TAMPER-RTC 3
1 2 OSC_OUT 6 PD0-OSC_IN PC14-OSC32_IN 4
15K_0402_1%
R86 MCU@ 2.2K_0402_1% PD1-OSC_OUT PC15-OSC32_OUT

SWD_NRST 7 44
2
Y4MCU@ NRST BOOT0

4 3
VSS_1
VSS_2
VSS_3
1
VSSA
1 2
MCU@
1
12MHZ_12PF_5YEA12000122IFA2Q3 C59 10K_0402_5%
0.1U_0402_16V4Z R87
23
35
47
1
C60 C61 MCU@
2
12P_0402_50V8J 12P_0402_50V8J2
MCU@ MCU@
2
MCU@
Reserved for debug

SWD_NRST R75 1 MCU@ 2 0_0402_5%
T93
SWCLK R99 1 MCU@ 2 0_0402_5%

T94
SWDIO R100 1 MCU@ 2 0_0402_5%

T101
B B
A A
Title
<Title>

D <Doc> <RevCode>

5 4 3 2 1

Compal La-B751p, La-B753p Echo 15 17 With Nvidia GFX Rev 0.1 (x00)

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Compal La-B751p, La-B753p Echo 15 17 With Nvidia GFX Rev 0.1 (x00)

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A B C D E

MODEL NAME : Echo 15 17 nVidia

BOM P/N : 4319UA31L01 / 4319UA31L02 for NV

@ : Nopop Component DIS@ : Discrete Part

4 BDW@ : Intel BOARDWELL DAB0000P000

Echo 15"/17'' Block Diagram

mini DP DP 1.2 (DDI2) Broadwell M-Processor Memory Bus Dual Channel

Caldera USB3.0 port5 USB2.0 port3

RJ45 Page30 LAN(Gigabit) PCI-E2.0 port3 USB2.0 port6

Card slot RTS5227Page31 USB3.0 port2

NGFF (M.2) SATA3.0 port1

NGFF (M.2) SATA3.0 port5

NGFF (M.2) SATA3.0 port4

NGFF (M.2) SATA3.0 port3

Led x 2 Coaxial/Wire Combo

FFC Daughter/B USB3.0

KSI/KSO Backlight Wire

Wire Wire Wire

Alien Slits-R Light/B Alien head badge/B Alien Slits-L Light/B

Led x 2 Led x 2 Led x 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Caldera(Echo graphic expander) block diagram

TO EC Control CALDERA PWRGD

USB3.0 USB3.0 HUB 4x USB3.0

All POWER ready

Security Classification Compal Secret Data Compal Electronics, Inc.

Port5 Touch screen

NV AMD PCI EXPRESS

Lane 3 10/100/1000 LAN

Lane 4 M.2 Card WLAN

CLOCK SIGNAL Lane 5 PCIE 4x MUX

CLKOUT_PCIE2 10/100/1000 LAN SATA0 HDD

CLKOUT_PCIE3 M.2 Card WLAN SATA1 NGFF SSD

CLKOUT_PCIE4 dGPU (N15P) SATA2 NGFF SSD

CLKOUT_PCIE5 DGPU (Caldera) SATA3

: means Digital Ground

Broadwell AN1 SML0CLK

5 JTP SMBUS Address [TBD]

0 ohm N-MOS 0 ohm UV28

KBC N-MOS UV28

Security Classification Compal Secret Data Compal Electronics, Inc.

PECI SM_DRAMRST 0_0402_5%

<12,17,43> SYS_PWROK B 4 PM_SYS_PWRGD_BUF

XDP_TDI_R RC29 2 @ 1 51_0402_5%

DS3@ RC30 XDP_TDO_R 1 8

NODS3@ TMS/TDI no require pull high on Check list

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data

COMPENSATION PU FOR eDP

EDP Panel EDP_COMP 2 1

Security Classification Compal Secret Data Compal Electronics, Inc.

CPU1K HASWELL_BGA CFG Straps for Processor

1: (Default) PEG Train immediately following xxRESETB

0: PEG Wait for BIOS for training

Security Classification Compal Secret Data Compal Electronics, Inc.

+1.35V +1.35V_CPU_VDDQ +1.35V_CPU_VDDQ

Note: AT13 C34 AD46 H42

AT19 C36 AD8 H43

AT23 C38 AE46 H45

AV37 VDDQ VCC C45 AG46 VCC VCC H9

BB27 D38 AK8 J38

BB31 D42 AL46 J40