Digital Circuits - - Unit 7 - Week 6 : Unit 6 https://onlinecourses.nptel.ac.in/noc18_ee33/un...

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Unit 7 - Week 6 : Unit 6

Course
outline
Week 6 Assignment 6
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the portal assignment.

Week 1 : Unit 1 1) Identify the circuit shown in the figure. 1 point

Week 2 : Unit 2

Week 3 : Unit 3

Week 4 : Unit 4

Week 5 : Unit 5 a. Positive edge triggered D Flip Flop where X is input, Y is clock, Q is output

b. Negative edge triggered D Flip Flop where X is input, Y is clock, Q is output

Week 6 : Unit 6
c. Positive edge triggered D Flip Flop where Y is input, X is clock, Q is output
Lecture 26
:Decoders, d. Negative edge triggered D Flip Flop where Y is input, X is clock, Q is output
Multiplexers,
PLA (Contd.) No, the answer is incorrect.
Score: 0
Lecture 27 :
Decoders, Accepted Answers:
Multiplexers, a. Positive edge triggered D Flip Flop where X is input, Y is clock, Q is output
PLA (Contd.)
2) An SR-latch is created using only two NOR gates with S and R inputs feeding one NOR 1 point
Lecture 28 : gate each. If both S and R inputs are set to one, the outputs will be
Sequential
Circuits
a. Q and Q' both 1
Lecture 29 :
Sequential b. No change in circuit output
Circuits
c. Q and Q' both 0
(Contd.)
d. Q and Q' complementary to each other
Lecture 30 :
Sequential No, the answer is incorrect.
Circuits
Score: 0
(Contd.)
Accepted Answers:
Lecture
c. Q and Q' both 0
Materials

Quiz : Week 6 3) Serial inputs are applied in the following manner to the J-K flip flop through AND gates as 1 point
© 2014
shown in theNPTEL - Privacy
figure. & Terms
What would - Honor
be the Codeserial
resulting - FAQs - that would be present at the output Q?
data
Assignment 6
A project of In association with
There is one clock pulse for each bit time. Assume that Q is initially 0. Preset and Clear signals are
Feedback for
always high. The input bits are applied from left to right.
Week 6

Week 7 : Unit 7 Funded by

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Digital Circuits - - Unit 7 - Week 6 : Unit 6 https://onlinecourses.nptel.ac.in/noc18_ee33/un...

Week 8 : Unit 8

Week 9 : Unit 9

Week 10 : Unit
10

Week 11 : Unit 11

Week 12 a. Q : 0 0 1 1 0 0 0

Download b. Q : 1 0 1 1 0 0 0
Videos
c. Q : 0 0 1 1 1 1 1

Assignment d. Q : 0 0 0 1 0 0 0
Solution
No, the answer is incorrect.
Interactive Score: 0
Session with Accepted Answers:
Students
a. Q : 0 0 1 1 0 0 0

4) A positive edge triggered D flip flop is connected as shown in the figure below. What would 1 point
be the Q output in relation to the clock? Assume Q is initially 0.

a. Timing Diagram A

b. Timing Diagram B

c. Timing Diagram C

d. Timing Diagram D

No, the answer is incorrect.

Score: 0
Accepted Answers:
d. Timing Diagram D

5) Consider the 1:4 demultiplexercircuit shown below. What would be the output bits for input 1 point
condition S0 = 1, S1 = 1 and Din = 1?

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a. Y0 = 0, Y1 = 1, Y2= 1, Y3 = 1

b. Y0 = 0, Y1 = 0, Y2= 0, Y3 = 1

c. Y0 = 0, Y1 = 0, Y2= 1, Y3 = 0

d. Y0 = 0, Y1 = 0, Y2= 1, Y3 = 1

No, the answer is incorrect.

Score: 0
Accepted Answers:
b. Y0 = 0, Y1 = 0, Y2= 0, Y3 = 1

6) Identify the PLA circuit shown in the figure. 1 point

a. Binary Full Adder where X is sum output, and Y is carry output.

b. Binary Full Adder where Y is sum output, and X is carry output.

c. Binary Full Subtractor where X is differenceoutput, and Y is borrow output.

d. Binary Full Subtractor where Y is differenceoutput, and X is borrow output.

No, the answer is incorrect.

Score: 0
Accepted Answers:
a. Binary Full Adder where X is sum output, and Y is carry output.

7) Consider the circuit shown below. Which of the following statements is true? 1 point

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a. The circuit would hold the previous state for S = 0, R = 0.

b. The circuit would hold the previous state for S = 0, R = 1.

c. The circuit would hold the previous state for S = 1, R = 1.

d. The circuit would never be able to hold the previous state under any condition.

No, the answer is incorrect.

Score: 0
Accepted Answers:
d. The circuit would never be able to hold the previous state under any condition.

8) You are having a D flip-flop, which you want to use as a J-K flip-flop. The input of the D 1 point
flip-flop in terms of external inputs J and K can be written as (Consider Qn is the output of the D
flip-flop)

a. D = JQn + KQn

b. D = J’Qn + K’Qn

c. D = JQ’n + K’Qn

d. D = JQ’n + KQ’n

No, the answer is incorrect.

Score: 0
Accepted Answers:
c. D = JQ’n + K’Qn

9) You are having a D flip-flop, which you want to use as a S-R flip-flop. The input of the D 1 point
flip-flop in terms of external inputs S and R can be written as (Consider Qn is the output of the D
flip-flop)

a. D = S + RQn

b. D = S + R’Qn

c. D = S’ + RQn

d. D = S’ + R’Qn

No, the answer is incorrect.

Score: 0
Accepted Answers:
b. D = S + R’Qn

10) 0 points

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Digital Circuits - - Unit 7 - Week 6 : Unit 6 https://onlinecourses.nptel.ac.in/noc18_ee33/un...

a. Fixed at 0 and 1 respectively

b. X = 10101010…., Y = 01010101….

c. Fixed at 1 and 0 respectively

d. X = 10101010…., Y = 10101010….

No, the answer is incorrect.

Score: 0
Accepted Answers:
a. Fixed at 0 and 1 respectively

11)Identify the circuit shown below 1 point

a. Bidirectional Buffer

b. De-multiplexer

c. Multiplexer

d. Encoder

No, the answer is incorrect.

Score: 0
Accepted Answers:
c. Multiplexer

12)Which of the following statements is NOT correct? 1 point

a. Race around condition occurs in a JK latch when both the inputs are one.

b. A flip flop is used to store one bit information.

c. A transparent latch is D-type flip-flop with enable (level triggered) in place of a clock.

d. Master-slave configuration is used in flip-flop to store two bits information.

No, the answer is incorrect.

Score: 0
Accepted Answers:
d. Master-slave configuration is used in flip-flop to store two bits information.

13)How many 2 × 1 MUX is required to implement a 30 × 1 MUX 1 point

a. 15

b. 28

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c. 29

d. 30

No, the answer is incorrect.

Score: 0
Accepted Answers:
c. 29

14)The logic function depicting the behavior of the complementary output of T flip-flop is given 1 point
by

a. Q’ = T XOR Q

b. Q’ = T XNOR Q

c. Q’ = T OR Q

d. Q’ = T NOR Q

No, the answer is incorrect.

Score: 0
Accepted Answers:
b. Q’ = T XNOR Q

15)The logic function depicting the behaviour of the complementary output of JK flip-flop is 1 point
given by

a. Q’ = J’Q’ + KQ

b. Q’ = JQ’ + K’ Q

c. Q’ = J’K’

d. Q’ = J’K’ + Q

No, the answer is incorrect.

Score: 0
Accepted Answers:
a. Q’ = J’Q’ + KQ

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