Chaitanya Gadigatla

gadigatla@gmail.com | 602.327.1577 | https://www.linkedin.com/in/chaitanyagadigatla

SUMM ARY
Expert in co-optimizing process technology and standard cell library/methodologies for better PPA (Power Performance
Area) of logic blocks. Known as the “go-to” guy for physical design (architecture, layout quality, extraction) and verification
(DRC, LVS, EM, IR drop, DFM) details of Intel 10nm standard cell libraries. Filed 2 patents. Developed flows by working
with CAD teams to improve physical design quality and cut turnaround time of libraries and blocks by 2x. Experienced in
taking blocks from Synthesis to APR to evaluate PPA tradeoffs for different library/methodology choices. Knowledgeable
about Verilog and RTL design. Skilled in defining clear problem statements and then taking a structured approach in solving
them. Mentored 3 Engineers on various aspects of library design and enabled them to support libraries on their own.
CORE COMPETENCIES
Standard Cell Library Architecture Definition and Optimization ECO libraries design Parasitic Extraction
Design Technology Co-optimization for better PPA Physical Verification Cadence Virtuoso IC design suite
Device, Cell, Block-level PPA Analysis Timing Analysis Synopsys DC, ICC, Prime Time
Circuit and Layout Design and Optimization Synthesis to APR Perl, Tcl and Shell scripting
WORK EXPERIENCE
Physical Design Engineer, Intel Corporation, Hillsboro, OR, USA May 2010 – Present
o Architected Intel 10nm mid-height library and drove design-technology co-optimization effort to improve total power
by 8-10%, performance by 1-7% and area by 5-8% w.r.t PPA provided by Intel 10nm tall-height library for various
blocks operating in 1.5-2.5 GHz range. Owned library development from content definition to layout design.
Developed methodologies to automate layout variant generation that cut down library development time by 2x.
Designed flows to check cell abutment cleanliness and layout quality, which eventually got adopted for all libraries
at Intel. Successfully validated library architecture and physical design in Silicon with a ScanRU block on a TestChip.
o Reduced power consumption of every IP block used by an Intel 10nm lead product by >5%. Achieved this by
identifying top contributor cells to power and then reducing Cdyn with techniques like miller cap reduction, clock
network clustering, device re-ordering and transistor sizing etc.
o Evaluated impact of multiple DR/DFM rule changes on Intel 10nm libraries and co-optimized rule definitions to
reduce negative impact on PPA as much as possible. Automated layout fixes for new DRs/DFMs wherever possible
to reduce turnaround time of the library. Trained physical design team of 20+ layout designers to do detailed layout
fixes without losing much performance and area.
o Developed guidelines to fix DFM and Density violations in Intel 10nm standard cell libraries which resulted in 25 -
35% DFM error reduction, 15-20x density violation reduction across various blocks.
o Optimized circuit content (new topologies and drive strengths) and sizing for better cell-level and block-level PPA.
o Co-pioneered a methodology to generate high performance and similar looking layouts across different drive
strengths of a family with an Intel internal layout generation tool.
o Led development of mock standard cell libraries (based on previous technology libraries) during early technology
definition phase to get early PPA results. Developed Tcl scripts to automate mock library generation. Worked closely
with PPA team to identify key bottlenecks and optimized DRs/Cell architecture/Metal stacks accordingly.
o Designed ECO libraries for Physical Debug from spec to characterization on Intel 14nm and 10nm technologies.
These libraries enabled faster bug fixes through metal only ECOs in both pre and post silicon phases for multiple
Intel products and helped them to go through PRQ in 1 stepping.
o Filed patents for 1) Pin Connects for Improved Performance Power Shared Architecture and 2) Standard Cell
Architecture with Power Metals Completely Inside the Cell.
o Received 14 divisional awards for outstanding contributions to standard cell library and block-level designs.
o Co-authored “Design-Technology Co-Optimization of Standard Cell Libraries on Intel 10nm Process” paper for
2018 IEEE International Electron Devices Meeting (IEDM), pp. 28.2.1-28.2.4
EDUC ATION
Master of Science in Electrical Engineering Dec 2009
Arizona State University, Tempe, AZ