MUX 4-1 USING MUX 2-1 VERILOG CODE AND ITS TESTBENCH:

Mux 2-1:
module mux2x1(out,a,b,s);

input a,b,s;

wire and_1,and_2,s_c;

output out;

not (s_c,s);

and (and_1,a,s_c);

and (and_2,b,s);

or (out,and_1,and_2);

endmodule

mux 4-1:
module mux4x2(out,i0,i1,i2,i3,s1,s0);

input i0,i1,i2,i3,s1,s0;

output out;

wire mux1,mux2;

mux2x1 mux_1(mux1,i0,i1,s1);

mux2x1 mux_2(mux2,i2,i3,s1);

mux2x1 mux_3(out,mux1,mux2,s0);

endmodule

Testbench:
module mux4x2_tb;

wire t_out;

reg t_a, t_b, t_c, t_d, t_s1, t_s0;

mux4x2 my_4x2_mux( .i0(t_a), .i1(t_b), .i2(t_c), .i3(t_d), .s1(t_s1), .s0(t_s0), .out(t_out) );

initial

begin
// 1

t_a = 1'b1;

t_b = 1'b0;

t_c = 1'b1;

t_d = 1'b1;

t_s0 = 1'b0;

t_s1 = 1'b1;

#5 //2

t_a = 1'b0;

t_b = 1'b1;

t_c = 1'b0;

t_d = 1'b0;

t_s0 = 1'b0;

t_s1 = 1'b1;

#5 //3

t_a = 1'b0;

t_b = 1'b0;

t_c = 1'b1;

t_d = 1'b0;

t_s0 = 1'b1;

t_s1 = 1'b0;

#5 //4

t_a = 1'b0;

t_b = 1'b0;

t_c = 1'b0;

t_d = 1'b1;

t_s0 = 1'b1;

t_s1 = 1'b1;

#5 //5

t_a = 1'b1;

t_b = 1'b0;
t_c = 1'b0;

t_d = 1'b0;

t_s0 = 1'b0;

t_s1 = 1'b0;

end

endmodule

MUX 8-1 USING MUX 4-1 VERILOG CODE AND ITS TESTBENCH

MUX 4-1:
module mux(in1,in2,in3,in4,select,op);
input in1,in2,in3,in4;
input [1:0] select;
output reg op;
always@(in1 or in2 or in3 or in4 or select) begin
case (select)
2'b00 : op <= in1;
2'b01 : op <= in2;
2'b10 : op <= in3;
2'b11 : op <= in4;
endcase
end
endmodule

MUX 8-1:
module mux_8x1(

input a,b,c,d,e,f,g,h,

input [2:0] sel,

output out

);
wire w1,w2,w3,w4,w5;

mux mx1(a,b,c,d,sel[1:0],w1);

mux mx2(e,f,g,h,sel[1:0],w2);

not n1(w3,sel[2]);

and a1(w4,w1,w3);

and a2(w5,w2,sel[2]);

or o1(out,w4,w5);

endmodule

TESTBENCH:

module tb_8to1_mux;

// Inputs

reg a,b,c,d,e,f,g,h;

reg [2:0] sel;

integer i;

// Outputs

wire out;

// Instantiate the Unit Under Test (UUT)

mux_8x1 uut (

.a(a),

.b(b),

.c(c),

.d(d),

.e(e),

.f(f),

.g(g),

.h(h),
 .sel(sel),

.out(out)

);

initial begin

// Initialize Inputs

$dumpfile("muxx.vcd");

$dumpvars(0,tb_8to1_mux);

$monitor ("[%0t] sel=0x%0h a=0x%0h b=0x%0h c=0x%0h d=0x%0h e=0x%0h f=0x%0h g=0x%0h
h=0x%0h out=0x%0h", $time, sel, a, b, c, d, e, f, g, h, out);

sel <= 0;

a <= $random;

b <= $random;

c <= $random;

d <= $random;

e <= $random;

f <= $random;

g <= $random;

h <= $random;

for (i = 0; i < 7; i=i+1)

begin

#5 sel <= i;

end

#5 $finish;

end

endmodule