Avionics Lab Manual

AVIONICS LABORATORY
[AAE-4111]
AVIONICS LABORATORY MANUAL

VII SEMESTER, B.E./B.Tech. (AERONAUTICAL)
(Academic Year 2017-2018)
Student Name :
Class : Aeronautical Engineering , VII Semester

Roll No. :
Registration No. :
Batch :
Department of Aeronautical and Automobile Engineering

MANIPAL INSTITUTE OF TECHNOLOGY, MANIPAL
(A Constituent College of Manipal University)
MANIPAL – 576104
August 2017
MIT/AAE/AVL/LM/R1-2017
AVIONICS LABORATORY
[AVL]
[AAE-4111]
AVIONICS LABORATORY MANUAL

VII SEMESTER, B.E./B.Tech. (AERONAUTICAL)
(Academic Year 2017-2018)
Prepared By
KAMLESH KUMAR & VISHNU G NAIR
Student Name :
Class : Aeronautical Engineering , VII Semester

Roll No. :
Registration No. :
Batch :
Department of Aeronautical and Automobile Engineering

MANIPAL INSTITUTE OF TECHNOLOGY, MANIPAL
(A Constituent College of Manipal University)
MANIPAL – 576104
August 2017
MANIPAL INSTITUTE OF
TECHNOLOGY MANIPAL – 576 104
(A Constituent Institution of Manipal University)
Department of Aeronautical & Automobile

Engineering
CERTIFICATE
This is to certify that Mr./ Ms.………………………………………..Bearing

Registration No. -------------------------- has satisfactorily completed the
Laboratory work in Avionics Lab[AAE-4111] as prescribed by the
Manipal University for the partial fulfillment of VII Sem. B.E./B.Tech.,
program in Aeronautical Engineering, during the academic term from
………………….to ………………..., which has been evaluated and duly
certified.
Place : ……………….
Date : ………………..
Name & signature of the Signature of Head of the

Faculty In charge Department
Dept. of Aeronautical & Automobile Engineering , MIT Manipal
GENERAL INSTRUCTIONS FOR LABORATORY CLASSES
➢ Enter Lab with CLOSED FOOTWEAR

➢ Boys should “TUCK IN” the shirts
➢ Students should wear uniform only
➢ LONG HAIR should be protected, let it not be loose especially near ROTATING
MACHINERY.
➢ Any other machines/ equipments should not be operated other than the
prescribed one for that day.
➢ POWER SUPPLY to your test table should be obtained only through the LAB
TECHNICIAN
➢ Do not LEAN and do not be CLOSE to the rotating components
➢ TOOLS, APPARATUS & GUAGE Sets are to be returned before leaving the
Lab
➢ HEADINGS & DETAILS should be neatly written
o Neat Diagram/ Flow charts
o Specifications/ Designs details
o Tabulation
o Graph
o Result/ Discussions
o Validate the results from the Faculty in-charge.
➢ Experiment date should be written in the appropriate place
➢ After completing the experiments, the answer to the VIVA-VOCE Questions
should be neatly written in the workbook and should be produced in the next
week. Be PATIENT, STEADY, SYSTEMATIC, & REGULAR.
UNIVERSITY PRACTICAL EXAMINATION
Allotment of Marks
1. Internal Assessment = 60 marks

2. Practical Examination = 40 marks
INTERNAL ASSESSMENT [60 Marks]
Staff should maintain the assessment Register and the Head of the Department should
monitor it.
SPLIT UP OF INTERNAL MARKS
a) Record Note = 40 marks
Avionics Laboratory Page 4
i. Tabulation
ii. Calculations
iii. Graph
iv. Results and Conclusion
b) Viva questions =15 marks
c) Overall conduct = 5 marks
UNIVERSITY EXAMINATION [40 Marks]
The mode of examination shall contain performing one major and one minor
experiment
Split up of Practical Examination Marks
a) Aim and Procedure = 10 marks

b) Tabulation = 6 marks
c) Formulae and Calculation = 12 marks
d) Graph and Result = 4 marks
e) Viva Voce = 8 marks
AVIONICS LABORTORY OBJECTIVES
1. To apply digital electronics theory, design digital circuit on IC trainer and learn
its theory and concepts.
2. To apply microprocessor theory and demonstrate an assembly programming on
microprocessor trainer kit.
3. Demonstrate an understanding of flight simulator.
4. To apply the aircraft dynamics to modeling, simulation, analysis and
demonstrate the simulator using MATLAB/SIMULINK.
5. To demonstrate and simulate the antenna design theory and understand its
application in an aircraft.
6. Understand the ARINC-429 & MIL-STD 1553B data buses protocol through
software.
7. Demonstrate an understanding of communication challenges between avionics
subsystem.
8. To design, apply and demonstrate the various avionics subsystems integration
knowledge in aerospace vehicle.
9. Apply the knowledge of Satellite training, radar training, antenna design training,
aerospace embedded systems development in real world application.
10. To learn and improve laboratory report documents and technical writing which
include:
i. Experimental objectives and procedures.
ii. Presentation of results in an organized and clear manner.
iii. Draw graphs and figures to summarize key findings.
INDEX
AAE-411: AVIONICS LABORATORY [0 0 6 2],
LIST OF EXPERIMENTS
Experime Name of the Experiment Page Marks Remarks
nt No. No.
Digital Circuit Verification and IC trainer Hands on
Module 1: Experience
Exp. 1 Logic Gates: 08
o Key parameters
o Implementation of Boolean functions
Exp. 2 Arithmetic circuits : Adders & Subtractors 11
Exp. 3 Magnitude comparator 16
Exp. 4 Multiplexers & De-multiplexers 20
Exp. 5 Encoders & Decoders 24
Exp. 6 Study of Flip flops 27
Microprocessor Programming and Microprocessor
Module 2: trainer Hands
Exp. 7 Microprocessor Trainer Kit (MPS85-3) 33
Exp. 8 Dual DAC Interface 41
MATLAB & SIMULINK based Programming &
Module 3: Software-in- Loop Simulation[UAV]
Six-DOF Mathematical Modeling and Simulation of an
Exp. 9 Aircraft and Avionics integration 46
Module 4: Flight Simulator-Prepar3D/X-Plane 51
Exp. 10A Cessna 172 Analog
Exp. 10B Cessna 172 Glass
Module 5: Antenna Design & Simulation 56
Study of antenna theory, simulation using PCAAD, CEM
ONE SOLUTION & MATLAB [PCAAD-Personal
Exp. 11A Computer Aided Antenna Design]
Various Antenna Analysis using PCAAD, CEM ONE
SOLUTION & MATLAB [PCAAD-Personal Computer
Exp. 11B Aided Antenna Design]
Data Bus Protocol-MIL STD 1553 & ARINC-429
Software Demo, Documentation, radar and satellite
Module 6: trainer
Demo of MIL-STD 1553 & ARINC-429, Software
Exp. 12 analysis and project documentation 60
Module 7: Mini-Project
Any Next Gen Avionics Research Issues. Regularity,
Preparation, Documentation, class performance.
Date ……………
Experiment No. 01 LOGIC GATES
Aim:
• To get familiarization with IC trainer kit.

• To verify the characteristics of logic gates.
• To realize basic logic functions using universal gates.
• To construct and test simple combinational circuits.
Equipments and components required:
o ICs – 7400, 7402, 7408, 7432, 7486.

o IC trainer kit and patch chords.
o Multimeter ,CRO, and CRO probes.
Digital Logic IC’s:
7408: Quad 2-input AND

gates 7432: Quad 2-input OR
gates 7404: Hex inverters
7400: Quad 2-input NAND
gates 7402: Quad 2-input NOR
gates 7486: Quad 2-input XOR
gates
Note:
1. Refer to Appendix II/ data manuals for pin diagram and pin descriptions of the above
IC’s.
2. Refer to Appendix I for theory related to the experiment
Procedure:
1. Ensure that power supply to IC trainer kit is switched off.
2. Insert the required logic IC into the appropriate ZIF socket.
3. Using connecting wires/ patch cords make connections to Vcc, Gnd, inputs
and outputs.
4. Switch on the power to IC trainer kit.
5. Apply proper inputs to logic gate and observe the outputs.
6. Switch off the power to IC trainer kit and then remove the connecting wires
and ICs.
A. Universality of NAND ad NOR gates:
• Basic logic functions using NAND gates:
• Basic logic functions using NOR gates:
• Compare the truth tables of above logic circuits with that of basic
gates.
B. Construction of Combinational Circuits:
Design a logic circuit with 4 inputs A,B,C,D that will produce output ‘1’ only whenever two
adjacent input variables are 1’s. A and D should also be treated as adjacent. Implement it using
universal logic.
Truth Table
INPUT OUTPUT
A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Logic Expression F= (A+C)(B+D)
Note: Get the expression in SOP form for the above function, implement the circuit and see
the result.
Exercises:
1. Design a combinational circuit to produce 2’s compliment of a 4bit binary number.
2. Design a circuit that can be built using AOI logic and outputs a 1 when a 4 bit
hexadecimal input is an odd number from 0 to 9.
Experiment No. 02 ARITHMETIC CIRCUITS
Aim:
• To design, implement and test Half adder and half subtractor, Full adder and
Full subtractor.
• To study 4-bit parallel adder - IC 7483.
Equipment’s & Components Required:
o ICs 7408, 7432, 7404, 7400, 7486, 7410, 7483

o IC trainer kit, Connecting wires
A. Half adder: A half adder circuit adds two bits to give the sum and carry outputs.
Truth table
Inputs Outputs
A B C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
S = A.B + A.B
C = A.B
B. Half Subtractor:
Truth table
Inputs Outputs
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
D= A’B +AB’
B= A’B
C. Full adder: Full adder adds two bits and also another bit called carry-in that is propagated
from the previous stage. In effect, a full adder adds three bits to give out two outputs –
sum and carry out. A,B and Cin are the three inputs, out of which Cin is to be considered
as carry propagated from the previous stage. S and Cout are the three outputs.
Truth table
D.
Inputs Outputs
A B bi D b
D=bi (AB+A’B’) + bi’(AB’ + A’B)
0 0 0 0 0
0 0 1 1 1
= bi (AʘB) + bi’ (A  B)
0 1 0 1 1
0 1 1 0 1
b= A’B + (A ʘ B)bi
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
E. 4 –bit Binary full adder (IC 7483): The 7483 adds two 4-bit binary words plus the
incoming carry .This contains 4 inter connected full adder and a look ahead carry adder
circuit. Sum outputs are S3 to S0, the out-going carry is Cout
A3 A2 A1 A0 B3 B2 B1 B0
VCC 7483 CIN
GND
COUT S3 S2 S1 S0
o Connect Vcc and Ground to the respective pins.

o Connect A3-A0 and B3–B0 to logic input switches.
o Connect Cout, S3-S0 to logic output LEDs.
o Give the inputs and note down the outputs.
F. 4 Bit adder / 2’s complement subtractor:

b3 b2 b1 b0
a3 a2 a1 a0
A3 A2 A1 A0 B3 B2 B1 B0
VCC CIN
Add/Sub
Control.
GND 7483
0 = Add
1 = Sub
When control input is 0, input B = b3 b2 b1 b0 is added to input A = a3 a2 a1 a0.

When control input is 1, 2’s complement of B is added to input A. (i.e., A –
B)
Difference is available at S3 S2 S1 S0, borrow output at Cout..
G. BCD adder: When two 4 bit BCD numbers are added, if the sum exceeds 9 or if there is
a carry ,then 6 is added to the sum and a carry is generated to the next decimal digit.
Carry from the addition of 6 (if any) is neglected.
Exercises:
1. Implement half adder circuit using only NOR gates.

2. Implement half subtractor using only NAND gates.
3. Implement full adder using two half adder circuits and one OR gate.
4. Implement full subtractor using two half subtractors and any additional gate.
5. Implement BCD subtractor using 7483 IC with result in 10’s complement notation.
6. Design an 4bit XS-3 ADDER using 7483 IC.
Experiment No. 03 MAGNITUDE COMPARATOR
Aim:
• To design, implement and study magnitude comparators.
• To study the working of 4 bit magnitude comparator IC 7485.
Equipments & Components Required:

o IC 7404, IC 7408, IC 7486, IC 7485
o IC trainer kit & Connecting wires
A. One bit magnitude comparator: A and B are two single bit inputs for the comparator
and has three output lines, i.e. (A>B), (A<B), and (A=B).
o When input A is greater than input B, output (A>B) will be high

o When input A is less than input B, output (A<B) will be high
o When input A is equal to input B, output (A=B) will be high
Note that only one out of three outputs will be high at any time.
Truth Table:
INPUTS OUTPUTS
A B A> B A< B A=B
0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1
B. Two bit magnitude comparator: Compares two 2-bit inputs, where A1 and A0 are the
two bits of the first number. B1 and B0 are the two bits of the second number.
Truth Table:
INPUTS 0UTPUTS
A1 A0 B1 B0 A>B A<B A=B
0 0 0 0 0 0 1
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 0 0
0 1 0 1 0 0 1
0 1 1 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 0 1 1 0 1 0
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 0 1
Parity generator / checker
Aim:
• To design, implement and study 3-bit odd parity generator /checker
• To study the working of parity generator /checker IC 74180.
Equipments & Components Required:

o IC 7486, IC 74180
o IC trainer kit & Connecting wires
C. 3-bit odd parity generator/checker: An odd parity generator generates a 1 for an

even number of 1’s in the message, else 0.
Step 1: Consider a 3-bit message XYZ to be transmitted with an odd parity bit.
Step 2: Obtain an expression for P in terms of the message bits and realize using gates.
P
X Y Z Generated
parity
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Step3: The odd parity checker consists of a 4-bit data consisting of X,Y, Z, P
C
X Y Z P (Output) Note: Even number of 1's received indicates
0 0 0 0 1 error which is detected as 1 at the output of the
0 0 0 1 0 checker.
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
EXERCISES:
1. Design and implement 8-bit comparator using ICs 7485.
2. Design a 5-bit comparator using single IC 7485 and one gate.
3. Design and implement a 4 bit even parity generator/checker.
4. Design a 9 bit odd parity checker using a 74180 and an inverter.
Experiment No. 04 MULTIPLEXERS AND DEMULTIPLEXERS
MULTIPLEXERS – A multiplexer or data selector is a logic circuit that accepts several data
inputs and allows only one of them at a time to get through the output. The routing of the desired
data input to the output is controlled by SELECT inputs. The multiplexer acts like a digitally
controlled multi position switch. The digital code applied to the SELECT inputs determines
which data input to be switched to the output.
DEMULTIPLEXER – A demultiplexer or data distributaor is a circuit that receives information

on a single line and transmits this information on one of the 2n possible output lines. The
selection of a specific output line is controlled by n selection lines. A decoder can function as
demultiplexer if enable line is taken as data input.
Aim:
• To design and implement various multiplexer circuits and to generate logic functions
using multiplexers.
• To design and implement Demultiplexers.
Components and Equipments Required:

o ICs 74151, 74153
o Basic gates, universal gates
o IC trainer kit, connecting wires
A. 4:1 Multiplexer using only NAND gates
Logic Symbol
S1 S0
D0
D1
Y
D2
4:1 MUX
D
3
Truth Table
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
74153 – Dual 4:1 Mux 74151 – 8:1 Mux 74157 – Quad 2:1 Mux
Note:
• Pin no.16 = Vcc, pin no.8 = GND for all the three ICs.
• For pin-details of the ICs, refer data manual.
• Test all the three ICs by giving appropriate inputs and observing the corresponding
outputs. Thus verify the functional tables of these ICs.
B. Implement f = ∑m (0, 3, 5, 7, 8, 10, 14) using i) 8:1 MUX ii) 4:1 MUX and additional gates
C. Design a 1 to 4 Demultiplexer using basic gates
Select lines Data Outputs

S1 S0 D Y0 Y1 Y2 Y3
0 0 0/1 D 0 0 0
0 1 0/1 0 D 0 0
1 0 0/1 0 0 D 0
1 1 0/1 0 0 0 D
Exercises:
1. Implement f (a, b, c) = AB + BC +ABC using (i) 8:1 MUX (ii) 4:1 MUX
2. Implement full adder using 4:1 MUX and 8:1 MUX
3. Implement 8:1 MUX using 2:1 multiplexers
4. Design 3 bit binary to gray code converter using 4:1 MUX
5. Implement F = ∑ m ( 0,5,7,11,15,16,18,25,29 ) using two 8:1 and one 2:1 MUX
6. Construct 16:1 DEMUX using 74138 IC and additional gates if required.
7. Verify 16:1 DEMUX truth table using 74154 IC.
Date …………………
Experiment No. 05 ENCODERS AND DECODERS
ENCODER – An encoder has 2n(or less)input lines and n output lines. The output lines
generate the binary code for 2n inputs.
DECODER – It is a logic circuit that converts an N-bit binary input code into M output lines such
that only one line is activated for each one of those possible combinations of inputs.
Aim:
• To design and implement Decoders and Encoders.

o ICs 74139, 74138, 74154, 74148
o Basic gates, universal gates
A. Design and implement 2 to 4 decoder using basic gates:
INPUTS OUTPUTS
A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
B. Design and implement 2 to 4 decoder with enable input using only NAND gates
Inputs Outputs
E A B D0 D1 D2 D3
0 X X 1 1 1 1
1 0 0 0 1 1 1
1 0 1 1 0 1 1
1 1 0 1 1 0 1
1 1 1 1 1 1 0
C. Design and implement Octal to Binary encoder using basic gates
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
A = D4 + D5 + D6 + D7
B = D2 + D3 + D6 + D7
C = D1 + D3 + D5 + D7
Exercises:
1. Study and verify the truth table of 74148 ,a 8 to 3 Priority Encoder

2. Implement a decimal to BCD encoder.
3. Design and implement 4 to 16 decoder using two 74138 decoders.
4. Implement F =AB + ABC using 74138 and additional gate.
5. Implement one bit full adder using 74138 and additional gate
6. Implement f(A,B,C,D) = ∑( 0,3,5,9) using two 74138 ICs and additional gate
7. Implement the following multi output Combinational circuit using a 4 to 16 decoder:
F1(A, B, C, D) = ∑(2, 4, 8, 13)
F2(A, B, C, D) = ∑(5, 9, 11, 14)
Experiment No. 06 STUDY OF FLIPFLOPS
Aim:
• To study the operations of SR Flip-flop, D Flip-flop, JK Flip-flop, T Flip-flop.
• To study the IC –7474 & IC – 7473.
o ICs 7400, 7473, 7474
o Cathode Ray Oscilloscope
Note : Refer the IC data manual, draw the block & pin diagram of ICs 7473 & 7474.
A. SR Flip-flop using NAND gates:
Note : Apply high-going mono pulse to CLK
B. D Flip-flop using NAND gates:
C. JK Flip-Flop using NAND gates:
Symbol
D. T-Flip Flop using NAND gates:
E. Study of IC 7474: Positive edge triggered dual D flip-flops with preset and clear.
NOTE: Draw the pin diagram of 7474 IC from the manual
F. Study of 74LS73A: Negative edge triggered dual JK Flip-flops with clear
NOTE: Draw the pin diagram of IC 7473 from the manual
G. Conversion of flip flops:
(a) Convert SR flip flop to D flip flop
Note: Build SR flipflop using Nand gates
(b) Convert D to SR Flip flop
S R Q Q+ D
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 X X
1 1 1 X X
Using K map we get the expression for D
D=R’Q + S
Exercise:
1. Convert T flip flop to JK flip flop

2. Convert D flip flop to T flip flop
3. Convert JK flip flop to SR flip flop.
4. Construct SR flip flop using NOR gates.
Experiment No.7– MICROPROCESSOR TRAINER KIT
(MPS85-3)
Aim:
To get familiarization with ESA microprocessor 8085(MPS85-3) trainer kit.

To learn and verify the microprocessor 8085 programming.
To realize operational mode of trainer interface through serial mode and keyboard
(Hexadecimal).
To learn and verify the various Interface modules for training.
Equipment's and components required:
ESA MPS85-3 trainer kit
For Serial Mode-Host PC with RS-232C interface, PC Host with installed Win853 driver
Software (Depends Version of Firmware Available).
Power Adapter-Regulated DC Power Supply (+30 Volts (100 mA), +12 Volt (250 mA), -
12 Volts (250 mA), +5 Volts (3.0 Amp))
Connectors RS-232(On Board Connector J6 9 pin D-type female connector) and 9 pin
D-type female connecter with horn pin to power adapter.
Note:
1. For the trainers the configuration DIP Switch must be set correctly to reflect the
operational mode.(Refers the user manual of trainer)
Procedure:
1. Ensure that power supply to MPS85-3 trainer kit is switched off.

2. Insert the required 9 pin D-type female connecter into the appropriate 9 pin D-type male
connector to power the trainer with +5 Volts (3.0 A) from power adapter.
3. Connect the MPS 85-3 to the Host PC through RS-232C cable over the connector J6.
3. Switch on the power to MPS85-3 trainer kit.
4. Select the Operational Mode either Hexadecimal Keyboard mode or Serial Mode.
Display on board will be –UPS 85 or SERIAL.
5. Execute the programming based on operation mode selected.
6. Switch off the power to MPS85-3 trainer kit and then remove the connectors and
modules.
Operation Mode Selection:-
Switch 4 of the DIP switch Operational Mode

OFF Hexadecimal Keyboard Mode(Default)
ON SERIAL MODE
Baud Rate Selection:-
S3 S2 S1 Baud Rate
ON ON ON 110
ON ON OFF 300
ON OFF ON 600
ON OFF OFF 1200
OFF ON ON 2400
OFF ON OFF 4800
OFF OFF ON 9600
(Default)
OFF OFF OFF 19,200
Introduction
In many microprocessor based systems, analog input signals have to be converted into digital
values. Here, ADC 0816 device utilizes to show effect of analog-to-digital conversion. This
interface allows user to become familiar with the techniques of using ADC’s.
Description of the Circuit
This interface has a 16-channel, 8- bit; A-D converter ADC 0816 can be fed from the connector
J2.
Diagram:
Schematic Diagram:
Demonstration of Program:-
1)
; PROGRAM FOR SUBTRACTION OF TWO 8 BIT NUMBERS.

; PLACE THE 2 NUMBERS WHICH YOU WANT TO SUBTRACT IN 9000H & 9001H
LOCATIONS.
; RESULT(DATA OF 9000H LOCATION - DATA OF 9001H LOCATION) WILL BE DISPLAYED
AT 9002H LOCATION.
; BORROW WILL BE DISPLAYED AT 9003H LOCATION.
ORG 8000H
LXI H,9000H
MOV A,M ; GET THE 1ST NUMBER
INX H
SUB M ; SUBTRACT THE 2ND NUMBER
PUSH PSW
INX H
MOV M,A ; STORE THE RESULT
INX H
POP PSW
JC SET
MVI C,00H
L1: MOV M,C ; STORE THE BORROW

RST 3
SET: MVI C,01H

JMP L1
2)
; PROGRAM FOR MULTIPLICATION OF TWO 8BIT NUMBERS USING BIT ROTATION

METHOD.
; PLACE THE 2 NUMBERS IN 9000H(MULTIPLICAND) & 9001H(MULTIPLIER) LOCATIONS.
; RESULT WILL BE DISPLAYED AT 9002H(HIGHER BYTE) & 9003H(LOWER BYTE)
LOCATIONS.
ORG 8000H
LXI H,9000H
MOV E,M ; GET MULTIPLICAND

MVI D,00H ; EXTEND TO 16 BIT
INX H ; INCREMENT MEMORY POINTER
MOV A,M ; GET MULTIPLIER
LXI H,0000H ; PRODUCT =0
MVI B,08H ; INITIALIZE COUNTER AS COUNT = 8
MUL: DAD H ; PRODUCT = PRODUCT * 2

RAL
JNC SKIP ; IS CARRY FROM MULTIPLIER
DAD D ; YES, PRODUCT = PRODUCT + MULTIPLICAND
SKIP: DCR B ; IS COUNTER = 0

JNZ MUL ; NO REPEAT
XCHG ; YES XCHANGE HL,DE PAIR

LXI H,9002H ; POINT TO MEMORY LOCATION
MOV M,D ; STORE THE HIGHER BYTE OF THE RESULT
INX H ; INCREMENT MEMORY POINTER
MOV M,E ; STORE THE LOWER BYTE OF THE RESULT
RST 3
3)
; PROGRAM FOR DIVISION OF TWO 8BIT NUMBERS USING BIT ROTATION METHOD.
; PLACE THE TWO 8 BIT NUMBERS IN 9000H(dividend) & 9001H(Divisor) LOCATIONS.
; RESULTENT QUOTIENT WILL BE DISPLAYED AT 9002H LOCATION.
; RESULTENT REMAINDER WILL BE DISPLAYED AT 9003H LOCATION.
ORG 8000H
MVI E,00H ; QUOTIENT = 0
LXI H, 9000H
MOV A,M
MVI H,00H
MOV L,A ; GET DEVIDEND
LDA 9001H ; GET DIVISOR
MOV B,A ; STORE DIVISOR
MVI C,08H ; COUNT = 8
NEXT: DAD H ; DIVIDEND = DIVIDEND * 2

MOV A,E
RLC
MOV E,A ; QUOTIENT = * 2
MOV A,H
SUB B ; IS DIVIDEND > DIVISOR
JC SKIP ; NO, GOTO NEXT STEP
MOV H,A ; YES, SUBTRACT DIVISOR
INR E ; AND QUOTIENT = QUOTIENT +1
SKIP: DCR C ; COUNT = COUNT -1

JNZ NEXT ; IS COUNT NOT 0 RPEAT
MOV A,E
STA 9002H
MOV A,H ; STORE QUOTIENT
STA 9003H ; STORE REMAINDER
RST 3
4)
; PROGRAM FOR DIVISION OF TWO 8 BIT NUMBERS USING REPEATED SUBTRACTION

METHOD.
; PLACE THE TWO 8 BIT NUMBERS IN 9000H(dividend) & 9001H(Divisor) LOCATIONS.
; RESULTENT QUOTIENT WILL BE DISPLAYED AT 9002H LOCATION.
; RESULTENT REMAINDER WILL BE DISPLAYED AT 9003H LOCATION.
ORG 8000H
MVI C,00H
LXI H,9000H
MOV A,M ; GET DIVIDEND
INX H
MOV B,M ; GET DEVISOR
AGAIN: SUB B ; SUBTRACT DIVISOR

INR C ; INCREMENT QUOTIENT
CMP B
JC FINISH ; IF CARRY JUMP TO FINISH
JMP AGAIN ; ELSE JUMP TO AGAIN
FINISH: INX H
MOV M,C ; STORE QUOTIENT
INX H
MOV M,A ; STORE REMAINDER
RST 3
5)
; PROGRAM FOR SUBTRACTION OF TWO 16 BIT NUMBERS

; PLACE THE ONE 16 BIT NUMBER IN 9000H(HIGHER BYTE) & 9001H(LOWER BYTE)
LOCATIONS
; PLACE THE ANOTHER 16 BIT NUMBER IN 9002H(HIGHER BYTE) & 9003H(LOWER BYTE)
LOCATIONS
; RESULT WILL BE IN 9004H(HIGHER BYTE) & 9005(LOWER BYTE) LOCATIONS
; BORROW WILL BE DISPLAYED IN 9006H LOCATION
ORG 8000H
LXI H,9001H
MOV A,M ; GET THE LOWER BYTE OF 1ST NUMBER
LXI H,9003H
SUB M ; SUBTRACT LOWER BYTE OF 2ND NUMBER
LXI H,9005H
MOV M,A ; STORE THE RUSULT
LXI H,9000H
MOV A,M ; GET THE HIGHER BYTE OF 1ST NUMBER
LXI H,9002H
SBB M ; SUBTRACT HIGHER BYTE OF 2ND NUMBER WITH BORROW
PUSH PSW
LXI H,9004H
MOV M,A ; STORE THE RUSULT
LXI H,9006H
POP PSW
JC SET ; STORE THE BORROW
MVI C,00H
L1: MOV M,C

RST 3
SET: MVI C,01H

JMP L1
Exercise:-
1. Write the assemble program to get the data into any register and read the result from
accumulator.
2. Write the assemble programming for addition of two 8 bit numbers and flash the program.
3. Write the assemble programming for subtraction of two 8 bit numbers and flash the
program.
4. Write the assemble programming for multiplication of two 8 bit numbers and flash the
program.
5. Write the assemble programming for division of two 8 bit numbers and flash the program.
Experiment No.8 - DUAL DAC INTERFACE
Aim:
To get familiarization with Dual DAC & MPS85-3 trainer kit.

To verify the characteristics of Digital to Analog Converter.
To realize basic functions using Dual DAC & CRO.
To interface and test working principle of DAC & CRO.
DUAL DAC module & 26-pin connector.
ESA MPS85-3 trainer kit
For Serial Mode-Host PC with RS-232C interface, PC Host with installed Win853 driver
Software (Depends Version of Firmware Available).
Power Adapter-Regulated DC Power Supply (+30 Volts (100 mA), +12 Volt (250 mA), -
12 Volts (250 mA), +5 Volts (3.0 Amp))
Connectors RS-232(On Board Connector J6 9 pin D-type female connector) and 9 pin
D-type female connecter with horn pin to power adapter.
Multimeter, +12 Volts & +5 Volt Power Supply, CRO, and CRO probes.
Note:
2. If the trainer is 68K, it can be operated in serial mode only. Thus ignore the description
related to the keyboard mode of operation.
3. For the other trainers the configuration DIP Switch must be set correctly to reflect the
operational mode.(Refers the user manual of trainer)
Procedure:
1. Ensure that power supply to MPS85-3 trainer kit is switched off.

2. Insert the required 9 pin D-type female connecter into the appropriate 9 pin D-type male
connector to power the trainer with +5 Volts (3.0 A) from power adapter.
3. Connect the MPS 85-3 to the Host PC through RS-232C cable over the connector J6.
4. Install the interface module as below:-
The interface module has a 26-pin connector at one edge of the card. This is used for
connecting the interface to the trainer with a flat cable connector set. Here MPS85-3
microprocessor trainer kit interface is connected to J2.
5. External power supplies +12 Volts & -12 Volts and GND respectively on the DAC card
through the 4-pin connector provided on the interface.
6. Select the Operational Mode either Hexadecimal Keyboard mode or Serial Mode.
Display on board will be –UPS 85 or SERIAL.
7. Execute the programming based on operation mode selected and observe it on CRO.
8. Switch off the power to MPS 85-3 trainer kit and then remove the connecting wires and
interface modules.
Operation Mode Selection:-
Switch 4 of the DIP switch Operational Mode

OFF Hexadecimal Keyboard Mode(Default)
ON SERIAL MODE
Baud Rate Selection:-
S3 S2 S1 Baud Rate
ON ON ON 110
ON ON OFF 300
ON OFF ON 600
ON OFF OFF 1200
OFF ON ON 2400
OFF ON OFF 4800
OFF OFF ON 9600
(Default)
OFF OFF OFF 19,200
Introduction
The dual DAC interface can be used to generate different interesting waveform using
microprocessor. There are two eight bit digital to analog converter provided, based on DAC0800.
The digital inputs to these DACs are provided through the port A and port B of 8255 used as
output ports. The analog output from the DACs is given to operational amplifiers which act as
current to voltage converters. Two 10K ohm pots are provided for the offset balancing of opamps.
The reference voltage needed for the DACs is obtained from onboard voltage regulator uA723.
The voltage generated by this regulator is about 8V. The outputs from the DACs vary between 0
to 5 volt corresponding to values between 00 to FF. Different waveforms can be observed at the
opamp outputs depending upon the the digital input patterns.
Description of the Circuit
Schematic circuit of this is given below. Circuit only 17 lines used totally from the connector. The
port A and port B of 8255 programmable peripheral interface are used as output ports. The digital
inputs to the DACs are provided through the port A and B of 8255. The analog outputs of the
DACs are connected to the inverting inputs of opamp uA741 which act as current to voltage
converters. The outputs from the opamps are connected to points marked Xout & Yout at which
the waveforms are observed on a CRO. (Port A is used to control Xout and Port B is used to
control Yout). The reference voltage needed for the DACs is obtained from onboard voltage
regulator uA723. The voltage generated by this regulator is about 8V. The offset balancing of
opamps is done by making use of the two 10K pots provided. The output waveforms are observed
at Xout and Yout on an oscilloscope.
Component Layout Diagram:
Schematic Diagram:
Demonstration of Program:-
Follow the Manual for Program or Demo Program available in Systems.
; Assume the interface is connected over J2 of the trainer.

; The trainer can be in KEYBOARD MODE or SERIAL MODE.
ORG 8000H
MVI A,80H ;Initialise 8255
;for mode 0.
OUT 43H ;Port A & Port
;B as output Ports
XRA A ;Start with a
;value 00H.
LOOP1: OUT 40H ;Out to DAC 1.
OUT 41H ;Out to DAC 2.
INR A ;Increment the
;DAC input.
CPI 0FFH ;Has the Peak value
;been reached.
JNZ LOOP1 ;No, loop back.
LOOP2: OUT 40H ;Out to DAC 1
OUT 41H ;Out to DAC 2
DCR A ;Decrement the
;DAC input.
JNZ LOOP2 ;Minimum value not
;reached, loop back
JMP LOOP1 ;Repeat for ever
END
Exercises:-
1. Write the assembly programming for ramp signals and flash through keyboard mode as
well as serial mode. [Only one output signal should be there] .
2. Write the assembly programming for ramp signals and flash through keyboard mode as
well as serial mode.
3. Write the assembly programming for square wave signals and flash through keyboard
mode as well as serial mode.
4. Write the assembly programming for sinusoidal signals and flash through keyboard mode
as well as serial mode.
5. Generate the different type of signals based on vary of frequency.
Experiment No.9 – SIX-DOF SIMULATION, NAVIGATION, GUIDANCE AND AUTOPILOT

DESIGN OF AIRCRAFT
Aim:
To get familiarization with MATLAB & SIMULINK Programming.

To get familiarization with six DOF of UAV/Aircraft dynamics, mathematical modeling
and simulation.
To get familiarization with Aircraft Nonlinear and linear model.
To get familiarization with Autopilot Design of Aircraft.
To get familiarization on Navigation, Guidance and Control, its application in aerospace.
Integrate all modules and validate the Six DoF simulation using Virtual Flight Gear.
Personal Computer and Associated Hardware
MATLAB & Simulink Software, LabVIEW Software
Wind Tunnel/Flight test/CFD data/Mathematical Model of an Aircraft.
Procedure:
1. Ensure that power supply to personal computer is switched on.

2. Ensure that MATLAB, Simulink & LabVIEW already installed in personal computer.
3. Read the Aircraft data material provided with you and understand every parameter need
in six DoF simulations.
4. Understand Actuator Model, Thrust Model/Lift Model, Force and Moment Generation
Model, Rigid Body Dynamics, Coordinate Transformation, Navigation Model and
Atmospheric Model etc.
5. Nonlinear mathematical modeling and simulation of aircraft and its linearization about
different mode as takeoff, climb, cruise, approach/ descent and landing trimming point.
6. Understand autopilot design of the aircraft. And also understand the need of navigation,
guidance and control in aerospace field.
7. Open the MATLAB application and execute the programming based on Laboratory
Instructor/Faculty instruction.
8. Do the programming step by step as instruction given by instructor, analyze, simulate on
virtual flight gear and make report of it.
9. Close the MATLAB application, shutdown the PC and Switch off the power to the PC.
1. Equations of Motion of a Fixed-Wing Aircraft
The aerodynamic forces and moments are obtained from the dimensionless aerodynamic
coefficients at a given flight condition as follows,
The force equations in wind-axes are introduced as follows,
Aerodynamic coefficients for forces and moments:
Where, e is the Oswald coefficient and AR is the main wing aspect ratio.
A linear parameterization:
The measurements for model identification are provided by the on-board sensor suite. Among
these sensors, accelerometers and rate gyros capture the dynamic behavior of the airplane,
which yields the aerodynamic force coefficients expressed in the body axes as follows:
where the thrust force was assumed to be only exerted along the body x-axis and is modeled as
a function of the rotating speed of the propeller and the forward flight speed as discussed in Sec.
II.C. The aerodynamic moment coefficients are also obtained as follows:
A linear regression model structure was opted for by taking into account the decoupled
longitudinal and lateral dynamics of the aircraft. Hence, decoupled longitudinal and lateral
derivatives are associated with each aerodynamic coefficient as follows:
Support material for simulation:- Dongwon Jung¤ and Panagiotis Tsiotras., “Modeling and
Hardware-in-the-Loop Simulation for a Small Unmanned Aerial Vehicle,” Aerial Vehicle,” AIAA
Infotech at Aerospace, Rohnert Park, CA, May 2007, AIAA.
Details mathematical model, data and 6-DOF MATLAB/Simulink model will be provided in the
lab.[Uploaded in each PC during experiment.]
Exercise:-
1. Simulate and verified results of any six –DOF aircraft simulation research paper.
Experiment No.10 – Flight Simulator
Exp. 10A Cessna 172 Analog

Exp. 10B Cessna 172 Glass
Aim:
To get familiarization with Cessna 172 Analog/Glass flight simulation/X-Plane.

To learn and verify the instrument panels and information.
To realize flight simulation capability of Cessna -172 aircraft using Prepar3D Lockheed
Martin flight simulation software
To learn and verify the various Interface modules, VFR & IFR during flight.
Flight Simulator
15-Cockpit Live Share (CLS)
Audio Systems.
Power source availability and air condition in lab..
Note:
General Instruction pre start:
1. Checking the Power switches on for Main Simulator & all 15 CLS.
2. Checking the all 3 AC on (17 Degree C).
3. Checking charging condition of Batteries for audio jack.
CLS Startup Procedure:
1. Switch on the mains power.

2. Switch on the main simulator.
3. CLS will come alive with the simulator.
4. Audio on the CLS’s headphones come alive when the main sim's audio power connector
is plugged into the 12V battery.
5. Volume on each individual headset on the CLS units may be adjusted through the volume
adjust knob.
Procedure:
1. Make Sure the Albatross Sim is receiving 220V AC Power. This is confirmed by the dim
wash lights in the cockpit (for the flaps, counter, and trim wheel).
2. Insert the Sim key into the slot near the Hour Counter. Turning to the ‘ON’ position (right)
enables the Sim ON/OFF button on the right-most instrument panel.
3. Press the SIM ON/OFF button once and release. Very soon, the CPU fans will activate,
confirmed by a ‘beep.
4. Restore the Sim key position to ‘OFF’ position (left). This prevents any accidental
shutdown of the sim.
5. Allow the flight simulator computer to start up. Ensure that all screens display the red
‘X/Aerxlab’ mark on a black background.
6. Double Click on either ‘X Plane’ or the Cessna Glass or Analog icons on the desktop. This
will start either X plane or Prepar3D.
7. Plug in the audio system power connector (red connector, outside the sim, under the sim
door). This enables the headset intercom in the sim. This can be checked by speaking
into the mic on either headset, and listening on the other.
8. The flight simulator is now ready to use.
9. Close the door with care. Anticipate a high closing force when closing. Keep clear all body
parts.
10. Follow the Simulator manual for details
Operation Mode Selection:
1. Cessna-172 Analog
2. Cessna-172 Glass
Introduction
The FE – HE – 03 ‘Albatross’ was designed specifically for the academia.
The entire flight simulator system, comprising of one Albatross Flight Simulator (FE-HE-03),
serving as the main simulator, and a Cockpit Live Share system comprising fifteen (15) slave
simulator desks, is the most unique academic flight simulator setup across the world. This flight
simulator system allows up to 30 students to understand avionics, aerodynamics and associated
subjects at one go.
The flight simulator further allows students to design and develop their own virtual aircraft and
test fly to validate the aircraft design, as part of 'Aircraft Design'. Students can also 'design' their
own instruments using simple xml coding and load the codes onto the six pack devices to test
and validate their basic avionic instrumentation designs.
With the flight simulator system, students at the university are given an opportunity to graduate
with the highest degree of understanding, making them preferred candidates for both the industry
and academia, while allowing for research within the department.
Description of the Simulator:
Cockpit Live Share

Aircraft Design using X-Plane software and Aerodynamics analysis over aircraft
Follow the lab instructor to fly with different condition and observe the flight and other
data.
Experiment No.11 – Study of antenna theory, simulation using PCAAD, CEM ONE
SOLUTION & MATLAB [PCAAD-Personal Computer Aided Antenna Design]
EXP 11A :- Study of antenna theory, simulation using PCAAD, CEM ONE SOLUTION & MATLAB
[PCAAD-Personal Computer Aided Antenna Design]
EXP 11B :-Various Antenna Analysis using PCAAD, CEM ONE SOLUTION & MATLAB [PCAAD-
Personal Computer Aided Antenna Design]
Aim:
To get familiarization of antenna theory.

To learn PCAAD–Antenna design software.
To learn CEM ONE –Antenna design software.
To learn, design and analyze the Dipole, Thin wire and patch antenna
Compare the results.
PC installed software
CEM ONE SOLUTION-ANTENNA DESIGN SOFTWARE
PCAAD SOFTWARE AND MATLAB
Power source.
Note:
General Instruction pre start:
4. Checking the Power switches on.

5. Checking the software license is working.
Procedure:
1. STARTING THE PROGRAM :Start the Efield program and the Efield launcher window is
shown;
2. GEOMETRY: Create a geometry as per problem. The excitation will be a delta gap voltage
excitation at the midpoint of the dipole. Create/edit points tool in the manual processing
tool. Enter the point name in the entry Name and the coordinates in the entries X, Y, Z
under Coordinates and press Apply.
3. MATERIAL AND PROPERTIES: Open the Efield Materials and Properties Tool in the
EfieldFD toolbox. Click on the button Create and the window Define Material is opened.
For example :Enter the name WIRE, select as Type Wire nd Subtype Wire and enter the
radius 0.001 m (radius given in meters) in the Radius entry and let the resistance be zero
and press the OK button.
4. MESHING :Open the Mesh Manager Tool located in the EfieldFD toolbox. Elements tab:
In the Elements tab select Lines under Type and then Select all by right click in the list
window. Select 2- node beam in the drop down menu under Filter and the element type
is set to BE2 in the Element list. Select the element BE2 by clicking on this field and press
the Apply button. The lines should now have been assigned. Style tab: In the Style tab
select as Default mesh style in the drop down menu Delaunay meshing (EfieldFD).
Sizing tab: In the Sizing tab select the sub tab Advanced which is the most general tool
to set the division along the lines which is used to control the density of the mesh.
Meshing: Select the lines (can be done in the Density tab or in some of the other tabs)
and press the MESH button.
5. Displaying the mesh: In the Display tab the user can select colour for the elements
(segments) and nodes using the colour menu. The centre node with number 2 will be the
excitation node used in the delta gap excitation.
6. EXPORT THE MESH: To export mesh and geometry definitions the Mesh and Geometry
Export button is used.
7. EM GUI:The EfieldFD Electro- Magnetic Graphical User Interface (EfieldFD EM GUI) is

started by using the EfieldFD EM GUI icon . The EfieldFD EM GUI is used to create a
solver input file with extension .dat. In this example the input solver file will have the name
dipole.dat since the model name starts with dipole.
8. Frequency: Press the Frequency button and the Frequency window will be displayed.
Select Frequency interval and let Scale be Linear. Enter in the entry First frequency,
in the entry Last frequency and in the Steps entry. Press the Add Frequency button (à)
to define the frequency in the Defined list. Press OK to leave the Frequency window.
9. Excitations and Sources: Press the Excitations and Sources button and the
Excitation and Sources window will be displayed. Select Delta Gap from the list of
excitations. Use the Node pick entry in the DELTA GAP part of the window to select the
central node with node number 2. Either type the number of the node or pick in the model.
The user has to plot the nodes in the model window to be able to pick the nodes. Use the
Add Delta Gap button (à) to define the delta gap excitation in the Defined list. Use the
Add Source Excitation button (à) to add the delta gap excitation to the Excitation list.
Exit the Excitation and Sources window by pressing the OK button.
10. Field Computations:Press the Field Computations button and the Fields and Currents
window is opened. Select Currents to get the wire currents in the results and select
General Farfield and the window is expanded. Enter the details require and press OK to
exit the Fields and Currents window.
11. Output:Press the Output button and the Final Output window is opened. No changes
need to be done from the default values. Exit the window by pressing the OK button.
12. Creating the solver input file:In the EfieldFD EM GUI, select the options Show data file
after Make and press the Make button to create the data file. When the option Show data
file after Make is selected the data file is displayed in a separate window. After the data
file has been created exit the EfieldFD EM GUI, Figure 24, by pressing Close and the
settings is saved in the current Efield session. The Quit button is used to exit the window
without saving the settings made.
13. RUNNING SOLVERS: The Efield Run Manager is started with the icon . The solver input
file dipole.dat is loaded automatically. Press the Start simulation button and the solver
is running. Output from the solver is echoed in the text output window in Efield Run
Manager window. After the solver has finished select Exit under the File menu. The solver
has now created an output file called dipole.nc which is a netCDF database file.
14. RESULTS: Creating the result data base
15. Loading the result database into the Result Manager

16. Plotting the input impedance against frequencies
17. Plotting the wire current in a graph
18. Plotting wire current as contour lines on geometry
19. Plotting vectors and numerical values on wire
20. Plot the far field:
PCAAD Software will be used to compare the results. Follow the detail instruction from PCAAD
and CEM ONE –Antenna Design software user manual.
Exercise:- Model the following:
1. Half wavelength dipole

2. Monopole modeled as a thin wire
3. Monopole modeled as a port
4. Monopole modeled as a Cylinder
5. Patch antenna
Experiment No.12– Digital Data Bus Communication-MIL-STD 1553B (PCI-1553, SIM-1553,

SIM-ARINC429)[Software Study]
Aim:
To get familiarization with MIL-STD 1553B data bus card.

To learn and verify the SIM-1553, SIM-ARINC429 communication protocol.
To realize operational mode of PCI-1553 (MIL STD-1553B data bus card)
To learn the various Interface remote terminal (RTs) module. (Facility not available)
To learn, design and verify the communication between BM to Monitor, BC-RT, RT-BC,
RT-RT, BC-Monitor communication. (Few features are not currently available)
PCI-1553 (MIL STD-1553B) data bus card & Connector
PC Host with installed AltaAPI, AltaView, AltaRTVal Software
Note:
4. For the understanding of protocol follow the AltaView Analyzer software.

5. Single pc have installed PCI-1553 DATA Card.
6. Hands on experience is limited only to software analysis.
7. Follow the Alta View User Manual.
Procedure:
1. Switch on the PC installed Alta View Software.

2. Start or open the AltaAPI, AltaView, AltaRTVal.
3. Select either SIM MIL-STAD 1553B or SIM ARINC 429.
3. Learn the every features of SIM MIL-STAD 1553B protocol through alta software.
4. Learn the every features of SIM ARINC 429protocol through alta software.
5. Log the simulated data file and plot in the MATLAB.
5. Make the report on MIL-STAD 1553B and ARINC 429 transmission protocol.
6. Close the application and shutdown the monitor/PC.
Scope:
This standard establishes requirements for digital, command/response, time division multiplexing
(Data Bus) techniques. It encompasses the data bus line and its interface electronics illustrated
on Figure 1, and also defines the concept of operation and information flow on the multiplex data
bus and the electrical and functional formats to be employed.
Application:
When invoked in a specification or statement of work, these requirements shall apply to the
multiplex data bus and associated equipment which is developed either alone or as a portion of
a weapon system or subsystem development. The contractor is responsible for invoking all the
applicable requirements of this Military Standard on any and all subcontractors he may employ.
Note:- Refer the manual and supported pdf for documentation and understanding.
Exercise :
1. Explain the MIL-STD-1553B.

2. Explain the ARINC-429.
3. Write the other data buses available in the aviation fields.
4. What is the difference between the Remote Terminal, Bus Controller and Bus Monitoring?
5. What you learn from this experiments

Avionics Lab Manual

Загружено:

Сведения о документе

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Avionics Lab Manual

Загружено:

Авторское право:

Доступные форматы

AVIONICS LABORATORY

AVIONICS LABORATORY MANUAL

Class : Aeronautical Engineering , VII Semester

Department of Aeronautical and Automobile Engineering

AVIONICS LABORATORY MANUAL

Class : Aeronautical Engineering , VII Semester

Department of Aeronautical and Automobile Engineering

Department of Aeronautical & Automobile

This is to certify that Mr./ Ms.………………………………………..Bearing

Name & signature of the Signature of Head of the

➢ Enter Lab with CLOSED FOOTWEAR

UNIVERSITY PRACTICAL EXAMINATION

1. Internal Assessment = 60 marks

INTERNAL ASSESSMENT [60 Marks]

SPLIT UP OF INTERNAL MARKS

a) Record Note = 40 marks

UNIVERSITY EXAMINATION [40 Marks]

Split up of Practical Examination Marks

a) Aim and Procedure = 10 marks

AVIONICS LABORTORY OBJECTIVES

• To get familiarization with IC trainer kit.

o ICs – 7400, 7402, 7408, 7432, 7486.

7408: Quad 2-input AND

A. Universality of NAND ad NOR gates:

• Basic logic functions using NAND gates:

• Basic logic functions using NOR gates:

B. Construction of Combinational Circuits:

Logic Expression F= (A+C)(B+D)

1. Design a combinational circuit to produce 2’s compliment of a 4bit binary number.

Experiment No. 02 ARITHMETIC CIRCUITS

Equipment’s & Components Required:

o ICs 7408, 7432, 7404, 7400, 7486, 7410, 7483

VCC 7483 CIN

o Connect Vcc and Ground to the respective pins.

F. 4 Bit adder / 2’s complement subtractor:

When control input is 0, input B = b3 b2 b1 b0 is added to input A = a3 a2 a1 a0.

1. Implement half adder circuit using only NOR gates.

Experiment No. 03 MAGNITUDE COMPARATOR

Equipments & Components Required:

o When input A is greater than input B, output (A>B) will be high

Parity generator / checker

Equipments & Components Required:

C. 3-bit odd parity generator/checker: An odd parity generator generates a 1 for an

Experiment No. 04 MULTIPLEXERS AND DEMULTIPLEXERS

DEMULTIPLEXER – A demultiplexer or data distributaor is a circuit that receives information

Components and Equipments Required:

A. 4:1 Multiplexer using only NAND gates

Select lines Data Outputs

Experiment No. 05 ENCODERS AND DECODERS

Components and Equipments Required:

A. Design and implement 2 to 4 decoder using basic gates:

C. Design and implement Octal to Binary encoder using basic gates

1. Study and verify the truth table of 74148 ,a 8 to 3 Priority Encoder

Experiment No. 06 STUDY OF FLIPFLOPS

A. SR Flip-flop using NAND gates:

Note : Apply high-going mono pulse to CLK

B. D Flip-flop using NAND gates:

C. JK Flip-Flop using NAND gates:

D. T-Flip Flop using NAND gates:

NOTE: Draw the pin diagram of 7474 IC from the manual

F. Study of 74LS73A: Negative edge triggered dual JK Flip-flops with clear

NOTE: Draw the pin diagram of IC 7473 from the manual

G. Conversion of flip flops:

(a) Convert SR flip flop to D flip flop