Академический Документы
Профессиональный Документы
Культура Документы
As CMOS scaling extends into 28nm technology, structures with channel width/length of 1umlO.03um are
transistor behavior depends not only on its channel length and studied. The LPE trends are analyzed by the threshold voltage
width, but also on other layout geometric parameters and the (Vtsat) and saturated drive current (Idsat). For PMOS, we used
surrounding neighborhood. In this paper, a systematic study the absolute value of these two parameters.
c
EXPERIMENTS 1 z
10 100 10 100
ASE.lon,ctt.nn.lwldthdlr.ctlon (.rbltl'lryunlt)
(c) (d)
Fig 6: N/PMOS electrical parameters and ASE (a) (b)
correlation. (a) idsat and ASE correlation along channel Fig8:NMOS electrical parameters and WPE correlation.
length direction. (b) Vtsat and ASE correlation along (a) Jdsat and WPE correlation, (b) Vtsat and WPE
channel length direction. (c) idsat and ASE correlation correlation
.
along channel width direction. (d) Vtsat and ASE
JUll1u\
correlation along width direction.
.�'
1£.02 __________-,
-
. �. :-:
� - .
II ... , .
.
. -
�
• �mOlIl AA �clr�LNMOS
.IOIf8� AA �KinLNMOS Active area
" ...
10 1) 12 13 U 15 16 17 18 19 20
IOSAT (.rbltrtry unh)
. ·
channel width direction Fig9: mechanism ofWPE
I.'''' --------,
When AA spacing is reduced, weaker STI tensile stress is
bad along channel length direction and is good along channel • -
width direction for PMOS. But in fact, PMOS ASE trends are '§ 1.E+02 •• • !111-
..
similar for the two directions. The root cause is that the
dominant factor of PMOS ASE is not STI stress, but likely the
i� 1.£+01
• •
• �r ·
eSiGe stress. We suspect that with the reduction of AA spacing, • small well toM edgE' spacinlLNMOS
• large well to AA edge SpaCinlLNMOS
AA has a larger pattern density within the same area. I.E.oo
10 11 12 13 H 15 16 17 IS 19 :::.'0
Consequently, eSiGe has a larger pattern density, which brings IOSAT(arbitrary unit)
two results. The first one is less eSiGe volume which leads to
Fig] 0: NMOS Jdsat vs. JojJ plot ofdifferent well to AA edge
weaker compressive stress. The second one is the more tapered
spacing
eSiGe profIle in smaller SA transistor which leads to deeper
source/drain implantation and worse short channel effect, as Compared to NMOS, PMOS WPE trend is weaker. This
mentioned before. The weaker compressive stress makes Idsat could be due to less scattering of well and Vt implantation
decrease. The worse short channel effect makes Vtsat drop and species and/or less impact on carrier mobility in PMOS.
Idsat increase. Finally, both Vtsat and Idsat drop as shown in
Fig.6. SUMMARY
Well proximity effect Layout proximity effects for 28nm PolySiON have been
As shown in Fig.I, for the different well to AA edge studied systematically, including LOD, DPS, ASE and WPE
spacing, whether along channel length or along channel width effects. We explored the mechanisms behind these LPEs and
direction, device electrical parameters may change, which is proposed physical models that can explain the LPEs' impacts
on transistor electrical behavior. We found that for NMOS, the
change of dopant distribution and mobility at different
transistor geometric parameters are the two major factors that
cause LPEs. For PMOS, although dopant distribution and STI
stress still have influence on the electrical parameters, eSiGe
stressor plays a more important role in LOD and ASE effects.
When the eSiGe volume decreases, compressive stress
becomes weaker. As a result, Idsat decreases and device
performance degrades. When the eSiGe profile becomes
tapered, PMOS source/drain implantation gets deeper. It leads
to worse short channel effect and Vtsat drop. If the eSiGe
process and the related junction engineering can be improved,
PMOS LPE trends should be more flat.
REFERENCES
[I] John V. Faricelli, IEEE Custom Integrated Circuits Conference
(CICC), pp.l-8, 2010.
[2] Eij i Morifuj i, Hisashi Aikawa, Hisao Yoshimura, et al. IEEE
Transactions on, Electron Devices, vol. 56, pp. 1991-1998, 2009.
[3] Doyong Jang, Marie Garcia Bardon, Dmitry Yakimets, et al.
Solid-State Device Research Conference (ESSDERC), 2013
Proceedings of the European, pp.l59-162, 2013.
[4] Youn Sung Choi, Guoda Lian, Catherine Vartuli, et al. IEEE
Transactions on, Electron Devices, vol. 57, pp.2886-289l, 2010.
[5] Geert Eneman, Peter Verheyen, Rita Rooyackers, et al. IEEE
Transactions on, Electron Devices, vol. 53, pp.1647-l656, 2006.
[6] Chung-Yun Cheng, Yean-Kuen Fang, Jang-Cheng Hsieh, et al.
IEEE Transactions on, Electron Devices, vol. 56, pp.16l8-l623,
2009.
[7] Xiwei Lin, ICSICT2008, 9th International Conference,
Solid-State and Integrated-Circuit Technology, pp.2228-223l,
2008.
[8] P. G. Drennan, M. L. Kniffin, D. R. Locascio, 1EEE, 1 Custom
1ntegrated Circuits Conference, pp.169-176, 2006.
[9] Yi-Ming Sheu, Ke-Wei Su, Shiyang Tian, et al. 1EEE
Transactions on, Electron Devices. vol. 53. pp.2792-2798, 2006.