ACCELERATE EARLY DESIGN

EXPLORATION & VERIFICATION

FOR FASTER TIME TO MARKET

NERMEEN HOSSAM AND JOHN FERGUSON

MENTOR, A SIEMENS BUSINESS

W H I T E P A P E R

D E S I G N T O S I L I C O N

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Accelerate early design exploration & verification for faster time to market

CHALLENGES OF CHIP-LEVEL VERIFICATION

Given the size and complexity of advanced node
designs, combined with the never-ending
competition to be the first to market, system on
chip (SoC) design teams don’t have the luxury of
waiting until all chip blocks are completely
finished to start their chip assembly. Accordingly,
SoC designers typically start chip integration in
parallel with block development to capture and
correct any routing violations early in the design
cycle, helping them reduce that critical time to
market. By eliminating errors early, when they are
easier to fix without significant impacts on the
layout, designers can reduce the number of
design rule checking (DRC) iterations required to
achieve tapeout (Figure 1). Figure 1: Identifying and fixing chip integration
issues in parallel with block development
However, early chip-level physical verification minimizes the number of DRC iterations
faces many challenges. Typically, during very throughout the design implementation flow.
early phases of floorplanning, the number of
reported violations in the unfinished blocks is
huge. Many systematic issues may be widely distributed across the design, contributing to this
large error count. Characteristic examples of systematic issues include off-grid block placement
at the SoC level, merged IP outside the SoC MACRO footprint, routing in IP on a reserved
routing layer, incorrect via type on a clock net, and IP placement
orientation mismatch in the SoC, as shown in Figure 2. It is no trivial
task at this stage to differentiate between block-level violations and
top-level routing violations.

Using the default settings in foundry rule decks for initial DRC runs
typically results in very long runtimes, a massive number of
reported violations, and an extremely large generated results
database, all of which makes debugging extremely difficult and
time-consuming.

At this early stage, the SoC designer’s goal is usually to minimize

Figure 2: Systematic errors often contribute
to the large number of violations found in
early chip-level verification.
the runtime of each DRC iteration and focus only on the violations
that are relevant at this time. In addition to separating out block
violations from the routing violations they need to debug, SoC
designers can send block violations back to the block owners for
debug and correction. Ultimately, the SoC designer’s goal is to find
and fix SoC systematic issues, from early floorplan through final
tapeout.

IMPROVING DIRTY BLOCK/CHIP-LEVEL VERIFICATION

The Calibre™ Reconnaissance (Calibre Recon) tool is a complete package of functionalities that
enables design teams to begin exploration and physical verification of full chip design layouts
during very early stages of the design cycle, while the different components are still immature.
The Calibre Recon tool is very effective in identifying early potential integration issues and
providing fast feedback to design teams for proper corrective actions, ultimately resulting in
fewer DRC iterations, reduced total turnaround time, and faster time to market. In addition, the
Calibre Recon tool is engineered to deliver all these capabilities from the very first run using any

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foundry/independent device manufacturer (IDM) Calibre sign-off design kits “as is” on any
process technology node.

AUTOMATIC CHECK SELECTION

Some rule checks are known to be prone to long
runtimes in the presence of errors. Deselecting such
rules can significantly speed runs, but how does the
designer decide which set of checks to deselect?
Deselect the checks with many operations? Or choose a
certain category to deselect, such as antenna checks, or
all connectivity checks? Selecting the “best” set of
checks to run is not easy, and it may require a lot of
advanced analysis, as well as some editing to the
foundry rule deck (Figure 3).
Figure 3: Selecting the correct set of checks
The Calibre Recon tool automatically deselects the for early verification requires careful
checks that are not relevant for the current analysis.
development phase. The Calibre engine makes the
decision on which checks to deselect, based on the check type and the number of operations
executed for the check, with the goal of providing good coverage, fast runtime, and less
memory consumption. On average, the Calibre Recon tool reduces the number of checks
performed by about 50% across a range of process nodes. The deselected checks/categories are
reported in the transcript for user reference. The Calibre Recon tool also honors any checks/
categories manually deselected by the user.

Automatic deselection of checks typically results in the total number of reported violations
being reduced to about 70% of the original count (Figure 4). However, these violations are more
meaningful to the targeted implementation stage, which facilitates analysis and debugging of
real systematic issues.

Figure 4: Reductions in the

total number of rule checks
performed and the resulting
number of reported
violations when using
Calibre Recon functionality.

The Calibre Recon tool reduces overall DRC runtime by up to 14x, while still checking ~50% of
the total DRC set. The subset of rules automatically selected by the Calibre engine are effective
in identifying floorplan and sub-chip integration issues, providing fast feedback to the design
team for proper corrective action and resulting in a significantly reduced total turnaround time.
Figure 5 shows DRC runtime results based on testing across different chips.

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Figure 5: Results of testing

Calibre Recon automatic
check selection across a
variety of chips shows
substantial reductions in
DRC runtimes and memory
consumption in early
implementation stages.

Calibre Recon verification not only helps SoC designers with early chip-level validation, but also
supports early block verification. Because block and chip design are being done in parallel, a
block designer can run Calibre Recon verification on the block. If errors are reported, the block
designer can fix the systematic issues. If the Calibre Recon results are clean, the block can be
passed to the chip, while the block designer runs the remaining rules in parallel on that block.
As shown in Figure 6, running the Calibre Recon tool on blocks (tiles) during initial routing
resulted in up to an 8x runtime improvement and a 4x memory improvement.
Figure 6: Comparison of
Calibre Recon runs to full
Calibre nmDRC runs for both
tiles and full chip at different
stages of development,
showing reductions in
runtimes and memory
usage.

GRAY BOX EXCLUSION

Following the same exclusion concept,
but this time from a design perspective, is
it possible to ignore some parts of the
design (mainly immature blocks) to focus
on interface and routing violations and
decrease runtimes? The Calibre Recon
gray box feature allows the designer to
check top-level routing while ignoring
cell details. The gray box designation
removes data from within the specified
cell without removing geometries from
the higher-up parent (Figure 7).
Accordingly, any routing violation over
the specified cells is still captured. In
addition, designers can keep a certain Figure 7: The Calibre Recon gray box designation enables
halo around the removed geometries by designers to exclude certain portions of the layout from
sizing the extent of the cell down, to DRC, while still allowing them to check those areas for
capture interface violations between the interface or routing violations.
specified cells and their neighbors.

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The gray box solution is equally applicable to both rectangular and non-rectangular cells,
although the designer may need to specify the layer that represents the extent of the non-
rectangular cells (boundary layers can be used for this purpose).

Although the gray box feature improves runtime, removing the geometries from the specified
cells may introduce some new DRC violations, which will require additional debugging to
differentiate between real violations and those that were created by cutting the geometries
from the specified cells. To avoid this issue, and eliminate the need to edit the foundry rule deck
to add the specification statement for the gray box feature, the designer can use the Calibre
Recon gray box feature in conjunction with Calibre Auto-Waivers functionality. As shown in
Figure 8, the main purpose is to reduce runtimes by not checking geometries from incomplete
blocks, with the secondary benefit of waiving any violations introduced by excluding regions
from the specified cells. This combination allows designers to focus on the original (valid) DRC
interface violations. All waived violations are saved to a waiver results database files for later
review, if required.

Figure 8: Combining the

Calibre Recon gray box
feature with Calibre Auto-
Waiver functionality enables
designers to perform
interface and top-level
routing validation without
worrying about errors
created by removing
geometries from the gray
boxed cells.

The gray box solution provides the SoC team with pointers to interface DRC errors that require
their attention. It also isolates integration and routing violations associated with assembly from
the immature block violations. As Figure 9 shows, combining this feature with automatic
selection of relevant checks further reduces runtime by focusing on selected violations reported
on areas in the design that require more attention during a particular phase. Accordingly, it
helps design teams resolve more of the critical interface issues early in the cycle, and avoids
unpleasant last-minute surprises.

Figure 9: Using Calibre

Recon automatic check
selection in conjunction
with the gray box feature
helps focus verification on
critical interface and routing
issues in early design
implementation phases.

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DRC ANALYZE
The Calibre Recon DRC Analyze function helps designers quickly analyze their designs and
visually look at the distribution of errors to identify the opportunistic areas for quick
enhancement of layout quality.

The DRC Analyze function allows designers to draw different histograms (based on hierarchical
cells or windows) for chip analysis, and specify custom scaling ranges for these histograms.
Colormaps of the results can also be drawn, either on standalone windows or mapped on the
design, to enable designers to probe down to see error details (per cell and per window), where
the results are shown distributed across the design (Figure 10).

Figure 10: The Calibre Recon

DRC Analyze function
enables fast, in-depth
visualization and analysis
during error review and
debugging.

However, the main advantage of the DRC Analyze function is that designers can use the foundry
rule deck to do all the required analysis, without any editing. The overhead (an average 10%
runtime increase and 20% memory increase) is minimal compared to the value this analysis
delivers during chip analysis and debugging.

CONCLUSION
SoC design teams face huge runtime issues during DRC runs on their chips. Their designs are
too immature early in development to run full DRC, and it is not an easy task to manually
identify the proper subset of rules that would allow them to quickly identify relevant design
problems or exclude dirty blocks without incurring a big penalty in DRC runtime.

The Calibre Recon solution enables designers to quickly and easily find and resolve integration
issues early in the design cycle, using the foundry/IDM Calibre sign-off design kit, while
reducing total DRC runtime, accelerating design closure (and accordingly, time to market), and
ensuring they deliver high-quality designs. For companies targeting demanding end-markets
such as the Internet of Things, artificial intelligence, autonomous driving, and 5G
communications spaces, these advantages can make the difference between just being in the
market, and being a market leader.

What’s more, early design exploration and verification with the Calibre Recon tool is just the
first functionality to be made available from our ongoing research and development work in
physical verification technologies. New capabilities that take advantage of today’s emerging
technologies (such as machine learning and artificial intelligence) will help design companies
and foundries/IDMs produce better designs faster and more economically at all nodes.

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For more information about Calibre Recon,

visit the Calibre nmDRC webpage

or

contact a Calibre representative

For the latest product information, call us or visit: w w w . m e n t o r . c o m

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