Course: DIGITAL ELECTRONICS AND LOGIC DESIGN Instructor:

Your home assignments

SrNo Section/Unit Question Question Question Answer Weightage Deadline Submit Marks Teacher
No file (if file (if Date Assignment Remark
any) any)

1 1 17 Convert T FF to following FF’s. 10.0 14-10- NA Please

OverDue
2019 submit
a) JK FF
assignment
b) SR FF

c)D FF

2 1 7 Demonstrate how A > B output can 10.0 14-10- OverDue NA Please

be generated using IC74181 ALU. 2019 submit
Also, show how A>=B condition assignment
can be checked. 

3 1 18 Convert DFF to following FF’s. 10.0 14-10- NA Please

OverDue
2019 submit
a) JK FF
assignment
b) SR FF

c) T FF

4 1 22 Discuss drawbacks of JK FF’s with 10.0 14-10- NA Please

OverDue
suitable timing diagram. List out 2019 submit
different method to overcome assignment
drawbacks of JK FF’s.

5 1 20 Show mod-8  asynchronous  up 10.0 14-10- NA Please

OverDue
counter act as frequency divider 2019 submit
 circuit with suitable timing assignment
diagram .Use positive edge trigger
JK FF

6 2 41 Design 1-0-1-1 Mealy sequences 10.0 17-10- NA Please

OverDue
detector using suitable PLA 2019 submit
assignment

7 2 30 Discuss CMOS NOR gate with 10.0 17-10- OverDue NA Please

suitable circuit diagram. 2019 submit
assignment

8 2 35 Discuss TTL AND gate with 10.0 17-10- NA Please

OverDue
suitable circuit diagram. 2019 submit
assignment

9 2 33 Discuss TTL OR gate with suitable 10.0 17-10- NA Please

OverDue
circuit diagram. 2019 submit
assignment

10 2 29 Discuss CMOS AND gate with 10.0 17-10- NA Please

OverDue
suitable circuit diagram. 2019 submit
assignment