MC14001B Series

B-Suffix Series CMOS Gates

MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure http://onsemi.com
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC−14 TSSOP−14
• All Outputs Buffered D SUFFIX DT SUFFIX
• Capable of Driving Two Low−power TTL Loads or One Low−power CASE 751A CASE 948G

Schottky TTL Load Over the Rated Temperature Range.

MARKING DIAGRAMS
• Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B 14
14
• Pin−for−Pin Replacements for Corresponding CD4000 Series 14
B Suffix Devices 140xxBG 0xxB
AWLYWW
• NLV Prefix for Automotive and Other Applications Requiring ALYWG
G
Unique Site and Control Change Requirements; AEC−Q100 1
1
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
SOIC−14 TSSOP−14

MAXIMUM RATINGS (Voltages Referenced to VSS) xx = Specific Device Code

A = Assembly Location
Symbol Parameter Value Unit WL, L = Wafer Lot
VDD DC Supply Voltage Range −0.5 to +18.0 V YY, Y = Year
WW, W = Work Week
Vin, Vout Input or Output Voltage Range −0.5 to VDD + 0.5 V G or G = Pb−Free Package
(DC or Transient)
(Note: Microdot may be in either location)
Iin, Iout Input or Output Current ± 10 mA
(DC or Transient) per Pin
DEVICE INFORMATION
PD Power Dissipation, per Package 500 mW
(Note 1)
Device Description
TA Ambient Temperature Range −55 to +125 °C MC14001B Quad 2−Input NOR Gate
Tstg Storage Temperature Range −65 to +150 °C MC14011B Quad 2−Input NAND Gate
TL Lead Temperature 260 °C MC14023B Triple 3−Input NAND Gate
(8−Second Soldering)
MC14025B Triple 3−Input NOR Gate
VESD ESD Withstand Voltage V
Human Body Model > 3000 MC14071B Quad 2−Input OR Gate
Machine Model > 300
Charged Device Model MC14073B Triple 3−Input AND Gate
N/A
Stresses exceeding those listed in the Maximum Ratings table may damage the MC14081B Quad 2−Input AND Gate
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected. MC14082B Dual 4−Input AND Gate
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high ORDERING INFORMATION
static voltages or electric fields. However, precautions must be taken to avoid See detailed ordering and shipping information in the package
applications of any voltage higher than maximum rated voltages to this dimensions section on page 8 of this data sheet.
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

July, 2014 − Rev. 11 MC14001B/D
 MC14001B Series

LOGIC DIAGRAMS
NOR NAND OR AND

MC14001B MC14011B MC14071B MC14081B

Quad 2−Input NOR Gate Quad 2−Input NAND Gate Quad 2−Input OR Gate Quad 2−Input AND Gate

1 1 1 1
3 3 3 3
2 2 2 2

5 5 5 5
2 INPUT

4 4 4 4
6 6 6 6

8 8 8 8
10 10 10 10
9 9 9 9

12 12 12 12
11 11 11 11
13 13 13 13

MC14025B MC14023B MC14073B MC14082B

Triple 3−Input NOR Gate Triple 3−Input NAND Gate Triple 3−Input AND Gate Dual 4−Input AND Gate

1 1 1 2
2 9 2 9 2 9
3 1
8 8 8
4
3 INPUT

3 3 3 5
4 6 4 6 4 6 9
5 5 5
10 13
11 11 11 11
12 10 12 10 12 10 12
13 13 13 NC = 6, 8
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES

PIN ASSIGNMENTS
MC14001B MC14011B MC14023B MC14025B
Quad 2−Input NOR Gate Quad 2−Input NAND Gate Triple 3−Input NAND Gate Triple 3−Input NOR Gate

IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD

IN 2A 2 13 IN 2D IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C
OUTA 3 12 IN 1D OUTA 3 12 IN 1D IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C
OUTB 4 11 OUTD OUTB 4 11 OUTD IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C
IN 1B 5 10 OUTC IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 3B 5 10 OUTC
IN 2B 6 9 IN 2C IN 2B 6 9 IN 2C OUTB 6 9 OUTA OUTB 6 9 OUTA
VSS 7 8 IN 1C VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 3A

MC14071B MC14073B MC14081B MC14082B

Quad 2−Input OR Gate Triple 3−Input AND Gate Quad 2−Input AND Gate Dual 4−Input AND Gate
IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD OUTA 1 14 VDD
IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 2D IN 1A 2 13 OUTB
OUTA 3 12 IN 1D IN 1B 3 12 IN 2C OUTA 3 12 IN 1D IN 2A 3 12 IN 4B
OUTB 4 11 OUTD IN 2B 4 11 IN 1C OUTB 4 11 OUTD IN 3A 4 11 IN 3B
IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 1B 5 10 OUTC IN 4A 5 10 IN 2B
IN 2B 6 9 IN 2C OUTB 6 9 OUTA IN 2B 6 9 IN 2C NC 6 9 IN 1B
VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 1C VSS 7 8 NC

NC = NO CONNECTION

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 MC14001B Series

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

− 55_C 25_C 125_C

VDD Typ
Characteristic Symbol Vdc Min Max Min (Note 2) Max Min Max Unit
Output Voltage “0” Level VOL 5.0 − 0.05 − 0 0.05 − 0.05 Vdc
Vin = VDD or 0 10 − 0.05 − 0 0.05 − 0.05
15 − 0.05 − 0 0.05 − 0.05
“1” Level VOH 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc
Vin = 0 or VDD 10 9.95 − 9.95 10 − 9.95 −
15 14.95 − 14.95 15 − 14.95 −
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 − 1.5 − 2.25 1.5 − 1.5
(VO = 9.0 or 1.0 Vdc) 10 − 3.0 − 4.50 3.0 − 3.0
(VO = 13.5 or 1.5 Vdc) 15 − 4.0 − 6.75 4.0 − 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 − 3.5 2.75 − 3.5 −
(VO = 1.0 or 9.0 Vdc) 10 7.0 − 7.0 5.50 − 7.0 −
(VO = 1.5 or 13.5 Vdc) 15 11 − 11 8.25 − 11 −
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 –3.0 − –2.4 –4.2 − –1.7 −
(VOH = 4.6 Vdc) 5.0 –0.64 − –0.51 –0.88 − –0.36 −
(VOH = 9.5 Vdc) 10 –1.6 − –1.3 –2.25 − –0.9 −
(VOH = 13.5 Vdc) 15 –4.2 − –3.4 –8.8 − –2.4 −
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc
(VOL = 0.5 Vdc) 10 1.6 − 1.3 2.25 − 0.9 −
(VOL = 1.5 Vdc) 15 4.2 − 3.4 8.8 − 2.4 −
Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc
Input Capacitance Cin − − − − 5.0 7.5 − − pF
(Vin = 0)
Quiescent Current IDD 5.0 − 0.25 − 0.0005 0.25 − 7.5 mAdc
(Per Package) 10 − 0.5 − 0.0010 0.5 − 15
15 − 1.0 − 0.0015 1.0 − 30
Total Supply Current (Notes 3, 4) IT 5.0 IT = (0.3 mA/kHz) f + IDD/N mAdc
(Dynamic plus Quiescent, 10 IT = (0.6 mA/kHz) f + IDD/N
Per Gate, CL = 50 pF) 15 IT = (0.9 mA/kHz) f + IDD/N
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.

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 MC14001B Series

B−SERIES GATE SWITCHING TIMES

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

VDD Typ
Characteristic Symbol Vdc Min (Note 6) Max Unit
Output Rise Time, All B−Series Gates tTLH ns
tTLH = (1.35 ns/pF) CL + 33 ns 5.0 − 100 200
tTLH = (0.60 ns/pF) CL + 20 ns 10 − 50 100
tTLH = (0.40 ns/PF) CL + 20 ns 15 − 40 80

Output Fall Time, All B−Series Gates tTHL ns

tTHL = (1.35 ns/pF) CL + 33 ns 5.0 − 100 200
tTHL = (0.60 ns/pF) CL + 20 ns 10 − 50 100
tTHL = (0.40 ns/pF) CL + 20 ns 15 − 40 80

Propagation Delay Time tPLH, tPHL ns

MC14001B, MC14011B only
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns 5.0 − 125 250
tPLH, tPHL = (0.36 ns/pF) CL + 32 ns 10 − 50 100
tPLH, tPHL = (0.26 ns/pF) CL + 27 ns 15 − 40 80
All Other 2, 3, and 4 Input Gates
tPLH, tPHL = (0.90 ns/pF) CL + 115 ns 5.0 − 160 300
tPLH, tPHL = (0.36 ns/pF) CL + 47 ns 10 − 65 130
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns 15 − 50 100
8−Input Gates (MC14068B, MC14078B)
tPLH, tPHL = (0.90 ns/pF) CL + 155 ns 5.0 − 200 350
tPLH, tPHL = (0.36 ns/pF) CL + 62 ns 10 − 80 150
tPLH, tPHL = (0.26 ns/pF) CL + 47 ns 15 − 60 110
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

14 VDD 20 ns 20 ns
VDD
INPUT 90%
INPUT 50%
PULSE 10% 0V
OUTPUT tPHL tPLH
GENERATOR

CL 90% VOH
* 50%
OUTPUT 10%
INVERTING VOL
tTHL tTLH
tPLH tPHL
7 VSS OUTPUT VOH
90%
NON-INVERTING 50%
*All unused inputs of AND, NAND gates must be connected to VDD. 10% VOL
All unused inputs of OR, NOR gates must be connected to VSS. tTLH tTHL

Figure 1. Switching Time Test Circuit and Waveforms

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 MC14001B Series

CIRCUIT SCHEMATIC
NOR, OR GATES

MC14001B, MC14071B MC14025B

One of Four Gates Shown One of Three Gates Shown

VDD VDD
14 VDD
1, 6, 8, 13 1, 3, 11

*
2, 5, 9, 12 2, 4, 12

14 VDD
3, 4, 10, 11

VSS
7 VSS 9, 6, 10
VSS
VDD
*Inverter omitted in MC14001B

8, 5, 13
7 VSS

VSS
*Inverter omitted in MC14025B

CIRCUIT SCHEMATIC
NAND, AND GATES

MC14023B, MC14073B MC14011B, MC14081B

One of Three Gates Shown One of Four Gates Shown
VDD 14 VDD

3, 4, 10, 11

2, 4, 12 14 VDD 2, 5, 9, 12

1, 3, 11 1, 6, 8, 13
VSS 7 VSS
* *Inverter omitted in MC14011B
VDD

9, 6, 10
8, 5, 13

7 VSS
VSS
*Inverter omitted in MC14023B

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 MC14001B Series

TYPICAL B−SERIES GATE CHARACTERISTICS

N−CHANNEL DRAIN CURRENT (SINK) P−CHANNEL DRAIN CURRENT (SOURCE)

5.0 - 10
- 9.0
4.0 - 8.0 TA = - 55°C
ID , DRAIN CURRENT (mA)

ID , DRAIN CURRENT (mA)

- 7.0
TA = - 55°C - 40°C
3.0 - 6.0
- 40°C
- 5.0
+ 85°C + 25°C + 25°C
2.0 - 4.0 + 85°C
+ 125°C
- 3.0 + 125°C
1.0 - 2.0
- 1.0
0 0
0 1.0 2.0 3.0 4.0 5.0 0 - 1.0 - 2.0 - 3.0 - 4.0 - 5.0
VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = − 5.0 Vdc

20 - 50
18 - 45
TA = - 55°C
16 - 40
ID , DRAIN CURRENT (mA)

ID , DRAIN CURRENT (mA)

14 - 40°C - 35
12 + 25°C - 30 TA = - 55°C
+ 85°C
10 - 25 - 40°C
8.0 + 125°C - 20 + 25°C
+ 85°C
6.0 - 15
4.0 - 10 + 125°C

2.0 - 5.0
0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 - 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10
VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

Figure 4. VGS = 10 Vdc Figure 5. VGS = − 10 Vdc

50 - 100
45 - 90
40 - 80
ID , DRAIN CURRENT (mA)

ID , DRAIN CURRENT (mA)

35 TA = - 55°C - 70
30 - 40°C - 60
TA = - 55°C
25 + 25°C - 50 - 40°C
20 + 85°C - 40 + 25°C
+ 125°C + 85°C
15 - 30
+ 125°C
10 - 20
5.0 - 10
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 0 - 2.0 - 4.0 - 6.0 - 8.0 - 10 - 12 - 14 - 16 - 18 - 20
VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

Figure 6. VGS = 15 Vdc Figure 7. VGS = − 15 Vdc

These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.

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 MC14001B Series

TYPICAL B−SERIES GATE CHARACTERISTICS (cont’d)

VOLTAGE TRANSFER CHARACTERISTICS

V out , OUTPUT VOLTAGE (Vdc)

V out , OUTPUT VOLTAGE (Vdc)

SINGLE INPUT NAND, AND SINGLE INPUT NAND, AND
5.0 MULTIPLE INPUT NOR, OR MULTIPLE INPUT NOR, OR
10

4.0 8.0
SINGLE INPUT NOR, OR SINGLE INPUT NOR, OR
3.0 MULTIPLE INPUT NAND, AND 6.0 MULTIPLE INPUT NAND, AND
2.0 4.0

1.0 2.0

0 0
0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc

16 DC NOISE MARGIN
SINGLE INPUT NAND, AND
14 MULTIPLE INPUT NOR, OR The DC noise margin is defined as the input voltage range
V out , OUTPUT VOLTAGE (Vdc)

12 from an ideal “1” or “0” input level which does not produce
SINGLE INPUT NOR, OR output state change(s). The typical and guaranteed limit
10 MULTIPLE INPUT NAND, AND values of the input values VIL and VIH for the output(s) to
8.0
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
6.0 in Figure 11.
Guaranteed minimum noise margins for both the “1” and
4.0
“0” levels =
2.0 1.0 V with a 5.0 V supply
0 2.0 V with a 10.0 V supply
0 2.0 4.0 6.0 8.0 10
2.5 V with a 15.0 V supply
Vin, INPUT VOLTAGE (Vdc)

Figure 10. VDD = 15 Vdc

Vout VDD Vout VDD

VO VO

VO VO

VDD VDD
0 Vin 0 Vin

VIL VIH VIL VIH

VSS = 0 VOLTS DC
(a) Inverting Function (b) Non−Inverting Function

Figure 11. DC Noise Immunity

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 MC14001B Series

ORDERING INFORMATION
Device Package Shipping†
MC14001BDG SOIC−14
55 Units / Rail
NLV14001BDG* (Pb−Free)

MC14001BDR2G SOIC−14
NLV14001BDR2G* (Pb−Free)
2500 Units / Tape & Reel
MC14001BDTR2G TSSOP−14
NLV14001BDTR2G* (Pb−Free)

MC14001BFELG SOEIAJ−14
2000 Units / Tape & Reel
(Pb−Free)

MC14011BDG SOIC−14
55 Units / Rail
NLV14011BDG* (Pb−Free)

MC14011BDR2G SOIC−14
NLV14011BDR2G* (Pb−Free)
2500 Units / Tape & Reel
MC14011BDTR2G TSSOP−14
NLV14011BDTR2G* (Pb−Free)

MC14011BFG SOEIAJ−14 50 Units / Rail

MC14011BFELG (Pb−Free) 2000 Units / Tape & Reel

MC14023BDG SOIC−14
55 Units / Rail
(Pb−Free)

MC14023BDR2G SOIC−14
2500 Units / Tape & Reel
NLV14023BDR2G* (Pb−Free)

MC14023BFELG SOEIAJ−14
2000 Units / Tape & Reel
(Pb−Free)

MC14025BDG SOIC−14
55 Units / Rail
NLV14025BDG* (Pb−Free)

MC14025BDR2G SOIC−14
2500 Units / Tape & Reel
NLV14025BDR2G* (Pb−Free)

MC14071BDG SOIC−14
55 Units / Rail
NLV14071BDG* (Pb−Free)

MC14071BDR2G SOIC−14
2500 Units / Tape & Reel
NLV14071BDR2G* (Pb−Free)

MC14071BDTG 96 Units per Rail

MC14071BDTR2G TSSOP−14
(Pb−Free) 2500 Units / Tape & Reel
NLV14071BDTR2G*

MC14073BDG SOIC−14
55 Units / Rail
(Pb−Free)

MC14073BDR2G SOIC−14
2500 Units / Tape & Reel
(Pb−Free)

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 MC14001B Series

ORDERING INFORMATION (continued)

Device Package Shipping†
MC14081BDG SOIC−14
55 Units / Rail
NLV14081BDG* (Pb−Free)

MC14081BDR2G SOIC−14
NLV14081BDR2G* (Pb−Free)
2500 Units / Tape & Reel
MC14081BDTR2G TSSOP−14
NLV14081BDTR2G* (Pb−Free)

MC14082BDG
SOIC−14 55 Units / Rail
NLV14082BDG*
(Pb−Free)
MC14082BDR2G 2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

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 MC14001B Series

PACKAGE DIMENSIONS

TSSOP−14
CASE 948G
ISSUE B

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE
−U− N DAMBAR PROTRUSION. ALLOWABLE
PIN 1 DAMBAR PROTRUSION SHALL BE 0.08
IDENT. F (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
0.15 (0.006) T U S
A K DETERMINED AT DATUM PLANE −W−.

ÉÉÉ
ÇÇÇ
−V− K1 MILLIMETERS INCHES
DIM MIN MAX MIN MAX

ÇÇÇ
ÉÉÉ
A 4.90 5.10 0.193 0.200
J J1 B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
SECTION N−N F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
C −W−
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
0.10 (0.004) K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
−T− SEATING D G H DETAIL E M 0_ 8_ 0_ 8_
PLANE

SOLDERING FOOTPRINT*

7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 MC14001B Series

PACKAGE DIMENSIONS

SOIC−14 NB
CASE 751A−03
ISSUE K
D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
b DIM MIN MAX MIN MAX
0.25 M B M 13X
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
A h D 8.55 8.75 0.337 0.344
X 45 _ E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
M L 0.40 1.25 0.016 0.049
e A1
SEATING M 0_ 7_ 0_ 7_
C PLANE

SOLDERING FOOTPRINT*
6.50 14X
1.18
1

1.27
PITCH

14X
0.58

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
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