A B C D E

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1 1

Compal Confidential
2
EA50_KV M/B Schematics Document 2

AMD Kaveri(FP3) + Bolton(M3)

AMD OPAL / JET

3 3

2013-02-11
REV : 0.3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 1 of 52
A B C D E
 A B C D E

Compal Confidential
Model Name : Z5WAK
www.qdzbwx.com
VRAM 1G/2G Memory BUS
1

64M16/128M16 x 8 (DDR3/DDR3L) 204pin DDRIII-SO-DIMM X2

1

page 23, 24 Dual Channel BANK 0, 1, 2, 3 Page 11,12

DDR3 AMD Kaveri 1.5V DDR3/DDR3L

fequence support :800~2133MHz

AMD JET/OPAL PCIe x 8 Gen3

128Bit DDR3
uFCBGA-962 AMD FP3 APU
DP2
Page 13~19 APU HDMI
(UMA / Muxless) Kaveri
DP1 USB3.0 USB30
Package Port 0
HDMI Conn. M/B*1
page 27
page 36
DP0 Page 5~10
2 2
P_GPP x 3 DP x 4
eDP Panel UMA eDP GEN2 (DP1 TXP/N 0~4) UMI
ML for FCH VGA
page 25

CRT Conn. CMOS Touch Mini TP

USB20 Camera screen
page 26
Sub/B*2
Card 1 Bridge
USB3.0 page 25 page 25 page 28 page 29
FCH CRT (VGA DAC) page 36
FCH USB2.0 Port 0
USB2.0
Port10 Port 2 Port 3 Port 4 Port 5
3.3V 48MHz Port 1
GPP0 GPP1 BOLTON - M3
HD Audio 3.3V 24.576MHz/48Mhz
uFCBGA-656
3
LAN(GbE) MINI Card 1 SATA Gen3 3

Realtek (Wireless LAN) Page 20~24

page 29 page 28
RTL8411B port 0 port 1
LPC BUS
LED SATA HDD SATA ODD HDA Codec
page 32 Conn. page 33
Conn. page 33
ALC283
page 34
RTC CKT. RJ45 Conn SD/MMC 2 IN 1
page 30 ENE
page 13
Card Reader
page 30 KB9012/KB9022
page 35

Power On/Off CKT.

page 32
Touch Pad Int.KBD D-MIC Speaker
page 36 page 34 page 34
page 31
Fan Control
page 31
4
Sub board 4

DC/DC LID SW - Power/B

page 32
Interface CKT.page 37
BIOS ROM Security Classification Compal Secret Data Compal Electronics, Inc.
2012/09/12 2015/07/08 Title
USB20/B Issued Date Deciphered Date
Block Diagrams
Power Circuit -USB20 x2 SYS BIOS (8M) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
page 38~52 page 36 page 14 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
Z5WAK M/B LA-B221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

I'm from VIETNAM sualaptop365

Date: Wednesday, February 12, 2014 Sheet 2 of 52
A B C D E
 A B C D E

ZZZ
Voltage Rails
SIGNAL
Power Plane Description S0 S3 S4 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
PCB PCB@
DA60014Q000
VIN Adapter power supply (19V) ON ON ON ON Full ON HIGH HIGH HIGH HIGH ON ON ON ON LA-B221P REV0

B+ AC or battery power rail for power circuit. ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for APU ON OFF OFF OFF

1
+CPU_CORE_NB Voltage for VDDNB ON OFF OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 1

+VGA_CORE 0.95-1.2V switched power rail DIS OFF OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VDDCI 0.95-1.2V switched power rail DIS OFF OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+0.95VSDGPU 1.0V switched power rail for VGA DIS OFF OFF OFF
+1.1VALW 1.1V switched power rail for FCH ON ON AC/DC AC/DC
+1.1VS 1.1V switched power rail for FCH ON OFF OFF OFF
+1.05VS 1.05VS switched power rail for APU ON OFF OFF OFF Board ID / SKU ID Table for AD channel BOARD ID Table
+1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF OFF Board ID PCB Revision
+1.5VS 1.5VS switched power rail ON OFF OFF OFF 0 EVT
+1.5VSDGPU 1.5V switched power rail for VGA DIS OFF OFF OFF 1 DVT
+1.8VSDGPU 1.8V switched power rail for VGA DIS OFF OFF OFF 2
+1.8VS 1.8VS for CPU_VDDA ON OFF OFF OFF 3
+3VALW 3.3V always on power rail ON ON ON ON 4
+3V_LAN 3.3V power rail for LAN ON ON WOL WOL 5
+3VS_WLAN 3.3V power rail for WLAN ON IOAC IOAC OFF 6
2
+3VS 3.3V switched power rail ON OFF OFF OFF 7 2

+5VALW 5V always on power rail ON ON ON ON

+5VS 5V switched power rail ON OFF OFF OFF
BOM Option Table
+RTCVCC RTC power ON ON ON ON BOM
Structure Description

9022@ Use EC 9022

9012@ Use EC 9012
EC SM Bus1 address EC SM Bus2 address UMA@ Display output from APU (UMA only)
VGA@ Use VGA (PX or DIS only)
Device Address HEX Device Address HEX
AL@ Use Auto load EC code function
Smart Battery 0001 011X 16H SB-TSI (APU) 1001 100X 96H
AC@ Support AC Function
VGA Internal Thermal
NOAC@ No Support AC Function
TPM@ Support D TPM function
CONN@ Connector (Control by ME)
HDT@ Debug Connector
EMC@ EMC Component
3
FCH FCH XEMC@ Reservec for EMC 3

SM Bus 0 address SM Bus 1 address TPSM@ Use APU SMBus for T/P
TPBRI@ Use USB to I2C IC for T/P
Device Address HEX Device Address HEX
USBTP@ Use USB T/P
DDR DIMM1 1010 000Xb A0H
MOS@ Use MOSART soluation USB to I2C TP
DDR DIMM2 1010 001Xb A2H
X76@ VRAM ID Table (Load By X76J)
MINI CARD
128@ VRAM x 8pcs
OPAL@ ATI OPAL VGA CONTROLLER
JET@ ATI JET VGA CONTROLLER
BL@ BACK LIGHT CIRCUIT
@ Unpop
X76@ VRAM type select

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 3 of 52
A B C D E
 5 4 3 2 1

BATTERY BATT+ PU301 PU801 +CPU_CORE

www.qdzbwx.com AMD APU FP3
+APU_CORE 0.8~1.15V VDD CORE 38A
11.1V CHARGER RT8880AGQW +CPU_CORE_NB
BQ24725ARGRR +APU_CORE_NB 0.8~1.15V VDDNB 40A
PU702 +1.8VS +1.8VS VDDA 0.7A
SY8032ABC +1.5V +1.5V VDDIO 2.5A
PU601 +1.05VS
AC ADAPTOR VIN +1.05VS +1.05VS VDDR 4.9A VDDP 4.1A
D SY8208DQNC D
19V 65W/40W

RAM DDR3L SODIMMX2

+1.5V +1.5V +1.5V
PU501 +1.5V VDD_MEM 5.6A
+0.75VS
RT8207MZQW +0.75VS VTT_MEM 2A
B+ +0.75VS

VGA ATI

+3VALW
+VGA_CORE Opal/Jet
PU1201 +VGA_CORE
ISL62883CHRTZ-T 0.775V~
1.125V VDDC + VDDCI =28A

PU1101
+0.95VSG DP_VCCC: 280 mA
+1.5VSG SY8033BDBC
PU1001 SPLL_VDDC: 100 mA
TPS51212DSCR +0.95VSG BIF_VDDC: 800 mA
PCIE_VDDC: 1000 mA

+3VALW
+1.5VSG VRAM X8pcs DDR3
+1.5VSG VDDR1: 1500 mA
PU701 +1.1VALW
SY8208DQNC VDD_CT: 13mA +1.5VSG 3.2 A
DP_VDDR: 237mA
SPLL_PVDD: 75mA
C MPLL_PVDD: 160mA C
PCIE_PVDD: 100mA
TSVDD: 13mA
PU401 +3VALW
VDDR4: 30mA
PU402 U11 +1.8VSG AVDD: 70mA
SY8208BQNC +5VALW
TPS22966DPUR U16 +1.8VSG VDD1DI: 117mA
TPS22966DPUR
+3VSG
+3VSG VDDR: 25mA

+3VS
+INVPWR_B+

+LCDVDD

LCD panel
FCH AMD Bolton M3
U8
15.6"
G5243T11U VDDAN_11_PCIE: 1.088A
VDDAN_11_SATA: 1.337A
B+ 500mA U15 VDDAN_11_CLK: 0.34A
+1.1VS +1.1VS
+3.3 1500mA TPS22966DPUR VDDCR_11: 1.007A

+5VS +5VS
+3VS

VDDCR_11_S_[2:1] : 187mA
FAN Control VDDPL_11_SYS_S: 70mA
+1.1VALW
B
U31 VDDAN_11_USB_S_[2:1]: 140mA B
+1.1VALW
AP2113AMTR VDDCR_11_USB_S_[2:1]: 42mA
VDDAN_11_SSUSB_S_[5:1]: 282mA
VDDCR_11_SSUSB_S_[4:1]: 424mA
+5VS 500mA U29
SY6288D10CAC
+5VALW VDDIO_33_PCIGP: 102 mA
(U66 colay VDDPL_33_PCIE: 47 mA
+USB_VCCA SY6288C20A) VDDPL_33_SATA: 12 mA
+3VS VDDAN_33_DAC: 30 mA
+3VS +3VS VDDPL_33_SYS: 47 mA

USB 3.0

+5V 2.0A
+3VALW VDDIO_33_S_[8:1]: 59 mA
+3VALW VDDXL_33_S: 5 mA
+3VALW VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S_[12:1]: 470 mA
VDDPL_33_SSUSB_S: 11 mA
SATA Audio Codec EC LAN +Cardreader VDDAN_33_HWM_S: 12 mA
HDD*1 ALC283-CG ENE KB9012/9022 RTL8411B-CG Mini Card
ODD*1 +1.5VS
+1.5VS VDDIO_AZ_S: 26mA
+5V 2.8A +5V 1500mA +3.3VALW 30mA +3.3VALW 1.4A +1.5VS 500mA
+3.3VS 594mA +3.3VS 3mA +3.3VS 1A
+3.3V +1.5VS 16mA OR
+3.3VALW 1A RTC RTC BAT VDDBT_RTC_G
Bettary
A A
+1.5VS

Security Classification Compal Secret Data

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title
POWER DELIVERY CHART
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Z5WAK LA-B221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
I'm from VIETNAM
5 sualaptop365
4 3 2
Date: Wednesday, February 12, 2014
1
Sheet 4 of 52
 5 4 3 2 1

PEG_GTX_C_HRX_P[7..0] PEG_HTX_C_GRX_P[7..0]
13 PEG_GTX_C_HRX_P[7..0] PEG_HTX_C_GRX_P[7..0] 13
PEG_GTX_C_HRX_N[7..0] PEG_HTX_C_GRX_N[7..0]
13 PEG_GTX_C_HRX_N[7..0] PEG_HTX_C_GRX_N[7..0] 13

U65A
PCI EXPRESS
D D
PEG_GTX_C_HRX_P0 Y8 AB2 PEG_HTX_GRX_P0 C153 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P0
P_GFX_RXP0/RSVD P_GFX_TXP0/DP6_TXP4
PEG_GTX_C_HRX_N0 Y9 AB1 PEG_HTX_GRX_N0 C164 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N0
P_GFX_RXN0/RSVD P_GFX_TXN0/DP6_TXN4
PEG_GTX_C_HRX_P1 Y4 P_GFX_RXP1/RSVD P_GFX_TXP1/DP6_TXP5
AB3 PEG_HTX_GRX_P1 C154 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P1
PEG_GTX_C_HRX_N1 W5 AA2 PEG_HTX_GRX_N1 C151 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N1
P_GFX_RXN1/RSVD P_GFX_TXN1/DP6_TXN5
PEG_GTX_C_HRX_P2 W7 P_GFX_RXP2/RSVD P_GFX_TXP2/DP6_TXP6
AA1 PEG_HTX_GRX_P2 C155 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P2
PEG_GTX_C_HRX_N2 W8 Y1 PEG_HTX_GRX_N2 C152 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N2
P_GFX_RXN2/RSVD P_GFX_TXN2/DP6_TXN6
PEG_GTX_C_HRX_P3 U5 Y2 PEG_HTX_GRX_P3 C157 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P3
P_GFX_RXP3/RSVD P_GFX_TXP3/RSVD
PEG_GTX_C_HRX_N3 V4 P_GFX_RXN3/RSVD P_GFX_TXN3/RSVD
W2 PEG_HTX_GRX_N3 C156 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N3
PEG_GTX_C_HRX_P4 U7 V2 PEG_HTX_GRX_P4 C166 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P4
P_GFX_RXP4/RSVD P_GFX_TXP4/DP6_TXP0
PEG_GTX_C_HRX_N4 U8 V1 PEG_HTX_GRX_N4 C167 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N4
P_GFX_RXN4/RSVD P_GFX_TXN4/DP6_TXN0
PEG_GTX_C_HRX_P5 T4 V3 PEG_HTX_GRX_P5 C168 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P5
P_GFX_RXP5/RSVD P_GFX_TXP5/DP6_TXP1
PEG_GTX_C_HRX_N5 R5 U2 PEG_HTX_GRX_N5 C169 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N5

GRAPHICS
P_GFX_RXN5/RSVD P_GFX_TXN5/DP6_TXN1
PEG_GTX_C_HRX_P6 R7 P_GFX_RXP6/RSVD P_GFX_TXP6/DP6_TXP2
U1 PEG_HTX_GRX_P6 C170 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P6
PEG_GTX_C_HRX_N6 R8 T1 PEG_HTX_GRX_N6 C171 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N6
P_GFX_RXN6/RSVD P_GFX_TXN6/DP6_TXN2
PEG_GTX_C_HRX_P7 P8 P_GFX_RXP7/RSVD P_GFX_TXP7/DP6_TXP3
T2 PEG_HTX_GRX_P7 C172 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P7
PEG_GTX_C_HRX_N7 P7 R2 PEG_HTX_GRX_N7 C173 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N7
P_GFX_RXN7/RSVD P_GFX_TXN7/DP6_TXN3
P4 P2
P_GFX_RXP8/RSVD P_GFX_TXP8/DP5_TXP0
P5 P1
P_GFX_RXN8/RSVD P_GFX_TXN8/DP5_TXN0
M8 P3
P_GFX_RXP9/RSVD P_GFX_TXP9/DP5_TXP1
M7 N2
P_GFX_RXN9/RSVD P_GFX_TXN9/DP5_TXN1
M5 N1
P_GFX_RXP10/RSVD P_GFX_TXP10/DP5_TXP2
M4 M1
P_GFX_RXN10/RSVD P_GFX_TXN10/DP5_TXN2
L6 M2
P_GFX_RXP11/RSVD P_GFX_TXP11/DP5_TXP3
L5 L2
P_GFX_RXN11/RSVD P_GFX_TXN11/DP5_TXN3
L8 K2
P_GFX_RXP12/RSVD P_GFX_TXP12/DP4_TXP0
L9 K1
P_GFX_RXN12/RSVD P_GFX_TXN12/DP4_TXN0
J5 K3
P_GFX_RXP13/RSVD P_GFX_TXP13/DP4_TXP1
K4 J2
P_GFX_RXN13/RSVD P_GFX_TXN13/DP4_TXN1
J7 J1
P_GFX_RXP14/RSVD P_GFX_TXP14/DP4_TXP2
J8 H1
P_GFX_RXN14/RSVD P_GFX_TXN14/DP4_TXN2
H4 H2
C P_GFX_RXP15/RSVD P_GFX_TXP15/DP4_TXP3 C
H5 G2
P_GFX_RXN15/RSVD P_GFX_TXN15/DP4_TXN3
AH4 AM2 PCIE_PTX_DRX_P0 C17 1 2 0.1U_0402_16V7K
29 PCIE_PRX_DTX_P0 P_GPP_RXP0 P_GPP_TXP0 PCIE_PTX_C_DRX_P0 29
AH3 AM1 PCIE_PTX_DRX_N0 C18 1 2 0.1U_0402_16V7K LAN
29 PCIE_PRX_DTX_N0 P_GPP_RXN0 P_GPP_TXN0 PCIE_PTX_C_DRX_N0 29
AG7 AL2 PCIE_PTX_DRX_P1 C19 1 2 0.1U_0402_16V7K
28 PCIE_PRX_DTX_P1 P_GPP_RXP1 P_GPP_TXP1 PCIE_PTX_C_DRX_P1 28
AF6 AL1 PCIE_PTX_DRX_N1 C20 1 2 0.1U_0402_16V7K WLAN
28 PCIE_PRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_PTX_C_DRX_N1 28
AE8 AK2
P_GPP_RXP2 P_GPP_TXP2

GPP
AE7 AK1
P_GPP_RXN2 P_GPP_TXN2
AE5 AK3
P_GPP_RXP3 P_GPP_TXP3
AF4 AJ2
P_GPP_RXN3 P_GPP_TXN3
AC9 AJ1
P_GPP_RXP4/RSVD P_GPP_TXP4/DP3_TXP0
AC8 AH1
P_GPP_RXN4/RSVD P_GPP_TXN4/DP3_TXN0
AC6 AH2
P_GPP_RXP5/RSVD P_GPP_TXP5/DP3_TXP1
AC5 AG2
P_GPP_RXN5/RSVD P_GPP_TXN5/DP3_TXN1
AB9 AF2
P_GPP_RXP6/RSVD P_GPP_TXP6/DP3_TXP2
AB8 AF1
P_GPP_RXN6/RSVD P_GPP_TXN6/DP3_TXN2
AB4 AF3
P_GPP_RXP7/RSVD P_GPP_TXP7/DP3_TXP3
AB5 AE2
P_GPP_RXN7/RSVD P_GPP_TXN7/DP3_TXN3
AJ7 AM9 UMI_ATX_FRX_P0 C21 1 2 0.1U_0402_16V7K
20 UMI_FTX_C_ARX_P0 P_UMI_RXP0 P_UMI_TXP0 UMI_ATX_C_FRX_P0 20
AJ8 AM10 UMI_ATX_FRX_N0 C22 1 2 0.1U_0402_16V7K
20 UMI_FTX_C_ARX_N0 P_UMI_RXN0 P_UMI_TXN0 UMI_ATX_C_FRX_N0 20
AK6 AN8 UMI_ATX_FRX_P1 C23 1 2 0.1U_0402_16V7K
20 UMI_FTX_C_ARX_P1 P_UMI_RXP1 P_UMI_TXP1 UMI_ATX_C_FRX_P1 20
AK7 AN9 UMI_ATX_FRX_N1 C24 1 2 0.1U_0402_16V7K
20 UMI_FTX_C_ARX_N1 P_UMI_RXN1 P_UMI_TXN1 UMI_ATX_C_FRX_N1 20
AK5 AM7 UMI_ATX_FRX_P2 1 2

UMI
P_UMI_RXP2 P_UMI_TXP2 C25 0.1U_0402_16V7K
20 UMI_FTX_C_ARX_P2 AJ5 AM8 UMI_ATX_FRX_N2 1 2 UMI_ATX_C_FRX_P2 20
P_UMI_RXN2 P_UMI_TXN2 C26 0.1U_0402_16V7K
20 UMI_FTX_C_ARX_N2 AL4 AN6 UMI_ATX_FRX_P3 1 2 UMI_ATX_C_FRX_N2 20
P_UMI_RXP3 P_UMI_TXP3 C27 0.1U_0402_16V7K
20 UMI_FTX_C_ARX_P3 AK4 AM6 UMI_ATX_FRX_N3 1 2 UMI_ATX_C_FRX_P3 20
P_UMI_RXN3 P_UMI_TXN3 C28 0.1U_0402_16V7K
20 UMI_FTX_C_ARX_N3 UMI_ATX_C_FRX_N3 20
1 2 P_ZVDDP AN18 P_ZVDDP AM18 P_ZVSS 1 2
+1.05VS P_ZVSS
CR V1.03 R1 196_0402_1% FP3 REV 0.52 R34 196_0402_1%
8/12 mils CR V1.03
B PH to VDDIO_RUN with 196 ohm 8/12 mils B
@ KAVERI-FP3-2.7G_BGA854
PH to VDDIO_RUN with 196 ohm

U65 A10@ U65 A8@ U65 2367@ U65 4467@

A A

SA00007S300 SA00007S200 SA00007D100 SA00007D000

A10-7300_854P_19W A8-7100_854P_19W KAVERI_1.8G BGA 854P KAVERI_1.8G BGA 854P
Change to PC sample PN
02/11
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/12 Deciphered Date 2012/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP3 PCIE/UMI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 5 of 52
5 4 3 2 1
 5 4 3 2 1

www.qdzbwx.com
U65B U65C
11 DDRA_SMA[15..0] DDRA_SMA0 AB31
MEMORY CHANNEL A
H13DDRA_SDQ0 DDRA_SDQ[63..0] 11 12 DDRB_SMA[15..0] DDRB_SMA0 AC36
MEMORY CHANNEL B
C18 DDRB_SDQ0 DDRB_SDQ[63..0] 12
MA_ADD0 MA_DATA0 MB_ADD0 MB_DATA0
DDRA_SMA1 U33 MA_ADD1 MA_DATA1
F13 DDRA_SDQ1 DDRB_SMA1 U36
MB_ADD1 MB_DATA1
B19 DDRB_SDQ1
DDRA_SMA2 U32 MA_ADD2 MA_DATA2
H16DDRA_SDQ2 DDRB_SMA2 U37
MB_ADD2 MB_DATA2
C22 DDRB_SDQ2
DDRA_SMA3 R30 F16 DDRA_SDQ3 DDRB_SMA3 T35 A22 DDRB_SDQ3
MA_ADD3 MA_DATA3 MB_ADD3 MB_DATA3
DDRA_SMA4 T34 G11DDRA_SDQ4 DDRB_SMA4 T37 A18 DDRB_SDQ4
MA_ADD4 MA_DATA4 MB_ADD4 MB_DATA4
DDRA_SMA5 R31 E11DDRA_SDQ5 DDRB_SMA5 T36 B18 DDRB_SDQ5
MA_ADD5 MA_DATA5 MB_ADD5 MB_DATA5
DDRA_SMA6 R33 MA_ADD6 MA_DATA6
E14DDRA_SDQ6 DDRB_SMA6 R36
MB_ADD6 MB_DATA6
A21 DDRB_SDQ6
D DDRA_SMA7 P33 J14 DDRA_SDQ7 DDRB_SMA7 P37 B21 DDRB_SDQ7 D
MA_ADD7 MA_DATA7 MB_ADD7 MB_DATA7
DDRA_SMA8 P32 DDRB_SMA8 P36
MA_ADD8 MB_ADD8
DDRA_SMA9 P30 J17 DDRA_SDQ8 DDRB_SMA9 N36 B24 DDRB_SDQ8
MA_ADD9 MA_DATA8 MB_ADD9 MB_DATA8
DDRA_SMA10AD34 MA_ADD10 MA_DATA9
F17 DDRA_SDQ9 DDRB_SMA10 AD36 MB_ADD10 MB_DATA9
A24 DDRB_SDQ9
DDRA_SMA11 P34 H21DDRA_SDQ10 DDRB_SMA11 P35 B27 DDRB_SDQ10
MA_ADD11 MA_DATA10 MB_ADD11 MB_DATA10
DDRA_SMA12 M30 MA_ADD12 MA_DATA11
E21DDRA_SDQ11 DDRB_SMA12 N37
MB_ADD12 MB_DATA11
A28 DDRB_SDQ11
DDRA_SMA13AF33 E16DDRA_SDQ12 DDRB_SMA13 AH37 B22 DDRB_SDQ12
MA_ADD13 MA_DATA12 MB_ADD13 MB_DATA12
DDRA_SMA14 M31 G17DDRA_SDQ13 DDRB_SMA14 M36 B23 DDRB_SDQ13
MA_ADD14 MA_DATA13 MB_ADD14 MB_DATA13
DDRA_SMA15 L32 MA_ADD15 MA_DATA14
F19 DDRA_SDQ14 DDRB_SMA15 L36
MB_ADD15 MB_DATA14
B26 DDRB_SDQ14
D20DDRA_SDQ15 C26 DDRB_SDQ15
MA_DATA15 MB_DATA15
DDRA_SBS0#AC33 DDRB_SBS0# AD35
11 DDRA_SBS0# MA_BANK0 12 DDRB_SBS0# MB_BANK0
DDRA_SBS1#AB30 D22DDRA_SDQ16 DDRB_SBS1# AD37 A29 DDRB_SDQ16
11 DDRA_SBS1# MA_BANK1 MA_DATA16 12 DDRB_SBS1# MB_BANK1 MB_DATA16
DDRA_SBS2# M34 E22DDRA_SDQ17 DDRB_SBS2# M37 B29 DDRB_SDQ17
11 DDRA_SBS2# MA_BANK2 MA_DATA17 12 DDRB_SBS2# MB_BANK2 MB_DATA17
D26DDRA_SDQ18 B32 DDRB_SDQ18
11 DDRA_SDM[0..7] MA_DATA18 12 DDRB_SDM[0..7] MB_DATA18
DDRA_SDM0 E13 E25DDRA_SDQ19 DDRB_SDM0 A20 C32 DDRB_SDQ19
MA_DM0 MA_DATA19 MB_DM0 MB_DATA19
DDRA_SDM1 D18 MA_DM1 MA_DATA20
G21DDRA_SDQ20 DDRB_SDM1 C24
MB_DM1 MB_DATA20
B28 DDRB_SDQ20
DDRA_SDM2 H22 F22 DDRA_SDQ21 DDRB_SDM2 A30 C28 DDRB_SDQ21
MA_DM2 MA_DATA21 MB_DM2 MB_DATA21
DDRA_SDM3 H27 G24DDRA_SDQ22 DDRB_SDM3 B35 B31 DDRB_SDQ22
MA_DM3 MA_DATA22 MB_DM3 MB_DATA22
DDRA_SDM4 AG30 MA_DM4 MA_DATA23
H24DDRA_SDQ23 DDRB_SDM4 AL35
MB_DM4 MB_DATA23
A32 DDRB_SDQ23
DDRA_SDM5 AK26 MA_DM5 DDRB_SDM5 AN32
MB_DM5
DDRA_SDM6 AK20 MA_DM6 MA_DATA24
E27DDRA_SDQ24 DDRB_SDM6 AN26
MB_DM6 MB_DATA24
C34 DDRB_SDQ24
DDRA_SDM7 AF14 G27DDRA_SDQ25 DDRB_SDM7 AN21 A34 DDRB_SDQ25
MA_DM7 MA_DATA25 MB_DM7 MB_DATA25
F34 E30DDRA_SDQ26 E37 C36 DDRB_SDQ26
MA_DM8 MA_DATA26 MB_DM8 MB_DATA26
G30DDRA_SDQ27 C37 DDRB_SDQ27
MA_DATA27 MB_DATA27
DDRA_SDQS0 F14 F25 DDRA_SDQ28 DDRB_SDQS0 C20 A33 DDRB_SDQ28
11 DDRA_SDQS0 MA_DQS_H0 MA_DATA28 12 DDRB_SDQS0 MB_DQS_H0 MB_DATA28
DDRA_SDQS0#G14 MA_DQS_L0 MA_DATA29
H25DDRA_SDQ29 DDRB_SDQS0# B20 MB_DQS_L0 MB_DATA29
B33 DDRB_SDQ29
11 DDRA_SDQS0# DDRA_SDQS1 H19 D30DDRA_SDQ30 12 DDRB_SDQS0# DDRB_SDQS1 B25 D35 DDRB_SDQ30
11 DDRA_SDQS1 MA_DQS_H1 MA_DATA30 12 DDRB_SDQS1 MB_DQS_H1 MB_DATA30
DDRA_SDQS1#J19 H28DDRA_SDQ31 DDRB_SDQS1# A25 B37 DDRB_SDQ31
11 DDRA_SDQS1# MA_DQS_L1 MA_DATA31 12 DDRB_SDQS1# MB_DQS_L1 MB_DATA31
DDRA_SDQS2 D24 MA_DQS_H2 DDRB_SDQS2 C30 MB_DQS_H2
11 DDRA_SDQS2 12 DDRB_SDQS2
DDRA_SDQS2#E24 MA_DQS_L2 MA_DATA32
AJ31DDRA_SDQ32 DDRB_SDQS2# B30 MB_DQS_L2 MB_DATA32
AL36DDRB_SDQ32
11 DDRA_SDQS2# DDRA_SDQS3 F28 AK32DDRA_SDQ33 12 DDRB_SDQS2# DDRB_SDQS3 B36 AM37DDRB_SDQ33
11 DDRA_SDQS3 MA_DQS_H3 MA_DATA33 12 DDRB_SDQS3 MB_DQS_H3 MB_DATA33
DDRA_SDQS3#E28 AK28DDRA_SDQ34 DDRB_SDQS3# A36 AN34DDRB_SDQ34
C 11 DDRA_SDQS3# MA_DQS_L3 MA_DATA34 12 DDRB_SDQS3# MB_DQS_L3 MB_DATA34 C
DDRA_SDQS4AJ30 AF27DDRA_SDQ35 DDRB_SDQS4 AN36 AM34DDRB_SDQ35
11 DDRA_SDQS4 MA_DQS_H4 MA_DATA35 12 DDRB_SDQS4 MB_DQS_H4 MB_DATA35
AK30
DDRA_SDQS4# AJ33DDRA_SDQ36 DDRB_SDQS4# AM36 AK37DDRB_SDQ36
11 DDRA_SDQS4# MA_DQS_L4 MA_DATA36 12 DDRB_SDQS4# MB_DQS_L4 MB_DATA36
DDRA_SDQS5AH24 MA_DQS_H5 MA_DATA37
AK33DDRA_SDQ37 DDRB_SDQS5 AN31 MB_DQS_H5 MB_DATA37
AK36DDRB_SDQ37
11 DDRA_SDQS5 AG24
DDRA_SDQS5# AH28DDRA_SDQ38 12 DDRB_SDQS5 DDRB_SDQS5# AM31 AN35DDRB_SDQ38
11 DDRA_SDQS5# MA_DQS_L5 MA_DATA38 12 DDRB_SDQS5# MB_DQS_L5 MB_DATA38
DDRA_SDQS6AG19 AJ28DDRA_SDQ39 DDRB_SDQS6 AM25 AL34DDRB_SDQ39
11 DDRA_SDQS6 MA_DQS_H6 MA_DATA39 12 DDRB_SDQS6 MB_DQS_H6 MB_DATA39
AF19
DDRA_SDQS6# DDRB_SDQS6# AL26
11 DDRA_SDQS6# MA_DQS_L6 12 DDRB_SDQS6# MB_DQS_L6
DDRA_SDQS7AH14 MA_DQS_H7 MA_DATA40
AF25DDRA_SDQ40 DDRB_SDQS7 AM20 MB_DQS_H7 MB_DATA40
AL32DDRB_SDQ40
11 DDRA_SDQS7 AJ14 AH25 12 DDRB_SDQS7
DDRA_SDQS7# MA_DQS_L7 MA_DATA41 DDRA_SDQ41 DDRB_SDQS7# AL20 MB_DQS_L7 MB_DATA41
AM32DDRB_SDQ41
11 DDRA_SDQS7# G31 AG22DDRA_SDQ42 12 DDRB_SDQS7# F37 AN29DDRB_SDQ42
MA_DQS_H8 MA_DATA42 MB_DQS_H8 MB_DATA42
F31 AJ22DDRA_SDQ43 F36 AL28DDRB_SDQ43
MA_DQS_L8 MA_DATA43 MB_DQS_L8 MB_DATA43
AH27DDRA_SDQ44 AM33DDRB_SDQ44
MA_DATA44 MB_DATA44
DDRA_CLK0 Y30 AJ27DDRA_SDQ45 DDRB_CLK0 AA37 AN33DDRB_SDQ45
11 DDRA_CLK0 MA_CLK_H0 MA_DATA45 12 DDRB_CLK0 MB_CLK_H0 MB_DATA45
DDRA_CLK0# Y29 AE24DDRA_SDQ46 DDRB_CLK0# AA36 AM30DDRB_SDQ46
11 DDRA_CLK0# MA_CLK_L0 MA_DATA46 12 DDRB_CLK0# MB_CLK_L0 MB_DATA46
DDRA_CLK1 Y32 AF22DDRA_SDQ47 DDRB_CLK1 Y37 AM29DDRB_SDQ47
11 DDRA_CLK1 MA_CLK_H1 MA_DATA47 12 DDRB_CLK1 MB_CLK_H1 MB_DATA47
DDRA_CLK1# Y33 DDRB_CLK1# Y36
11 DDRA_CLK1# MA_CLK_L1 12 DDRB_CLK1# MB_CLK_L1
W33 AH21DDRA_SDQ48 Y34 AM27DDRB_SDQ48
MA_CLK_H2 MA_DATA48 MB_CLK_H2 MB_DATA48
W34 AJ21DDRA_SDQ49 Y35 AM26DDRB_SDQ49
MA_CLK_L2 MA_DATA49 MB_CLK_L2 MB_DATA49
W30 AF17DDRA_SDQ50 V35 AN24DDRB_SDQ50
MA_CLK_H3 MA_DATA50 MB_CLK_H3 MB_DATA50
W31 AJ17DDRA_SDQ51 W36 AM24DDRB_SDQ51
MA_CLK_L3 MA_DATA51 MB_CLK_L3 MB_DATA51
AK22DDRA_SDQ52 AN28DDRB_SDQ52
MA_DATA52 MB_DATA52
DDRA_CKE0 L33 AF21DDRA_SDQ53 DDRB_CKE0 K36 AM28DDRB_SDQ53
11 DDRA_CKE0 MA_CKE0 MA_DATA53 12 DDRB_CKE0 MB_CKE0 MB_DATA53
DDRA_CKE1 L30 AJ19DDRA_SDQ54 DDRB_CKE1 K37 AN25DDRB_SDQ54
11 DDRA_CKE1 MA_CKE1 MA_DATA54 12 DDRB_CKE1 MB_CKE1 MB_DATA54
K34 AE17DDRA_SDQ55 K35 AL24DDRB_SDQ55
MA_CKE2 MA_DATA55 MB_CKE2 MB_DATA55
J30 J37
MA_CKE3 MB_CKE3
AF16DDRA_SDQ56 AN22DDRB_SDQ56
MA_DATA56 MB_DATA56
DDRA_ODT0 AH34 AJ16DDRA_SDQ57 DDRB_ODT0 AH36 AL22DDRB_SDQ57
11 DDRA_ODT0 MA0_ODT0 MA_DATA57 12 DDRB_ODT0 MB0_ODT0 MB_DATA57
DDRA_ODT1 AH33 AF13DDRA_SDQ58 DDRB_ODT1 AJ37 AK18DDRB_SDQ58
11 DDRA_ODT1 MA0_ODT1 MA_DATA58 12 DDRB_ODT1 MB0_ODT1 MB_DATA58
AE30 AE13DDRA_SDQ59 AF35 AL18DDRB_SDQ59
MA1_ODT0 MA_DATA59 MB1_ODT0 MB_DATA59
AJ34 AH17DDRA_SDQ60 AK35 AM23DDRB_SDQ60
MA1_ODT1 MA_DATA60 MB1_ODT1 MB_DATA60
AE16DDRA_SDQ61 AM22DDRB_SDQ61
MA_DATA61 MB_DATA61
DDRA_SCS0#AE31 AJ13DDRA_SDQ62 DDRB_SCS0# AF36 AN20DDRB_SDQ62
11 DDRA_SCS0# MA0_CS_L0 MA_DATA62 12 DDRB_SCS0# MB0_CS_L0 MB_DATA62
DDRA_SCS1#AG31 AG13DDRA_SDQ63 DDRB_SCS1# AJ36 AM19DDRB_SDQ63
B 11 DDRA_SCS1# MA0_CS_L1 MA_DATA63 12 DDRB_SCS1# MB0_CS_L1 MB_DATA63 B
AC30 AE36
MA1_CS_L0 MB1_CS_L0
AF32 E33 AH35 E36
MA1_CS_L1 MA_CHECK0 MB1_CS_L1 MB_CHECK0
F33 F35
MA_CHECK1 MB_CHECK1
DDRA_SRAS#AC32 H31 DDRB_SRAS# AE37 H36
11 DDRA_SRAS# MA_RAS_L MA_CHECK2 12 DDRB_SRAS# MB_RAS_L MB_CHECK2
DDRA_SCAS#AF34 J31 DDRB_SCAS# AG36 H37
11 DDRA_SCAS# MA_CAS_L MA_CHECK3 12 DDRB_SCAS# MB_CAS_L MB_CHECK3
DDRA_SWE# AE33 D32 DDRB_SWE# AF37 D36
11 DDRA_SWE# MA_WE_L MA_CHECK4 12 DDRB_SWE# MB_WE_L MB_CHECK4
D34 D37
MA_CHECK5 MB_CHECK5
MEM_MA_RST# J33 H33 MEM_MB_RST# J36 G36
11 MEM_MA_RST# MA_RESET_L MA_CHECK6 12 MEM_MB_RST# MB_RESET_L MB_CHECK6
AB33
MEM_MA_EVENT# H34 AB36
MEM_MB_EVENT# H35
11 MEM_MA_EVENT# MA_EVENT_L MA_CHECK7 12 MEM_MB_EVENT# MB_EVENT_L MB_CHECK7
V36
M_VREF
H11 E19 B17 A26
MA_VREFDQ RSVD_5 MB_VREFDQ RSVD_11
U30 D28 V37 B34
+MEM_VREF MA_ZVDDIO RSVD_6 MB_ZVDDIO RSVD_12
AK24 AL30
15mil M33
RSVD_7
AG16 M35
RSVD_13
AM21
+MA_VREFDQ AB34
RSVD_3 RSVD_8 15mil +MB_VREFDQ AB35
RSVD_9 RSVD_14
RSVD_4 RSVD_10
1 2 MA_ZVDDIO FP3 REV 0.52 FP3 REV 0.52
+1.5V 1 2 MB_ZVDDIO
R3 39.2_0402_1%
+1.5V KAVERI-FP3-2.7G_BGA854
R4 39.2_0402_1% @
Place them close to APU within 3" @ KAVERI-FP3-2.7G_BGA854
Place them close to APU within 3"

EVENT# pull high +1.5V 0.75V reference voltage

+1.5V
2

A R5 A
1K_0402_1% +MEM_VREF
R6 1 2 1K_0402_5% MEM_MA_EVENT#
15mil
1

R7 1 2 1K_0402_5% MEM_MB_EVENT#
2

R8
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
1K_0402_1% C29 C30 Issued Date 2012/09/12 2012/07/29 Title
1000P_0402_50V7K
Deciphered Date
2 1
0.1U_0402_16V7K
FP3 DDRIII MEMORY I/F
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 6 of 52
5 4 3 2 1
 5 4 3 2 1

www.qdzbwx.com U65D
ANALOG/DISPLAY/MISC

Place near APU

C37 1 2 0.1U_0402_16V7K DP0_TXP0 AL6 DP0_TXP0 DP0_AUXP AG8 APU_VGA_AUXP C35 1 2 0.1U_0402_16V7K
21 APU_VGA_TXP0 1 2 0.1U_0402_16V7K APU_VGA_AUXP_C 21
C38 DP0_TXN0 AM5 AG10 APU_VGA_AUXN C36 1 2 0.1U_0402_16V7K
21 APU_VGA_TXN0 DP0_TXN0 DP0_AUXN APU_VGA_AUXN_C 21To FCH
C39 1 2 0.1U_0402_16V7K DP0_TXP1 AN5 B2

DISPLAY PORT 0
21 APU_VGA_TXP1 DP0_TXP1 DP1_AUXP APU_EDP1_AUXP 25
C40 1 2 0.1U_0402_16V7K DP0_TXN1 AM4 B1 To eDP Conn
21 APU_VGA_TXN1 DP0_TXN1 DP1_AUXN APU_EDP1_AUXN 25
C41 1 2 0.1U_0402_16V7K DP0_TXP2 AN4 B6
21 APU_VGA_TXP2 DP0_TXP2 DP2_AUXP APU_HDMI_CLK 27
C42 1 2 0.1U_0402_16V7K DP0_TXN2 AN3 DP0_TXN2 DP2_AUXN B7 To HDMI
D 21 APU_VGA_TXN2 APU_HDMI_DATA 27 D

C43 1 2 0.1U_0402_16V7K DP0_TXP3 AM3 H7

21 APU_VGA_TXP3 DP0_TXP3 DP3_AUXP +1.5VS
C44 1 2 0.1U_0402_16V7K DP0_TXN3 AN2 G7 U64

DISPLAY PORT MISC.

21 APU_VGA_TXN3 DP0_TXN3 DP3_AUXN +1.5VS
1 5
F2 Y6 NC VCC
25 APU_EDP1_TXP0 DP1_TXP0 DP4_AUXP
F1 Y5 DP_ENBKL 2 APU_SVD 2 @ 1 R120
25 APU_EDP1_TXN0 DP1_TXN0 DP4_AUXN A 4 1K_0402_5%
Y ENBKL 35
F3 AD2 3 APU_SVC 2 @ 1 R65

DISPLAY PORT 1
25 APU_EDP1_TXP1 DP1_TXP1 DP5_AUXP GND
E2 AC2 1K_0402_5%
25 APU_EDP1_TXN1 DP1_TXN1 DP5_AUXN
74AUP1G07GW_TSSOP5 APU_SVT 2 @ 1 R35
E1 AH7 FCH/CRT SA00005U600 1K_0402_5%
DP1_TXP2 DP0_HPD FCH_CRT_HPD 21
D1 B3 eDP APU_RST# 2 1 R36
DP1_TXN2 DP1_HPD DP1_HPD 25
DP2_HPD D7 HDMI 300_0402_5%
D2 F8 DP2_HPD 27 +1.5VS 2 1 R37
DP1_TXP3 DP3_HPD U67 APU_PWRGD
C1 DP1_TXN3 DP4_HPD AB6 1 5 300_0402_5%
AD1 NC VCC
DP5_HPD +3VS
A2 DP_ENVDD 2
27 APU_DP2_P0 DP2_TXP0 A
A3 DP2_TXN0 DP_BLON D12 DP_ENBKL VDDIO level 4 RP16
27 APU_DP2_N0 B11 DP_ENVDD 3 Y APU_ENVDD 25 8 1
DP_DIGON APU_ENVDD
B4 C12 DP_INT_PWM Need Level shift GND ENBKL 7 2

DISPLAY PORT 2
27 APU_DP2_P1 DP2_TXP1 DP_VARY_BL
A4 74AUP1G07GW_TSSOP5 6 3
27 APU_DP2_N1 DP2_TXN1
D3 DP_AUX_ZVSS R13 1 2 150_0402_1% SA00005U600 APU_INVT_PWM 5 4
DP_AUX_ZVSS
C4 DP2_TXP2
27 APU_DP2_P2 B5 L27
DP2_TXN2 TEST6 4.7K_0804_8P4R_5%
27 APU_DP2_N2 +1.5V
TEST9 P27
CLK net has no test points. A5 P28 U68 +1.5VS RP2
27 APU_DP2_P3 DP2_TXP3 TEST10
A6 C10 APU_TEST14 R15 1 @ 2 1K_0402_5% 1 5 APU_SID 8 1
27 APU_DP2_N3 DP2_TXN3 TEST14 NC VCC
TEST15 B9 APU_TEST15 T3 APU_SIC 7 2
CLK_APU R147 1 2 22_0402_5% CLK_APU_R AM13
CLKIN_H TEST16
A10 APU_TEST16 R16 1 @ 2 1K_0402_5% DP_INT_PWM 2 APU_ALLOW_STOP 6 3
20 CLK_APU A

CLK
CLK_APU# R148 1 2 22_0402_5% CLK_APU_R# AN13 B10 APU_TEST17 R17 1 @ 2 1K_0402_5% 4 APU_ALERT# 5 4

TEST
20 CLK_APU# CLKIN_L TEST17 Y APU_INVT_PWM 25
A12 APU_TEST18 3
TEST18 GND
CLK_APU_DISP AM11 B12 APU_TEST19 1K_0804_8P4R_5%
20 CLK_APU_DISP DISP_CLKIN_H TEST19
CLK_APU_DISP# AN11 DISP_CLKIN_L TEST20 C8 APU_TEST20 74AUP1G07GW_TSSOP5
20 CLK_APU_DISP# AJ10 D8 APU_TEST24
RSVD_16 TEST24 SA00005U600
TEST25_H AM12 APU_TEST25_H R22 1 2 510_0402_5% RP15
APU_SVC R150 1 2 0_0402_5% APU_SVC_R B16
SVC TEST25_L
AN12 APU_TEST25_L R23 1 2 510_0402_5%
+1.05VS DP_ENVDD 8 1
45 APU_SVC
APU_SVD R149 1 2 0_0402_5% APU_SVD_R C16
SVD TEST28_H
A8 APU_TEST28_H T4 DP_ENBKL 7 2
45 APU_SVD
APU_SVT A16 B8 APU_TEST28_L 6 3

SER.
C SVT TEST28_L T5 C
45 APU_SVT AA27
TEST30_H R25 1 @ 2 DP_INT_PWM 5 4
APU_SIC AL14 SIC TEST30_L AA28 39.2_0402_1%
APU_SID AK14 V28 APU_TEST31 R26 1 @ 2 100K_0804_8P4R_5%
SID TEST31 +1.5V
Y27 39.2_0402_1% RP7
TEST32_H
R445 1 RS@ 2 0_0402_5% APU_RST#_R AM14 RESET_L TEST32_L Y28 APU_TEST18 1 8
20 APU_RST#
R446 1 RS@ 2 0_0402_5% APU_PWRGD_R AL12
PWROK R27 1 @ 210K_0402_5% APU_TEST19 2 7
20,45 APU_PWRGD

CTRL
APU_TEST20 3 6
APU_PROCHOT# AL10 AK10 APU_RSVD_15 R28 1 @ 210K_0402_5% APU_TEST24 4 5
20 APU_PROCHOT# PROCHOT_L RSVD_15 +1.5V
APU_THERMTRIP# AK11 AM15 APU_ALLOW_STOP
THERMTRIP_L DMAACTIVE_L
APU_ALERT# AN15 ALERT_L 1K_0804_8P4R_5%
T27 APU_TEST4

MISC
TEST4 T10
APU_TDI A14 TDI TEST5 T28 APU_TEST5 T11 R30 1 2300_0402_5% +1.5V DP_STEREOSYNC change to PU
APU_TDO C14 for HDMI can not output
TDO
APU_TCK B15 A9 DP_STEREOSYNC R31 1 @ 2300_0402_5%
TCK DP_STEREOSYNC 20131126
APU_TMS B14 TMS
JTAG

APU_TRST# D14 D16 APU_COREYYPE R32 1 @ 2 0_0402_5%

TRST_L CORETYPE +3VLP
APU_DBRDY A13 DBRDY
RSVD

APU_DBREQ# B13
DBREQ_L
A17 APU_RSVD_1
RSVD_1 T12
E10 VSS_SENSE_A RSVD_2 K28 APU_RSVD_2 T13
45 APU_VDD_SEN_L D9
Route as differential 45 APU_VDD_SEN_H VDD_SENSE
D10
with VSS_SENSE 45 APU_VDDNB_SEN_H VDDNB_SENSE
SENSE

F10 F7
VDDIO_SENSE RSVD_17 +1.5V
AE10 E4
VDDP_SENSE RSVD_18
AUDIO

AF11 VDDR_SENSE RSVD_19 E5

AF10 E7
VSS_SENSE_B RSVD_20
RSVD_21 D5
FP3 REV 0.52

2
Q3

G
KAVERI-FP3-2.7G_BGA854 @
@ APU_ALLOW_STOP 1 3 ALLOW_STOP
ALLOW_STOP 20

S
BSH111 1N_SOT23-3

For debug, place the Caps close to APU R24 1 RS@ 2 0_0402_5%
B B
XEMC@
APU_ALLOW_STOP C53 1 2 27P_0402_50V8J

EMC@
APU_PWRGD C54 1 2 27P_0402_50V8J

EMC@ +1.5VS
APU_RST# C55 1 2 27P_0402_50V8J HDT+ Debug conn
1 HDT@ 2
1
R121 HDT@ 21K_0402_5%
R122 1K_0402_5% +1.5V
+1.5V
+1.5V JHDT1 RP1
1 2 APU_TCK 1 8
1 2 APU_TMS 2 7
Asserted as an input to force the 3 4 APU_TDI 3 6
CPU TSI interface level shift 3 4
2

processor into the HTC-active state APU_DBREQ# 4 5

R29 5 6
1K_0402_5% 5 6 1K_0804_8P4R_5%
+1.5V 7 8 APU_TDO
R38 7 8 DB2J31400L_SOD323-2
1

1 2 APU_TRST# 1 HDT@ 2 R39 9 10 APU_PWRGD_BUF 1 D29 2 APU_PWRGD_HDT

APU_PROCHOT# R33 1 RS@ 2 0_0402_5% 1K_0402_5% 0_0402_5% 9 10 HDT@
PROCHOT# 35,45
R47 1 HDT@ 2 11 12 APU_RST#_BUF 1 D30 2 APU_RST#_HDT
11 12
BSH111, the Vgs is: 10K_0402_5% HDT@
+1.5V R48 1 HDT@ 2 13 14 APU_DBRDY DB2J31400L_SOD323-2
+1.5VS
min = 0.4V 13 14
C935 10K_0402_5%
R40 1 @ 2 1 2 0.1U_0402_16V4Z Max = 1.3V THERMTRIP shutdown Indicates to the FCH that a thermal trip R50 1 HDT@ 2 15 16
0_0402_5% 10K_0402_5% 15 16
temperature: 115 degree has occurred. Its assertion will cause the FCH
1

17 18 APU_TEST19
1 2 1 2 When APU High -> MOS OFF (Vgs < 0.4V ) to transition the system to S5 immediately 17 18
+3VS
2

R537 R538 APU Low -> MOS ON (Vgs > 1.3V) 19 20 APU_TEST18
31.6K_0402_1% 30K_0402_1% 19 20
R622 R620
2 2

1K_0402_5% 10K_0402_5%
B

Q9 Vg = 1.607 V SAMTE_ASP-136446-07-B EVT check can remove RP1 or not

1
2
G

A Q12 HDT@ A
E

APU_THERMTRIP# 3 1 R623 1 RS@ 2 0_0402_5%

H_THERMTRIP# 22
C

APU_SID 3 1 EC_SMB_DA2
EC_SMB_DA2 14,35
LBSS138LT1G_SOT-23-3 MMBT3904_SOT23-3 1 2 APU_PWRGD_HDT 1 HDT@ 2 R41 APU_PWRGD
S

MAINPWON 35,39,41
R621 @ 0_0402_5% 0_0402_5%
APU_RST#_HDT 1 HDT@ 2 R42 APU_RST#
To power protect 0_0402_5%

Q10
2
G

APU_SIC 3 1 EC_SMB_CK2
EC_SMB_CK2 14,35
Security Classification Compal Secret Data Compal Electronics, Inc.
LBSS138LT1G_SOT-23-3 2012/09/12 2012/07/29
S

Issued Date Title

Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP3 Display/MISC/HDT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
5 I'm from VIETNAM sualaptop365
4 3 2
Date: Wednesday, February 12, 2014
1
Sheet 7 of 52
 5 4 3 2 1

Power Name Consumption

VDD
U65F
+1.5V
Check list CH47 +APU_CORE 38A
L29
L31
L34
VDDIO_1
VDDIO_2
POWER

www.qdzbwx.com +APU_CORE_NB
Decoupling
+APU_CORE Decoupling
Power Side
22uF x11 @ x2
VDDNB
+APU_CORE_NB
VDDIO
40A
L37
VDDIO_3 Power Side
M29
VDDIO_4
VDDIO_5 22uF x10 @ x2 0.22uF x2 +1.5V 2.5A
M32
VDDIO_6 0.22uF x3 0.01uF x3 VDDP / VDDR
N27
N34
VDDIO_7
VDDIO_8 180pF x4 180pF x3 +1.05VS 4.0A / 3.9A
P29 VDDA
D VDDIO_9 D
P31
R29
VDDIO_10
VDDIO_11
+1.8VS 0.7A
R32
VDDIO_12
R34
VDDIO_13
R37
VDDIO_14
U29
VDDIO_15
U31
VDDIO_16
U34
VDDIO_17
V27
VDDIO_18
V34
VDDIO_19 +APU_CORE +APU_CORE_NB
W29
VDDIO_20
W32 U65E
VDDIO_21
W37 POWER
VDDIO_22
Y31
VDDIO_23
AA34 T11 E8
VDDIO_24 +1.05VS +1.05VS VDD_1 VDDNB_1
AB29 T14 F4
VDDIO_25 VDD_2 VDDNB_2
AB32 T17 F5
VDDIO_26 VDD_3 VDDNB_3
AB37 T21 G4
VDDIO_27 VDD_4 VDDNB_4
AC29 VDDP: VDDR: T24 G8
VDDIO_28 VDD_5 VDDNB_5

0.22U_0402_10V4Z

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

0.22U_0402_10V4Z

0.22U_0402_10V4Z

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

0.22U_0402_10V4Z

0.22U_0402_10V4Z
AC31 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V10 G10
VDDIO_29 VDD_6 VDDNB_6

C63

C64

C65

C66
AC34 V13 H3
VDDIO_30 VDD_7 VDDNB_7

C57

C58

C59

C60

C61

C62

C68

C69

C70

C71

C72

C73
AC37 V16 H6
AE32
VDDIO_31 22u x3 22u x4 V19
VDD_8 VDDNB_8
H10
VDDIO_32 VDD_9 VDDNB_9
AE34
VDDIO_33
2 2 2 2 2 2 2 2 0.22u x2 2 2 2 2 2 2 2 2 0.22u x2 V22
VDD_10 VDDNB_10
J10
AF30 V24 J13
AF31
VDDIO_34 180P x2 180P x2 Y7
VDD_11 VDDNB_11
J22
VDDIO_35 VDD_12 VDDNB_12
AG34 Y10 J25
VDDIO_36 VDD_13 VDDNB_13
AG37 Y13 K11
VDDIO_37 VDD_14 VDDNB_14
Y16 K14
VDD_15 VDDNB_15
Y19 K17
VDD_16 VDDNB_16
Y22 K21
VDD_17 VDDNB_17
Y25 K24
C VDD_18 VDDNB_18 C
AA4 L4
VDD_19 VDDNB_19
AA11 L7
VDD_20 VDDNB_20
AA14 L10
+1.05VS +1.05VS VDD_21 VDDNB_21
AA17 L13
VDD_22 VDDNB_22
VDDR_CAP AA21 L16
+1.8VS VDD_23 VDDNB_23
AK16 AK17 AA24 L19
VDDP_1 VDDR_1 4.7U_0603_6.3V6K VDD_24 VDDNB_24

0.22U_0402_6.3V6K

3300P_0402_50V7K
AL16 AM17 1 1 1 1 VDDR_CAP: AB7 L22
VDDP_2 VDDR_2 VDD_25 VDDNB_25

1
C74

C75

C76
AM16 AN17 C77 C78 AC4 L25
VDDP_3 VDDR_3 VDD_26 VDDNB_26
AN16
VDDP_4 VDDA: @ 22u x1 AC10
VDD_27 VDDNB_27
M3
22U_0805_6.3V6M 22U_0805_6.3V6M 22u AC13 N11
x1@ VDD_28 VDDNB_28

2
2 2 4.7u x1 2 2 AC16
VDD_29 VDDNB_29
N14
AC19 N17
0.22u x1 AC22
VDD_30 VDDNB_30
N21
VDD_31 VDDNB_31
VDDR_CAP
AC27 VDDR_CAP 3.3n x1 AC25
VDD_32 VDDNB_32
N24
AD4 P10
VDD_33 VDDNB_33
AH11 AD11 P13
VDDA_1 VDD_34 VDDNB_34
AJ11 AD14 P16
VDDA_2 VDD_35 VDDNB_35
VDDP_CAPAC11 VDDP_CAP AD17 P19
VDD_36 VDDNB_36
D6 R54 1 @ 2 0_0402_5% AD21 P22
RSVD_22 +1.5VS VDD_37 VDDNB_37
1 1 1 AD24 P25
FP3 REV 0.52 VDD_38 VDDNB_38
C79 C80 C81 AE6 R4
VDD_39 VDDNB_39
@ AE22 R6
VDD_40 VDDNB_40
22U_0805_6.3V6M 22U_0805_6.3V6M KAVERI-FP3-2.7G_BGA854 22U_0805_6.3V6M AE25
VDD_41 VDDNB_41
R9
2 2 @ 2 AF5 T3
VDD_42 VDDNB_42
AF8
+1.5V VDD_43
AG11
VDD_44
AH5
VDD_45
AH8
VDD_46
AH10
VDD_47
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

180P_0402_50V8J

180P_0402_50V8J

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AK8
VDD_48
C82

C83

C84

C85

C99

C100

C103

C104

C105

C106

C107

C108
C88

C89

C90

C93

C94

C95

C96
B B
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FP3 REV 0.52

@ KAVERI-FP3-2.7G_BGA854

VDDIO Decoupling

22uF x3
APU sequence : GROUP A need ramp before GROUP B 4.7uFx4
0.22uF x6
0.22uF x4 (return path)
SYSON 180pF x2 (return path)
APU_VDDIO_SUS
SUSP#

Group A +5/+3.3 VS
+1.1/+1.5/+1.8 VS
VDDA_PWRGD
VR_ON
A A
+APU_CORE
+APU_CORE_NB
Group B
+1.05VS
1.05VS_PWRGD Security Classification Compal Secret Data Compal Electronics, Inc.
FCH_PWRGD Issued Date 2012/09/12 Deciphered Date 2012/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP3 Power
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 8 of 52
5 4 3 2 1
 5 4 3 2 1

www.qdzbwx.com
U65G U65H
VSS
VSS
A1 K13 AC1 AN10
VSS_1 VSS_61 VSS_121 VSS_181
A7 K16 AC7 AN14
VSS_2 VSS_62 VSS_122 VSS_182
A11 K19 AC14 AN19
D VSS_3 VSS_63 VSS_123 VSS_183 D
A15 K22 AC17 AN23
VSS_4 VSS_64 VSS_124 VSS_184
A19 K25 AC21 AN27
VSS_5 VSS_65 VSS_125 VSS_185
A23 L1 AC24 AN30
VSS_6 VSS_66 VSS_126 VSS_186
A27 L11 AC28 AN37
VSS_7 VSS_67 VSS_127 VSS_187
A31 L14 AD3 AD27
VSS_8 VSS_68 VSS_128 VSS_188
A35 L17 AD10 K27
VSS_9 VSS_69 VSS_129 VSS_189
A37 L21 AD13 AE11
VSS_10 VSS_70 VSS_130 VSS_190
C2 L24 AD16
VSS_11 VSS_71 VSS_131
C3 L28 AD19
VSS_12 VSS_72 VSS_132
C6 M6 AD22
VSS_13 VSS_73 VSS_133
C35 M9 AD25
VSS_14 VSS_74 VSS_134
D4 N4 AD28
VSS_15 VSS_75 VSS_135
D11 N10 AE1
VSS_16 VSS_76 VSS_136
D13 N13 AE4
VSS_17 VSS_77 VSS_137
D15 N16 AE14
VSS_18 VSS_78 VSS_138
D17 N19 AE19
VSS_19 VSS_79 VSS_139
D19 N22 AE21
VSS_20 VSS_80 VSS_140
D21 N25 AE27
VSS_21 VSS_81 VSS_141
D23 N28 AE28
VSS_22 VSS_82 VSS_142
D25 P6 AF7
VSS_23 VSS_83 VSS_143
D27 P9 AF24
VSS_24 VSS_84 VSS_144
D29 P11 AF28
VSS_25 VSS_85 VSS_145
D31 P14 AG1
VSS_26 VSS_86 VSS_146
D33 P17 AG4
VSS_27 VSS_87 VSS_147
E17 P21 AG14
VSS_28 VSS_88 VSS_148
E31 P24 AG17
VSS_29 VSS_89 VSS_149
E34 R1 AG21
VSS_30 VSS_90 VSS_150
F11 T10 AG25
VSS_31 VSS_91 VSS_151
F21 T13 AG27
VSS_32 VSS_92 VSS_152
F24 T16 AG28
VSS_33 VSS_93 VSS_153
F27 T19 AH13
VSS_34 VSS_94 VSS_154
F30 T22 AH16
C VSS_35 VSS_95 VSS_155 C
G1 T25 AH19
VSS_36 VSS_96 VSS_156
G13 U4 AH22
VSS_37 VSS_97 VSS_157
G16 U6 AH30
VSS_38 VSS_98 VSS_158
G19 U9 AH31
VSS_39 VSS_99 VSS_159
G22 V11 AJ4
VSS_40 VSS_100 VSS_160
G25 V14 AJ24
VSS_41 VSS_101 VSS_161
G28 V17 AJ25
VSS_42 VSS_102 VSS_162
G34 V21 AK9
VSS_43 VSS_103 VSS_163
G37 V25 AK12
VSS_44 VSS_104 VSS_164
H8 W1 AK13
VSS_45 VSS_105 VSS_165
H14 W4 AK15
VSS_46 VSS_106 VSS_166
H17 W6 AK19
VSS_47 VSS_107 VSS_167
H30 W9 AK21
VSS_48 VSS_108 VSS_168
H32 Y3 AK23
VSS_49 VSS_109 VSS_169
J4 Y11 AK25
VSS_50 VSS_110 VSS_170
J6 Y14 AK27
VSS_51 VSS_111 VSS_171
J11 Y17 AK29
VSS_52 VSS_112 VSS_172
J16 Y21 AK31
VSS_53 VSS_113 VSS_173
J21 Y24 AK34
VSS_54 VSS_114 VSS_174
J24 AA10 AL3
VSS_55 VSS_115 VSS_175
J27 AA13 AL8
VSS_56 VSS_116 VSS_176
J28 AA16 AL37
VSS_57 VSS_117 VSS_177
J32 AA19 AM35
VSS_58 VSS_118 VSS_178
J34 AA22 AN1
VSS_59 VSS_119 VSS_179
K10 AA25 AN7
VSS_60 VSS_120 VSS_180
FP3 REV 0.52 FP3 REV 0.52

KAVERI-FP3-2.7G_BGA854
@ @ KAVERI-FP3-2.7G_BGA854

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2012/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP3 GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 9 of 52
5 4 3 2 1
 5 4 3 2 1

www.qdzbwx.com Panel ENBKL

D D

C
Panel ENVDD C

B B

Panel PWM

A A

Security Classification Compal Secret Data

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title
AMD FS1R2 Singal Level Shifter
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 10 of 52
5 4 3 2 1
 A B C D E

+MA_VREF_DQ +1.5V 3.56A +1.5V

DDRA_SDQ0
DDRA_SDQ1
15mil 1
3
5
7
JDIMM1
VREF_DQ
VSS2
DQ0
DQ1
VSS1
DQ4
DQ5
VSS3
2
4
6
8
DDRA_SDQ4
DDRA_SDQ5
www.qdzbwx.com
9 10 DDRA_SDQS0#
VSS4 DQS#0 DDRA_SDQS0# 6
DDRA_SDM0 11 12 DDRA_SDQS0
13 DM0 DQS0 14 DDRA_SDQS0 6
DDRA_SDQ2 15 VSS5 VSS6 16 DDRA_SDQ6
DDRA_SDQ3 17 DQ2 DQ6 18 DDRA_SDQ7
19 DQ3 DQ7 20
DDRA_SDQ8 21 VSS7 VSS8 22 DDRA_SDQ12 DDRA_SDQ[0..63]
DDRA_SDQ9 23 DQ8 DQ12 24 DDRA_SDQ13 DDRA_SDQ[0..63] 6
25 DQ9 DQ13 26 DDRA_SDM[0..7]
1
DDRA_SDQS1# 27 VSS9 VSS10 28 DDRA_SDM1 DDRA_SDM[0..7] 6 1
6 DDRA_SDQS1# 29 DQS#1 DM1 30 DDRA_SMA[0..15]
DDRA_SDQS1 MEM_MA_RST#
6 DDRA_SDQS1 DQS1 RESET# MEM_MA_RST# 6 DDRA_SMA[0..15] 6
31 32
DDRA_SDQ10 33 VSS11 VSS12 34 DDRA_SDQ14
DQ10 DQ14 2
DDRA_SDQ11 35 36 DDRA_SDQ15
37 DQ11 DQ15 38 C186
DDRA_SDQ16 39 VSS13 VSS14 40 DDRA_SDQ20 0.1U_0402_16V4Z
DDRA_SDQ17 41 DQ16 DQ20 42 DDRA_SDQ21 1 XEMC@
43 DQ17 DQ21 44
DDRA_SDQS2# 45 VSS15 VSS16 46 DDRA_SDM2
6 DDRA_SDQS2# DQS#2 DM2
DDRA_SDQS2 47 48 Place near DIMM1
6 DDRA_SDQS2 49 DQS2 VSS17 50 DDRA_SDQ22
DDRA_SDQ18 51 VSS18 DQ22 52 DDRA_SDQ23
DDRA_SDQ19 53 DQ18 DQ23 54 +1.5V
55 DQ19 VSS19 56 DDRA_SDQ28
DDRA_SDQ24 57 VSS20 DQ28 58 DDRA_SDQ29 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
DDRA_SDQ25 59 DQ24 DQ29 60
DQ25 VSS21 2 2 2 1 1 1 1 1 1 1
61 62 DDRA_SDQS3#
63 VSS22 DQS#3 64 DDRA_SDQS3# 6
DDRA_SDM3 DDRA_SDQS3 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118
DM3 DQS3 DDRA_SDQS3 6
65 66
DDRA_SDQ26 67 VSS23 VSS24 68 DDRA_SDQ30 1 1 1 2 2 2 2 2 2 2
DDRA_SDQ27 69 DQ26 DQ30 70 DDRA_SDQ31 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
71 DQ27 DQ31 72
VSS25 VSS26

DDRA_CKE0 73 74 DDRA_CKE1
6 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 6
75 76 +0.75VS
77 VDD1 VDD2 78 DDRA_SMA15
DDRA_SBS2# 79 NC1 A15 80 DDRA_SMA14 1U_0402_6.3V6K
6 DDRA_SBS2# BA2 A14
81 82 2 1 1
DDRA_SMA12 83 VDD3 VDD4 84 DDRA_SMA11
DDRA_SMA9 85 A12/BC# A11 86 DDRA_SMA7 C119 C120 C121
87 A9 A7 88
DDRA_SMA8 89 VDD5 VDD6 90 DDRA_SMA6 1 2 2
DDRA_SMA5 91 A8 A6 92 DDRA_SMA4 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
93 A5 A4 94
DDRA_SMA3 95 VDD7 VDD8 96 DDRA_SMA2
2 2
DDRA_SMA1 97 A3 A2 98 DDRA_SMA0
99 A1 A0 100
DDRA_CLK0 101 VDD9 VDD10 102 DDRA_CLK1
6 DDRA_CLK0 103 CK0 CK1 104 DDRA_CLK1 6
DDRA_CLK0# DDRA_CLK1#
6 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 6
105 106 Follow CRB design
DDRA_SMA10 107 VDD11 VDD12 108 DDRA_SBS1#
A10/AP BA1 DDRA_SBS1# 6
DDRA_SBS0# 109 110 DDRA_SRAS#
6 DDRA_SBS0# BA0 RAS# DDRA_SRAS# 6
111 112
DDRA_SWE# 113 VDD13 VDD14 114 DDRA_SCS0# +VREF_CA +1.5V
6 DDRA_SWE# WE# S0# DDRA_SCS0# 6
DDRA_SCAS# 115 116 DDRA_ODT0
6 DDRA_SCAS# 117 CAS# ODT0 118 DDRA_ODT0 6
VDD15 VDD16

2
DDRA_SMA13 119 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 6
DDRA_SCS1# 121 122 R55
6 DDRA_SCS1# 123 S1# NC2 124 1K_0402_1%
125 VDD17 VDD18 126
15mil
NCTEST VREF_CA +VREF_CA
127 128 15mil

1
DDRA_SDQ32 129 VSS27 VSS28 130 DDRA_SDQ36 +VREF_CA
DDRA_SDQ33 131 DQ32 DQ36 132 DDRA_SDQ37
133 DQ33 DQ37 134

1000P_0402_50V7K
0.1U_0402_16V4Z
VSS29 VSS30

4.7U_0603_6.3V6K
DDRA_SDQS4# 135 136 DDRA_SDM4
6 DDRA_SDQS4# 137 DQS#4 DM4 138
DDRA_SDQS4 1 1 1
6 DDRA_SDQS4 DQS4 VSS31

2
139 140 DDRA_SDQ38 @ C123 C124
VSS32 DQ38

C122
DDRA_SDQ34 141 142 DDRA_SDQ39 R56
DDRA_SDQ35 143 DQ34 DQ39 144 1K_0402_1%
145 DQ35 VSS33 146 DDRA_SDQ44 2 2 2
DDRA_SDQ40 147 VSS34 DQ44 148 DDRA_SDQ45

1
DDRA_SDQ41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDRA_SDQS5#
153 VSS36 DQS#5 154 DDRA_SDQS5# 6
DDRA_SDM5 DDRA_SDQS5
DM5 DQS5 DDRA_SDQS5 6
155 156
DDRA_SDQ42 157 VSS37 VSS38 158 DDRA_SDQ46
DDRA_SDQ43 159 DQ42 DQ46 160 DDRA_SDQ47
161 DQ43 DQ47 162
DDRA_SDQ48 163 VSS39 VSS40 164 DDRA_SDQ52
DDRA_SDQ49 165 DQ48 DQ52 166 DDRA_SDQ53
167 DQ49 DQ53 168 +MB_VREFDQ
DDRA_SDQS6# 169 VSS41 VSS42 170 DDRA_SDM6 +1.5V +MB_VREF_DQ
3 6 DDRA_SDQS6# DQS#6 DM6 3
DDRA_SDQS6 171 172 RP17
6 DDRA_SDQS6 173 DQS6 VSS43 174 1 8
DDRA_SDQ54 R61 1 @ 2 0_0402_5%
DDRA_SDQ50 175 VSS44 DQ54 176 DDRA_SDQ55 2 7
DDRA_SDQ51 177 DQ50 DQ55 178 3 6
179 DQ51 VSS45 180 DDRA_SDQ60 4 5 R58 1 @ 2 0_0402_5%
DDRA_SDQ56 181 VSS46 DQ60 182 DDRA_SDQ61
DDRA_SDQ57 183 DQ56 DQ61 184 1K_0804_8P4R_1%
185 DQ57 VSS47 186 DDRA_SDQS7# +MA_VREF_DQ
187 VSS48 DQS#7 188 DDRA_SDQS7# 6
DDRA_SDM7 DDRA_SDQS7 +MA_VREFDQ
DM7 DQS7 DDRA_SDQS7 6
189 190
DDRA_SDQ58 191 VSS49 VSS50 192 DDRA_SDQ62
DDRA_SDQ59 193 DQ58 DQ62 194 DDRA_SDQ63
195 DQ59 DQ63 196
197 VSS51 VSS52 198 MEM_MA_EVENT#
+3VS SA0 EVENT# MEM_MA_EVENT# 6
199 200
+3VS VDDSPD SDA FCH_SDATA0 12,22,28 +MA_VREF_DQ
201 202
203 SA1 SCL 204 FCH_SCLK0 12,22,28
VTT1 VTT2 +0.75VS
205 206
15mil
1 1 G1 G2
C128 C129 +MA_VREF_DQ
FOX_AS0A621-U4R6-7H
2.2U_0603_6.3V6K 0.1U_0402_16V7K CONN@

0.1U_0402_16V4Z
2 2

4.7U_0603_6.3V6K
@

1000P_0402_50V7K
1 1 1
@ C126 C127

C125
2 2 2
DIMM_A STD H:9.2mm
<Address: 00>

follow CRB design

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2012/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DIMM_A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
A I'm from VIETNAM sualaptop365B C D
Date: Wednesday, February 12, 2014
E
Sheet 11 of 52
 A B C D E

+MB_VREF_DQ +1.5V 3.56A +1.5V

JDIMM2 DDRB_SDQ[0..63]
15mil 1 2 DDRB_SDQ[0..63] 6
3 VREF_DQ VSS1 4 DDRB_SDQ4 DDRB_SDM[0..7]
DDRB_SDQ0 5 VSS2 DQ4 6 DDRB_SDQ5 DDRB_SDM[0..7] 6
DDRB_SDQ1 7 DQ0 DQ5 8 DDRB_SMA[0..15]
9 DQ1 VSS3 10 DDRB_SDQS0# DDRB_SMA[0..15] 6
DDRB_SDM0 11 VSS4 DQS#0 12 DDRB_SDQS0 DDRB_SDQS0# 6
13 DM0 DQS0 14 DDRB_SDQS0 6
DDRB_SDQ2 15 VSS5 VSS6 16 DDRB_SDQ6
DDRB_SDQ3 17 DQ2 DQ6 18 DDRB_SDQ7
Place near DIMM2
19 DQ3 DQ7 20
1 DDRB_SDQ8 21 VSS7 VSS8 22 DDRB_SDQ12 1
DDRB_SDQ9 23 DQ8 DQ12 24 DDRB_SDQ13 +1.5V
25 DQ9 DQ13 26
DDRB_SDQS1# 27 VSS9 VSS10 28 DDRB_SDM1 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
6 DDRB_SDQS1# DDRB_SDQS1 29 DQS#1 DM1 30 MEM_MB_RST#
6 DDRB_SDQS1 DQS1 RESET# MEM_MB_RST# 6 2 2 2 1 1 1 1 1 1 1
31 32
DDRB_SDQ10 33 VSS11 VSS12 34 DDRB_SDQ14 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139
DQ10 DQ14 2
DDRB_SDQ11 35 36 DDRB_SDQ15
37 DQ11 DQ15 38 C143 1 1 1 2 2 2 2 2 2 2
DDRB_SDQ16 39 VSS13 VSS14 40 DDRB_SDQ20 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
DDRB_SDQ17 41 DQ16 DQ20 42 DDRB_SDQ21 1 XEMC@
43 DQ17 DQ21 44
DDRB_SDQS2# 45 VSS15 VSS16 46 DDRB_SDM2
6 DDRB_SDQS2# 47 DQS#2 DM2 48
DDRB_SDQS2 +1.5V
6 DDRB_SDQS2 49 DQS2 VSS17 50 DDRB_SDQ22
DDRB_SDQ18 51 VSS18 DQ22 52 DDRB_SDQ23 +0.75VS
DDRB_SDQ19 53 DQ18 DQ23 54
DQ19 VSS19 1
55 56 DDRB_SDQ28 1U_0402_6.3V6K @
DDRB_SDQ24 57 VSS20 DQ28 58 DDRB_SDQ29 + C185
DQ24 DQ29 2 1 1
DDRB_SDQ25 59 60 330U_2.5V_M
61 DQ25 VSS21 62 DDRB_SDQS3# C140 C141 C142
DDRB_SDM3 63 VSS22 DQS#3 64 DDRB_SDQS3 DDRB_SDQS3# 6 2
65 DM3 DQS3 66 DDRB_SDQS3 6 1 2 2 SF000002Z00
DDRB_SDQ26 67 VSS23 VSS24 68 DDRB_SDQ30 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 330U 2.5V H4.2
DDRB_SDQ27 69 DQ26 DQ30 70 DDRB_SDQ31
71 DQ27 DQ31 72
17mohm OSCON
VSS25 VSS26

DDRB_CKE0 73 74 DDRB_CKE1
6 DDRB_CKE0 75 CKE0 CKE1 76 DDRB_CKE1 6
77 VDD1 VDD2 78 DDRB_SMA15
2 DDRB_SBS2# 79 NC1 A15 80 DDRB_SMA14 2
6 DDRB_SBS2# 81 BA2 A14 82
DDRB_SMA12 83 VDD3 VDD4 84 DDRB_SMA11
DDRB_SMA9 85 A12/BC# A11 86 DDRB_SMA7
87 A9 A7 88
DDRB_SMA8 89 VDD5 VDD6 90 DDRB_SMA6
DDRB_SMA5 91 A8 A6 92 DDRB_SMA4
93 A5 A4 94
DDRB_SMA3 95 VDD7 VDD8 96 DDRB_SMA2
DDRB_SMA1 97 A3 A2 98 DDRB_SMA0
99 A1 A0 100
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1
6 DDRB_CLK0 103 CK0 CK1 104 DDRB_CLK1 6 +VREF_CA +MB_VREF_DQ
DDRB_CLK0# DDRB_CLK1#
6 DDRB_CLK0# 105 CK0# CK1# 106 DDRB_CLK1# 6
DDRB_SMA10 107 VDD11 VDD12 108 DDRB_SBS1#
15mil
DDRB_SBS0# 109 A10/AP BA1 110 DDRB_SRAS# DDRB_SBS1# 6 15mil +VREF_CA +MB_VREF_DQ
6 DDRB_SBS0# 111 BA0 RAS# 112 DDRB_SRAS# 6
VDD13 VDD14

1000P_0402_50V7K
DDRB_SWE# 113 114 DDRB_SCS0#

0.1U_0402_16V4Z

0.1U_0402_16V4Z
6 DDRB_SWE# WE# S0# DDRB_SCS0# 6

1000P_0402_50V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
DDRB_SCAS# 115 116 DDRB_ODT0
6 DDRB_SCAS# 117 CAS# ODT0 118 DDRB_ODT0 6
VDD15 VDD16 1 1 1 1 1 1
DDRB_SMA13 119 120 DDRB_ODT1 @ C146 @ C148 C149
A13 ODT1 DDRB_ODT1 6 C145

C144

C147
DDRB_SCS1# 121 122
6 DDRB_SCS1# 123 S1# NC2 124
125 VDD17 VDD18 126
15mil 2 2 2 2 2 2
NCTEST VREF_CA +VREF_CA
127 128
DDRB_SDQ32 129 VSS27 VSS28 130 DDRB_SDQ36
DDRB_SDQ33 131 DQ32 DQ36 132 DDRB_SDQ37
133 DQ33 DQ37 134
DDRB_SDQS4# 135 VSS29 VSS30 136 DDRB_SDM4
6 DDRB_SDQS4# DDRB_SDQS4 137 DQS#4 DM4 138
6 DDRB_SDQS4 139 DQS4 VSS31 140 DDRB_SDQ38
DDRB_SDQ34 141 VSS32 DQ38 142 DDRB_SDQ39
3 DDRB_SDQ35 143 DQ34 DQ39 144 3
145 DQ35 VSS33 146 DDRB_SDQ44
DDRB_SDQ40 147 VSS34 DQ44 148 DDRB_SDQ45
DDRB_SDQ41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDRB_SDQS5#
DDRB_SDM5 153 VSS36 DQS#5 154 DDRB_SDQS5 DDRB_SDQS5# 6
155 DM5 DQS5 156 DDRB_SDQS5 6
DDRB_SDQ42 157 VSS37 VSS38 158 DDRB_SDQ46
DDRB_SDQ43 159 DQ42 DQ46 160 DDRB_SDQ47
161 DQ43 DQ47 162
DDRB_SDQ48 163 VSS39 VSS40 164 DDRB_SDQ52
DDRB_SDQ49 165 DQ48 DQ52 166 DDRB_SDQ53
167 DQ49 DQ53 168
DDRB_SDQS6# 169 VSS41 VSS42 170 DDRB_SDM6
6 DDRB_SDQS6# 171 DQS#6 DM6 172
DDRB_SDQS6
6 DDRB_SDQS6 173 DQS6 VSS43 174 DDRB_SDQ54
DDRB_SDQ50 175 VSS44 DQ54 176 DDRB_SDQ55
DDRB_SDQ51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDRB_SDQ60
DDRB_SDQ56 181 VSS46 DQ60 182 DDRB_SDQ61
DDRB_SDQ57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDRB_SDQS7#
DDRB_SDM7 187 VSS48 DQS#7 188 DDRB_SDQS7 DDRB_SDQS7# 6
189 DM7 DQS7 190 DDRB_SDQS7 6
DDRB_SDQ58 191 VSS49 VSS50 192 DDRB_SDQ62
DDRB_SDQ59 193 DQ58 DQ62 194 DDRB_SDQ63
R63 10K_0402_5% 195 DQ59 DQ63 196
1 2 197 VSS51 VSS52 198 MEM_MB_EVENT#
SA0 EVENT# MEM_MB_EVENT# 6
199 200
+3VS 201 VDDSPD SDA 202 FCH_SDATA0 11,22,28
203 SA1 SCL 204 FCH_SCLK0 11,22,28
VTT1 VTT2 +0.75VS
4 205 206 4
G1 G2

LCN_DAN06-K4406-0100

CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

2012/09/12 2012/07/29 Title
DIMM_B STD H:5.2mm Issued Date Deciphered Date
DIMM_B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
<Address: 01> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 12 of 52
A B C D E
 A B C D E

GFX PCIE LANE REVERSAL

U51A
PEG_HTX_C_GRX_P[0..7] PEG_GTX_C_HRX_P[0..7]
5 PEG_HTX_C_GRX_P[0..7] PART 1 0F 9 PEG_GTX_C_HRX_P[0..7] 5
PEG_HTX_C_GRX_N[0..7] PEG_GTX_C_HRX_N[0..7]
5 PEG_HTX_C_GRX_N[0..7] PEG_GTX_C_HRX_N[0..7] 5

U51G
PEG_HTX_C_GRX_P0 AA38 Y33 PEG_GTX_HRX_P0 C161 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P0
PEG_HTX_C_GRX_N0 Y37 PCIE_RX0P PCIE_TX0P Y32 PEG_GTX_HRX_N0 C163 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N0 PART 7 0F 9
1 1
PCIE_RX0N PCIE_TX0N
AK27
PEG_HTX_C_GRX_P1 Y35 W33 PEG_GTX_HRX_P1 C159 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P1 RSVD/VARY_BL AJ27
PEG_HTX_C_GRX_N1 W36 PCIE_RX1P PCIE_TX1P W32 PEG_GTX_HRX_N1 C158 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N1 RSVD/DIGON
PCIE_RX1N PCIE_TX1N LVDS CONTROL

PEG_HTX_C_GRX_P2 W38 U33 PEG_GTX_HRX_P2 C150 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P2

PEG_HTX_C_GRX_N2 V37 PCIE_RX2P PCIE_TX2P U32 PEG_GTX_HRX_N2 C165 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N2 AK35
PCIE_RX2N PCIE_TX2N TXCBP_DPB3P AL36
TXCBM_DPB3N
PEG_HTX_C_GRX_P3 V35 U30 PEG_GTX_HRX_P3 C162 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P3 AJ38
PEG_HTX_C_GRX_N3 U36 PCIE_RX3P PCIE_TX3P U29 PEG_GTX_HRX_N3 C160 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N3 TX3P_DPB2P AK37
PCIE_RX3N PCIE_TX3N TX3M_DPB2N
AH35
PEG_HTX_C_GRX_P4 U38 T33 PEG_GTX_HRX_P4 C175 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P4 TX4P_DPB1P AJ36
PEG_HTX_C_GRX_N4 T37 PCIE_RX4P PCIE_TX4P T32 PEG_GTX_HRX_N4 C174 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N4 TX4M_DPB1N
PCIE_RX4N PCIE_TX4N AG38
TX5P_DPB0P AH37
PEG_HTX_C_GRX_P5 T35 T30 PEG_GTX_HRX_P5 C176 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P5 TX5M_DPB0N
PEG_HTX_C_GRX_N5 R36 PCIE_RX5P PCIE_TX5P T29 PEG_GTX_HRX_N5 C177 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N5 AF35

LVTMDP
PCIE_RX5N PCIE_TX5N NC#AF35 AG36
NC#AG36
PEG_HTX_C_GRX_P6 R38 P33 PEG_GTX_HRX_P6 C178 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P6
PEG_HTX_C_GRX_N6 P37 PCIE_RX6P PCIE_TX6P P32 PEG_GTX_HRX_N6 C179 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N6
PCIE_RX6N PCIE_TX6N
AP34
PEG_HTX_C_GRX_P7 P35 P30 PEG_GTX_HRX_P7 C180 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P7 TXCAP_DPA3P AR34
PEG_HTX_C_GRX_N7 N36 PCIE_RX7P PCIE_TX7P P29 PEG_GTX_HRX_N7 C181 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N7 TXCAM_DPA3N
2 PCIE_RX7N PCIE_TX7N AW37 2
TX0P_DPA2P AU35
N38 N33 TX0M_DPA2N
M37 NC#N38 NC#N33 N32 AR37
NC#M37 NC#N32 TX1P_DPA1P AU39
TX1M_DPA1N
PCI EXPRESS INTERFACE

M35 N30 AP35

L36 NC#M35 NC#N30 N29 TX2P_DPA0P AR35
NC#L36 NC#N29 TX2M_DPA0N
AN36
L38 L33 NC#AN36 AP37
K37 NC#L38 NC#L33 L32 NC#AP37
NC#K37 NC#L32

K35 L30
J36 NC#K35 NC#L30 L29 2160842006A0MARSXT_FCBGA962
NC#J36 NC#L29 @

J38 K33
H37 NC#J38 NC#K33 K32
NC#H37 NC#K32

H35 J33
G36 NC#H35 NC#J33 J32
NC#G36 NC#J32

G38 K30
F37 NC#G38 NC#K30 K29
NC#F37 NC#K29
3 3
F35 H33
E37 NC#F35 NC#H33 H32
NC#E37 NC#H32

CLOCK
AB35
20 CLK_PEG_VGA PCIE_REFCLKP
AA36
20 CLK_PEG_VGA# PCIE_REFCLKN

CALIBRATION
Y30 VGA_PCIE_CALRP R794 1 VGA@ 2 1.69K_0402_1% +0.95VSDGPU
PCIE_CALR_TX
2 VGA@ 1 AH16 Y29 VGA_PCIE_CALRN R796 1 VGA@ 2 1K_0402_1% +0.95VSDGPU
R795 1K_0402_5% TEST_PG PCIE_CALR_RX
3.3-V tolerant
PLTRST_VGA# AA30
20 PLTRST_VGA# PERSTB

2160842006A0MARSXT_FCBGA962
@

4 4

U51 U51

Security Classification Compal Secret Data Compal Electronics, Inc.

JET XT M2 OPAL XT M2 FCBGA 2012/09/12 2013/07/10 Title
JET@ OPAL@
Issued Date Deciphered Date OPAL-Pro_PCIE
SA000079000 SA000078V20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHANGE TO R3 PN Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
02/11 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
Date: W ednesday, February 12, 2014 Sheet 13 of 52
I'm
A from VIETNAM sualaptop365
B C D E
 A B C D E

U51B U51I 130mA L64

MBK1608121YZF_0603
+3VSDGPU External VGA Thermal Sensor PART 2 0F 9

PART 9 0F 9
+MPLL_PVDD 2 1
+1.8VSDGPU
U52 @ MUTI GFX VGA@
1 8 VGA_SMB_CK2 AD29 AU24
VDD SCLK T109 GENLK_CLK NC#AU24
1 AC29 AV23 VGA@ 1 VGA@ 1 SM010030010 200ma
T110 GENLK_VSYNC NC#AV23
0.1U_0402_16V4Z
C823

1U_0402_6.3V6K
C825

10U_0603_6.3V6M
C826
@ GPU_THERM_D+ 2 7 VGA_SMB_DA2
2200P_0402_50V7K D+ SDATA AT25 120ohm@100mhz DCR 0.2
C827 1 2 3 6 THM_ALERT# AJ21 NC#AT25 AR24 AV33 XTALIN
2 @ D- ALERT# AK21 SWAPLOCKA DPA NC#AR24 XTALIN 2 2
GPU_THERM_D- 4 5 1 @ 2 SWAPLOCKB AU26
THERM# GND +3VSDGPU NC#AU26
R798 4.7K_0402_5% AV25
NC#AV25 L65
AR8 AT27
75mA
ADM1032ARMZ-2REEL_MSOP8 MBK1608121YZF_0603
AU8 NC#AR8 NC#AT27 AR26 +SPLL_PVDD 2 1
NC#AU8 NC#AR26 +1.8VSDGPU
T111
AP8 AU34 XTALOUT VGA@
+3VSDGPU AW8 DBG_CNTL0 AR30 XTALOUT
1 AR3 NC#AW8 NC#AR30 AT29 VGA@ 1 VGA@ 1 1
+3VSDGPU NC#AR3 NC#AT29

1U_0402_6.3V6K
C829

10U_0603_6.3V6M
C830
AR1
AU1 NC#AR1 AV31 +MPLL_PVDD H7
T112 DBG_DATA0 NC#AV31 MPLL_PVDD

2
AU3 AU30 H8
T113 DBG_DATA1 DPB NC#AU30 MPLL_PVDD 2 2
R800 R801 T114
AW3
4.7K_0402_5% 4.7K_0402_5% Q54B VGA@ AP6 DBG_DATA2 AR32 AW34 XO_IN 1 @ 2
T115 DBG_DATA3 NC#AR32 XO_IN

5
VGA@ VGA@ DMN66D0LDW-7_SOT363-6 T118
AW5 AT31 0_0402_5% R799
AU5 DBG_DATA4 NC#AT31 +SPLL_PVDD AM10

PLLS/XTAL
T117
1

1
VGA_SMB_CK2 4 3 EC_SMB_CK2 AR6 DBG_DATA5 AT33 SPLL_PVDD L66
EC_SMB_CK2 35,7 T119
AW6 DBG_DATA6 NC#AT33 AU32
100mA
T121 MBK1608121YZF_0603
AU6 DBG_DATA7 NC#AU32 +SPLL_VDDC 2 1
T120 DBG_DATA8 +0.95VSDGPU

2
Q54A VGA@ T122
AT7 AU14 +SPLL_VDDC AN9 AW35 XO_IN2 2 @ 1 VGA@
DMN66D0LDW-7_SOT363-6 AV7 DBG_DATA9 NC#AU14 AV13 SPLL_VDDC XO_IN2 0_0402_5% R802
T124 DBG_DATA10 NC#AV13
VGA_SMB_DA2 1 6 EC_SMB_DA2 AN7 VGA@ 1 VGA@ 1
EC_SMB_DA2 35,7 T123 DBG_DATA11

1U_0402_6.3V6K
C832

10U_0603_6.3V6M
C833
AV9 AT15
T125 DBG_DATA12 NC#AT15
T127
AT9 AR14 SPLL_PVSS AN10
AR10 DBG_DATA13 NC#AR14 SPLL_PVSS
T126 DBG_DATA14 DPC 2 2
AW10 AU16 SPLL_PVSS
T128 DBG_DATA15 NC#AU16
AU10 AV15
T130 DBG_DATA16 NC#AV15
T129
AP10 AK10 T137
AV11 DBG_DATA17 AT17 AF30 CLKTESTA AL10
T131 DBG_DATA18 NC#AT17 NC_XTAL_PVDD CLKTESTB T138
T133
AT11 AR16 AF31
DBG_DATA19 NC#AR16 NC_XTAL_PVSS

0.1U_0402_16V4Z 51.1_0402_1%

0.1U_0402_16V4Z 51.1_0402_1%
T132
AR12 1 1
DBG_DATA20

C892

C891
T134
AW12 AU20 @ @ OPAL MLPS configuration
AU12 DBG_DATA21 NC#AU20 AT19
T136 DBG_DATA22 NC#AT19
AP12
T135 DBG_DATA23 AT21 2 2 Bits[5:1] PU(1%) PD(1%) Cap
NC#AT21 AR20
NC#AR20 2160842006A0MARSXT_FCBGA962
xx000 NC 4.75k

1
VGA_SMB_CK2 AJ23 DPD AU22 @
SMBCLK SMBus NC#AU22 xx001 8.45k 2.00k

R904

R841
VGA_SMB_DA2 AH23 AV21 @ @
SMBDATA NC#AV21
AT23
xx010 4.53k 2.00k
+3VSDGPU NC#AT23 AR22
Slave ID: 0x41 xx011 6.98k 4.99k

2
AK26 NC#AR22
AJ26 SCL I2C
2 SDA xx100 4.53k 4.99k 2
2

R409 AD39
100K_0402_5% R AD37
T154 xx101 3.24k 5.62k
GENERAL PURPOSE I/O
VGA@ GPU_DPRSLPVR AH20 AVSSN
49 GPU_DPRSLPVR AH18 GPIO_0 AE36
xx110 3.40k 10.0k
GPIO_1 G T156
D22 AN16 AD35
xx111 4.75k NC
1

1 2 GPU_ACIN_D GPIO_2 AVSSN

35 GPU_ACIN AUD[1:0]:
AF37 00 - No audio function
DB2J31400L_SOD323-2 GPU_ACIN_D AH17 B AE38
T155 00xxx 680nF
VGA@ GPU_VID_4 AJ17 GPIO_5_AC_BATT AVSSN
49 GPU_VID_4 AK17 GPIO_6_TACH DAC1 AC36 AUD_1 R803 1 @ 2 10K_0402_5%
01xxx 82nF
AJ13 GPIO_7_BLON HSYNC AC38 AUD_0 R804 1 2 10K_0402_5%
AH15 GPIO_8_ROMSO VSYNC @
10xxx 10nF
GPU_VID_5 AJ16 GPIO_9_ROMSI
49 GPU_VID_5 AK16 GPIO_10_ROMSCK AB34 RSET R805 1 OPAL@ 2 499_0402_1%
10mil 11xxx NC
AL16 GPIO_11 RSET (SUN NC) L67
AM16 GPIO_12 AD34 +AVDD 2 1
70mA
GPIO_13 AVDD +1.8VSDGPU
AM14 AE34 (SUN NC) OPAL@
GPIO_14_HPD2 AVSSQ

1U_0402_6.3V6K
C834

0.1U_0402_16V4Z
C835
GPU_VID_1 AM13 1 1 0_0603_5%
49 GPU_VID_1 AK14 GPIO_15_PWRCNTL_0 AC33
GPU_VID_3 +VDD1DI PS0_[1]=1 : same as GPIO_11 Since the frame buffer size is 512 MB
49 GPU_VID_3 AG30 GPIO_16 VDD1DI AC34
THM_ALERT# PS0_[2]=0 : same as GPIO_12 the aperture size is set to 256 MB.
AN14 GPIO_17_THERMAL_INT VSS1DI @ @
R806 10K_0402_5% 1 @ 2 GPIO_19_CTF AM17 GPIO_18_HPD3 (SUN NC) 2 2 PS0_[3]=0 : same as GPIO_13
GPU_VID_2 AL13 GPIO_19_CTF V13 PS0_[4]=1 : Reserved for internal use only. Must be 1
49 GPU_VID_2 AJ14 GPIO_20_PWRCNTL_1 NC#V13 U13 PS0_[5]=1 : AUD_PORT_CONN_PINSTRAP[0]
AK13 GPIO_21 NC#U13 AF33
AN13 GPIO_22_ROMCSB NC#AF33 AF32
10mil
CLKREQB NC#AF32
L68 100 - 512Kbit M25P05A (ST)
(GPIO1, 2, 7, 11, 12, 13, 18, 21 is NC at SUN) AA29 117mA 0_0603_5% 101 - 1Mbit M25P10A (ST)
NC#AA29 AG21 2 1
NC#AG21 +1.8VSDGPU 101 - 2Mbit M25P20 (ST)
AG32 AC32 OPAL@
AG33 GPIO_29 NC#AC32 101 - 4Mbit M25P40 (ST)
GPIO_30 1 1@

0.1U_0402_16V4Z
C837

1U_0402_6.3V6K
C838
AC31 @ 101 - 8Mbit M25P80 (ST)
AJ19 NC_SVI2#AC31 AD30
GENERICA NC_SVI2#AD30 100 - 512Kbit Pm25LV512 (Chingis)
AK19 AD32
AJ20 GENERICB NC_SVI2#AD32 2 2 101 - 1Mbit Pm25LV010 (Chingis)
AK20 GENERICC
3 3
AJ24 GENERICD
AH26 GENERICE_HPD4
GENERICF_HPD5
PS_1[1] = 0 : PCIeR GEN3 is not supported.
VREFG:Use a voltage divider to set AH24 PS_1[2] = 0 : Reserved for internal use only
GENERICG_HPD6
VREFG = 1.80 V / 3 (or 0.60-V nominal). PS_1[3] = 0 : Reserved for internal use only
AM34 PS_0
PS_0 PS_1[4] = 1 : TX_PWRS_ENB: Full Tx output swing.
AC30 PS_1[5] = 1 : TX_DEEMPH_EN: Tx deemphasis enabled.
CEC_1
+1.8VSDGPU R810 1 OPAL@ 2 499_0402_1% AK24 AD31 PS_1
HPD1 MLPS PS_1
20mil PS_2[1] = 0 : Reserved.
R811 1 OPAL@ 2 249_0402_1% PS_2[2] = 0 : Reserved.
C841 1 2 0.1U_0402_16V4Z +VGA_VREF AH13 AG31 PS_2 PS_2[3] = 0 : BIOS_ROM_EN :Disable the external BIOS ROM device.
OPAL@ (SUN NC) DBG_VREFG PS_2 PS_2[4] = 0 : VGA_DIS : 0=VGA controller capacity enabled.
PS_2[5] = 0 : Reserved.
Place VREFG divider and cap close to ASIC BACO
AL21 AD33 PS_3
PX_EN PS_3
2

Pull high @ VGA side PS_3[1] = x :

R813 PS_3[2] = x : VRAM ID
R814 0_0402_5% +VDDC_CT +VDDC_CT +VDDC_CT +VDDC_CT
+3VSDGPU 5.11K_0402_1% PS_3[3] = x :
@ DEBUG DDC/AUX PS_3[4] = 1 : AUD_PORT_CONN_PINSTRAP[1]
2 @ 1 AM26
1

DDC1CLK

1
AN26 PS_3[5] = 1 : AUD_PORT_CONN_PINSTRAP[2]
2 VGA@ 1 TESTEN AD28 DDC1DATA X76@ @ @ VGA@
VGA@ +3VSDGPU R817 1K_0402_5% TESTEN AM27 R812 R821 R816 R808
AUX1P AL27
R822
AUX1N
10K_0402_5% 10K_0402_5% 8.45K_0402_1% 8.45K_0402_1% ======= VRAM ID for JET =======
1M_0402_5% RP21 000 Hynix H5TC2G63FFR-11C x 4

2
XTALOUT 2 1 XTALIN 1 8 JTAG_TRSTB AM23 AM19 PS_0
2 7 JTAG_TDI AN23 JTAG_TRSTB DDC2CLK AL19 PS_1 001 Micron MT41J128M16JT-093G:K x 4
X2 3 6 JTAG_TCK AK23 JTAG_TDI DDC2DATA PS_2 010 SAM K4W2G1646Q-BC1A x 4
VGA@ 4 5 JTAG_TMS AL24 JTAG_TCK AN20 PS_3
Crystal AM24 JTAG_TMS AUX2P AM20
3 4 JTAG_TDO AUX2N
OUT GND
10K_0804_8P4R_5% T18 @ @ @ @ @ ======= VRAM ID for OPAL =======

1
@ AL30 1 1 1 1 000 Hynix H5TC2G63FFR-11C x 8
NC#AL30
0.1U_0402_16V7K
C842

0.01U_0402_16V7K
C847

0.1U_0402_16V7K
C843

0.1U_0402_16V7K
C840
2 1 AM30 X76@
4 GND IN NC#AM30 R815 R823 R818 R809 001 Micron MT41J128M16JT-093G:K x 8 4
2 2
THERMAL AL29 10K_0402_5% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1% 010 SAM K4W2G1646Q-BC1A x 8
C848 27MHZ_10PF_X3G027000BA1H-U C849 +3VSDGPU GPU_THERM_D+ AF29 NC#AL29 AM29 2 2 2 2 VGA@ VGA@ VGA@ 011 Hynix H5TC4G63AFR-11C x 4

2
10P_0402_50V8J GPU_THERM_D- AG29 DPLUS NC#AM29
1
10P_0402_50V8J
1 VGA@ DMINUS 100 Micron MT41J256M16HA-093G:E x 4
VGA@ 1 @ 2 AN21
R819 10K_0402_5% NC#AN21 AM21 101 SAM K4W4G1646D-BC1A x 4
1 VGA@ 2 MLPS_EN# AK32 NC#AM21
R820 10K_0402_5% GPIO_28_FDO AK30
AL31 NC#AK30 AK29
+1.8VSDGPU TS_A NC#AK29
Crystals must have a max ESR of 80 ohm
L69 @ 13mA 10mil AJ30 Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 0_0603_5% +TSVDD AJ32 DDCVGACLK AJ31 2012/09/12 2013/07/10 Title
AJ33 TSVDD
TSVSS
DDCVGADATA Issued Date Deciphered Date OPAL-Pro_STRAP
10U_0603_6.3V6M 2 1 @ C844
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1U_0402_6.3V6K 2 1 @ C845 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1U_0402_16V4Z 2 1 VGA@ C846 2160842006A0MARSXT_FCBGA962 Custom 0.2
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
Date: Wednesday, February 12, 2014 Sheet 14 of 52
A B C D E

I'm from VIETNAM sualaptop365

 A B C D E

U51D MAA[0..15]
MAA[0..15] 18
U51C
PART 4 0F 9 DQMA#[0..7]
PART 3 0F 9 MDB[0..63] DQMA#[0..7] 18
MDA[0..63] 19 MDB[0..63] GDDR5/DDR3 QSA[0..7]
GDDR5/DDR3 MDB0 C5 P8 MAB0
18 MDA[0..63] DQB0_0 MAB0_0/MAB_0 QSA[0..7] 18
MDA0 C37 G24 MAA0 MDB1 C3 T9 MAB1
MDA1 C35 DQA0_0 MAA0_0/MAA_0 J23 MAA1 MDB2 E3 DQB0_1 MAB0_1/MAB_1 P9 MAB2 QSA#[0..7]
DQA0_1 MAA0_1/MAA_1 DQB0_2 MAB0_2/MAB_2 QSA#[0..7] 18
(SUN 64 bin on at Channel B) MDA2 A35 H24 MAA2 MDB3 E1 N7 MAB3
MDA3 E34 DQA0_2 MAA0_2/MAA_2 J24 MAA3 MDB4 F1 DQB0_3 MAB0_3/MAB_3 N8 MAB4
MDA4 G32 DQA0_3 MAA0_3/MAA_3 H26 MAA4 MDB5 F3 DQB0_4 MAB0_4/MAB_4 N9 MAB5
DQA0_4 MAA0_4/MAA_4 DQB0_5 MAB0_5/MAB_5

MEMORY INTERFACE A
MDA5 D33 J26 MAA5 MDB6 F5 U9 MAB6
MDA6 F32 DQA0_5 MAA0_5/MAA_5 H21 MAA6 MDB7 G4 DQB0_6 MAB0_6/MAB_6 U8 MAB7 MAB[0..15]
DQA0_6 MAA0_6/MAA_6 DQB0_7 MAB0_7/MAB_7 MAB[0..15] 19
MDA7 E32 G21 MAA7 MDB8 H5 Y9 MAB8
1
MDA8 D31 DQA0_7 MAA0_7/MAA_7 H19 MAA8 MDB9 H6 DQB0_8 MAB1_0/MAB_8 W9 MAB9 DQMB#[0..7] 1
DQA0_8 MAA1_0/MAA_8 DQB0_9 MAB1_1/MAB_9 DQMB#[0..7] 19
MDA9 F30 H20 MAA9 MDB10 J4 AC8 MAB10
MDA10 C30 DQA0_9 MAA1_1/MAA_9 L13 MAA10 MDB11 K6 DQB0_10 MAB1_2/MAB_10 AC9 MAB11 QSB[0..7]
DQA0_10 MAA1_2/MAA_10 DQB0_11 MAB1_3/MAB_11 QSB[0..7] 19
MDA11 A30 G16 MAA11 MDB12 K5 AA7 MAB12
MDA12 F28 DQA0_11 MAA1_3/MAA_11 J16 MAA12 MDB13 L4 DQB0_12 MAB1_4/MAB_12 AA8 B_BA2 QSB#[0..7]

MEMORY INTERFACE B
DQA0_12 MAA1_4/MAA_12 DQB0_13 MAB1_5/BA2 B_BA2 19 QSB#[0..7] 19
MDA13 C28 H16 A_BA2 MDB14 M6 Y8 B_BA0
+1.5VSDGPU DQA0_13 MAA1_5/MAA_BA2 A_BA2 18 DQB0_14 MAB1_6/BA0 B_BA0 19
MDA14 A28 J17 A_BA0 MDB15 M1 AA9 B_BA1
DQA0_14 MAA1_6/MAA_BA0 A_BA0 18 DQB0_15 MAB1_7/BA1 B_BA1 19
MDA15 E28 H17 A_BA1 MDB16 M3
DQA0_15 MAA1_7/MAA_BA1 A_BA1 18 DQB0_16
MDA16 D27 MDB17 M5 H3 DQMB#0
MDA17 F26 DQA0_16 A32 DQMA#0 MDB18 N4 DQB0_17 W CKB0_0/DQMB_0 H1 DQMB#1
DQA0_17 W CKA0_0/DQMA_0 DQB0_18 W CKB0B_0/DQMB_1
1

MDA18 C26 C32 DQMA#1 MDB19 P6 T3 DQMB#2

R825 MDA19 A26 DQA0_18 W CKA0B_0/DQMA_1 D23 DQMA#2 MDB20 P5 DQB0_19 W CKB0_1/DQMB_2 T5 DQMB#3
MDA20 F24 DQA0_19 W CKA0_1/DQMA_2 E22 DQMA#3 MDB21 R4 DQB0_20 W CKB0B_1/DQMB_3 AE4 DQMB#4
40.2_0402_1% MDA21 C24 DQA0_20 W CKA0B_1/DQMA_3 C14 DQMA#4 MDB22 T6 DQB0_21 W CKB1_0/DQMB_4 AF5 DQMB#5
OPAL@
15mil MDA22 A24 DQA0_21 W CKA1_0/DQMA_4 A14 DQMA#5 MDB23 T1 DQB0_22 W CKB1B_0/DQMB_5 AK6 DQMB#6 +1.5VSDGPU
2

MVREFDA MDA23 E24 DQA0_22 W CKA1B_0/DQMA_5 E10 DQMA#6 MDB24 U4 DQB0_23 W CKB1_1/DQMB_6 AK5 DQMB#7
MDA24 C22 DQA0_23 W CKA1_1/DQMA_6 D9 DQMA#7 MDB25 V6 DQB0_24 W CKB1B_1/DQMB_7
DQA0_24 W CKA1B_1/DQMA_7 DQB0_25
1

1 OPAL@ MDA25 A22 MDB26 V1 F6 QSB0

DQA0_25 DQB0_26 EDCB0_0/QSB_0

1
1U_0402_6.3V6K
C850

R826 MDA26 F22 C34 QSA0 MDB27 V3 K3 QSB1

MDA27 D21 DQA0_26 EDCA0_0/QSA_0 D29 QSA1 MDB28 Y6 DQB0_27 EDCB0_1/QSB_1 P3 QSB2 R824
100_0402_1% MDA28 A20 DQA0_27 EDCA0_1/QSA_1 D25 QSA2 MDB29 Y1 DQB0_28 EDCB0_2/QSB_2 V5 QSB3 VGA@
OPAL@ 2 MDA29 F20 DQA0_28 EDCA0_2/QSA_2 E20 QSA3 MDB30 Y3 DQB0_29 EDCB0_3/QSB_3 AB5 QSB4 40.2_0402_1% 15mil
2

MDA30 D19 DQA0_29 EDCA0_3/QSA_3 E16 QSA4 MDB31 Y5 DQB0_30 EDCB1_0/QSB_4 AH1 QSB5

2
MDA31 E18 DQA0_30 EDCA1_0/QSA_4 E12 QSA5 MDB32 AA4 DQB0_31 EDCB1_1/QSB_5 AJ9 QSB6 MVREFDB
MDA32 C18 DQA0_31 EDCA1_1/QSA_5 J10 QSA6 MDB33 AB6 DQB1_0 EDCB1_2/QSB_6 AM5 QSB7
DQA1_0 EDCA1_2/QSA_6 DQB1_1 EDCB1_3/QSB_7

1
MDA33 A18 D7 QSA7 MDB34 AB1
DQA1_1 EDCA1_3/QSA_7 DQB1_2
1

MDA34 F18 MDB35 AB3 G7 QSB#0 1 VGA@

+1.5VSDGPU DQA1_2 DQB1_3 DDBIB0_0/QSB_0B

1U_0402_6.3V6K
C851
R900 MDA35 D17 A34 QSA#0 MDB36 AD6 K1 QSB#1 R827 VGA@
0_0402_5% MDA36 A16 DQA1_3 DDBIA0_0/QSA_0B E30 QSA#1 MDB37 AD1 DQB1_4 DDBIB0_1/QSB_1B P1 QSB#2 100_0402_1%
@ MDA37 F16 DQA1_4 DDBIA0_1/QSA_1B E26 QSA#2 MDB38 AD3 DQB1_5 DDBIB0_2/QSB_2B W4 QSB#3
2 2

2
MDA38 D15 DQA1_5 DDBIA0_2/QSA_2B C20 QSA#3 MDB39 AD5 DQB1_6 DDBIB0_3/QSB_3B AC4 QSB#4 2
2

DQA1_6 DDBIA0_3/QSA_3B DQB1_7 DDBIB1_0/QSB_4B

1

MDA39 E14 C16 QSA#4 MDB40 AF1 AH3 QSB#5

R828 MDA40 F14 DQA1_7 DDBIA1_0/QSA_4B C12 QSA#5 MDB41 AF3 DQB1_8 DDBIB1_1/QSB_5B AJ8 QSB#6
MDA41 D13 DQA1_8 DDBIA1_1/QSA_5B J11 QSA#6 MDB42 AF6 DQB1_9 DDBIB1_2/QSB_6B AM3 QSB#7
DQA1_9 DDBIA1_2/QSA_6B DQB1_10 DDBIB1_3/QSB_7B

1
40.2_0402_1% 15mil MDA42 F12 F8 QSA#7 MDB43 AG4
OPAL@ MDA43 A12 DQA1_10 DDBIA1_3/QSA_7B MDB44 AH5 DQB1_11 T7 ODTB0 R901
ODTB0 19
2

MVREFSA MDA44 D11 DQA1_11 J21 ODTA0 MDB45 AH6 DQB1_12 ADBIB0/ODTB0 W7 ODTB1 0_0402_5%
DQA1_12 ADBIA0/ODTA0 ODTA0 18 DQB1_13 ADBIB1/ODTB1 ODTB1 19 +1.5VSDGPU
MDA45 F10 G19 ODTA1 MDB46 AJ4 @
DQA1_13 ADBIA1/ODTA1 ODTA1 18 DQB1_14
1

1 OPAL@ MDA46 A10 MDB47 AK3 L9 CLKB0

CLKB0 19

2
DQA1_14 DQB1_15 CLKB0
1U_0402_6.3V6K
C852

R830 MDA47 C10 H27 CLKA0 MDB48 AF8 L8 CLKB0#

DQA1_15 CLKA0 CLKA0 18 DQB1_16 CLKB0B CLKB0# 19
MDA48 G13 G27 CLKA0# MDB49 AF9
DQA1_16 CLKA0B CLKA0# 18 DQB1_17

1
100_0402_1% MDA49 H13 MDB50 AG8 AD8 CLKB1
2 DQA1_17 DQB1_18 CLKB1 CLKB1 19
OPAL@ MDA50 J13 J14 CLKA1 MDB51 AG7 AD7 CLKB1# R829
CLKA1 18 CLKB1# 19
2

MDA51 H11 DQA1_18 CLKA1 H14 CLKA1# MDB52 AK9 DQB1_19 CLKB1B VGA@
DQA1_19 CLKA1B CLKA1# 18 DQB1_20
MDA52 G10 MDB53 AL7 T10 RASB0# 40.2_0402_1% 15mil
DQA1_20 DQB1_21 RASB0B RASB0# 19
MDA53 G8 K23 RASA0# MDB54 AM8 Y10 RASB1#
RASA0# 18 RASB1# 19

2
MDA54 K9 DQA1_21 RASA0B K19 RASA1# MDB55 AM7 DQB1_22 RASB1B MVREFSB
DQA1_22 RASA1B RASA1# 18 DQB1_23
MDA55 K10 MDB56 AK1 W 10 CASB0#
DQA1_23 DQB1_24 CASB0B CASB0# 19

1
MDA56 G9 K20 CASA0# MDB57 AL4 AA10 CASB1# 1 VGA@
DQA1_24 CASA0B CASA0# 18 DQB1_25 CASB1B CASB1# 19

1U_0402_6.3V6K
C853
MDA57 A8 K17 CASA1# MDB58 AM6 R831
DQA1_25 CASA1B CASA1# 18 DQB1_26
MDA58 C8 MDB59 AM1 P10 CSB0# VGA@
DQA1_26 DQB1_27 CSB0B_0 CSB0# 19
MDA59 E8 K24 CSA0# MDB60 AN4 L10 100_0402_1%
DQA1_27 CSA0B_0 CSA0# 18 DQB1_28 CSB0B_1 2
MDA60 A6 K27 MDB61 AP3

2
MDA61 C6 DQA1_28 CSA0B_1 MDB62 AP1 DQB1_29 AD10 CSB1#
DQA1_29 DQB1_30 CSB1B_0 CSB1# 19
MDA62 E6 M13 CSA1# MDB63 AP5 AC10
DQA1_30 CSA1B_0 CSA1# 18 DQB1_31 CSB1B_1
MDA63 A5 K16
DQA1_31 CSA1B_1 U10 CKEB0
CKEB0 CKEB0 19
MVREFDA L18 K21 CKEA0 MVREFDB Y12 AA11 CKEB1
MVREFDA CKEA0 CKEA0 18 MVREFDB CKEB1 CKEB1 19
MVREFSA L20 J20 CKEA1 MVREFSB AA12
3 MVREFSA CKEA1 CKEA1 18 MVREFSB 3
N10 WEB0#
W EB0B WEB0# 19
L27 K26 WEA0# AB11 WEB1#
NC#L27 W EA0B WEA0# 18 W EB1B WEB1# 19
N12 L15 WEA1#
NC#N12 W EA1B WEA1# 18
AG12
NC#AG12 T8 MAB13
H23 MAA13 MAB0_8/MAB_13 W8 MAB14
R835 1 VGA@ 2 MEM_CALRP0 M27 MAA0_8/MAA_13 J19 MAA14 MAB1_8/MAB_14 U12 MAB15
120_0402_1% MEM_CALRP0 MAA1_8/MAA_14 M21 MAA15 MAB0_9/MAB_15 V12
M12 MAA0_9/MAA_15 M20 MAB1_9/RSVD
AH12 NC#M12 MAA1_9/RSVD AH11 1 2 1 2
NC#AH12 DRAM_RST VRAM_RST# 18,19
VGA@ VGA@
R838 R839

2
10_0402_5% 1 VGA@ 51.1_0402_1%
2160842006A0MARSXT_FCBGA962 VGA@ C854
@ R840 120P_0402_50V8
2160842006A0MARSXT_FCBGA962 4.99K_0402_1%
@ 2

1
Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2

The suggested components are tested on the AMD

reference board only. Customers must measure the slew
on each memory part to ensure that the slew rate meets
4 the DRAM specification. 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2012/09/12 2013/07/10 Title
Issued Date Deciphered Date OPAL-Pro_MEMORY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z5WAK M/B LA-B221P
Date: Wednesday, February 12, 2014 Sheet 15 of 52
I'm from VIETNAM
A
sualaptop365
B C D E
 A B C D E

U51E
PART 5 0F 9

1.5A AC7
MEM I/O
AA31
+1.5VSDGPU
VGA@ @ VGA@ @ VGA@ AD11 VDDR1 NC#AA31 AA32
20mil
VDDR1 NC#AA32 +1.8VSDGPU

0.01U_0402_16V7K
C856

0.01U_0402_16V7K
C857

0.01U_0402_16V7K
C858

0.01U_0402_16V7K
C859

0.01U_0402_16V7K
C860
1 1 1 1 1 AF7 AA33 VGA@ @ @
AG10 VDDR1 NC#AA33 AA34
VDDR1 NC#AA34 1 1 1

1U_0402_6.3V6K
C861

1U_0402_6.3V6K
C862

10U_0603_6.3V6M
C863
AJ7 W30 NC For Mars
AK8 VDDR1 NC#W30 Y31
2 2 2 2 2 AL9 VDDR1 NC#Y31 V28
G11 VDDR1 NC_BIF_VDDC W29 2 2 2
G14 VDDR1 NC_BIF_VDDC AB37
100mA

PCIE
G17 VDDR1 PCIE_PVDD
G20 VDDR1 G30
1 1
VGA@ @ VGA@ @ VGA@ G23 VDDR1 PCIE_VDDC G31
VDDR1 PCIE_VDDC +0.95VSDGPU

0.1U_0402_16V4Z
C864

0.1U_0402_16V4Z
C865

0.1U_0402_16V4Z
C866

0.1U_0402_16V4Z
C867

0.1U_0402_16V4Z
C868
1 1 1 1 1 G26 H29 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
G29 VDDR1 PCIE_VDDC H30
VDDR1 PCIE_VDDC 2.5A 100mil 1 1 1 1 1 1

1U_0402_6.3V6K
C869

1U_0402_6.3V6K
C872

1U_0402_6.3V6K
C873

1U_0402_6.3V6K
C874

1U_0402_6.3V6K
C875

10U_0603_6.3V6M
C876
H10 J29
J7 VDDR1 PCIE_VDDC J30
2 2 2 2 2 J9 VDDR1 PCIE_VDDC L28
K11 VDDR1 PCIE_VDDC M28 2 2 2 2 2 2
K13 VDDR1 PCIE_VDDC N28
K8 VDDR1 PCIE_VDDC R28
L12 VDDR1 PCIE_VDDC T28
VGA@ VGA@ VGA@ @ @ VGA@ VGA@ VGA@ L16 VDDR1 PCIE_VDDC U28
VDDR1 PCIE_VDDC

2.2U_0402_6.3V6M
C880

2.2U_0402_6.3V6M
C881

2.2U_0402_6.3V6M
C882

2.2U_0402_6.3V6M
C883

2.2U_0402_6.3V6M
C884
1 1 1 1 1 1 1 1 L21
VDDR1

10U_0603_6.3V6M
C877

10U_0603_6.3V6M
C878

10U_0603_6.3V6M
C879
L23
L26 VDDR1 N27
L7 VDDR1 BACO BIF_VDDC T27
1.4A 60mil
2 2 2 2 2 2 2 2 VDDR1 BIF_VDDC +0.95VSDGPU
M11 VGA@ VGA@ VGA@
N11 VDDR1
VDDR1 1 1 1

1U_0402_6.3V6K
C890

1U_0402_6.3V6K
C889

10U_0603_6.3V6M
C888
P7 AA15 +VGA_CORE
R11 VDDR1 CORE VDDC AA17
U11 VDDR1 VDDC AA20
U7 VDDR1 VDDC AA22
30A (TBD) 2 2 2
Y11 VDDR1 VDDC AA24
Y7 VDDR1 VDDC AA27
VDDR1 VDDC AB16
VDDC AB18
VDDC AB21
VDDC AB23
+VDDC_CT VDDC AB26
20mil 13mA LEVEL VDDC
Must always be connected to PCIE_VDDC.
TRANSLATION AB28 0.95 V for "Mars" and
12 +VDDC_CT AF26 VDDC AC17
+1.8VSDGPU VDD_CT VDDC "Heathrow"/"Chelsea" on both BACO and
L70 VGA@ VGA@ AF27 AC20
VDD_CT VDDC non-BACO designs.

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z
MBK1608121YZF_0603 1 1 1 AG26 AC22
@ AG27 VDD_CT VDDC AC24
VGA@ VDD_CT VDDC

C885

C886

C887
AC27
2 VDDC AD18 2
2 2 2 10mil 25mA VDDC AD21
I/O
+VDDR3 AF23 VDDC AD23
AF24 VDDR3 VDDC AD26
AG23 VDDR3 VDDC AF17
2 1 AG24 VDDR3 VDDC AF20
+3VSDGPU VDDR3 VDDC
L71 @ VGA@ VGA@ AF22
VDDC

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z
MBK1608121YZF_0603 1 1 1 300mA DVP AG16
VDDC

C896

C897

C898
VGA@ AD12 AG18
AF11 VDDR4 VDDC
AF12 VDDR4 AH22
2 2 2 AF13 VDDR4 VDDC AH27
VDDR4 VDDC AH28
VDDC M26
AF15 VDDC N24
AG11 VDDR4 VDDC R18
20mil AG13 VDDR4 VDDC R21
2 1 +VDDR4 AG15 VDDR4 VDDC R23
+1.8VSDGPU VDDR4 VDDC
L72 OPAL@ OPAL@ R26
VDDC
0.1U_0402_16V4Z

MBK1608121YZF_0603 1 1 1 (SUN NC) T17

VDDC
10U_0603_6.3V6M
C907

1U_0402_6.3V6K
C908

C899

@ T20
OPAL@ VDDC T22
VDDC T24
2 2 2 VDDC U16
VDDC U18
VDDC U21
VDDC U23
VDDC U26
VDDC V17
VDDC V20
VDDC V22
VDDC V24
VDDC V27
VDDC Y16
VDDC Y18
3 3
VDDC Y21
VDDC Y23
VDDC Y26
VDDC Y28
VDDC
AA13
VDDCI AB13
360mil
VDDCI +VGA_CORE
AC12
VDDCI AC15 VGA@ VGA@ VGA@
VDDCI AD13
3.5A (DDR3)
VDDCI

0.1U_0402_16V4Z
C917

0.1U_0402_16V4Z
C918

0.1U_0402_16V4Z
C919
AD16 1 1 1
VDDCI M15
VDDCI M16
VDDCI M18
VOLTAGE VDDCI M23 2 2 2
ISOLATED

10mil SENESE VDDCI

CORE I/O

N13
VCC_GPU_SENSE AF28 VDDCI N15
49 VCC_GPU_SENSE FB_VDDC VDDCI N17
VDDCI N20
AG28 VDDCI N22
T139 FB_VDDCI VDDCI R12
VDDCI R13
VSS_GPU_SENSE AH29 VDDCI R16
49 VSS_GPU_SENSE FB_GND VDDCI T12
VDDCI T15
VDDCI V15
VDDCI
1

Y13
@ VDDCI
R842
0_0402_5% 2160842006A0MARSXT_FCBGA962
@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2012/09/12 2013/07/10 Title
Issued Date Deciphered Date OPAL-Pro_PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
Date: Wednesday, February 12, 2014 Sheet 16 of 52

I'm from VIETNAM sualaptop365

A B C D E
 A B C D E

U51F
PART 6 0F 9

AB39 A3
E39 PCIE_VSS GND A37
F34 PCIE_VSS GND AA16
F39 PCIE_VSS GND AA18
G33 PCIE_VSS GND AA2
G34 PCIE_VSS GND AA21
H31 PCIE_VSS GND AA23
H34 PCIE_VSS GND AA26
H39 PCIE_VSS GND AA28
J31 PCIE_VSS GND AA6
1 J34 PCIE_VSS GND AB12 1
K31 PCIE_VSS GND AB15
K34 PCIE_VSS GND AB17
K39 PCIE_VSS GND AB20
L31 PCIE_VSS GND AB22
L34 PCIE_VSS GND AB24
M34 PCIE_VSS GND AB27
M39 PCIE_VSS GND AC11
N31 PCIE_VSS GND AC13
N34 PCIE_VSS GND AC16
P31 PCIE_VSS GND AC18
P34 PCIE_VSS GND AC2
P39 PCIE_VSS GND AC21
R34 PCIE_VSS GND AC23
T31 PCIE_VSS GND AC26
T34 PCIE_VSS GND AC28
T39 PCIE_VSS GND AC6 U51H
U31 PCIE_VSS GND AD15
U34 PCIE_VSS GND AD17 PART 8 0F 9
V34 PCIE_VSS GND AD20
V39 PCIE_VSS GND AD22 DP_VDDR DP_VDDC
W31 PCIE_VSS GND AD24 AP31
20mil
W34 PCIE_VSS GND AD27 DP_VDDC AP32
PCIE_VSS GND DP_VDDC +0.95VSDGPU
Y34 AD9 AN33
Y39 PCIE_VSS GND AE2 DP_VDDC AP33
PCIE_VSS GND AE6 AN24 DP_VDDC AL33
280mA
GND NC#AN24 DP_VDDC 1 VGA@ 1 VGA@ 1 VGA@

0.1U_0402_16V4Z
C927

1U_0402_6.3V6K
C928

10U_0603_6.3V6M
C929
AF10 AP24 AM33
GND AF16 AP25 NC#AP24 DP_VDDC AK33
GND AF18 AP26 NC#AP25 DP_VDDC AK34
GND AF21 AU28 NC#AP26 DP_VDDC AN31 2 2 2
GND GND NC#AU28 DP_VDDC
AG17 AV29
F15 GND AG2 NC#AV29
2 F17 GND GND AG20 2
F19 GND GND AP20 AP13
F21 GND AG6 AP21 NC#AP20 NC#AP13 AT13
F23 GND GND AG9 AP22 NC#AP21 NC#AT13 AP14
F25 GND GND AH21 AP23 NC#AP22 NC#AP14 AP15
F27 GND GND AJ10 AU18 NC#AP23 NC#AP15
F29 GND GND AJ11 AV19 NC#AU18
F31 GND GND AJ2 NC#AV19 DP GND
F33 GND GND AJ28 AN27
F7 GND GND AJ6 AH34 DP_VSSR AP27
F9 GND GND AK11 AJ34 DP_VDDR DP_VSSR AP28
G2 GND GND AK31 AF34 DP_VDDR DP_VSSR AW24
G6 GND GND AK7 AG34 DP_VDDR DP_VSSR AW26
H9 GND GND AL11 AM37 DP_VDDR DP_VSSR AN29
J2 GND GND AL14
237mA AL38 DP_VDDR DP_VSSR AP29
J27 GND GND AL17 AM32 DP_VDDR DP_VSSR AP30
GND GND +1.8VSDGPU DP_VDDR DP_VSSR
J6 AL2 @ VGA@ VGA@ AW30
GND GND DP_VSSR

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z
J8 AL20 1 1 1 AW32
GND GND DP_VSSR

C936

C937

C938
K14 AN17
K7 GND AL23 DP_VSSR AP16
L11 GND GND AL26 DP_VSSR AP17
L17 GND GND AL32 2 2 2 DP_VSSR AW14
L2 GND GND AL6 DP_VSSR AW16
L22 GND GND AL8 DP_VSSR AN19
L24 GND GND AM11 DP_VSSR AP18
L6 GND GND AM31 DP_VSSR AP19
M17 GND GND AM9 DP_VSSR AW20
M22 GND GND AN11 CALIBRATION DP_VSSR AW22
M24 GND GND AN2 DP_VSSR AN34
N16 GND GND AN30 DP_VSSR AP39
N18 GND GND AN6 AW28 DP_VSSR AR39
N2 GND GND AN8 NC#AW28 DP_VSSR AU37
3 N21 GND GND AP11 DP_VSSR AF39 3
N23 GND GND AP7 DP_VSSR AH39
N26 GND GND AP9 AW18 DP_VSSR AK39
N6 GND GND AR5 NC#AW18 DP_VSSR AL34
R15 GND GND B11 R845 DP_VSSR AV27
R17 GND GND B13 150_0402_1% DP_VSSR AR28
R2 GND GND B15 2 OPAL@ 1 AM39 DP_VSSR AV17
R20 GND GND B17 DP_CALR DP_VSSR AR18
R22 GND GND B19 DP_VSSR AN38
R24 GND GND B21 DP_VSSR AM35
R27 GND GND B23 DP_VSSR AN32
R6 GND GND B25 DP_VSSR
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9 2160842006A0MARSXT_FCBGA962
T26 GND GND C1 @
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND GND
U27 GND
U6 GND
V11 GND AG22
V16 GND NC#AG22
V18 GND
V21 GND
V23 GND
4 V26 GND 4
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND A39
Y24 GND VSS_MECH AW1
Y27 GND VSS_MECH AW39 Security Classification Compal Secret Data Compal Electronics, Inc.
GND VSS_MECH
2012/09/12 2013/07/10 Title
Issued Date Deciphered Date OPAL-Pro_PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2160842006A0MARSXT_FCBGA962 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
@ Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 17 of 52
A B C D E
 A B C D E

U54 U55 U56 U57

VREFCA_A1 M8 E3 MDA23 VREFDA_Q1 M8 E3 MDA25 VREFCA_A3 M8 E3 MDA35 VREFDA_Q3 M8 E3 MDA48

VREFDA_Q1 H1 VREFCA DQL0 F7 MDA19 VREFCA_A1 H1 VREFCA DQL0 F7 MDA30 VREFDA_Q3 H1 VREFCA DQL0 F7 MDA32 VREFCA_A3 H1 VREFCA DQL0 F7 MDA51
VREFDQ DQL1 F2 MDA22 VREFDQ DQL1 F2 MDA24 VREFDQ DQL1 F2 MDA38 VREFDQ DQL1 F2 MDA55
MAA0 N3 DQL2 F8 MDA18 MAA0 N3 DQL2 F8 MDA29 MAA0 N3 DQL2 F8 MDA34 MAA0 N3 DQL2 F8 MDA54 X76
MAA1 P7 A0 DQL3 H3 MDA21 MAA1 P7 A0 DQL3 H3 MDA26 MAA1 P7 A0 DQL3 H3 MDA37 MAA1 P7 A0 DQL3 H3 MDA50 ZZZ1
MAA2 P3 A1 DQL4 H8 MDA16 MAA2 P3 A1 DQL4 H8 MDA31 MAA2 P3 A1 DQL4 H8 MDA36 MAA2 P3 A1 DQL4 H8 MDA52
MAA3 N2 A2 DQL5 G2 MDA20 MAA3 N2 A2 DQL5 G2 MDA27 MAA3 N2 A2 DQL5 G2 MDA39 MAA3 N2 A2 DQL5 G2 MDA49
MAA4 P8 A3 DQL6 H7 MDA17 MAA4 P8 A3 DQL6 H7 MDA28 MAA4 P8 A3 DQL6 H7 MDA33 MAA4 P8 A3 DQL6 H7 MDA53
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5
MAA[0..15] MAA7 R2 A6 D7 MDA0 MAA7 R2 A6 D7 MDA14 MAA7 R2 A6 D7 MDA43 MAA7 R2 A6 D7 MDA63
15 MAA[0..15] A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0 X76
MAA8 T8 C3 MDA5 MAA8 T8 C3 MDA11 MAA8 T8 C3 MDA44 MAA8 T8 C3 MDA58 X76550BOL41
MDA[0..63] MAA9 R3 A8 DQU1 C8 MDA1 MAA9 R3 A8 DQU1 C8 MDA12 MAA9 R3 A8 DQU1 C8 MDA40 MAA9 R3 A8 DQU1 C8 MDA60 HYN1G@
1 15 MDA[0..63] MAA10 L7 A9 DQU2 C2 MDA7 MAA10 L7 A9 DQU2 C2 MDA10 MAA10 L7 A9 DQU2 C2 MDA45 MAA10 L7 A9 DQU2 C2 MDA59 1
DQMA#[0..7] MAA11 R7 A10/AP DQU3 A7 MDA3 MAA11 R7 A10/AP DQU3 A7 MDA13 MAA11 R7 A10/AP DQU3 A7 MDA42 MAA11 R7 A10/AP DQU3 A7 MDA61 ZZZ2
15 DQMA#[0..7] MAA12 N7 A11 DQU4 A2 MDA4 MAA12 N7 A11 DQU4 A2 MDA9 MAA12 N7 A11 DQU4 A2 MDA46 MAA12 N7 A11 DQU4 A2 MDA56
QSA[0..7] MAA13 T3 A12 DQU5 B8 MDA2 MAA13 T3 A12 DQU5 B8 MDA15 MAA13 T3 A12 DQU5 B8 MDA41 MAA13 T3 A12 DQU5 B8 MDA62
15 QSA[0..7] MAA14 T7 A13 DQU6 A3 MDA6 MAA14 T7 A13 DQU6 A3 MDA8 MAA14 T7 A13 DQU6 A3 MDA47 MAA14 T7 A13 DQU6 A3 MDA57
QSA#[0..7] MAA15 M7 A14 DQU7 MAA15 M7 A14 DQU7 MAA15 M7 A14 DQU7 MAA15 M7 A14 DQU7
15 QSA#[0..7] A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU
X76
M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 X76550BOL42
15 A_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9
A_BA1 A_BA1 A_BA1 MRN1G@
15 A_BA1 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7
15 A_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 ZZZ3
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
CLKA0 J7 VDD N9 CLKA0 J7 VDD N9 CLKA1 J7 VDD N9 CLKA1 J7 VDD N9
CLKA0# K7 CK VDD R1 CLKA0# K7 CK VDD R1 CLKA1# K7 CK VDD R1 CLKA1# K7 CK VDD R1
K9 CK VDD R9 CKEA0 K9 CK VDD R9 K9 CK VDD R9 CKEA1 K9 CK VDD R9
15 CKEA0 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU 15 CKEA1 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU X76
X76550BOL43
ODTA0 K1 A1 ODTA0 K1 A1 ODTA1 K1 A1 ODTA1 K1 A1 SAM1G@
15 ODTA0 L2 ODT/ODT0 VDDQ A8 L2 ODT/ODT0 VDDQ A8 15 ODTA1 L2 ODT/ODT0 VDDQ A8 L2 ODT/ODT0 VDDQ A8
CSA0# CSA1#
15 CSA0# J3 CS/CS0 VDDQ C1 RASA0# J3 CS/CS0 VDDQ C1 15 CSA1# J3 CS/CS0 VDDQ C1 RASA1# J3 CS/CS0 VDDQ C1 ZZZ4
15 RASA0# K3 RAS VDDQ C9 CASA0# K3 RAS VDDQ C9 15 RASA1# K3 RAS VDDQ C9 CASA1# K3 RAS VDDQ C9
15 CASA0# L3 CAS VDDQ D2 WEA0# L3 CAS VDDQ D2 15 CASA1# L3 CAS VDDQ D2 WEA1# L3 CAS VDDQ D2
15 WEA0# WE VDDQ E9 WE VDDQ E9 15 WEA1# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA2 F3 VDDQ H2 QSA3 F3 VDDQ H2 QSA4 F3 VDDQ H2 QSA6 F3 VDDQ H2
QSA0 C7 DQSL VDDQ H9 QSA1 C7 DQSL VDDQ H9 QSA5 C7 DQSL VDDQ H9 QSA7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ X76
X76550BOL44
HYN2G@
DQMA#2 E7 A9 DQMA#3 E7 A9 DQMA#4 E7 A9 DQMA#6 E7 A9
DQMA#0 D3 DML VSS B3 DQMA#1 D3 DML VSS B3 DQMA#5 D3 DML VSS B3 DQMA#7 D3 DML VSS B3 ZZZ5
2 DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1 2
VSS G8 VSS G8 VSS G8 VSS G8
QSA#2 G3 VSS J2 QSA#3 G3 VSS J2 QSA#4 G3 VSS J2 QSA#6 G3 VSS J2
QSA#0 B7 DQSL VSS J8 QSA#1 B7 DQSL VSS J8 QSA#5 B7 DQSL VSS J8 QSA#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS VSS VSS VSS X76
P1 P1 P1 P1 X76550BOL45
VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 MRN2G@
15,19 VRAM_RST# RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9 ZZZ6
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
R846 L1 NC/ODT1 VSSQ B9 R847 L1 NC/ODT1 VSSQ B9 R848 L1 NC/ODT1 VSSQ B9 R849 L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ X76
E2 E2 E2 E2 X76550BOL46
2

2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8 SAM2G@
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96
X76@ X76@ X76@ X76@
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU
1

1
R850 R851 R854 R855
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
3 128@ 128@ 128@ 128@ 3

15mil 15mil 15mil 15mil

2

2
VREFCA_A1 VREFDA_Q1 VREFCA_A3 VREFDA_Q3
1

1
1 1 1 1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R858 C939 R859 R862 C943 R863 C944
4.99K_0402_1% 4.99K_0402_1% C940 4.99K_0402_1% 4.99K_0402_1% 128@
128@ 128@ 128@ 128@ 128@ 128@ 128@
2 2 2 2
2

2
+1.5VSDGPU
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU

128@ 128@ 128@ @ @

128@ 128@ 128@ @ @ 128@ 128@ 128@ @ @ 128@ 128@ 128@ @ @ 1 1 1 1 1

1U_0402_6.3V6K
C962

1U_0402_6.3V6K
C963

1U_0402_6.3V6K
C964

1U_0402_6.3V6K
C965

1U_0402_6.3V6K
C966
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
C947

1U_0402_6.3V6K
C948

1U_0402_6.3V6K
C949

1U_0402_6.3V6K
C950

1U_0402_6.3V6K
C951

1U_0402_6.3V6K
C952

1U_0402_6.3V6K
C953

1U_0402_6.3V6K
C954

1U_0402_6.3V6K
C955

1U_0402_6.3V6K
C956

1U_0402_6.3V6K
C957

1U_0402_6.3V6K
C958

1U_0402_6.3V6K
C959

1U_0402_6.3V6K
C960

1U_0402_6.3V6K
C961
128@
1 2
15 CLKA0 2 2 2 2 2
R866 40.2_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
128@
1 2
15 CLKA0#
R867 40.2_0402_1%
+1.5VSDGPU +1.5VSDGPU
1
+1.5VSDGPU +1.5VSDGPU
C395
0.01U_0402_16V7K 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@
2 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@
128@ 1 10U_0603_6.3V6M 1 1 1 1 1 1 1
C972

10U_0603_6.3V6M
C973

10U_0603_6.3V6M
C974

10U_0603_6.3V6M
C975

10U_0603_6.3V6M
C1029

10U_0603_6.3V6M
C1028

10U_0603_6.3V6M
C1027

10U_0603_6.3V6M
C1030
4
1 1 1 1 1 1 1 1 4
128@
10U_0603_6.3V6M
C968

10U_0603_6.3V6M
C969

10U_0603_6.3V6M
C970

10U_0603_6.3V6M
C971

10U_0603_6.3V6M
C1024

10U_0603_6.3V6M
C1026

10U_0603_6.3V6M
C1023

10U_0603_6.3V6M
C1025

1 2
15 CLKA1 2 2 2 2 2 2 2 2
R868 40.2_0402_1%
2 2 2 2 2 2 2 2
128@
1 2
15 CLKA1#
R869 40.2_0402_1%
1 Security Classification Compal Secret Data Compal Electronics, Inc.
C406 Issued Date 2012/09/12 2013/07/10 Title
Deciphered Date
2
0.01U_0402_16V7K
128@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel A
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 18 of 52
A B C D E
 A B C D E

U58 U59 U60 U61

VREFCB_A1 M8 E3 MDB31 VREFDB_Q1 M8 E3 MDB23 VREFCB_A3 M8 E3 MDB35 VREFDB_Q3 M8 E3 MDB55

VREFDB_Q1 H1 VREFCA DQL0 F7 MDB26 VREFCB_A1 H1 VREFCA DQL0 F7 MDB16 VREFDB_Q3 H1 VREFCA DQL0 F7 MDB37 VREFCB_A3 H1 VREFCA DQL0 F7 MDB49
VREFDQ DQL1 F2 MDB25 VREFDQ DQL1 F2 MDB22 VREFDQ DQL1 F2 MDB34 VREFDQ DQL1 F2 MDB52
MAB0 N3 DQL2 F8 MDB29 MAB0 N3 DQL2 F8 MDB18 MAB0 N3 DQL2 F8 MDB39 MAB0 N3 DQL2 F8 MDB50
MAB1 P7 A0 DQL3 H3 MDB28 MAB1 P7 A0 DQL3 H3 MDB21 MAB1 P7 A0 DQL3 H3 MDB33 MAB1 P7 A0 DQL3 H3 MDB53
MAB2 P3 A1 DQL4 H8 MDB30 MAB2 P3 A1 DQL4 H8 MDB19 MAB2 P3 A1 DQL4 H8 MDB38 MAB2 P3 A1 DQL4 H8 MDB48
MAB[0..15] MAB3 N2 A2 DQL5 G2 MDB24 MAB3 N2 A2 DQL5 G2 MDB20 MAB3 N2 A2 DQL5 G2 MDB32 MAB3 N2 A2 DQL5 G2 MDB54
15 MAB[0..15] MAB4 P8 A3 DQL6 H7 MDB27 MAB4 P8 A3 DQL6 H7 MDB17 MAB4 P8 A3 DQL6 H7 MDB36 MAB4 P8 A3 DQL6 H7 MDB51
MDB[0..63] MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
15 MDB[0..63] MAB6 R8 A5 MAB6 R8 A5 MAB6 R8 A5 MAB6 R8 A5
DQMB#[0..7] MAB7 R2 A6 D7 MDB12 MAB7 R2 A6 D7 MDB2 MAB7 R2 A6 D7 MDB46 MAB7 R2 A6 D7 MDB59
15 DQMB#[0..7] MAB8 T8 A7 DQU0 C3 MDB11 MAB8 T8 A7 DQU0 C3 MDB4 MAB8 T8 A7 DQU0 C3 MDB43 MAB8 T8 A7 DQU0 C3 MDB62
QSB[0..7] MAB9 R3 A8 DQU1 C8 MDB15 MAB9 R3 A8 DQU1 C8 MDB0 MAB9 R3 A8 DQU1 C8 MDB47 MAB9 R3 A8 DQU1 C8 MDB58
1 15 QSB[0..7] MAB10 L7 A9 DQU2 C2 MDB9 MAB10 L7 A9 DQU2 C2 MDB6 MAB10 L7 A9 DQU2 C2 MDB41 MAB10 L7 A9 DQU2 C2 MDB63 1
QSB#[0..7] MAB11 R7 A10/AP DQU3 A7 MDB13 MAB11 R7 A10/AP DQU3 A7 MDB3 MAB11 R7 A10/AP DQU3 A7 MDB44 MAB11 R7 A10/AP DQU3 A7 MDB56
15 QSB#[0..7] MAB12 N7 A11 DQU4 A2 MDB8 MAB12 N7 A11 DQU4 A2 MDB7 MAB12 N7 A11 DQU4 A2 MDB42 MAB12 N7 A11 DQU4 A2 MDB61
MAB13 T3 A12 DQU5 B8 MDB14 MAB13 T3 A12 DQU5 B8 MDB1 MAB13 T3 A12 DQU5 B8 MDB45 MAB13 T3 A12 DQU5 B8 MDB57
MAB14 T7 A13 DQU6 A3 MDB10 MAB14 T7 A13 DQU6 A3 MDB5 MAB14 T7 A13 DQU6 A3 MDB40 MAB14 T7 A13 DQU6 A3 MDB60
MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU

M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2

15 B_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9
B_BA1 B_BA1 B_BA1
15 B_BA1 M3 BA1 VDD G7 B_BA2 M3 BA1 VDD G7 B_BA2 M3 BA1 VDD G7 B_BA2 M3 BA1 VDD G7
15 B_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
CLKB0 J7 VDD N9 CLKB0 J7 VDD N9 CLKB1 J7 VDD N9 CLKB1 J7 VDD N9
CLKB0# K7 CK VDD R1 CLKB0# K7 CK VDD R1 CLKB1# K7 CK VDD R1 CLKB1# K7 CK VDD R1
K9 CK VDD R9 CKEB0 K9 CK VDD R9 K9 CK VDD R9 CKEB1 K9 CK VDD R9
15 CKEB0 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU 15 CKEB1 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU

ODTB0 K1 A1 ODTB0 K1 A1 ODTB1 K1 A1 ODTB1 K1 A1

15 ODTB0 L2 ODT/ODT0 VDDQ A8 L2 ODT/ODT0 VDDQ A8 15 ODTB1 L2 ODT/ODT0 VDDQ A8 L2 ODT/ODT0 VDDQ A8
CSB0# CSB1#
15 CSB0# J3 CS/CS0 VDDQ C1 RASB0# J3 CS/CS0 VDDQ C1 15 CSB1# J3 CS/CS0 VDDQ C1 RASB1# J3 CS/CS0 VDDQ C1
15 RASB0# K3 RAS VDDQ C9 CASB0# K3 RAS VDDQ C9 15 RASB1# K3 RAS VDDQ C9 CASB1# K3 RAS VDDQ C9
15 CASB0# L3 CAS VDDQ D2 WEB0# L3 CAS VDDQ D2 15 CASB1# L3 CAS VDDQ D2 WEB1# L3 CAS VDDQ D2
15 WEB0# WE VDDQ E9 WE VDDQ E9 15 WEB1# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB3 F3 VDDQ H2 QSB2 F3 VDDQ H2 QSB4 F3 VDDQ H2 QSB6 F3 VDDQ H2
QSB1 C7 DQSL VDDQ H9 QSB0 C7 DQSL VDDQ H9 QSB5 C7 DQSL VDDQ H9 QSB7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9

DQMB#1 D3 DML VSS B3 DQMB#0 D3 DML VSS B3 DQMB#5 D3 DML VSS B3 DQMB#7 D3 DML VSS B3
2 DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1 2
VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 VSS J2 QSB#2 G3 VSS J2 QSB#4 G3 VSS J2 QSB#6 G3 VSS J2
QSB#1 B7 DQSL VSS J8 QSB#0 B7 DQSL VSS J8 QSB#5 B7 DQSL VSS J8 QSB#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9
15,18 VRAM_RST# RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
R870 L1 NC/ODT1 VSSQ B9 R871 L1 NC/ODT1 VSSQ B9 R872 L1 NC/ODT1 VSSQ B9 R873 L1 NC/ODT1 VSSQ B9
VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1
243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2

2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96
X76@ X76@ X76@ X76@
+1.5VSDGPU +1.5VSDGPU
+1.5VSDGPU +1.5VSDGPU
1

1
R874 R875
4.99K_0402_1% 4.99K_0402_1% R878 R879
3 VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% 3
VGA@ VGA@
2

2
VREFCB_A1 VREFDB_Q1
VREFCB_A3 VREFDB_Q3
1

1 1 +1.5VSDGPU

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

R882 C977 R883 C978 1 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.99K_0402_1% 4.99K_0402_1% R886 C981 R887 C982
VGA@ VGA@ VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% VGA@ VGA@ VGA@ @ @
2 2 VGA@ VGA@ VGA@ VGA@ 1 1 1 1 1
2

2 2

1U_0402_6.3V6K
C1001

1U_0402_6.3V6K
C1002

1U_0402_6.3V6K
C1003

1U_0402_6.3V6K
C1004

1U_0402_6.3V6K
C1005
2

2
R890 40.2_0402_1% 2 2 2 2 2
1 VGA@ 2 +1.5VSDGPU +1.5VSDGPU
15 CLKB0
+1.5VSDGPU

R891 40.2_0402_1% VGA@ VGA@ VGA@ @ @ VGA@ VGA@ VGA@ @ @

1 VGA@ 2 1 1 1 1 1 1 1 1 1 1 VGA@ VGA@ VGA@ @ @
15 CLKB0#
1U_0402_6.3V6K
C987

1U_0402_6.3V6K
C988

1U_0402_6.3V6K
C989

1U_0402_6.3V6K
C990

1U_0402_6.3V6K
C985

1U_0402_6.3V6K
C991

1U_0402_6.3V6K
C992

1U_0402_6.3V6K
C993

1U_0402_6.3V6K
C994

1U_0402_6.3V6K
C995

1 1 1 1 1

1U_0402_6.3V6K
C996

1U_0402_6.3V6K
C997

1U_0402_6.3V6K
C998

1U_0402_6.3V6K
C999

1U_0402_6.3V6K
C1000
1
C409 2 2 2 2 2 2 2 2 2 2
+1.5VSDGPU 2 2 2 2 2 +1.5VSDGPU
0.01U_0402_16V7K
2 +1.5VSDGPU
VGA@
R892
40.2_0402_1%
1 VGA@ 2 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 1 1 1
15 CLKB1
10U_0603_6.3V6M
C1009

10U_0603_6.3V6M
C1006

10U_0603_6.3V6M
C1007

10U_0603_6.3V6M
C1008

1 1 1 1 VGA@ VGA@ VGA@ VGA@

10U_0603_6.3V6M
C1038

10U_0603_6.3V6M
C1036

10U_0603_6.3V6M
C1035

10U_0603_6.3V6M
C1037
R893 VGA@ VGA@ VGA@ VGA@

10U_0603_6.3V6M
C1010

10U_0603_6.3V6M
C1011

10U_0603_6.3V6M
C1012

10U_0603_6.3V6M
C1013
40.2_0402_1%
1 VGA@ 2 +1.5VSDGPU 2 2 2 2 2 2 2 2
4 15 CLKB1# 2 2 2 2 4

1
C410 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
10U_0603_6.3V6M
C1031

10U_0603_6.3V6M
C1032

10U_0603_6.3V6M
C1033

10U_0603_6.3V6M
C1034

0.01U_0402_16V7K
2
VGA@
2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/12 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel B
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 19 of 52
A B C D E
 A B C D E

C1195 1 2
150P_0402_50V8J U25A
C1188 1 2
150P_0402_50V8J HUDSON-2
PCI Host Bus Reset (To EC) APU_PCIE_RST#_R R962 1 2 33_0402_5% AE2 AF3
R932 1 2 33_0402_5% AD5 PCIE_RST# PCICLK0 AF1

PCI CLKS
32,35 PLT_RST# A_RST# PCICLK1/GPO36 AF5 PCI_CLK1 23
C1189 1 2 .1U_0402_16V7K UMI_FTX_ARX_P0 AE30 PCICLK2/GPO37 AG2
5 UMI_FTX_C_ARX_P0 UMI_TX0P PCICLK3/GPO38 PCI_CLK3 23
C1190 1 2 .1U_0402_16V7K UMI_FTX_ARX_N0 AE32 AF6
5 UMI_FTX_C_ARX_N0 UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 23
C1191 1 2 .1U_0402_16V7K UMI_FTX_ARX_P1 AD33 For PCIE device reset on FS1
5 UMI_FTX_C_ARX_P1 UMI_TX1P
C1192 1 2 .1U_0402_16V7K UMI_FTX_ARX_N1 AD31 AB5
(GFX,GLAN,WLAN,LVDS Travis)
5 UMI_FTX_C_ARX_N1 UMI_TX1N PCIRST#
C1196 1 2 .1U_0402_16V7K UMI_FTX_ARX_P2 AD28
5 UMI_FTX_C_ARX_P2 UMI_TX2P
C1197 1 2 .1U_0402_16V7K UMI_FTX_ARX_N2 AD29 R407
5 UMI_FTX_C_ARX_N2 UMI_TX2N
C1198 1 2 .1U_0402_16V7K UMI_FTX_ARX_P3 AC30 AJ3 0_0402_5%
1 5 UMI_FTX_C_ARX_P3 UMI_TX3P AD0/GPIO0 1
C1194 1 2 .1U_0402_16V7K UMI_FTX_ARX_N3 AC32 AL5 2 @ 1
5 UMI_FTX_C_ARX_N3 UMI_TX3N AD1/GPIO1 AG4
UMI_ATX_C_FRX_P0 AB33 AD2/GPIO2 AL6
5 UMI_ATX_C_FRX_P0 AB31 UMI_RX0P AD3/GPIO3 AH3
UMI_ATX_C_FRX_N0
5 UMI_ATX_C_FRX_N0

PCI EXPRESS INTERFACES

UMI_ATX_C_FRX_P1 AB28 UMI_RX0N AD4/GPIO4 AJ5
5 UMI_ATX_C_FRX_P1 AB29 UMI_RX1P AD5/GPIO5 AL1 +3VS
UMI_ATX_C_FRX_N1
5 UMI_ATX_C_FRX_N1 UMI_ATX_C_FRX_P2 Y33 UMI_RX1N AD6/GPIO6 AN5 C1193 @
5 UMI_ATX_C_FRX_P2 UMI_ATX_C_FRX_N2 Y31 UMI_RX2P AD7/GPIO7 AN6 2 1
5 UMI_ATX_C_FRX_N2 UMI_ATX_C_FRX_P3 Y28 UMI_RX2N AD8/GPIO8 AJ1
5 UMI_ATX_C_FRX_P3 Y29 UMI_RX3P AD9/GPIO9 AL8
UMI_ATX_C_FRX_N3 0.1U_0402_16V4Z
5 UMI_ATX_C_FRX_N3 UMI_RX3N AD10/GPIO10

5
AL3
R834 1 2 590_0402_1% PCIE_CALRP AF29 AD11/GPIO11 AM7

VCC
R836 1 2 2K_0402_1% PCIE_CALRN AF31 PCIE_CALRP AD12/GPIO12 AJ6 1
+1.1VS_PCIE_VDDR PCIE_CALRN AD13/GPIO13 IN1
AK7 APU_PCIE_RST#_R 4
V33 AD14/GPIO14 AN8 2 OUT APU_PCIE_RST# 28,29

GND
V31 GPP_TX0P AD15/GPIO15 AG9 IN2 U26
W30 GPP_TX0N AD16/GPIO16 AM11 MC74VHC1G08DFT2G_SC70-5
W32 GPP_TX1P AD17/GPIO17 AJ10

3
GPP_TX1N AD18/GPIO18

1
AB26 AL12
AB27 GPP_TX2P AD19/GPIO19 AK11 R394
AA24 GPP_TX2N AD20/GPIO20 AN12 100K_0402_5%
AA23 GPP_TX3P AD21/GPIO21 AG12 R405
GPP_TX3N AD22/GPIO22 AE12 0_0402_5%
PCI_AD23 23

2
AA27 AD23/GPIO23 AC12 2 @ 1
AA26 GPP_RX0P AD24/GPIO24 AE13 PCI_AD24 23
W27 GPP_RX0N AD25/GPIO25 AF13 PCI_AD25 23 +3VS

PCI INTERFACE
V27 GPP_RX1P AD26/GPIO26 AH13 PCI_AD26 23
V26 GPP_RX1N AD27/GPIO27 AH14 PCI_AD27 23
GPP_RX2P AD28/GPIO28 T26
W26 AD15
GPP_RX2N AD29/GPIO29

5
W24 AC15 VGA_PWRGD_R Change to GPIO51
W23 GPP_RX3P AD30/GPIO30 AE16

VCC
GPP_RX3N AD31/GPIO31 AN3 PLT_RST# 1
2 CBE0# AJ8 IN1 4 2
CBE1# AN10 DGPU_HOLD_RST# 2 OUT PLTRST_VGA# 13

GND
CBE2# 22 DGPU_HOLD_RST# IN2
+1.1VS_CKVDD R833 1 2 2K_0402_1% CLK_CALRN F27 AD12
CLK_CALRN CBE3#

1
AG10
FRAME# AK9 R391

3
DEVSEL# AL10 U37 100K_0402_5%
G30 IRDY# AF10 MC74VHC1G08DFT2G_SC70-5 VGA@
G28 PCIE_RCLKP TRDY# AE10 VGA@
SS For "EXT" CLK mode, input to PCIE,

2
PCIE_RCLKN PAR AH1
CLK_APU_DISP R26 STOP# AM9
7 CLK_APU_DISP CLK_APU_DISP# T26 DISP_CLKP PERR# AH8
7 CLK_APU_DISP# DISP_CLKN SERR# AG15
H33 REQ0# AG13
NSS APU DISP DISP2_CLKP REQ1#/GPIO40
H31 AF15
DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41 AM17
REQ3#/CLK_REQ5#/GPIO42 T25
CLK_APU T24 AD16 RTCVCC_R
7 CLK_APU T23 APU_CLKP GNT0# AD13
APU CLK_APU#
7 CLK_APU# APU_CLKN GNT1#/GPO44 AD21
GNT2#/SD_LED/GPO45

1
CLK_PEG_VGA J30 AK17 D
13 CLK_PEG_VGA SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46 T24
VGA CLK_PEG_VGA# K29 AD19 CLKRUN# EC_RTCRST 2 Q22
13 CLK_PEG_VGA# SLT_GFX_CLKN CLKRUN# AH9 CLKRUN# 32 35 EC_RTCRST
G L2N7002LT1G_SOT23-3
CLK_PCIE_MINI1 H27 LOCK#
28 CLK_PCIE_MINI1 S

3
GPP_CLK0P

2
Wireless LAN CLK_PCIE_MINI1# H28 AF18
28 CLK_PCIE_MINI1# GPP_CLK0N INTE#/GPIO32 AE18 R914
CLK_PCIE_LAN J27 INTF#/GPIO33 AC16 10K_0402_5%
29 CLK_PCIE_LAN CLK_PCIE_LAN# K26 GPP_CLK1P INTG#/GPIO34 AD18 TP_INT#_FCH_INTH 2 1
Ethernet LAN 29 CLK_PCIE_LAN# GPP_CLK1N INTH#/GPIO35
@
TP_INT# 36
0_0402_5% R131

1
F33
CLOCK GENERATOR

F31 GPP_CLK2P
GPP_CLK2N B25 CLK0_LPC_EC
SS E33 LPCCLK0 CLK0_LPC_EC 23,35
E31 GPP_CLK3P D25 LPC_CLK1
GPP_CLK3N LPCCLK1 LPC_CLK1 23,32 add For EC do RTCRST(10/30), add 10k PL (12/10)
3 D27 LPC_AD0 3
M23 LAD0 C28 LPC_AD0 32,35
LPC_AD1
M24 GPP_CLK4P LAD1 A26 LPC_AD2 LPC_AD1 32,35
GPP_CLK4N LAD2 LPC_AD2 32,35
A29 LPC_AD3 RTCVCC_R XEMC@
LPC

LAD3 LPC_AD3 32,35

M27 A31 LPC_FRAME# APU_RST#
GPP_CLK5P LFRAME# LPC_FRAME# 32,35

2
M26 B27 @ C46 33P_0402_50V8J
GPP_CLK5N LDRQ0# AE27 JCMOS XEMC@
N25 LDRQ1#/CLK_REQ6#/GPIO49 AE19 SERIRQ SHORT PADS APU_PWRGD
SERIRQ 32,35

1
N26 GPP_CLK6P SERIRQ/GPIO48 C45 33P_0402_50V8J
GPP_CLK6N
R23
R24 GPP_CLK7P G25 ALLOW_STOP
check GPP_CLK7N DMA_ACTIVE# ALLOW_STOP 7
reserve under RAM door(1/21). for ESD Close FCH Side
1 2 E28 APU_PROCHOT#_R R853 1 RS@ 2 0_0402_5%
N27 PROCHOT# E26 APU_PWRGD APU_PROCHOT# 7
C1200 1
R27 GPP_CLK8P APU_PG G26 APU_PWRGD 45,7
10P_0402_50V8J APU_PG/APU_RST#/LDT_STP# : OD pin
APU

GPP_CLK8N LDT_STP# F26 APU_RST#

1 APU_RST# APU_RST# 7 DMA_ACTIVE# : IN/OD, 0.8V threshold
PROCHOT# : IN, 0.8V threshold
2 J26 LDT_STP : No use, NC
GND 14M_25M_48M_OSC H7
S5_CORE_EN DMA active. The FCH drives the DMA_ACTIVE# to
X1 R877 F1 CLK_RTC
RTCCLK F3 CLK_RTC 23 APU to notify DMA activity. This will cause the APU
25MHZ_10PF_7V25000014 1M_0402_5%
4 25M_X1 C31 INTRUDER_ALERT# E6 RTCVCC_R to reestablish the UMI link quicker.
GND 25M_X1 VDDBT_RTC_G
S5 PLUS

G2 32K_X1
3 32K_X1 +RTCVCC +CHGRTC
1 2 25M_X2 C33 W=20mils
C1201 3 25M_X2 1 R889 2
10P_0402_50V8J G4 32K_X2 510_0402_5%
32K_X2

2
0.1U_0402_16V4Z
1 1 W=20mils +RTCBATT

2
C1202 C1203 1

2
0.1U_0402_16V4Z 1U_0402_6.3V6K CMOS1 C1204
HUDSON-M2_FCBGA656 @ R860
4 2 2 0_0603_5% @ 4
0_0603_5% 2 D23

1
1 2 32K_X1 for Clear CMOS BAS40-04_SOT23-3

1
C1205 If a diode is implemented between the FCH and battery,
22P_0402_50V8J the VDDBT_RTC_G input voltage is within 200 mV of
1

the battery voltage.

1

R861 Y1
20M_0402_5% 32.768KHZ_12.5PF_Q13FC135000040
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/12 Deciphered Date 2015/07/08 Title
2

1 2 32K_X2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Bolton-M3-UMI/PCI/CLOCK/LPC/RTC
C1206 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
22P_0402_50V8J Close to HUDSON-M2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
Z5WAK M/B LA-B221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

I'm from VIETNAM sualaptop365

Date: Wednesday, February 12, 2014 Sheet 20 of 52
A B C D E
 A B C D E

U25B 8MB SPI ROM +3VALW

HUDSON-2 0.1U_0402_16V4Z C466

SATA_PTX_DRX_P0 AK19 AL14 2 1
33 SATA_PTX_DRX_P0 AM19 SATA_TX0P SD_CLK/SCLK_2/GPIO73 AN14
SATA_PTX_DRX_N0
33 SATA_PTX_DRX_N0 SATA_TX0N SD_CMD/SLOAD_2/GPIO74 AJ12
HDD U7
SATA_PRX_DTX_N0 AL20 SD_CD/GPIO75 AH12 FCH_SPI_CS1# 1 8 FCH_SPI_VCC
33 SATA_PRX_DTX_N0 SATA_RX0N SD_WP/GPIO76 CS# VCC

SD CARD
SATA_PRX_DTX_P0 AN20 AK13 FCH_SPI_MISO 2 7 FCH_SPI_HOLD#
33 SATA_PRX_DTX_P0 SATA_RX0P SD_DATA0/SDATI_2/GPIO77 AM13 3 DO(IO1) HOLD#(IO3) 6 FCH_SPI_HOLD# 22
FCH_SPI_W P# FCH_SPI_CLK
SATA_PTX_DRX_P1 AN22 SD_DATA1/SDATO_2/GPIO78 AH15 4 WP#(IO2) CLK 5 FCH_SPI_MOSI
33 SATA_PTX_DRX_P1 AL22 SATA_TX1P SD_DATA2/GPIO79 AJ14 GND DI(IO0)
SATA_PTX_DRX_N1
33 SATA_PTX_DRX_N1 SATA_TX1N SD_DATA3/GPIO80
ODD EN25QH64-104HIP_SO8
SATA_PRX_DTX_N1 AH20 AC4
1 33 SATA_PRX_DTX_N1 AJ20 SATA_RX1N GBE_COL AD3
1
SATA_PRX_DTX_P1
33 SATA_PRX_DTX_P1 SATA_RX1P GBE_CRS AD9
AJ22 GBE_MDCK W10 +3VALW
AH22 SATA_TX2P GBE_MDIO AB8 RP3
SATA_TX2N GBE_RXCLK AH7 1 8 FCH_SPI_CS1#
AM23 GBE_RXD3 AF7 2 7 GBE_PHY_INTR
AK23 SATA_RX2N GBE_RXD2 AE7 GBE_COL / GBE_CRS / GBE_MDIO 3 6 FCH_SPI_W P#
SATA_RX2P GBE_RXD1 AD7 4 5 FCH_SPI_HOLD#
GBE_RXD0 GBE_RXERR / Left unconnected.
AH24 AG8 FCH SCL V1.20 19-35
AJ24 SATA_TX3P GBE_RXCTL/RXDV AD1 10K_0804_8P4R_5% GBE_PHY_INTR
SATA_TX3N GBE_RXERR AB7 Pulled-up to +3.3V_S5 with a 10-KΩ 5% resistor.

GBE LAN
AN24 GBE_TXCLK AF9
SATA_RX3N GBE_TXD3 FCH SCL v1.20 #19-85
AL24 AG6
SATA_RX3P GBE_TXD2 AE8 RP4
AL26 GBE_TXD1 AD8 FCH_SPI_CS1# 1 8
AN26 SATA_TX4P GBE_TXD0 AB9 2 7 EC_SPI_CS1# 35
FCH_SPI_MISO
SATA_TX4N GBE_TXCTL/TXEN AC2 3 6 EC_SPI_MISO 35
FCH_SPI_MOSI

SERIAL ATA
AJ26 GBE_PHY_PD AA7 4 5 EC_SPI_MOSI 35
FCH_SPI_CLK
AH26 SATA_RX4N GBE_PHY_RST# W9 EC_SPI_CLK 35
GBE_PHY_INTR
SATA_RX4P GBE_PHY_INTR 0_0804_8P4R_5%
AN29 AL@
AL28 SATA_TX5P V6 FCH_SPI_MISO XEMC@
SATA_TX5N SPI_DI/GPIO164 V5 FCH_SPI_MOSI 1 XEMC@ 2 1 2 C31
SPI_DO/GPIO163

SPI ROM
AK27 V3 FCH_SPI_CLK R71
AM27 SATA_RX5N SPI_CLK/GPIO162 T6 FCH_SPI_CS1# 10_0402_5% 10P_0402_50V8J
SATA_RX5P SPI_CS1#/GPIO165 V1 FCH_SPI_W P#
AL29 ROM_RST#/SPI_WP#/GPIO161
AN31 NC6 RP20
NC7 L30 FCH_CRT_R FCH_CRT_R 1 8
AL31 VGA_RED FCH_CRT_R 26 2 7
FCH_CRT_G
AL33 NC8 3 6
2 NC9 L32 FCH_CRT_G FCH_CRT_B 4 5 2
AH33 VGA_GREEN FCH_CRT_G 26
AH31 NC10 150_0804_8P4R_1%
NC11 M29 FCH_CRT_B
AJ33 VGA_BLUE FCH_CRT_B 26

VGA DAC
AJ31 NC12
NC13 M28 FCH_CRT_HSYNC
VGA_HSYNC/GPO68 N30 FCH_CRT_HSYNC 26
FCH_CRT_VSYNC
VGA_VSYNC/GPO69 FCH_CRT_VSYNC 26
M33 FCH_CRT_DDC_SDA
VGA_DDC_SDA/GPO70 FCH_CRT_SDA 26
1K_0402_1% 2 1 R916 SATA_CALRP AF28 N32 FCH_CRT_DDC_SCL
SATA_CALRP VGA_DDC_SCL/GPO71 FCH_CRT_SCL 26

+1.1VS_AVDD_SATA 931_0402_1% 2 1 R925 SATA_CALRN AF27

SATA_CALRN K31 1 2
VGA_DAC_RSET R923 715_0402_1%
+3VS R902 1 2 10K_0402_5% AD22
SATA_ACT#/GPIO67 V28 APU_VGA_AUXP_C
AUX_VGA_CH_P V29 APU_VGA_AUXP_C 7
APU_VGA_AUXN_C
AF21 AUX_VGA_CH_N APU_VGA_AUXN_C 7
VGA MAINLINK

SATA_X1 U28 AUXCAL 1 2

AUXCAL +VDDAN_11_ML
R903 100_0402_1%
T31 APU_VGA_TXP0
ML_VGA_L0P T33 APU_VGA_TXP0 7
APU_VGA_TXN0
AG21 ML_VGA_L0N T29 APU_VGA_TXN0 7
APU_VGA_TXP1
SATA_X2 ML_VGA_L1P T28 APU_VGA_TXP1 7
APU_VGA_TXN1
ML_VGA_L1N R32 APU_VGA_TXN1 7
APU_VGA_TXP2
ML_VGA_L2P R30 APU_VGA_TXP2 7
APU_VGA_TXN2
ML_VGA_L2N P29 APU_VGA_TXN2 7
APU_VGA_TXP3
ML_VGA_L3P P28 APU_VGA_TXP3 7
APU_VGA_TXN3
ML_VGA_L3N APU_VGA_TXN3 7
FCH_CRT_HPD 2 1
+FCH_VDDAN_33_DAC_R
3 C29 FCH_CRT_HPD 10K_0402_5% R913 3
ML_VGA_HPD/GPIO229 FCH_CRT_HPD 7

AH16 N2 GPIO175 RP8

AM15 FANOUT0/GPIO52 VIN0/GPIO175 GPIO178 1 8
AJ16 FANOUT1/GPIO53 HW MONITOR M3 GPIO176 GPIO175 2 7
FANOUT2/GPIO54 VIN1/GPIO176 GPIO176 3 6
AK15 L2 GPIO177 GPIO182 4 5
AN16 FANIN0/GPIO56 VIN2/SDATI_1/GPIO177
AL16 FANIN1/GPIO57 N4 GPIO178 10K_0804_8P4R_5%
FANIN2/GPIO58 VIN3/SDATO_1/GPIO178 RP11
P1 GPIO179 GPIO180 1 8
GPIO171 K6 VIN4/SLOAD_1/GPIO179 GPIO179 2 7
TEMPIN0/GPIO171 P3 GPIO180 GPIO177 3 6
RP5 VIN5/SCLK_1/GPIO180 FCH_PCIE_W AKE# 4 5
22,29 FCH_PCIE_W AKE# +3VALW
1 8 GPIO174 GPIO172 K5 M1 1 @ 2
2 7 GPIO172 TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181 R75 10K_0402_5% 10K_0804_8P4R_5%
3 6 GPIO171 M5 GPIO182
4 5 GPIO173 GPIO173 K3 VIN7/GBE_LED3/GPIO182
TEMPIN2/GPIO173
10K_0804_8P4R_5% AG16
GPIO174 M6 NC1 AH10
GPIO181 Enabled integrated pull-down/up and left unconnected.
TEMPIN3/TALERT#/GPIO174 NC2 A28
NC3 G27
NC4 L4
NC5

HUDSON-M2_FCBGA656

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Bolton-M3-SATA/GBE/HWM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, February 12, 2014 Sheet 21 of 52
A B C D E
 A B C D E

U25D

HUDSON-2
AB6 G8

USB MISC
EC_LID_OUT# R2 PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
35 EC_LID_OUT# RI#/GEVENT22#
W7 B9 USB_RCOMP R894 1 2 11.8K_0402_1%
SLP_S3# T3 SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
35 SLP_S3# SLP_S3#
SLP_S5# W2 H1
35 SLP_S5# J4 SLP_S5# USB_FSD1P/GPIO186 H3
PBTN_OUT# Hudson-M2/M3
35 PBTN_OUT# PWR_BTN# USB_FSD1N
FCH_PWRGD N7 OHCI CTL
35 FCH_PWRGD PWR_GOOD

USB 1.1
H6 DEV 20, Fn 5

ACPI / WAKE UP EVENTS

T9 USB_FSD0P/GPIO185 H5
T15 TEST0 USB_FSD0N <Disable CTL>
T16 T10
V9 TEST1/TMS H10
T17 TEST2 USB_HSD13P G10
1
EC_GA20 AE22 USB_HSD13N 1
35 EC_GA20 GA20IN/GEVENT0# K10
EC_KBRST# AG19 USB_HSD12P J12
35 EC_KBRST# KBRST#/GEVENT1# USB_HSD12N
Hudson-M3
EC_SCI# R9 xHCI CTL
35 EC_SCI# LPC_PME#/GEVENT3#
THERMTRIP: EC_SMI# C26 G12 DEV 16, Fn 1
35 EC_SMI# LPC_SMI#/GEVENT23# USB_HSD11P
LPCPD# T5 F12 xHCI CTL
Need level shift from +3VALW to +1.5V 32 LPCPD# U4 LPC_PD#/GEVENT5# USB_HSD11N
SYS_RESET# DEV 16, Fn 0
Note: Ensure FCH internal pull-up resistor FCH_PCIE_WAKE# K1 SYS_RESET#/GEVENT19# K12 USB20_P10
to +3.3V S5 is disabled to prevent leakage 21,29 FCH_PCIE_WAKE# 2 1 V7 WAKE#/GEVENT8# USB_HSD10P K13 USB20_P10 36
@ TP_INT#_FCH_GEVENT USB20_N10 For USB3.0 Port x1
35,36 TP_I2C_INT# IR_RX1/GEVENT20# USB_HSD10N USB20_N10 36
when APU is powered down. 0_0402_5% R130 H_THERMTRIP# R10
7 H_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2#
WD_PWRGD AF19 B11
WD_PWRGD USB_HSD9P D11
USB_HSD9N Hudson-M2/M3
EC_RSMRST# U2 EHCI CTL
35 EC_RSMRST# RSMRST# E10
USB_HSD8P DEV 19, Fn 2
SM bus 0-->S0 PWR domain AG24 F10
AE24 CLK_REQ4#/SATA_IS0#/GPIO64 USB_HSD8N
SM bus 1-->S5 PWR domain AE26 CLK_REQ3#/SATA_IS1#/GPIO63 C10
MINI1_CLKREQ# AF22 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD7P A10

USB 2.0
28 MINI1_CLKREQ# AH17 CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N
AG18 SATA_IS4#/FANOUT3/GPIO55 H9
FCH_SPKR AF24 SATA_IS5#/FANIN3/GPIO59 USB_HSD6P G9
34 FCH_SPKR AD26 SPKR/GPIO66 USB_HSD6N
FCH_SCLK0

GPIO
11,12,28 FCH_SCLK0 SCL0/GPIO43
FCH_SDATA0 AD25 A8 USB20_P5
11,12,28 FCH_SDATA0 T7 SDA0/GPIO47 USB_HSD5P C8 USB20_P5 36
FCH_SCLK1 USB20_N5 USB to I2C bridge
36 FCH_SCLK1 SCL1/GPIO227 USB_HSD5N USB20_N5 36
PH on TP side 36 FCH_SDATA1 R7
FCH_SDATA1 SDA1/GPIO228
AG25 F8 USB20_P4
AG22 CLK_REQ2#/FANIN4/GPIO62 USB_HSD4P E8 USB20_P4 28
LAN_CLKREQ# USB20_N4 Mini Card Hudson-M2/M3
29 LAN_CLKREQ# CLK_REQ1#/FANOUT4/GPIO61 USB_HSD4N USB20_N4 28
J2 EHCI CTL
VGA_PG AG26 IR_LED#/LLB#/GPIO184 C6 USB20_P3
37,47,48,49 VGA_PG SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD3P USB20_P3 25 DEV 18, Fn 2
V8 A6 USB20_N3 TS <Support Wakeup>
DDR3_RST#/GEVENT7#/VGA_PD USB_HSD3N USB20_N3 25
W8
FCH_SPI_HOLD# Y6 GBE_LED0/GPIO183 C5 USB20_P2
21 FCH_SPI_HOLD# SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD2P USB20_P2 25
V10 A5 USB20_N2 Camera
AA8 GBE_LED2/GEVENT10# USB_HSD2N USB20_N2 25
AF25 GBE_STAT0/GEVENT11# C1 USB20_P1
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P USB20_P1 36
C3 USB20_N1
USB_HSD1N USB20_N1 36
For USB2.0 Port x2
2 M7 E1 USB20_P0 2
R8 BLINK/USB_OC7#/GEVENT18# USB_HSD0P E3 USB20_P0 36
USB20_N0
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 36
T1

USB OC
P6 USB_OC5#/IR_TX0/GEVENT17# C16 USBSS_CALRP R864 1 2 1K_0402_1%
F5 USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP A16 USBSS_CALRN R865 1 2 1K_0402_1%
T21 USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN +FCH_VDD_11_SSUSB_S
T22 P5
J7 USB_OC2#/TCK/GEVENT14# A14
T23 USB_OC1#/TDI/GEVENT13# USB_SS_TX3P
USB_OC0# T8 C14
36 USB_OC0# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N
Hudson-M3
C12 xHCI CTL
USB_SS_RX3P A12
USB_SS_RX3N
DEV 16, Fn 1
xHCI CTL
HDA_BITCLK AB3 D15 DEV 16, Fn 0
HDA_SDOUT AB1 AZ_BITCLK USB_SS_TX2P B15
HDA_SDIN0 AA2 AZ_SDOUT USB_SS_TX2N

HD AUDIO
34 HDA_SDIN0 AZ_SDIN0/GPIO167
RP10 HDA_SDIN1 Y5 E14

USB 3.0
1 8 HDA_SDIN2 Y3 AZ_SDIN1/GPIO168 USB_SS_RX2P F14
34 HDA_SDOUT_AUDIO AZ_SDIN2/GPIO169 USB_SS_RX2N
2 7 HDA_SDIN3 Y1
34 HDA_BITCLK_AUDIO AZ_SDIN3/GPIO170
3 6 HDA_SYNC AD6 F15
34 HDA_SYNC_AUDIO 4 5 AE4 AZ_SYNC USB_SS_TX1P G15
HDA_RST#
34 HDA_RST_AUDIO# AZ_RST# USB_SS_TX1N
33_0804_8P4R_5% H13
EMC@ USB_SS_RX1P G13
USB_SS_RX1N
+3VALW FCH_GPIO187 K19 J16 USB3_TX0_P
PS2_DAT/SDA4/GPIO187 USB_SS_TX0P USB3_TX0_P 36
FCH_GPIO188 J19 H16 USB3_TX0_N
J21 PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N USB3_TX0_N 36
FCH_GPIO166 On board
1 2 USB_OC0# SPI_CS2#/GBE_STAT2/GPIO166 J15 USB3_RX0_P
USB_SS_RX0P K15
USB3_RX0_P 36 USB Conn
R108 100K_0402_5% USB3_RX0_N
1 2 USB_SS_RX0N USB3_RX0_N 36
H_THERMTRIP#
R960 10K_0402_5% FCH_GPIO189 D21 RP6
FCH_GPIO190 C20 PS2KB_DAT/GPIO189 H19 FCH_GPIO193 FCH_GPIO196 1 8
D23 PS2KB_CLK/GPIO190 SCL2/GPIO193 G19 FCH_GPIO194 FCH_GPIO194 2 7
20 DGPU_HOLD_RST# PS2M_DAT/GPIO191 SDA2/GPIO194
C22 EMBEDDED CTRL G22 FCH_GPIO195 FCH_GPIO193 3 6
37 VGA_ON PS2M_CLK/GPIO192 SCL3_LV/GPIO195 G21 4 5
FCH_GPIO196 FCH_GPIO195
1 @ 2 EC_LID_OUT# SDA3_LV/GPIO196 E22
R881 100K_0402_5% EC_PWM0/EC_TIMER0/GPIO197 H22 10K_0804_8P4R_5%
F21 EC_PWM1/EC_TIMER1/GPIO198 J22
3 KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 FCH_GPIO199 23 3
E20 H21
1 @ 2 SYS_RESET# F20 KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200
R109 10K_0402_5% A22 KSO_2/GPIO211 K21
1 @ 2 LAN_CLKREQ# E18 KSO_3/GPIO212 KSI_0/GPIO201 K22
KSO_4/GPIO213 KSI_1/GPIO202 For PCIE device reset on FS1
R957 8.2K_0402_5% A20 F22
J18 KSO_5/GPIO214 KSI_2/GPIO203 F24
(GFX,GLAN,WLAN,LVDS Travis)
H18 KSO_6/GPIO215 KSI_3/GPIO204 E24
G18 KSO_7/GPIO216 KSI_4/GPIO205 B23
B21 KSO_8/GPIO217 KSI_5/GPIO206 C24
K18 KSO_9/GPIO218 KSI_6/GPIO207 F18
+3VALW D19 KSO_10/GPIO219 KSI_7/GPIO208
A18 KSO_11/GPIO220
OPAL@ VGA@ C18 KSO_12/GPIO221
B19 KSO_13/GPIO222
KSO_14/GPIO223
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

B17
KSO_15/GPIO224
1

A24
D17 KSO_16/GPIO225
KSO_17/GPIO226
R85

R86

R84

R88

R87

@ @ @

+3VS HUDSON-M2_FCBGA656
2

FCH_GPIO189
1 2 FCH_SCLK0 FCH_GPIO190
R954 2.2K_0402_5% FCH_GPIO188
1 2 FCH_SDATA0 FCH_GPIO187
R885 2.2K_0402_5% FCH_GPIO166
1 2 MINI1_CLKREQ#
1

1
100K_0402_5%
R93

100K_0402_5%
R95

100K_0402_5%
R89

100K_0402_5%

100K_0402_5%

R888 8.2K_0402_5%

@ @ @
1 2 WD_PWRGD
R94

R92

R884 10K_0402_5%
2

1 2 LAN_CLKREQ#
R953 8.2K_0402_5%
JET@ UMA@
1 2 EC_RSMRST#
R948 2.2K_0402_5%
1 @ 2 HDA_BITCLK
4 R952 10K_0402_5% 4

Project SKU ID Value

RP9 @
4 5 HDA_SDIN0 GPIO189 (use VGA) Low (UMA) High (VGA)
3 6 HDA_SDIN1
2 7 HDA_SDIN2 GPIO190 Low (JET) High (OPAL)
1 8 HDA_SDIN3
GPIO188
10K_0804_8P4R_5%
GPIO187
Security Classification Compal Secret Data Compal Electronics, Inc.
GPIO166 2012/09/12 2015/07/08 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Bolton-M3-ACPI/USB/EC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
A I'm from VIETNAM sualaptop365
B C D
Date: Wednesday, February 12, 2014
E
Sheet 22 of 52
 A B C D E

STRAP PINS
PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 FCH_GPIO199 CLK_RTC

1 1
PULL ALLOW USE NON_FUSION FCH EC CLKGEN LPC ROM S5 PLUS
HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED MODE
STRAPS DISABLED
DEFAULT DEFAULT DEFAULT

PULL FORCE IGNORE FUSION FCH EC CLKGEN SPI ROM S5 PLUS

LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE
STRAP MODE ENABLED
DEFAULT DEFAULT DEFAULT DEFAULT L47
HCB2012KF-221T30_0805 30mil
2 1

220 ohm
+3VS +FCH_VDDAN_33_DAC_R
+3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW
R905

R906 10K_0402_5%

R907 10K_0402_5%

R908 10K_0402_5%

R909 10K_0402_5%

R910 10K_0402_5%

R911 10K_0402_5%
1

1
10K_0402_5%

@ @ @ @ Remove VGA_PD
2

2
20 PCI_CLK1

2 20 PCI_CLK3 2

20 PCI_CLK4

20,35 CLK0_LPC_EC

20,32 LPC_CLK1

22 FCH_GPIO199

20 CLK_RTC 1 RS@ 2
R915 10K_0402_5%

R917 10K_0402_5%

R918 10K_0402_5%

R919 10K_0402_5%

R920 10K_0402_5%

R921 2.2K_0402_5%

R922 2.2K_0402_5%
R912 0_0603_5%
1

1
+1.1VS +FCH_VDDAN_11_MLDAC

@ @ @ 30mil
2

2
Support VGA connect +1.1VS
Remove VGA_PD

DEBUG STRAPS
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

3 3

PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE PCI RESERVED NORMAL USE DEFAULT DISABLE PCI

PULL PLL REFCLK PCIE STRAPS MEM BOOT
HIGH TERMINATION
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

PULL BYPASS RESERVED INVERT USE EEPROM ENABLE PCI

LOW PCI PLL REFCLK PCIE STRAPS MEM BOOT
TERMINATION

20 PCI_AD27

20 PCI_AD26

20 PCI_AD25

20 PCI_AD24

20 PCI_AD23
R926 2.2K_0402_5%

R927 2.2K_0402_5%

R928 2.2K_0402_5%

R929 2.2K_0402_5%

R930 2.2K_0402_5%

4 4
1

@ @ @ @ @
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Bolton-M3-STRAP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 23 of 52
A B C D E
 A B C D E

+1.1VS_VCC_FCH_R +1.1VS
U25C 1007mA
131mA 10mils 1 RS@ 2

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

10U_0603_6.3V6M
HUDSON-2
50mils

C1213

C1214

C1215

C1216

C1282
1 RS@ 2 +VDDIO_33_PCIGP AB17 T14 R937
+3VS +3VS VDDIO_33_PCIGP_1 VDDCR_11_1

22U_0805_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
R104 0_0603_5% AB18 T17 1 1 1 1 1 0_0805_5%
VDDIO_33_PCIGP_2 VDDCR_11_2

C1218

C1228

C1220

C1221
L3 AE9 T20 U25E

PCI/GPIO I/O
1 2 +VDDPL_3.3V AD10 VDDIO_33_PCIGP_3 VDDCR_11_3 U16
1 1 1 1 VDDIO_33_PCIGP_4 VDDCR_11_4

2.2U_0603_6.3V4Z
PBY160808T-221Y-N_2P AG7 U18 HUDSON-2

.1U_0402_16V7K
VDDIO_33_PCIGP_5 VDDCR_11_5 2 2 2 2 2

C1222

C1229

CORE S0
220 ohm AC13 V14 A3 T25
1 AB12 VDDIO_33_PCIGP_6 VDDCR_11_6 V17 A33 VSS VSS T27 1
1 1 2 2 2 2 VDDIO_33_PCIGP_7 VDDCR_11_7 VSS VSS
AB13 V20 B7 U6
AB14 VDDIO_33_PCIGP_8 VDDCR_11_8 Y17 B13 VSS VSS U14
AB16 VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1VS_CKVDD +1.1VS D9 VSS VSS U17
2 2 VDDIO_33_PCIGP_10 R106 D13 VSS VSS U20
47mA 10milsH24 20mils 340mA VSS VSS
H26 +1.1VS_CKVDD 1 RS@ 2 E5 U21
+VDDPL_3.3V VDDPL_33_SYS VDDAN_11_CLK_1 VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

22U_0805_6.3V6M
10milsV22 J25 0_0603_5% E12 U30
+FCH_VDDAN_33_DAC_R VDDAN_11_CLK_2 VSS VSS

C1223

C1224

C1225

C1226

C1283
K24 E16 U32

CLKGEN I/O
VDDPL_33_DAC VDDAN_11_CLK_3 L22 E29 VSS VSS V11
+FCH_VDDAN_33_DAC_R
10milsU22 VDDAN_11_CLK_4 M22
1 1 1 1 1
F7 VSS VSS V16
VDDPL_33_ML VDDAN_11_CLK_5 N21 F9 VSS VSS V18
10milsT22 VDDAN_11_CLK_6 VSS VSS
2.2U_0603_6.3V4Z

N22 F11 W4
2.2U_0603_6.3V4Z

.1U_0402_16V7K
0.1U_0402_16V4Z

VDDAN_33_DAC VDDAN_11_CLK_7 2 2 2 2 2 VSS VSS

C1209

C1210

C1227

C1231

10milsL18 P22 F13 W6

+FCH_VDDPL_33_SSUSB_S VDDAN_11_CLK_8 F16 VSS VSS W25
1 1 1 1 20mA VDDPL_33_SSUSB_S VSS VSS
17mA 10mils D7 F17 W28
+FCH_VDDPL_33_USB_S +1.1VS F19 VSS VSS Y14
VDDPL_33_USB_S 50mils VSS VSS
2 2 2 2
43mA 10mils VDDAN_11_PCIE_1
AB24 1088mA +1.1VS_PCIE_VDDR F23
VSS VSS
Y16
+VDDPL_33_PCIE AH29 Y21 +1.1VS_PCIE_VDDR 1 RS@ 2 F25 Y18
VDDPL_33_PCIE VDDAN_11_PCIE_2 VSS VSS

PCI EXPRESS

1U_0402_6.3V6K

.1U_0402_16V7K

22U_0805_6.3V6M
93mA 10mils AE25 F29 AA6
VDDAN_11_PCIE_3 VSS VSS

C1233

C1236

C1284
LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA AG28 AD24 R938 G6 AA12
VDDPL_33_SATA VDDAN_11_PCIE_4 AB23 0_0805_5% G16 VSS VSS AA13
supply for the RGB outputs VDDAN_11_PCIE_5 1 1 1 VSS VSS
For A11: Cap = 1nF @ AA22 G32 AA14
+3VALW 1 2 M31 VDDAN_11_PCIE_6 AF26 H12 VSS VSS AA16
+FCH_VDDAN_11_MLDAC For A12, Cap = DNI LDO_CAP VDDAN_11_PCIE_7 AG27 H15 VSS VSS AA17
L6 C1232 2.2U_0603_6.3V4Z
1 2 +FCH_VDDPL_33_SSUSB_S L24 VDDAN_11_PCIE_8 2 2 2 H29 VSS VSS AA25
7mA 10mils

GROUND
VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

PBY160808T-221Y-N_2P 1 2 V21 J6 AA28

VDDPL_11_DAC +1.1VS VSS VSS
C1238

C1239

PBY160808T-221Y-N_2P 60mils J9 AA30

VSS VSS
220 ohm 1 1 220 ohm/2A VDDAN_11_SATA_1
AA21 1337mA +1.1VS_AVDD_SATA J10
VSS VSS
AA32
+VDDAN_11_ML Y20 +1.1VS_AVDD_SATA 1 RS@ 2 J13 AB25
20mils VDDAN_11_SATA_4 VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

22U_0805_6.3V6M
Y22 AB21 J28 AC6
VDDAN_11_ML_1 VDDAN_11_SATA_2 VSS VSS

MAIN LINK
.1U_0402_16V7K

.1U_0402_16V7K

C1243

C1244

C1246

C1247
226mA V23 AB22 R941 J32 AC18

SERIAL ATA
2 2 VDDAN_11_ML_2 VDDAN_11_SATA_3 VSS VSS

C1240

4.7U_0603_6.3V6K
C1241

C1242
V24 AC22 1 1 1 1 0_0805_5% K7 AC28
2 V25 VDDAN_11_ML_3 VDDAN_11_SATA_5 AC21 K16 VSS VSS AD27 2
1 1 1 VDDAN_11_ML_4 VDDAN_11_SATA_6 VSS VSS
AA20 K27 AE6
VDDAN_11_SATA_7 AA18 K28 VSS VSS AE15
+VDDAN_33_USB VDDAN_11_SATA_8 AB20 2 2 2 2 L6 VSS VSS AE21
L7 2 2 2 VDDAN_11_SATA_9 AC19 L12 VSS VSS AE28
1 2 +FCH_VDDPL_33_USB_S AB10 VDDAN_11_SATA_10 +3VALW L13 VSS VSS AF8
VDDIO_33_GBE_S VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

PBY160808T-221Y-N_2P 10mils 59mA L15 AF12

VSS VSS
C1248

C1249

220 ohm AB11 N18 +VDDIO_33_S 1 RS@ 2 L16 AF16

VDDCR_11_GBE_S_1 VDDIO_33_S_1 VSS VSS

GBE LAN

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
1 1 AA11 L19 R107 0_0402_5% L21 AF33
VDDCR_11_GBE_S_2 VDDIO_33_S_2 VSS VSS

C1250

C1251

C1252
M18 M13 AG30
VDDIO_33_S_3 VSS VSS

3.3V_S5 I/O
AA9 V12 1 1 1 M16 AG32
AA10 VDDIO_GBE_S_1 VDDIO_33_S_4 V13 M21 VSS VSS AH5
2 2 +3VALW L54 VDDIO_GBE_S_2 VDDIO_33_S_5 Y12 M25 VSS VSS AH11
HCB2012KF-221T30_0805 658mA VDDIO_33_S_6 Y13 N6 VSS VSS AH18
2 1 +VDDAN_33_USB
30mils
G7 VDDIO_33_S_7 W11 2 2 2 N11 VSS VSS AH19
VDDAN_33_USB_S_1 VDDIO_33_S_8 VSS VSS
1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_16V7K
H8 N13 AH21
+3VS VDDAN_33_USB_S_2 +3VALW VSS VSS
C1253

C1254

C1255

C1256

C1257
220 ohm/3A J8 N23 AH23
L15 K8 VDDAN_33_USB_S_3 L28 N24 VSS VSS AH25
1 1 1 1 1 VDDAN_33_USB_S_4 10mils 5mA VSS VSS
1 2 +VDDPL_33_PCIE K9 G24 +VDDXL_3.3V 1 2 P12 AH27
VDDAN_33_USB_S_5 VDDXL_33_S VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

2.2U_0603_6.3V4Z
PBY160808T-221Y-N_2P M9 PBY160808T-221Y-N_2P P18 AJ18
VDDAN_33_USB_S_6 VSS VSS
C1258

C1259

C1261
220 ohm M10 220 ohm P20 AJ28
2 2 2 2 2 N9 VDDAN_33_USB_S_7 P21 VSS VSS AJ29
1 1 VDDAN_33_USB_S_8 1 VSS VSS
N10 VDDXL_33_S tied to P31 AK21
M12 VDDAN_33_USB_S_9 +3.3_S5 rail if Wake on LAN P33 VSS VSS AK25
N12 VDDAN_33_USB_S_10 R4 VSS VSS AL18
is supported
2 2 M11 VDDAN_33_USB_S_11 2 R11 VSS VSS AM21
+1.1VALW VDDAN_33_USB_S_12 R25 VSS VSS AM25
L57 +1.1VALW R28 VSS VSS AN1
140mA 10mils VSS VSS

USB
1 2 +VDDAN_11_USB_S U12 10mils 187mA T11 AN18
VDDAN_11_USB_S_1 VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

.1U_0402_16V7K

PBY160808T-221Y-N_2P U13 N20 +VDDCR_1.1V 1 RS@ 2 T16 AN28

+3VS VDDAN_11_USB_S_2 VDDCR_11_S_1 VSS VSS
C1262

C1263

C1277

1U_0402_6.3V6K

1U_0402_6.3V6K
220 ohm M20 R1145 0_0603_5% T18 AN33
VDDCR_11_S_2 VSS VSS

C1264

C1265
L22 1 1 1
3 1 2+VDDPL_33_SATA N8 T21 3
1 1 VSSAN_HWM VSSPL_DAC
2.2U_0603_6.3V4Z

.1U_0402_16V7K

PBY160808T-221Y-N_2P L28
VSSAN_DAC
C1266

C1267

220 ohm K25 K33

2 2 2 VSSXL VSSANQ_DAC N28
1 1 2 2 VSSIO_DAC
H25
VSSPL_SYS R6
+1.1VALW EFUSE
2 2 L59 +1.1VALW
197mA 10mils
1 2 +VDDCR_1.1V_USB T12 10mils 70mA L29
VDDCR_11_USB_S_1
10U_0603_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

PBY160808T-221Y-N_2P T13 J24 +VDDPL_1.1V 1 2 HUDSON-M2_FCBGA656

VDDCR_11_USB_S_2 VDDPL_11_SYS_S
C1268

C1269

C1270

2.2U_0603_6.3V4Z
220 ohm PBY160808T-221Y-N_2P

.1U_0402_16V7K
C1271

C1272
1 1 1 Connected to VSS through a dedicated via.
1 1

2 2 2
2 2

+3VALW
+FCH_VDD_11_SSUSB_S 12mA
20mils
P16
10mils
M8 1
282mA +VDDAN_33_HWM RS@ 2
VDDAN_11_SSUSB_S_1 VDDAN_33_HWM_S

2.2U_0603_6.3V4Z
M14 R100 0_0402_5% AMD reply:

.1U_0402_16V7K
VDDAN_11_SSUSB_S_2
1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

C1472

C1473
N14 VDDAN_33_HWM_S: Please connect
VDDAN_11_SSUSB_S_3
C1273

C1274

C1275

40mils P13 1 1 it to +3.3V_S5 directly if HWM is not used.

P14 VDDAN_11_SSUSB_S_4
1 1 1 VDDAN_11_SSUSB_S_5
USB SS

2 2
2 2 2 30mils
N16
N17 VDDCR_11_SSUSB_S_1 +3VS
P17 VDDCR_11_SSUSB_S_2
VDDCR_11_SSUSB_S_3 10mils 26mA
M17 AA4 +VDDIO_AZ 1 RS@ 2
4 VDDCR_11_SSUSB_S_4 VDDIO_AZ_S R99 0_0402_5% VDDIO_AZ_S should be tied to 4
L61 POWER 1 2 +3.3/1.5V_S5 rail if Wake on Ring
HCB2012KF-221T30_0805 424mA C1276 2.2U_0603_6.3V4Z is supported
2 1 HUDSON-M2_FCBGA656
+1.1VALW
10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K
C1278

C1279

C1280

C1281

42 ohm/4A 1 1 1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2 2 Issued Date 2012/09/12 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hudson-M2/M3-POWER/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 24 of 52
A B C D E
 A B C D E

Place closed to JLVDS1

LCD POWER CIRCUIT +LCDVDD
+3VS
+INVPWR_B+ B+
+3VS +LCDVDD
U8
W=60mils
1
W=60mils W=60mils 1 1
L11 C375 @ C419
5 OUT HCB2012KF-221T30_0805
1 IN 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1
1 1 2 2
2 C368 XEMC@ EMC@
GND
1U_0402_6.3V6K
C184

1000P_0402_50V7K
C364
4 0.1U_0402_16V4Z 1 1 XEMC@
IN @ C365
1 SM01000EJ00 3000ma
3 C367 2 2 68P_0402_50V8J 220ohm@100mhz
EN 4.7U_0603_6.3V6K
G5243T11U_SOT23-5 2 2 DCR 0.04
2
7 APU_ENVDD

LCD/ LED PANEL Conn.

@
1 R959 2
100K_0402_5%
+3VS
W=60mils JLVDS1
+5VS 1
+INVPWR_B+ 1

1
2 41
R383 3 2 G1 42
10K_0402_5% Q19 4 3 G2 43
4 G3

2
G
@ L2N7002LT1G_SOT23-3 5 44
@ APU_INVT_PWM 6 5 G4 45

2
3 1 EDP_HPD BKOFF# 7 6 G5 46
7 DP1_HPD 35 BKOFF# 7 G6
EDP_HPD 8

D
9 8
W=60mils +LCDVDD
10 9
10

1
1 2 TS_EN 11
2 35 TS_EN 12 11 2
R406
0_0402_5% R364 13 12
100K_0402_5% 14 13
15 14

2
16 15
17 16
APU_INVT_PWM 18 17
7 APU_INVT_PWM 19 18
20 19
21 20
21
1

22
R393 +3VS 23 22
@ 10K_0402_5% 1 R614 @2 24 23
100K_0402_1% C369 1 2 0.1U_0402_16V7K EDP1_AUXN_C 25 24
7 APU_EDP1_AUXN 25
7 APU_EDP1_AUXP C370 1 2 0.1U_0402_16V7K EDP1_AUXP_C 26
2

2 R615 @1 27 26
C371 1 2 0.1U_0402_16V7K EDP1_TXP0_C 28 27
7 APU_EDP1_TXP0 28
100K_0402_1% C372 1 2 0.1U_0402_16V7K EDP1_TXN0_C 29
7 APU_EDP1_TXN0 30 29
C373 1 2 0.1U_0402_16V7K EDP1_TXP1_C 31 30
7 APU_EDP1_TXP1 31
C374 1 2 0.1U_0402_16V7K EDP1_TXN1_C 32
7 APU_EDP1_TXN1 33 32
34 33
+5VS_TS 34
USB20_P3 35
22 USB20_P3 USB20_N3 36 35
22 USB20_N3 37 36
+3VS 37
USB20_P2_CAM 38
For Camera USB20_N2_CAM 39 38
40 39
40
E-T_0871K-F40N-00L
CONN@
3 3
SP010011Z00

CMOS co-layout 4pin conn & eDP conn

R442 1 RS@ 2 0_0402_5%

R428 1 RS@ 2 0_0402_5%
J17 L32
+5VS JUMP_43X39 +5VS_TS USB20_P2 3 4 USB20_P2_CAM
1 2 22 USB20_P2 3 4 +3VS
@ 1 2
USB20_N2 2 1 USB20_N2_CAM
22 USB20_N2 2 1
WCM2012F2SF-670T04_0805
XEMC@
JCAM1
R441 1 XEMC@ 2 0_0402_5% 1
R430 1 XEMC@ 2 0_0402_5% USB20_P2_EXCAM 2 1
USB20_N2_EXCAM 3 2
USB20_N2 2 1 USB20_N2_EXCAM 4 3
2 1 5 4
6 GND
USB20_P2 3 4 USB20_P2_EXCAM GND
3 4 CONN@
ACES_88266-04001
XEMC@ L31 SP02000K200
4 WCM2012F2SF-670T04_0805 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2012/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EDP CONN/Camera/TS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 25 of 52
A B C D E
 5 4 3 2 1

www.qdzbwx.com

D D
W=40mils

2
+HDMI_5V_OUT

2
@ @
D20 D21
T19

1
AZC199-02SPR7G_SOT23-3 AZC199-02SPR7G_SOT23-3

1
EMC@
L42 1 2

CRT Connector
FCH_CRT_R CRT_R_2 JCRT1
21 FCH_CRT_R 6
FCM2012CF-800T06_2P
EMC@ 11
FCH_CRT_G L43 1 2 CRT_G_2 1
21 FCH_CRT_G 7
FCM2012CF-800T06_2P
EMC@ 12
FCH_CRT_B L44 1 2 CRT_B_2 2
21 FCH_CRT_B 8
FCM2012CF-800T06_2P

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
13
1 1 1 1 1 1 3
1
2
3
4

C1175

C1176

C1177

C1178

C1179

C1180
9
14
150_0804_8P4R_1% 4
RP22 2 2 2 2 2 2 10 16
G
15 G 17
8
7
6
5

1@ 5
EMC@ EMC@ EMC@ EMC@ EMC@ EMC@ C1181
100P_0402_50V8J CCM_070546HR015M25FZR
CONN@
+HDMI_5V_OUT 2 T20 DC060005810
U23
1 5 1@ 2 C1182 L45 1 2 33_0603_5% CRT_HSYNC_2
OE Vcc 0.1U_0402_16V4Z FCH_CRT_SDA_1
C C
FCH_CRT_HSYNC 2 L46 1 2 33_0603_5% CRT_VSYNC_2 1
21 FCH_CRT_HSYNC IN A
1 1
@ @
3 4 CRT_HSYNC_1 C1183 C1184 @ FCH_CRT_SCL_1
GND OUT Y 10P_0402_50V8J 10P_0402_50V8J C1185 2
2 2 68P_0402_50V8J 1
@
M74VHC1GT125DF2G_SC70-5 C1186
68P_0402_50V8J
+HDMI_5V_OUT 2
U24
1 5
OE Vcc

FCH_CRT_VSYNC 2
21 FCH_CRT_VSYNC IN A

3 4 CRT_VSYNC_1
GND OUT Y

M74VHC1GT125DF2G_SC70-5
+3VS +HDMI_5V_OUT
RP13
FCH_CRT_SCL_1 8 1
FCH_CRT_SCL 7 2
FCH_CRT_SDA 6 3
+HDMI_5V_OUT FCH_CRT_SDA_1 5 4
C451 @ +3VS
1 2 0.1U_0402_16V4Z 2.2K_0804_8P4R_5%
1 2
B C452 @ B
0.1U_0402_16V4Z

1
2
7
U10
+3VS

VCC_VIDEO
VCC_SYNC

VCC_DDC
3 CRT_R_2
FCH_CRT_HSYNC 13 VIDEO_1 4 CRT_G_2
FCH_CRT_VSYNC 15 SYNC_IN1 VIDEO_2 5 CRT_B_2
SYNC_IN2 VIDEO_3
2

FCH_CRT_SCL 10 14 CRT_HSYNC_1
21 FCH_CRT_SCL 11 DDC_IN1 SYNC_OUT1 16
FCH_CRT_SDA CRT_VSYNC_1
21 FCH_CRT_SDA DDC_IN2 SYNC_OUT2
FCH_CRT_SDA 1 6 FCH_CRT_SDA_1
9 FCH_CRT_SCL_1
DMN66D0LDW-7_SOT363-6 1 2 8 DDC_OUT1 12 FCH_CRT_SDA_1
C454 BYP DDC_OUT2
Q56A
5

0.1U_0402_16V4Z DDC_CLK/DAT reserved PU Resistor

GND
@
FCH_CRT_SCL 4 3 FCH_CRT_SCL_1
For contact discharge ESD +/-8kV CM2009-00QR_QSOP16

6
@
Q56B
DMN66D0LDW-7_SOT363-6

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2012/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 26 of 52
5 4 3 2 1
 5 4 3 2 1

www.qdzbwx.com
+HDMI_5V_OUT
+5VS U6

3
W=40mils
D OUT D
1
EVT : Check List CH41 - 665 1% 1
IN C378
1 1
change to 500 ohm 12/27 (interlock V1.2) GND
2 0.1U_0402_16V4Z
RP25 C398 C396 2 EMC@
499_0804_8P4R_1% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C385 2 1 0.1U_0402_16V7K HDMI_CLK- 1 8 EMC@ 2 EMC@ 2 AP2330W-7_SC59-3
7 APU_DP2_N3
7 APU_DP2_P3 C386 2 1 0.1U_0402_16V7K HDMI_CLK+ 2 7
7 APU_DP2_N1 C381 2 1 0.1U_0402_16V7K HDMI_TX1- 3 6
7 APU_DP2_P1 C382 2 1 0.1U_0402_16V7K HDMI_TX1+ 4 5

7 APU_DP2_N0 C379 2 1 0.1U_0402_16V7K HDMI_TX2- 1 8

7 APU_DP2_P0 C380 2 1 0.1U_0402_16V7K HDMI_TX2+ 2 7
7 APU_DP2_N2 C383 2 1 0.1U_0402_16V7K HDMI_TX0- 3 6
7 APU_DP2_P2 C384 2 1 0.1U_0402_16V7K HDMI_TX0+ 4 5

RP26 HDMI_GND +3VS

3
499_0804_8P4R_1% +3VS
Q4B
+HDMI_5V_OUT
5

2
+3VS RP12 Q5A
DMN66D0LDW-7_SOT363-6 8 1 HDMI_SCLK

4
7 2 HDMI_SDATA 7 APU_HDMI_CLK
1 6 HDMI_SCLK
6 3 APU_HDMI_DATA

5
5 4 APU_HDMI_CLK DMN66D0LDW-7_SOT363-6

2.2K_0804_8P4R_5% 7 APU_HDMI_DATA 4 3 HDMI_SDATA

CRB use 4.7k, CL use 2.2k Q5B
C C
DMN66D0LDW-7_SOT363-6
Reserved for ESD

+3VS

2
R177
1M_0402_5%

2
1
SM070001310 400ma 90ohm@100mhz DCR 0.3
DP2_HPD 1 6 HDMI_DET
7 DP2_HPD
HDMI_CLK- R368 1 RS@ 2 0_0402_5% HDMI_R_CK-

4 3 Q4A
4 3

1
DMN66D0LDW-7_SOT363-6
1
WCM-2012-900T_0805 R178
L13 XEMC@ 1 2 100K_0402_5% C387
1 2 220P_0402_50V7K HDMI connector
HDMI_CLK+ R369 1 RS@ 2 0_0402_5% HDMI_R_CK+ 2 EMC@ JHDMI1

2
HDMI_DET 19
18 HP_DET
+HDMI_5V_OUT +5V
HDMI_TX0- R370 1 RS@ 2 0_0402_5% HDMI_R_D0- 17
HDMI_SDATA 16 DDC/CEC_GND
4 3 HDMI_SCLK 15 SDA
B 4 3 14 SCL B
Reserved

2
WCM-2012-900T_0805 13
L20 XEMC@ 1 2 HDMI_R_CK- 12 CEC
1 2 11 CK-
HDMI_TX0+ R371 1 RS@ 2 0_0402_5% HDMI_R_D0+ HDMI_R_CK+ 10 CK_shield
HDMI_R_D0- 9 CK+
8 D0-
HDMI_TX1- R372 1 RS@ 2 0_0402_5% HDMI_R_D1- D7 HDMI_R_D0+ 7 D0_shield
XEMC@ HDMI_R_D1- 6 D0+
4 3 5 D1-
YSLC05CH_SOT23-3

1
4 3 HDMI_R_CK- 1 2 HDMI_R_D1+ 4 D1_shield 20
WCM-2012-900T_0805 XEMC@ C565 10P_0402_50V8J HDMI_R_D2- 3 D1+ GND 21
L18 XEMC@ 1 2 HDMI_R_CK+ 1 2 2 D2- GND 22
1 2 XEMC@ C566 10P_0402_50V8J Reserved for ESD HDMI_R_D2+ 1 D2_shield GND 23
HDMI_TX1+ R373 1 RS@ 2 0_0402_5% HDMI_R_D1+ HDMI_R_D0- 1 2 D2+ GND
XEMC@ C568 10P_0402_50V8J SUYIN_100042GR019M23MZR
HDMI_R_D0+ 1 2 CONN@
HDMI_TX2- R374 1 RS@ 2 0_0402_5% HDMI_R_D2- XEMC@ C569 10P_0402_50V8J DC232001I00
HDMI_R_D1- 1 2
4 3 XEMC@ C571 10P_0402_50V8J
4 3 HDMI_R_D1+ 1 2
WCM-2012-900T_0805 XEMC@ C572 10P_0402_50V8J
L19 XEMC@ 1 2 HDMI_R_D2- 1 2
1 2 XEMC@ C579 10P_0402_50V8J ZZZ1 45@
HDMI_TX2+ R375 1 RS@ 2 0_0402_5% HDMI_R_D2+ HDMI_R_D2+ 1 2
XEMC@ C580 10P_0402_50V8J

Reserve for EMI 10/09

A HDMI Logo A

RO0000003HM

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2012/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI_CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
Date: Wednesday, February 12, 2014 Sheet 27 of 52
I'm from VIETNAM
5
sualaptop365
4 3 2 1
 5 4 3 2 1

Mini-Express Card for WLAN/WiMAX(Half)

www.qdzbwx.com
+3VS_WLAN
+3VALW
U17 W=60mils
1
5 OUT
D IN D

GND
2 Mini-Express Card(WLAN)
1U_0402_6.3V6K
C182

4
IN
1
3
Mini Card Power Rating
EN
AC@ G5243T11U_SOT23-5
2 AC@

+3VS_WLAN
35 WLAN_ON +3VS_WLAN
+1.5VS_WLAN
R429 1 2 4.7K_0402_5%
JMINI1
WLAN_WAKE# 1 2
35 WLAN_WAKE# 3 WAKE# 3.3V 4
5 NC GND 6
7 NC 1.5V 8
22 MINI1_CLKREQ# CLKREQ# NC
9 10
11 GND NC 12
20 CLK_PCIE_MINI1# 13 REFCLK- NC 14
20 CLK_PCIE_MINI1 15 REFCLK+ NC 16
17 GND NC 18
19 NC GND 20 WL_OFF#_EC
21 NC NC 22 APU_PCIE_RST# WL_OFF#_EC 35
23 GND PERST# 24 APU_PCIE_RST# 20,29
5 PCIE_PRX_DTX_N1 PERn0 +3.3Vaux
25 26
5 PCIE_PRX_DTX_P1 PERp0 GND
27 28
29 GND +1.5V 30 MINI1_SMBCLK R432 1 @ 2 0_0402_5%
GND SMB_CLK FCH_SCLK0 11,12,22
31 32 MINI1_SMBDATA R434 1 @ 2 0_0402_5%
C 5 PCIE_PTX_C_DRX_N1 PETn0 SMB_DATA FCH_SDATA0 11,12,22 C
33 34
5 PCIE_PTX_C_DRX_P1 35 PETp0 GND 36
37 GND USB_D- 38 USB20_N4 22
39 NC USB_D+ 40 USB20_P4 22
41 NC GND 42 R443 1 2 100K_0402_5%
+3VS_WLAN NC LED_WWAN# +3VS_WLAN
43 44
NC LED_WLAN# MINI1_LED# 35
45 46
47 NC LED_WPAN# 48
49 NC +1.5V 50
35 E51TXD_P80DATA 51 NC GND 52
+1.5VS +1.5VS_WLAN 35 E51RXD_P80CLK NC +3.3V
J1

1
JUMP_43X39 ECRX need support BT_ON 53 54
1 2 GND GND
1 2 R437
@ 1 100K_0402_5% ACES_50709-0524W-P01
@ C463 CONN@

2
0.1U_0402_16V4Z DC04000C400
2

+3VS
60mil +3VS_WLAN
@ J2
1 2
1 1 1
JUMP_43X118 C458 C459 C460
@ 0.1U_0402_16V4Z
B 4.7U_0603_6.3V6K 0.1U_0402_16V4Z B
2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2012/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI Card
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 28 of 52
5 4 3 2 1
 A B C D E

+3V_LAN
+3VALW
60mil
60mil U62
1
5 OUT
IN
2
4 GND
IN
2 3
EN
C1096 G5243T11U_SOT23-5
1 1U_0402_6.3V6K 1
1 Part Number = SA000028Y10 W=60mil +3V_LAN
IDC=1200mA +LAN_VDD W=60mil
35 LAN_PWR_EN 300mA 1.4A
L50
+REGOUT 1 2
W=60mil 2.2UH_NLC252018T-2R2J-N_5%

4.7U_0603_6.3V6K
C1097

.1U_0402_16V7K
C1098

.1U_0402_16V7K
C1099

.1U_0402_16V7K
C1100

.1U_0402_16V7K
C1101

.1U_0402_16V7K
C1102

.1U_0402_16V7K
C1104

1U_0402_6.3V6K
C1105

.1U_0402_16V7K
C1106

4.7U_0603_6.3V6K
C1107

.1U_0402_16V7K
C1108

.1U_0402_16V7K
C1109

.1U_0402_16V7K
C1110
1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2

Using for Switch mode

Place near Pin 3,8,33,46 Place near Pin 20 Using for Switch mode Place near Pin 11,32,48
The trace length from Lx to
From EC PIN48 (REGOUT) and from C to Lx The trace length
must < 200mils. from C to
High active. PIN46,47(VDDREG)
EN threshold voltage min:1.2V typ:1.6V max:2.0V
Current limit threshold 1.5~2.8A
Reserve for EMI please close to IC must < 200mils.

+3V_LAN Rising time must >0.5ms and <100ms

LAN_WAKE# pull high 100K to +3VALW R486 1 2 100K_0402_5%

+3V_LAN
U63
R607 1 @ 2 0_0402_5% Power Manahement/Isolation
2 21,22 FCH_PCIE_WAKE# 2
ISOLATEB 31
R608 1 RS@ 2 0_0402_5% LAN_PME# 39 ISOLATEBPIN
35 LAN_WAKE# LANWAKEB Card Reader
15 SD_D0 R609 1 RS@ 2 0_0402_5% SD_D0_R
SD_D0/MS_D1 14 1 SD_D0_R 30
PCI-Express SD_D1 R610 RS@ 2 0_0402_5% SD_D1_R
CLK_PCIE_LAN 23 SD_D1 16 SD_CLK 1 EMC@ 2 10_0402_5% SD_CLK_R SD_D1_R 30
20 CLK_PCIE_LAN R774 SD_CLK_R 30
CLK_PCIE_LAN# 24 REFCLK_P SD_CLK/MS_D0 17 SD_CMD R611 1 RS@ 2 0_0402_5% SD_CMD_R
20 CLK_PCIE_LAN# REFCLK_N SD_CMD/MS_D2 SD_CMD_R 30
18 SD_D3 R612 1 RS@ 2 0_0402_5% SD_D3_R 2
30 SD_D3/MS_D3 19 1 SD_D3_R 30
APU_PCIE_RST# SD_D2 R613 RS@ 2 0_0402_5% SD_D2_R
20,28 APU_PCIE_RST# LAN_CLKREQ# 29 PERSTBPIN SD_D2/MS_CLK 28 SD_WP SD_D2_R 30
C183
22 LAN_CLKREQ# CLKREQBPIN MS_BS/SD_WP# SD_WP 30
5P_0402_50V8C
C788 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_P0 25 1
5 PCIE_PRX_DTX_P0 HSOP XEMC@
C791 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_N0 26
5 PCIE_PRX_DTX_N0 21 HSON 42 SD_CD#
5 PCIE_PTX_C_DRX_P0 HSIP SD_CD# SD_CD# 30
22 43
5 PCIE_PTX_C_DRX_N0 HSIN MS_CD#
Transceiver Interface
LAN_MIDI0+ 1
30 LAN_MIDI0+ 2 MDIP0
LAN_MIDI0-
30 LAN_MIDI0- LAN_MIDI1+ 4 MDIN0
30 LAN_MIDI1+ LAN_MIDI1- 5 MDIP1 48 +3V_LAN
30 LAN_MIDI1- 6 MDIN1 HV_GIGA 11
LAN_MIDI2+
30 LAN_MIDI2+ LAN_MIDI2- 7 MDIP2 HV_GIGA 12
30 LAN_MIDI2- MDIN2 VDD33
1500mA
LAN_MIDI3+ 9 32
30 LAN_MIDI3+ LAN_MIDI3- 10 MDIP3 VDD33
30 LAN_MIDI3- MDIN3

XTLI 44 33
XTLO R6171 2 0_0402_5% XTLO_R 45 CKXTAL1 Clock VDD10 3
+LAN_VDD Protect cotact Card contact
CKXTAL2 AVDD10 8
AVDD10
300mA
Y6
25MHZ_10PF_7V25000014 Regulator and Reference Write protect Write Enable
3 +REGOUT 36 20 3
XTLI 1 3 XTLO 35 REG_OUT VDDTX (Lock) (Unlock)
1 3 +3V_LAN VDDREG
SWR mode 34 1000mA
1
GND GND
1 +LAN_VDD
46 ENSWREG 13
+CARD_3V3
Card Uninsert Open Open Open
LV_GEN CARD_3V3
C799 2 4 C800 R1041 2 1 2.49K_0402_1% LAN_RST 47 Card insert Open Close Close
10P_0402_50V8J RSET 27 +VDD33_18
10P_0402_50V8J DV33/18
2 2

.1U_0402_16V7K
C1113

4.7U_0603_6.3V6K
C1114

.1U_0402_16V7K
C1112
41
R6161 @ 2 0_0402_5% GPO 38 LED0
35 LAN_GPO LED1/GPO 1 1 1
37 LEDs
1 @ 2 40 LED2
+3V_LAN LED_CR
R1039 10K_0402_5% 49 @
E_PAD 2 2 2

+3VS
Place near Pin 27
1

R1042 RTL8411B-CGT_QFN48_6X6
1K_0402_5%
2

ISOLATEB
2

R1044
15K_0402_5%
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2012/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_RTL8411B
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 29 of 52
A B C D E
 5 4 3 2 1

www.qdzbwx.com
LAN Connector
JRJ1

D
T14 D
RJ45_MIDI0+ 1 9
LAN_TERMAL1 24 PR1+ SHLD1 10
LAN_MIDI3- 2 TCT1 MCT1 23 RJ45_MIDI3- RJ45_MIDI0- 2 SHLD2
29 LAN_MIDI3- TD1+ MX1+ PR1-
29 LAN_MIDI3+ LAN_MIDI3+ 3 22 RJ45_MIDI3+
TD1- MX1- RJ45_MIDI1+ 3
4 21 PR2+ JP1 XEMC@
LAN_MIDI2- 5 TCT2 MCT2 20 RJ45_MIDI2- RJ45_MIDI2+ 4 B88069X9231T203_4P5X3P2-2
29 LAN_MIDI2- TD2+ MX2+ PR3+
29 LAN_MIDI2+ LAN_MIDI2+ 6 19 RJ45_MIDI2+ 2 1
TD2- MX2- RJ45_MIDI2- 5
7 18 PR3- 40mil
LAN_MIDI1- 8 TCT3 MCT3 17 RJ45_MIDI1- RJ45_MIDI1- 6 RJ45_GND 1 2 LANGND
29 LAN_MIDI1- TD3+ MX3+ PR2-
29 LAN_MIDI1+ LAN_MIDI1+ 9 16 RJ45_MIDI1+ C814
TD3- MX3- RJ45_MIDI3+ 7 10P_0402_50V8J
10 15 PR4+

2
LAN_MIDI0- 11 TCT4 MCT4 14 RJ45_MIDI0- RJ45_MIDI3- 8 LANGND
29 LAN_MIDI0- TD4+ MX4+ PR4-

1
29 LAN_MIDI0+ LAN_MIDI0+ 12 13 RJ45_MIDI0+
TD4- MX4-

MESC5V02BD03_SOT23-3
R876

D39 EMC@
0_0603_5% JP2
XEMC@ XEMC@

1
4
3
2
1
GST5009-E B88069X9231T203_4P5X3P2-2
SP050006B10 75_0804_8P4R_1% SANTA_130452-0B

2
1 RP23 CONN@

C810
DC234005310

5
6
7
8

1
.1U_0402_16V7K
2
RJ45_GND
Del J3 01/21 confirm with EMI
Place close to TCT pin reserve 0 ohm by HW decide

C C

Card Reader Connector

JREAD1
29 SD_D3_R SD_D3_R 1
CD/DAT3
+CARD_3V3 29 SD_CMD_R SD_CMD_R 2
CMD
3
VSS1
B Close to Card Reader CONN 4 B
VDD

4.7U_0603_6.3V6K
C817

0.1U_0402_16V7K
C818
29 SD_CLK_R SD_CLK_R 5
CLK
1 1
6
VSS2
29 SD_D0_R SD_D0_R 7
2 2 DAT0
29 SD_D1_R SD_D1_R 8 12
DAT1 G1
29 SD_D2_R SD_D2_R 9 13
DAT2 G2
SD_CD# 10 14
29 SD_CD# CD G3
SD_WP 11 15
29 SD_WP WP G4
TAITW_PSDAT4-11GLBS1NN4H2
CONN@
SP07000ZC00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2014/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader/LAN Conn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Z5WAK M/B LA-B221P 0.2

I'm from VIETNAM sualaptop365

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 12, 2014 Sheet 30 of 52
5 4 3 2 1
 5 4 3 2 1

www.qdzbwx.com FAN1 Conn

KB Conn.
KSI[0..7]
KSI[0..7] 35
KSO[0..17]
KSO[0..17] 35 +5VS C632
D 4.7U_0603_10V6K D
1 2

KB BackLight Conn. Reserve

U31
JKB1 1 8
2 EN GND 7
KSO0 1 +VCC_FAN1 3 VIN GND 6
KSO1 2 1 4 VOUT GND 5
3 2 35 EN_DFAN1 VSET GND
KSO2
KSO3 4 3 NCT3942S SOP 8P
4 1
KSO4 5
KSO5 6 5 +5VS C626
KSO6 7 6 JBL1 0.1U_0402_16V4Z
8 7 3 1 4 6 2

D
KSO7 +5VS_BL @ NOTE : footprint is SA00005JO00 (X1)
KSO8 9 8 +5VALW 3 4 G2 5
KSO9 10 9 BL@ 2 3 G1 bom load SA00005CA00
KSO10 11 10 R451 Q44 1 2

G
2
KSO11 12 11 100K_0402_5% DMG2301U-7_SOT23-3 1
KSO12 13 12 1 BL@ 2 KBL_EN_R ACES_50504-0040N-001
KSO13 14 13 CONN@
KSO14 15 14 1 BL@ 2
15 SP01000Z300
KSO15 16 R592
16

1
KSO16 17 0_0402_5% D C627
17 1
KSO17 18 2 4.7U_0603_10V6K
18 35 KBL_EN# +3VS
KSI0 19 G C524 @ 1 2
KSI1 20 19 @ Q28 S 0.1U_0603_25V7K

3
KSI2 21 20 L2N7002LT1G_SOT23-3 2 @ C631
21

1
KSI3 22 1000P_0402_50V7K
KSI4 23 22 R516 1 2
KSI5 24 23 10K_0402_5%
KSI6 25 24 27
C KSI7 26 25 G1 28
40mil JFAN1 C

2
26 G2 +VCC_FAN1 1
2 1 4
35 FAN_SPEED1 3 2 GND 5
E-T_6905-E26N-01R
CONN@ 3 GND
1
SP01000IJ00 C630
1000P_0402_50V7K ACES_88231-03041
XEMC@ CONN@
2
SP020020710

H2 H27
H_6P5 H_3P7

FD1 FD2 FD3 FD4

B B

1
@ @
H4 H3 @ @ @ @
CPU H_3P0 H_3P0

H14 H13 H12

H_4P0 H_4P0 H_4P0 H17 H18
1

1
H_3P0N H_3P0X3P5N
1

@ @ @ @

1
H8 H6 H5
H_3P0 H_3P0 H_3P0
@ @ @
1

VGA
H16 H15 @ @ @
H_4P0 H_4P0

H11 H10 H9
H_3P0 H_3P0 H_3P0
1

@ @

A A
@ @ @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2012/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN/screw/KB/KB BL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 31 of 52
5 4 3 2 1
LED
www.qdzbwx.com
ON/OFF BTN PWR/B

JPWR1
+3VLP 1
LED LED6 +3VALW 1
2
2
3
+3VALW
+3VLP
LID_SW#
3 LID_SW# 35
BATT_BLUE_LED# 1 2 1 2 4 PWR_LED#
35 BATT_BLUE_LED# 4

2
B R699 330_0402_5% 7 5 ON/OFFBTN#
R535 8 G1 5 6
BATT_AMB_LED# 3 4 1 2
Test Only G2 6
35 BATT_AMB_LED# SW3 100K_0402_5%
A R698 560_0402_5% TJE-532QR5_4P ACES_51524-0060N-001
1 3 CONN@

1
LTST-C295TBKF-CA_AMBER-BLUE TOP ON/OFFBTN# SP010014M10
2 4 ON/OFFBTN# 35
LED7

PWR_LED# 1 2 1 2

6
5
B R700 330_0402_5%

PWR_SUSP_LED# 3 4 1 2
35 PWR_SUSP_LED# A R701 560_0402_5%

LTST-C295TBKF-CA_AMBER-BLUE
PWR_LED#

1
D Q21
2 L2N7002LT1G_SOT23-3
35 PWR_LED
G

1
S

3
R536
100K_0402_5%

avoid flash issue when

2
abnormall shutdown

TPM Board G-sensor

+3VALW +3VALW_TPM +3VS +3VS_TPM
R2600 R2601
1 2 1 2
10U_0603_6.3V6M

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0_0603_5% 0_0603_5%
C2600 TPM@

C2601 TPM@

C2602 TPM@

C2603 TPM@

C2604 TPM@

C2605 TPM@
TPM@ 1 1 TPM@ 1 1 1 1

2 2 near pin5 2 2 2 2

near pin10, 19, 24

BADD SELECTION
0 EEh - EFh

* 1 7Eh - 7Fh
U2600
5
VSB +3VALW_TPM
1 10
GPIO0/XOR_OUT VDD +3VS_TPM
2 19
GPIO3/BADD with Internal PH (default) 6 GPIO1 VDD 24
0_0402_5% 1 @ 2 R2602 TPM_BADD 9 GPIO2/GPX VDD
CLKRUN# 15 GPIO3/BADD 8
20 CLKRUN# GPIO4/CLKRUN# TEST
AMD CLKRUN# no need PH (DG1.1) LPC_AD0 26
20,35 LPC_AD0 23 LAD0/MISO
LPC_AD1
20,35 LPC_AD1 LPC_AD2 20 LAD1/MOSI 3
20,35 LPC_AD2 LPC_AD3 17 LAD2/SPI_IRQ# NC 12
20,35 LPC_AD3 LAD3 NC 13
NC 14
R447 1 @ 2 0_0402_5% 28 NC
LPCPD# had internal PH 22 LPCPD#
LPC_CLK1 21 LPCPD#
20,23 LPC_CLK1 LPC_FRAME# 22 LCLK/SCLK
20,35 LPC_FRAME# 16 LRFAME#/SCS# 4
PLT_RST#
20,35 PLT_RST# 27 LRSET#/SPI_RST# GND 11
SERIRQ no need PH SERIRQ
20,35 SERIRQ 7 SERIRQ GND 18
PP GND 25
GND

NPCT650AA0WX_TSSOP28
SA00007IO00
+3VS_TPM TPM@
1 @ 2 CLKRUN#
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
R2604 Issued Date 2012/09/12 2012/07/29 Title
LPC_CLK1 R2603 1 2 33_0402_5% C2606 1 2 22P_0402_50V8J Deciphered Date
CLKRUN# PH request by TPM chip DG 1/22
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR B/LED/TPM
XEMC@ XEMC@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
Date: Wednesday, February 12, 2014 Sheet 32 of 52

I'm from VIETNAM sualaptop365

 A B C D E F G H

www.qdzbwx.com
SATA ODD Conn. SATA HDD Conn.

JODD1
1 1 JHDD1 1
C401 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 2 GND
21 SATA_PTX_DRX_P1 A+
21 SATA_PTX_DRX_N1 C402 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3 1
4 A- SATA_PTX_DRX_P0 C392 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 GND
GND 21 SATA_PTX_DRX_P0 A+
C403 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 5
21 SATA_PTX_DRX_N0
SATA_PTX_DRX_N0 C393 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
21 SATA_PRX_DTX_N1 B- A-
C405 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 6 4
21 SATA_PRX_DTX_P1 7 B+ GND
SATA_PRX_DTX_N0 C391 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5
GND 21 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C394 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 B-
+5VS 21 SATA_PRX_DTX_P0 7 B+
@ J19 8 GND
1 2
80mils +5VS_ODD 9 DP
1 2 +5V

10U_0603_6.3V6M
C404

0.1U_0402_16V4Z
C407
1 10 8
+5V +3VS V33

1
JUMP_43X79 ODD_MD 11 9
12 MD 14 10 V33
T185 @ 13 GND GND 15 11 V33
2 2 GND GND 12 GND
@ J20 13 GND
SANTA_201902-1 1 2 +5VS_HDD 14 GND
+5VS 1 2 V5
CONN@ 15
JUMP_43X79 16 V5
SP01001RS00 17 V5
18 GND
19 Reserved 23
20 GND GND 24
21 V12 GND 25
22 V12 GND 26
V12 GND

CCM_C127043HR022M27FZR
CONN@

+3VS +5VS_HDD
DC010009X00
2 2

100mils

10U_0603_6.3V6M
C420

0.1U_0402_16V4Z
C397
1 1

1
0.1U_0402_16V4Z
C390
@

2
2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2012/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Conn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 33 of 52
A B C D E F G H
 A B C D E

HD Audio Codec
+5VS +VDDA
J4
40mil 40mil
www.qdzbwx.com C554

0.1U_0402_16V4Z
1

(output = 300 mA)

1

JUMP_43X118
@
2

4.75V

XEMC@2

Reserved for ESD

SM01000EJ00 3000ma 220ohm@100mhz DCR 0.04 +PVDD_HDA
40mil Int. Speaker Conn.
L33 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z GND
1 +VDDA +AVDD1_HDA 1
HCB2012KF-221T30_0805 1 1 40mil JSPK1

1
10U_0603_6.3V6M
C608
C558 C559 SPKR+ R98 1 RS@ 2 0_0603_5% SPK_R+ 1
R115 SPKR- R14 1 RS@ 2 0_0603_5% SPK_R- 2 1
@ 0.1U_0402_16V4Z
20mil 1 RS@ 2 SPKL+ R96 1 RS@ 2 0_0603_5% SPK_L+ 3 2 5
+VDDA

2
2 2 SPKL- R97 1 RS@ 2 0_0603_5% SPK_L- 4 3 G1 6
1 1 4 G2

C567
10U_0603_6.3V6M
0_0603_5%

1
GND GND C562 C561 ACES_88266-04001
Place near Pin41 Place near Pin46 @ 1 1 1 1 CONN@ GND
2 2 C606 C607 C609 C610 SP02000K200

2
0.1U_0402_16V4Z

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
+3VS_DVDD 2 2 2 2
GNDA
Place near Pin26
R113
1 RS@ 2 20mil 0.1U_0402_16V4Z +3VS_DVDD
+3VS
0_0603_5%
1 1 1 R114
C564 C636 C582 +1.5VS_VDDA 0.1U_0402_16V4Z 1 RS@ 2
+1.5VS
@ 1 0_0603_5% EMC@ EMC@ EMC@ EMC@

1
C605
10U_0603_6.3V6M
10U_0603_6.3V6M C604
2 2 2
0.1U_0402_16V4Z GND

2
2
Place near Pin1, 9 GND
GNDA
U36 Place near Pin40

41

46

26

40
1

PVDD1

PVDD2

AVDD1

AVDD2
DVDD

DVDD-IO
Digital MIC Conn.
LINE1-L 22
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPKL-
LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPKL+
24
23 LINE2-L(PORT-E-L)
SPK-OUT-L+
45 SPKR+
Slave +3VS
Main
40mil LINE2-R(PORT-E-R) SPK-OUT-R+ 44 SPKR-
RING2 17 SPK-OUT-R- MIC2 @
2 2
SLEEVE 18 MIC2-L(PORT-F-L) /RING2 +3VS 6 5 DMIC_DATA
Combo MIC MIC2-R(PORT-F-R) /SLEEVE MIC1 VDD DATA
32 HP_LEFT @
+MICBIAS 31 HPOUT-L(PORT-I-L) 33 HP_RIGHT 6 5 DMIC_DATA_S 2 4 DMIC_CLK
+MICBIAS LINE1-VREFO-L HPOUT-R(PORT-I-R) VDD DATA CS CLK
30
LINE1-VREFO-R 10 HDA_SYNC_AUDIO 2 4 DMIC_CLK 2 R460 1 1 3
SYNC HDA_SYNC_AUDIO 22 CS CLK ENHANCE GND
DMIC_DATA 2 6 HDA_BITCLK_AUDIO 0_0402_5%
GPIO0/DMIC-DATA BCLK HDA_BITCLK_AUDIO 22
DMIC_CLK 3 1 3 2DMIC@ S MIC ST MP45DT02TR
GPIO1/DMIC-CLK ENHANCE GND

2
1 XEMC@ 2 1 2 C573 XEMC@ GND 2 1DMIC@

2
R548 0_0402_5% 22P_0402_50V8J S MIC ST MP45DT02TR
0_0402_5%

@
EC_MUTE# 47 5 HDA_SDOUT_AUDIO D57
HDA_RST_AUDIO# 11 PDB
RESETB
ALC283-CG SDATA-OUT
SDATA-IN
8 HDA_SDIN0_AUDIO 1 EMC@ 2
HDA_SDOUT_AUDIO
HDA_SDIN0 22
22
C893
1 0.1U_0402_16V4Z
R462 MESC5V02BD03_SOT23-3
R547 33_0402_5% D58 R456 XEMC@

1
48 MESC5V02BD03_SOT23-3 0_0402_5%
+MIC2_VREFO

1
MONO_IN 12 SPDIF-OUT/GPIO2 XEMC@ 1DMIC@
PCBEEP 16
Close codec MONO-OUT
HP_PLUG# R545 2 1 39.2K_0402_1% SENSE_A 13 10U_0603_6.3V6M 2 1 C583 GND

1
14 SENSE A
10mil

1
SENSE B 29
1 MIC2-VREFO
37 10U_0603_6.3V6M 2 1 C574 GNDA
C570 35 CBP 7
2.2U_0402_6.3V6M CBN LDO3-CAP 39
2 LDO2-CAP 27 10U_0603_6.3V6M 2 1 C584 GNDA R526 Realtek add request
36 LDO1-CAP
+3VS_DVDD CPVDD 1 R526 2 10mil
28 CODEC_VREF 100K_0402_5%
1 @ R525 2100K_0402_5% 20 VREF
+3VS CPVREF 1 1 1

2.2U_0402_6.3V6M
C577

@
Realtek add request 15 20K_0402_1% 1 2 R546 GNDA @
JDREF

0.1U_0402_16V4Z
C576

10U_0603_6.3V6M
C578
10U_0603_6.3V6M 2 1 C585 19 34 CPVEE
GNDA MIC-CAP CPVEE
Close codec
2 2 2 +MIC2_VREFO
1
4
49 DVSS 25 C575
Thermal PAD AVSS1 38 2.2U_0402_6.3V6M
AVSS2

1
2
R540 R539
ALC283-CG_MQFN48_6X6 Place next pin27 2.2K_0402_5% 2.2K_0402_5%
3 GND GNDA 3
GND

2
GNDA
HPOUT_L_2 SLEEVE_L L75 1 2 EMC@ SLEEVE
HPOUT_R_2
RING2_L L76 1 2 EMC@ RING2

2
MESC5V02BD03_SOT23-3
D3

AZ5123-02S 3P C/A SOT23-3

D2 2 2
XEMC@ C587 C586
EMC@ EMC@ EMC@
680P_0402_50V7K 680P_0402_50V7K
R529
47K_0402_5% +3VALW +3VS +3VLP
1 1 Headphone Out
2 @ 1 BEEP#_R 1 2 MONO_IN
35 BEEP#

1
C555 GND GND
2

R530 1 1U_0402_6.3V6K
2

47K_0402_5% XEMC@ @ @ RING2 GND GND

100P_0402_50V8J
C556

4.7K_0402_5%
R531

2 1 R552 R551 R550

22 FCH_SPKR JHP1
100K_0402_5% 100K_0402_5%
2 100K_0402_5% 59_0603_1% R111 RING2_L 3
1

HP_LEFT R238 1 2 HPOUT_L_1 1 RS@ 2 HPOUT_L_2 1

1

DMN66D0LDW-7_SOT363-6 0_0603_5%
D
5 G

S Q32A HP_PLUG# 5
4
DMN66D0LDW-7_SOT363-6

6
GNDA HP_RIGHT R237 1 2 HPOUT_R_1 R112
6

EC_MUTE# 2 R553 1 Q32B 59_0603_1% 1 RS@ 2 HPOUT_R_2 2

35 EC_MUTE# D
10K_0402_5% 2 G 0_0603_5%
HDA_RST_AUDIO# 2 R554 1 S LINE1-L 1 2 2 2 SLEEVE_L 4
22 HDA_RST_AUDIO# 7
10K_0402_5% GNDA C557 4.7U_0402_6.3V6M C444 C445
1

LINE1-R 1 2 XEMC@ XEMC@

1 2 C560 4.7U_0402_6.3V6M 330P_0402_50V7K 330P_0402_50V7K SINGA_2SJ3080-001111F
1 1 GNDA CONN@
@ C563 +MICBIAS D6
GNDA DC23000B300
1U_0402_6.3V6K 2 2 R533 1
4 GNDA 4.7K_0402_5% 4
J16 J15 1
JUMP_43X39 JUMP_43X39 To solve the background noise while combo jack
1 2 1 2 connecting to an active 3 2 R534 1
@ 1 2 @ 1 2 4.7K_0402_5% GNDA
J7 J5 speaker and system entry into S3/S4/S5 without analog BAT54A-7-F_SOT23-3
JUMP_43X39 JUMP_43X39 power
1 2 1 2
@ 1 2 @ 1 2
J8 J6
JUMP_43X39 JUMP_43X39
1 2 1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
@ 1 2 @ 1 2
2012/07/10 2013/07/10 Title
Issued Date Deciphered Date
GND GNDA GND GNDA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC283
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
A I'm from VIETNAM sualaptop365 B C D
Date: Wednesday, February 12, 2014
E
Sheet 34 of 52
 A B C D E

+3VALW +3VALW_EC
Analog Board ID definition
R117 L73
0_0805_5% MBK1608121YZF_0603 +EC_VCCA +3VALW_EC
1 @ 2 C1345 C1346 C1347 C1348 C1349 C1350 2 1 +EC_VCCA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K

1000P_0402_50V7K
1 1 1 1 2 2

2
+3VLP
1
@ J18 C1351 R1024
1 2 @ 0.1U_0402_16V4Z Ra 100K_0402_5%
1 2 2 2 2 2 1 1
JUMP_43X79 2

1
ECAGND AD_BID0
ECAGND 39

1
1 1
1

www.qdzbwx.com C1356

111
125
Rb R1027

22
33
96

67
9
U32 15K_0402_1% 0.1U_0402_16V4Z
2

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC

2
EC_GA20 1 21 LAN_PWR_EN DVT BID=1
22 EC_GA20 2 GATEA20/GPIO00 GPIO0F 23 LAN_PWR_EN 29
EC_KBRST#
22 EC_KBRST# SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# 34
20,32 SERIRQ LPC_FRAME# 4 SERIRQ GPIO12 27 EC_RTCRST
20,32 LPC_FRAME# LPC_AD3 5 LPC_FRAME# ACOFF/GPIO13 EC_RTCRST 20 +3VALW_EC
C1352 R1014
20,32 LPC_AD3 7 LPC_AD3
22P_0402_50V8J 22_0402_5% LPC_AD2 PWM Output RP14
2 1 2 1 20,32 LPC_AD2 LPC_AD1 8 LPC_AD2 63 BATT_TEMP EC_SMB_CK1 8 1
20,32 LPC_AD1 10 LPC_AD1 BATT_TEMP/AD0/GPIO38 64 BATT_TEMP 39 7 2
XEMC@ XEMC@ LPC_AD0 LPC & MISC VCIN1_BATT_DROP EC_SMB_DA1
20,32 LPC_AD0 LPC_AD0 AD1/GPIO39 65 ADP_I VCIN1_BATT_DROP 39 EC_SMB_CK2 6 3
CLK0_LPC_EC 12 ADP_I/AD2/GPIO3A 66 AD_BID0 ADP_I 39,40 EC_SMB_DA2 5 4
20,23 CLK0_LPC_EC CLK_PCI_EC AD Input AD3/GPIO3B
PLT_RST# 13 75
2 9012@ 1 20,32 PLT_RST# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76
+3VALW_EC 2.2K_0804_8P4R_5%
R1011 47K_0402_5% EC_SCI# 20 EC_RST# IMON/AD5/GPIO43
2 1 22 EC_SCI# 38 EC_SCII#/GPIO0E
28 WLAN_ON GPIO1D
C1353 0.1U_0402_16V4Z
9012@ 68
DAC_BRIG/GPIO3C 70 EN_DFAN1 KBL_EN# 31
DA Output EN_DFAN1/GPIO3D EN_DFAN1 31
KSI0 55 71 TP_SENOFF#
KSO[0..17] KSI1 56 KSI0/GPIO30 IREF/GPIO3E 72 TP_SENOFF# 36 +3VALW_EC
KSO[0..17] 31 KSI2 57 KSI1/GPIO31 CHGVADJ/GPIO3F
KSI[0..7] KSI3 58 KSI2/GPIO32 83 EC_MUTE#
KSI[0..7] 31 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 EC_MUTE# 34 1 2
KSI4 USB_EN# LID_SW#
60 KSI4/GPIO34 USB_EN#/GPIO4B 85 USB_EN# 36
KSI5 EC_I2C_TPCLK R125 1 @ 2 0_0402_5% 100K_0402_5% R1031
61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 EC_SCLK1_TP 36
KSI6 PS2 Interface EC_I2C_TPDAT R126 1 @ 2 0_0402_5% LAN_WAKE# 1 @ 2
2 62 KSI6/GPIO36 EAPD/GPIO4D 87 1 EC_SDATA1_TP 36 2
KSI7 TP_CLK_R RS@ 2 10K_0402_5% R1032
KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA_R 1 2 TP_CLK 36 ENBKL 1 2
R1684 RS@0_0402_5% @
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 36
R1685 0_0402_5% 100K_0402_5% R1034
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 ENBKL
KSO4 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 GPU_ACIN ENBKL 7
KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 GPU_ACIN 14
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH 39
KSO7/GPIO27 SPI Device Interface
KSO8 47
KSO9 48 KSO8/GPIO28 119
KSO9/GPIO29 SPIDI/GPIO5B EC_SPI_MISO 21 For share ROM reserve
KSO10 49 120
50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SPI_MOSI 21 1 2
KSO11 SPI Flash ROM EC_RSMRST# @
KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 EC_SPI_CLK 21
4.7K_0402_5% R1021
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS1# 21
KSO14 53 KSO13/GPIO2D 1.1V_EN 1 @ 2
KSO15 54 KSO14/GPIO2E 73 4.7K_0402_5% R1020
KSO16 81 KSO15/GPIO2F ENBKL/AD6/GPIO40 74 VGATE
KSO16/GPIO48 PECI_KB930/AD7/GPIO41 VGATE 45
KSO17 82 89
KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_BLUE_LED#
BATT_CHG_LED#/GPIO52 91 TP_PWR_EN BATT_BLUE_LED# 32 BATT_TEMP 2 1
77 CAPS_LED#/GPIO53 92 TP_PWR_EN 36
EC_SMB_CK1 GPIO PWR_LED 100P_0402_50V8J C1360
39,40 EC_SMB_CK1 EC_SMB_DA1 78 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 93 BATT_AMB_LED# PWR_LED 32 ACIN 2 1
39,40 EC_SMB_DA1 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_AMB_LED# 32
EC_SMB_CK2 SM Bus SYSON 100P_0402_50V8J C1363
14,7 EC_SMB_CK2 EC_SMB_DA2 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 VR_ON SYSON 37,42
14,7 EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 1.1V_EN VR_ON 43,45
PM_SLP_S4#/GPIO59 1.1V_EN 44
EC_I2C_ALERT# 1 @ 2
SLP_S3# 6 100 EC_RSMRST# 1K_0402_5% R127
1 22 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# 22
RS@ 2 EC_I2C_ALERT# 14 101 EC_LID_OUT# EC_MUTE# 1 @ 2
+3VS
22,36 TP_I2C_INT# EC_SMI# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 VCIN1_PROCHOT EC_LID_OUT# 22
R1683 0_0402_5% 10K_0402_5% R1033
22 EC_SMI# 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 EC_THERM VCIN1_PROCHOT 39
3 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 EC_THERM 39 3
WL_OFF#_EC MAINPWON
28 WL_OFF#_EC 18 GPIO0B VCOUT0_PH/GPXIOA07 105 MAINPWON 39,41,7
WLAN_WAKE# GPO BKOFF#
28 WLAN_WAKE# TS_EN 19 GPIO0C BKOFF#/GPXIOA08 106 LAN_GPO BKOFF# 25 Delay SUSP# 10ms
25 TS_EN GPIO0D GPIO PBTN_OUT#/GPXIOA09 LAN_GPO 29
25 107 3V_EN
41 SPOK EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 3V_EN 41
FAN_SPEED1 28 108 MINI1_LED#
31 FAN_SPEED1 LAN_WAKE# 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 MINI1_LED# 28
9022@
29 LAN_WAKE# E51TXD_P80DATA 30 EC_PME#/GPIO15 1 2
28 E51TXD_P80DATA E51RXD_P80CLK 31 EC_TX/GPIO16 110 ACIN PROCHOT# 45,7
R1017
28 E51RXD_P80CLK FCH_PWRGD 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 EC_ON ACIN 40
22 FCH_PWRGD PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON 41
0_0402_5% Low Active (+1.5V)

1
PWR_SUSP_LED# 34 114 ON/OFFBTN# D
32 PWR_SUSP_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFFBTN# 32
36 GPI 115 LID_SW# EC_THERM 2 Q30
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 LID_SW# 32
SUSP# G 9012@
SUSP#/GPXIOD05 117 SUSP# 37,42,44
S L2N7002LT1G_SOT23-3

3
GPXIOD06 118
PECI_KB9012/GPXIOD07
High Active
+3VALW_EC
AGND/AGND

PBTN_OUT# 122
22 PBTN_OUT# 123 XCLKI/GPIO5D 124
SLP_S5# V18R R64 1 2 0_0603_5%
GND/GND
GND/GND
GND/GND
GND/GND

22 SLP_S5# XCLKO/GPIO5E V18R

GND0

9012@ 1
KB9012QF-A3_LQFP128_14X14 C1359 9012@
11
24
35
94
113

69

Part Number = SA00004OB20 20mil L74

MBK1608121YZF_0603 4.7U_0603_6.3V6K
ECAGND 2 1 2

4 4

U32 9022@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/12 Deciphered Date 2013/11/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB9012 /KB9022
SA000075S20 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
KB9022QC-A3_LQFP128_14X14 Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 35 of 52
A B C D E
 5 4 3 2 1

To TP/B Conn.
Colay 6/8 pin
www.qdzbwx.com +BRI_VCC
+BRI_VCC +3VALW +TP_VCC
U9 TPBRI@ +TP_VCC
1 @ 2 1
+3VALW OUT
2 2 0_0603_5% R155 5 1 R412 1 @ 2 0_0603_5%
IN +3VALW
1 TPBRI@ 2 C523 R411 1 @ 2 0_0603_5%
+3VS +3VS
U69 C1288 C1289 0_0603_5% R156 2 4.7U_0603_6.3V6K R410 1 @ 2 0_0603_5%
GND +5VALW
1 24 .1U_0402_16V7K 4.7U_0603_6.3V6K 4 TPBRI@ JTP1
+VDDD_M_M 1 MOS@ 2 +VDDD_M 2 SCB_0/GPIO_6 VDDD 23 TPBRI@ 1 1 IN 2 10
SCB_5/GPIO_7 SCB_4/GPIO_5 TPBRI@ 1 GND
R153 0_0402_5% 3 22 EC_SDATA1_TP C1293 3 C552 2@ 1 0.1U_0402_16V4Z 9
D TP_INT# 4 VSSD SCB_3/GPIO_4 21 EC_SCLK1_TP 1U_0402_6.3V6K EN 8 GND D
5 GPIO_8 SCB_2/GPIO_3 20 TPUSB_X2 TPBRI@ G5243T11U_SOT23-5 TP_CLK 7 8
GPIO_9 SCB_1/GPIO_2 2 TP_PWR_EN 35 35 TP_CLK 7
MOS@C1291 1
MOS@C1291 2.1U_0402_16V7K 6 19 TPUSB_X1 TP_DATA 6
GPIO_10 GPIO_1 35 TP_DATA 6
C1292 1
MOS@C1292
MOS@ 24.7U_0603_6.3V6K +VDDD_M_M 7 18 1 MOS@ 2 5
8 GPIO_11 GPIO_0 17 R152 0_0402_5% I2C_DAT_TP 4 5
@ C1290 1 2.1U_0402_16V7K 9 SUSPEND VSSA 16 I2C_CLK_TP 3 4
1 2 10 WAKEUP VSSD 15 2 @ 1 TP_I2C_INT# 2 3
22 USB20_P5 USBDP VBUS +5VS 22,35 TP_I2C_INT# 2
R143 1 TPBRI@ 2 0_0402_5% 11 14 R138 0_0603_5% 1
22 USB20_N5 USBDM nXRES 35 TP_SENOFF# 1
R144 TPBRI@ 0_0402_5% 12 13 1 1
VCCD VSSD 25 2 TPBRI@ 1
+BRI_VCC (For Wake Up and Interrupt) CONN@
+VDDD_M 1 @ 2 thermal pad R151 0_0603_5% ACES_50578-0080N-001
R140 0_0402_5% CY7C65211-24LTXI_QFN24_4X4 TPBRI@ TPBRI@ SP010010M00
1 MOS@ 2 TPBRI@ 2 2 TPUSB_X1
+3VALW
R154 0_0402_5% 1 C1286 C1287
.1U_0402_16V7K 4.7U_0603_6.3V6K Y9 MOS@
C1285 4 1
TPBRI@ USB20_P5 R141 1 USBTP@2 0_0402_5% I2C_DAT_TP
2 1U_0402_6.3V6K USB20_N5 R142 1 USBTP@2 0_0402_5% I2C_CLK_TP

1 R939 2 3 2 I2C_DAT R145 1 TPBRI@ 2 0_0402_5%

33P_0402_50V8J
1M_0402_5% TPUSB_X2 I2C_CLK R146 1 TPBRI@ 2 0_0402_5%

C67
MOS@ 12MHZ_18PF_7V12000001

1
10K_0402_5%
R452

33P_0402_50V8J
C86
Part Number = SJ10000C210

1
+TP_VCC PCB Footprint = Y_CRG3201212_4P
RP18

2
TP_CLK 8 1 +3VALW MOS@ +3VS

2
TP_DATA 7 2
FCH_SCLK1 6 3 MOS@ MOS@
22 FCH_SCLK1 FCH_SDATA1 5 4
22 FCH_SDATA1

2
4.7K_0804_8P4R_5%

G
1 6 TPBRI@ I2C_CLK
C 35 EC_SCLK1_TP C

D
+TP_VCC +3VS Q2505A Q2505B

5
RP19 DMN66D0LDW-7_SOT363-6
I2C_CLK_TP 8 1 DMN66D0LDW-7_SOT363-6

G
I2C_DAT_TP 7 2 TPBRI@ 4 3 I2C_DAT
35 EC_SDATA1_TP

2
G
TP_I2C_INT# 6 3

D
Q87 TPBRI@
5 4 L2N7002LT1G_SOT23-3 0_0402_5% 2 @ 1 R128
3 1 TP_I2C_INT#
20 TP_INT#
2.2K_0804_8P4R_5% 0_0402_5% 2 @ 1 R129

D
TPBRI@ INT to FCH for SMB Alert INT to EC for TP wake
INT to Bridge for I2C 1 @ 2
R132 0_0402_5%
+3VS
RP24
EC_SDATA1_TP 8 1
EC_SCLK1_TP 7 2 TP_CLK
TP_INT# 6 3 TP_DATA
5 4

100P_0402_50V8J
U69

100P_0402_50V8J
C553

XEMC@ C551
2.2K_0804_8P4R_5% NOTE : 1 1
TPBRI@
Cypress pop : TPBRI@
MOSART pop : TPBRI@ , MOS@ (default flash type)

XEMC@
2 2
EC I2C pop : R128,R129,R132,RP19 MOSART Bridge
USBTP pop : USBTP@, (Q87 or R132, R130 option) SA00007PR00
MOS@

B
USB3.0 +USB3_VCCA
U66
+5VALW
USB2.0 CONN B

1
OUT 5
+5VALW +USB3_VCCA 2 IN
GND For ESD request
W=60mils 4 USB_EN#
C483 EMC@ U29 USB_OC#_1 3 EN D15 XEMC@
1 8 OCB 1 1
0.1U_0402_16V4Z
GND OUT
U3RXDN0 10 9 U3RXDN0
1 2 2 7 R454 @ SA00007AO00

USB_EN#
3
4
IN
IN
OUT
OUT
6
5 USB_OC#_1 1
0_0402_5%
@ 2
SY6288D20AAC_SOT23-5 U3RXDP0 2 2 9 8 U3RXDP0 USB/B
35 USB_EN# EN/ENB OCB USB_OC0# 22
U3TXDN0 4 4 7 7 U3TXDN0
SY6288D10CAC_MSOP8 +USB3_VCCA
U3TXDP0 5 5 6 6 U3TXDP0
(USB Port 0, Port1)
W=100mils +5VALW
SF000002Y00 3 3
EMC@ JUSB2
EMC@ 1 1 220U 6.3V OSCON 1
DLW21HN900HQ2L_4P C487 8 2 1
ESR 17mohm@100Khz 2
0.1U_0402_16V4Z

C486 + 3
2 1 USB3_TX0_P_C 3 4 U3TXDP0 L05ESDL5V0NA-4 SLP2510P8 4 3
22 USB3_TX0_P 3 4 2 4
C484 0.1U_0402_16V7K 150U_6.3V_M_D2 USB_EN# 5

2 1 USB3_TX0_N_C 2 1 U3TXDN0
2
USB3.0 Conn. D24 USB20_N0
6
7
5
6
22 USB3_TX0_N 2 1 22 USB20_N0 7
C482 0.1U_0402_16V7K XEMC@ USB20_P0 8
U2DN10_L 3 6 22 USB20_P0 9 8
L27 JUSB1
1 I/O2 I/O4 USB20_N1 10 9
2 VBUS 22 USB20_N1 11 10 13
EMC@ U2DN10_L USB20_P1
U2DP10_L 3 D- +USB3_VCCA 22 USB20_P1 12 11 G1 14
DLW21HN900HQ2L_4P
4 D+ 2 5 12 G2
USB3_RX0_P 3 4 U3RXDP0 U3RXDN0 5 GND GND VDD CONN@
22 USB3_RX0_P 3 4 6 StdA-SSRX- 10
U3RXDP0 SP01001IS00
7 StdA-SSRX+ GND 11
A USB3_RX0_N 2 1 U3RXDN0 U3TXDN0 8 GND-DRAIN GND 12 1 4 U2DP10_L A
22 USB3_RX0_N 2 1 U3TXDP0 9 StdA-SSTX- GND 13 I/O1 I/O3
L30 StdA-SSTX+ GND AZC099-04S.R7G_SOT23-6
ACON_TARAC-9V1391
R458 1 XEMC@ 2 0_0402_5% CONN@
R461 1 XEMC@ 2 0_0402_5% DC23300AG00
USB20_P10 2 1 U2DP10_L
22 USB20_P10 2 1 Security Classification Compal Secret Data
Issued Date 2012/09/12 Deciphered Date 2013/11/12 Title
USB20_N10 3 4 U2DN10_L
22 USB20_N10 3 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0/ USB2.0 Ports/TP
L26 EMC@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DLW21HN900HQ2L_4P Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 36 of 52
5 4 3 2 1
 A B C D E

www.qdzbwx.com
+5VALW to +5VS +3VS to +3VSDGPU
+3VALW to +3VS +1.8VS to +1.8VSDGPU
U11 @ J10
1 14 +5VS_OUT 1 2 U16 @ J13
1 +5VALW VIN1 VOUT1 1 2 +5VS 1
2 13 1 14 +3VSD_OUT 1 2
VIN1 VOUT1 +3VS VIN1 VOUT1 1 2 +3VSDGPU
C342 JUMP_43X118 2 13
SUSP# R427 1 RS@ 2 0_0402_5% 5VS_ON 3 12 2 1 330P_0402_50V7K VIN1 VOUT1 C344 JUMP_43X118
ON1 CT1 VGA_ON R436 1 RS@ 2 0_0402_5% 3VSD_ON 3 12 2 1 330P_0402_50V7K
@ 1 2 4 11 ON1 CT1 VGA@
+5VALW VBIAS GND
C980 0.1U_0402_16V7K @ 1 2
+5VALW
4 11
R933 1 RS@ 2 0_0402_5% 3VS_ON 5 10 2 1 C986 0.1U_0402_16V7K VBIAS GND
ON2 CT2 330P_0402_50V7K R435 1 RS@ 2 0_0402_5% 1.8VSD_ON 5 10 2 1
6 9 22,47,48,49 VGA_PG ON2 CT2
C346 @ J9 VGA@ 330P_0402_50V7K
@ 1 2 7 VIN2 VOUT2 8 +3VS_OUT 1 2 6 9 C348 @ J14
+3VALW VIN2 VOUT2 1 2 +3VS +1.8VS VIN2 VOUT2
C979 0.1U_0402_16V7K @ 1 2 7 8 +1.8VSD_OUT 1 2
+1.8VSDGPU
15 JUMP_43X118 C1014 0.1U_0402_16V7K VIN2 VOUT2 1 2
GPAD 15 JUMP_43X118
TPS22966DPUR_SON14_2X3 GPAD
SA00006FD00 TPS22966DPUR_SON14_2X3
SA00006FD00
VGA@

+1.1VALW to +1.1VS
+1.5V to +1.5VS +3VS
U15 @ J11
1 14 +1.1VS_OUT 1 2
+1.1VALW VIN1 VOUT1 1 2 +1.1VS

5
2 13
VIN1 VOUT1 C343 JUMP_43X118

VCC
SUSP# R438 2 1 1K_0402_5% 1.1VS_ON 3 12 2 1 330P_0402_50V7K 1
ON1 CT1 22 VGA_ON IN1 4
2 1 2 4 11 OUT VGA_ON_R 48,49 2
R116 1 VGA@ 2 2

GND
+5VALW VBIAS GND +3VSDGPU IN2
C983 0.1U_0402_16V7K 20K_0402_1%

C196 VGA@
0.1U_0402_16V7K
R431 2 1 1K_0402_5% 1.5V_ON 5 10 2 1 1
ON2 CT2 330P_0402_50V7K

3
6 9 C347 @ J12 U38
+1.5V VIN2 VOUT2
EMC@ 1 2 7 8 +1.5VS_OUT 1 2
+1.5VS MC74VHC1G08DFT2G_SC70-5
C984 0.1U_0402_16V7K VIN2 VOUT2 1 2 2 VGA@
15 JUMP_43X118
GPAD
TPS22966DPUR_SON14_2X3
SA00006FD00

VGA sequence : default same as V5WE2

(0.95V can be option before VGA_CORE)

VGA_ON
+3VSDGPU
+5VALW +5VALW
VGA_ON_R
2

+VGA_CORE
R1108 R1098 +1.1VS
100K_0402_5% 100K_0402_5% VGA_PG
2

+0.95VSDGPUP
1

SUSP SYSON# @ R1101 +1.5VSDGPUP

470_0603_5%
6

3 Q52A Q52B +1.8VSDGPU 3

1

DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
1

2 5 @ Q83 D
35,42,44 SUSP# SYSON 35,42
L2N7002LT1G_SOT23-3 2 SUSP#
1

G
1

S
3

R1109 100K_0402_5%
10K_0402_5% R1035
2

+5VALW +3VSDGPU +1.8VSDGPU +0.95VSDGPU +VGA_CORE +1.5VSDGPU

+5VS +3VS +0.75VS +1.5V
1

2
2

2
R556 R574 R575 R570 R571
R259 R260 R258 R257 100K_0402_5% 470_0603_5% R557 47_0603_5% 47_0603_5% 47_0603_5%
470_0603_5% @ @ 470_0603_5% 470_0603_5% @ @ 470_0603_5% @ @ 47_0603_5% @ @ @
@
2

1
6 1

3 1

6 1

3 1

1
VGA_ON# +3VSDGPU_R +1.8VSDGPU_R +0.95VSDGPU_R +VGA_CORE_R +1.5VSDGPU_R
3

3
@
SUSP 2 @ @ 5 SUSP SUSP 2 @ 5 SYSON#
Q96A Q96B Q1A VGA_ON 5 2 VGA_ON# VGA_ON# 2 5 VGA_ON# VGA_ON# 2 5 VGA_ON#
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 Q1B Q55B Q41B Q45B
1

DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 Q55A Q41A DMN66D0LDW-7_SOT363-6 Q45A DMN66D0LDW-7_SOT363-6

4

4
4 @ DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 @ DMN66D0LDW-7_SOT363-6 @ 4
@ @ @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/12 Deciphered Date 2013/11/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK M/B LA-B221P
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 37 of 52
A B C D E
 A B C D

www.qdzbwx.com

1 VIN 1

@ PJP101 EMI@ PL101

ACES_50305-00441-001_4P HCB2012KF-121T50_0805
DC_IN_S1 1 2
1
2
3
4
GND
1

1
GND @ESD@ PC101 EMI@ PC102 EMI@ PC103
0.1U_0603_25V7K 100P_0603_50V8 1000P_0603_50V7K
2

2
2 2

3 3

@PR111
@ PR111
0_0402_5%
1 2
+3VLP +CHGRTC

- PBJ101 @ + PR112
560_0603_5%
PR113
560_0603_5%
2 1 1 2 1 2
+RTCBATT

ML1220T13RE

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/07/10 Deciphered Date 2013/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 12, 2014 Sheet 38 of 53
A B C D

I'm from VIETNAM sualaptop365

 A B C D

@ PJP201
SUYIN_200275GR008G13GZR
GND 9
10
www.qdzbwx.com +3VLP
GND 8
8 7
7 6
6 5 100_0402_1% PR209
5 4 EC_SMDA 1 2 EC_SMB_DA1 35,40
4 3

1
3 2 100_0402_1% PR208 @ PC202
1
2 1 1

1
EC_SMCK 1 2 EC_SMB_CK1 35,40 0.1U_0603_25V7K

2
1
@ PR204 @ PR205
2 1 10K_0402_1% 10K_0402_1%
PR201
+3VLP <45,47>

2
6.49K_0402_1%

1
TH 1 2 BATT_TEMP 35 @ PU201
PR210 @ PR206 1 8
0_0402_5% 100K_0402_1% VCC TMSNS1
2 7 2 1
PR211 GND RHYST1

1
BI 1 2 MAINPWON 3 6 @ PR207
OT1 TMSNS2 47K_0402_1%
1K_0402_1% 4 5 @ PH201
OT2 RHYST2 100K_0402_1%_NCP15WF104F03RC
EMI@ PL201 G718TM1U_SOT23-8

2
HCB2012KF-121T50_0805
BATT_S1 1 2 BATT+ <45,47>
EMI@ PL202 2013/10/28 update PH201 chang
HCB2012KF-121T50_0805
Common part SL200002H00
1

1 2
EMI@ PC201
1000P_0402_50V7K
2

2
---Battery_pin define--- ---Battery Con_pin define--- 2

PIN1 GND PIN8 GND

PIN2 GND PIN7 GND
PIN3 SMD PIN6 SMD
PIN4 SMC PIN5 SMC
For KB9022 For KB9012
PIN5 TS PIN4 TS OTP
Active Recovery sense 20mΩ
Active Recovery
PIN6 B/I PIN3 B/I
PIN7 Batt+ PIN2 Batt+ VCIN0_PH(V) 92C, 1V 56C, 2.044V 42.8W, 0.73V 34.4W,0.59V
PIN8 Batt+ PIN1 Batt+ 40W
PH202(ohm) 6.99K 26.03K 65W 69.55W, 0.73V 55.9W,0.59V

PH201 under CPU botten side :

CPU thermal protection at 92 degree C ( shutdown )
Recovery at 56 degree C +EC_VCCA
For 40W adapter==>action 42.8W , Recovery 34.4W
2013/10/02 42.8W:
ADP_I 35,40
3
Add for ENE9022 Battery Voltage drop detection. Iada= 0~2.253A (42.8W/19V=2.253A) 3

Connect to ENE9022 pin64 AD1. ADP_I=20*Iada*Rsense

1
ADP_I=20*2.253*0.02=0.901 PR216
16.9K_0402_1% PR202
Battery is 3-cell design. 34.4W: 10K_0402_1%
B+=9V

2
Iada= 0~1.811A (34.4W/19V=1.811A) 35 VCIN0_PH

B+ ADP_I=20*Iada*Rsense
ADP_I=20*1.811*0.02=0.724 @ PR227
26.1K_0402_1%
1 2 VCIN1_PROCHOT 35
35,41,7 MAINPWON
@9022@ CP=40W*0.85=34W @ PR223
1

PR230 100K_0402_1%

1
80.6K_0402_1% 1 2 EC_THERM 35
For 65W adapter==>action 69.55W , Recovery 55.9W PH202
100K_0402_1%_B25/50 4250K
@9022@ PR229 69.55W: B value:4250K±1%
2

0_0402_5%
Iada= 0~3.661A (69.55W/19V=3.661A)

2
1 2 VCIN1_BATT_DROP 35 PH1203 from SL200000V00 change to
ADP_I=20*Iada*Rsense common part SL200002H00 40W@ PR203

1
44.2K_0402_1%
ADP_I=20*3.661*0.02=1.464 2013/10/23
1

1_0402_1%
PR226
65W@ PR203
2

55.9W:

0_0402_5%
10K_0402_1%

PR225
@9022@ PC203 @9022@ PR228
0.1U_0402_25V6 10K_0402_1%

2
Iada= 0~2.942A (55.9W/19V=2.942A) @
1

@
ADP_I=20*Iada*Rsense
2

2
2
4 4

ADP_I=20*2.942*0.02=1.177
35 ECAGND

CP=65W*0.85=55.25W
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/07/10 Deciphered Date 2013/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 12, 2014 Sheet 39 of 53
I'm from VIETNAM sualaptop365
A B C D
 A B C D

Protection for reverse input

Vgs = 20V
www.qdzbwx.com

1
PQ301 D
2 Vds = 60V B+
G Id = 250mA
S 2N7002KW _SOT323-3

3
PR302
PR301
1 2 1 2 Rds(on) typ=35mohm max max Power loss 0.22W for 90W;
Vgs=20V 0.12W for 65W system Rds(on) = 35mohm max
1
1M_0402_5% 3M_0402_5% PL301 from SH00000MW00 change to Vgs = 20V 1

Need check the SOA for inrush Vds=30V CSR rating: 1W

common part SH00000YG00 Vds = 30V
ID= 7.7A (Ta=70C) VACP-VACN spec < 80.64mV
VIN 2013/10/23 ID = 7.7A (Ta=70C)
P1 P2
1 1 8 PR303 EMI@ PL301 CHG_B+
2 2 7 0.02_1206_1% 1UH_2.8A_30%_4X4X2_F 8 1
5 3 3 6 1 4 1 2 7 2
5 Isat: 4A 6 3

2200P_0402_25V7K
10U_0805_25V6K

10U_0805_25V6K
2 3 5
2200P_0402_50V7K

0.1U_0402_25V6
DCR: 27mohm

0.1U_0402_25V6
PQ303 PQ304
4

@EMI@ PC306
1

1
PC303

PC304

EMI@ PC305
PQ302 0_0402_5% AO4406AL_SO8 AO4406AL_SO8

0.01U_0402_50V7K
PC301

@ PR304

4
1

1
AON6414AL_DFN8-5 VIN PQ304 from AON4466

PC302

PC307
PQ303 from AON4466 change to AON4406

2
change to AON4406
2

VF = 0.5V 2014/01/08
2

2
3

2
2014/01/08
PD301
BQ24725A_ACDRV_1 BAS40CW _SOT323-3

0.1U_0402_25V6
BQ24725A_BATDRV 1 2BQ24725A_BATDRV_1

0.1U_0402_25V6
Rds(on) = 30mohm max

1
1
PC308
PR305

PC310
Vgs = 20V

1 1
1 2

10_1206_1%
PC311 4.12K_0603_1%
0.047U_0402_25V7K Vds = 30V

PR306
2
PC309 1 2 PL302 from SH00000M600 change to
0.1U_0402_25V6
ID = 7A (Ta=70C)
VF = 0.37V common part SH00000YB00

5
2.2_0603_5%
2013/10/23

PR307
PD302

BQ24725A_VCC2
RB751V-40_SOD323-2
7X7X3 Power loss: 0.32W for 3.5A

BQ24725A_ACP
@ PR308

BQ24725A_REGN
Isat: 3.8A CSR rating: 1W

BQ24725A_BST2

2
DH_CHG 1 2 4

BQ24725A_LX
VSRP-VSRN spec < 81.28mV
4.12K_0603_1%

4.12K_0603_1%

2 2

0_0402_5%
1

PC312 BATT+
PR309

PR310

DH_CHG
1 2 PQ305 PL302
AON7408L_DFN8-5
10UH_3.5A_20%_7X7X3_M PR311

3
2
1
1U_0603_25V6K 1 2 0.01_1206_1%

BQ24725A_ACN
BQ24725A_LX 1 2 CHG 1 4
2

PC313

5
1U_0603_25V6K 2 3

20

19

18

17

16
PU301

CSON1
CSOP1
1

680P_0402_50V7K 4.7_1206_5%
VCC

PHASE

HIDRV

BTST

REGN

10U_0805_25V6K

10U_0805_25V6K
21

@EMI@ PC319 @EMI@ PR312

PAD

0.1U_0402_25V6

0.1U_0402_25V6

PC314

PC315
1

1
1 15 DL_CHG 4
ACN LODRV

PC316

PC317
2

2
2 14 PQ306
ACP GND PR313 AON7408L_DFN8-5

3
2
1

2
1
BQ24725ARGRR_QFN20_3P5X3P5 10_0603_1%
BQ24725A_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP

1
PR314

2
6.8_0603_1%
BQ24725A_ACDRV 4 12 SRN1 2 CSON1

2
ACDRV SRN PC318
0.1U_0603_16V7K
1 2 5 11 BQ24725A_BATDRV **Design Notes**
+3VLP ACOK BATDRV
PR315 100K_0402_1%
ACDET
#For 65 /90W system, 3S1P/3S2P battery

IOUT

SDA

SCL

ILIM
Maximum Charging current 3.5A
35 ACIN Maximum Battery discharge power 55W.
#Register Setting
6

10
+3VALW
3
1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke 3
BQ24725A_ACDET

BQ24725A_ILIM 1 2 #Circuit Design

BQ24725A_IOUT

PR316
1. ACOK,ILIM pull high voltage need base on 3/5V enable control

100K_0402_1%
316K_0402_1%

0.01U_0402_25V7K
1
2. Use 10X10 choke and 3X3 H/L Side MOSFET

PC320
PR317

1
PR318 Charge current 3.5A
422K_0402_1%
VIN
1 2 Power loss : 1.82W

2
Power density : 0.81 (15X15)
2

3. If use 4S per cell 4.35V battery, need additional circuit

for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors
with PR222 for ACDET setting)
4. PC223 0.22U can't be changed. (Wrong adapter concern)
5. For the design, need double confirm PQ202,PQ203,PQ204 rating
#Protect function
0.22U_0402_16V7K

66.5K_0402_1%

EC_SMB_CK1 35,39 1. ACOVP : ACDET voltage > 3.14V

100P_0402_50V8J
1

2. Charger timeout : No communication within 175s(default)

PC321

1
PC322
PR319

3. ACOC : 3.33 X Input current DAC setting(default)

4. CHGOCP : 3/4.5/6A based on current current setting
2

EC_SMB_DA1 35,39
2

@ PR320 5. BATOVP : 103-106%

2

0_0402_5% 6. BATLOWV : 2.5V

1 2
ADP_I 35,39 7. TSHUT : 155C
1

8. IFAULT HI : 750mV (default)

@ PC323
9. IFAULT LOW : 150mV (default)
100P_0402_50V8J
2

Close EC chip
4 4

Vin Dectector
Min. Typ Max.
L-->H 17.16V 17.63V 18.12V
H-->L 16.76V 17.22V 17.70V
Security Classification Compal Secret Data Compal Electronics, Inc.
VILIM = 20*ILIM*Rsr Issued Date 2014/07/02 Deciphered Date 2013/10/01 Title
ILIM = 3.3*100/(100+107)/20/0.02
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
= 3.986 A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
I'm from VIETNAM sualaptop365 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, February 12, 2014 Sheet 40 of 53
A B C D
 A B C D E

Module model information

SY8208B_V2.mdd www.qdzbwx.com
SY8208C_V2.mdd

PR401 FAE review : change from

2.2_0603_5% to 1_0603_5% HW request add PR413, PR402
499K_0402_1%
1 and PC428-un-pop ENLDO_3V5V 1 2 1
EN1 and EN2 dont't floating B+

1
150K_0402_1%
@ PR413

PR404
1 2
3V_EN 35
0_0402_5%

1
@ PC428

2
0.1U_0402_10V7K

2
PU401
B+ EMI@ PL401 7 1 PC402 PR403
HCB2012KF-121T50_0805 EN2 EN1 0.01U_0402_25V7K 1K_0402_5%

2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB 1 2 1 2
IN FB PR401 PC403

10U_0805_25V6K

10U_0805_25V6K
@EMI@ PC401

EMI@ PC404
0.1U_0402_25V6
6 BST_3V 1 2 1 2
BS
1

1
PC406
1_0603_5%

PC405
0.1U_0603_25V7K
PL402
2

2
10 LX_3V 1 2
@ LX +3VALWP
9 4 1.5UH_PCMB053T-1R5MS_6A_20%
GND OUT

@EMI@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PR405
1

1
680P_0603_50V7K 4.7_1206_5%
2 5
+3VALWP PG LDO +3VLP

PC407

PC408

PC409

PC410
1
SY8208BQNC_QFN10_3X3

2
PC411

1 3V_SN
4.7U_0603_6.3V6M

2
1

Check pull up resistor of SPOK at HW side

PR412
100K_0402_5%

@EMI@

PC412
3.3V LDO 150mA~300mA
2

2
2 2
Vout is 3.234V~3.366V
35 SPOK
TDC=6A
@ PJ401
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118
B+ EMI@ PL403 EN1 and EN2 dont't floating
HCB2012KF-121T50_0805
1 2 5V_VIN
PR407 FAE review : change from
3V5V_EN @ PJ402
2.2_0603_5% to 0_0603_5% Vout is 4.998V~5.202V +5VALWP 1 2 +5VALW
1 2
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

PU402 PC413 PR406 JUMP_43X118

8 1 6800P_0402_25V7K 1K_0402_5%
TDC=6A
IN EN 1 2 1 2
1

1
PC414

PC415

EMI@ PC417

@EMI@ PC418

3 5V_FB @ PR407 PC416

FB 0_0603_5% 0.1U_0603_25V7K
6 BST_5V 1 2 1 2
2

BS
@
PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
VCC_3V 5 4 1.5UH_PCMB053T-1R5MS_6A_20%
VCC OUT

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PR408

680P_0603_50V7K 4.7_1206_5%

1
@EMI@
2 7
PG LDO VL
1

PC419

PC420

PC421

PC422

PC423

PC427
3 3
4.7U_0603_6.3V6M

2 SPOK_5V

SY8208CQNC_QFN10_3X3

2
1 5V_SN
2

2
1

PC424
4.7U_0603_6.3V6M
2

PC425

PR414 @
@EMI@

0_0402_5%
2
1

Add PC427 for 22U_0603 size

PR409
SPOK

2.2K_0402_5%
1 2 5V LDO 150mA~300mA
35 EC_ON
@PR415
@ PR415
1 2
35,39,7 MAINPWON
0_0402_5%

3V5V_EN
1M_0402_1%

4.7U_0402_6.3V6M
1

1
PR411

PC426
2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2013/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+3VALW/+5VALW
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

I'm from VIETNAM sualaptop365

Date: Wednesday, February 12, 2014 Sheet 41 of 53
A B C D E
 5 4 3 2 1

Module model information

www.qdzbwx.com
RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer

D D

Pin19 need pull separate from +1.35VP.

If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
EMI@ PL501 you can change from +1.35VP to +1.35VS. TDC 0.7A
HCB2012KF-121T50_0805
B+ 1 2 1.5V_B+ PR501 Peak Current 1A
2.2_0603_5%
BST_1.5V 1 2 BOOT_1.5V

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
+1.5VP
1

1
@EMI@ PC502

EMI@ PC503

PC504

PC505
DH_1.5V +0.75VSP
2

2
SW _1.5V

10U_0805_6.3V6K

10U_0805_6.3V6K
1

1
PC501

PC506

PC507
5
0.1U_0603_25V7K

16

17

18

19

20
2
C PU501 C

2
VLDOIN
PHASE

UGATE

BOOT

VTT
PC502 from SF00000KS00 change to 21
PQ501 PAD
common part SF00000YE00 AON7408L_DFN8-5 4 DL_1.5V 15 1
LGATE VTTGND
2013/10/23
14 2
PL502 PR502 PGND VTTSNS

1
2
3
1UH_11A_20%_7X7X3_M 13.7K_0402_1%
1 2 1 2 CS_1.5V 13 3
+1.5VP PC508 CS RT8207MZQW _W QFN20_3X3 GND
1

1U_0603_10V6K

5
1 2 12 4 VTTREF_1.5V
@EMI@ PR503 PQ502 PR504 VDDP VTTREF
SF000006S00 H=4.5 4.7_1206_5% AON7506_DFN33-8-5 5.1_0603_5%
1
330U_2.5V_ESR17M_6.3X4.5

1 2 VDD_1.5V 11 5
+5VALW +1.5VP
1 2

VDD VDDQ

1
+

PGOOD
PC509

ESR=17m ohm 4 PC510

TON
1
@EMI@ PC512 0.033U_0402_16V7K

FB
S5

S3

2
2 680P_0402_50V7K PC513
+5VALW
2

1U_0603_10V6K

10

6
1
2
3

1 2
+3VS

FB_1.5V
EN_0.75VSP
TON_1.5V
@ PR505 100K_0402_5% PR506

EN_1.5V
10.2K_0402_1%
PR507 1 2 +1.5VP
PC509 from SF000002Z00 change to 887K_0402_1%
B 1.5V_B+ 1 2 B
common part SF000006S00 MOSFET: 3x3 DFN

1
2013/10/23 H/S Rds(on): 27mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C @ PR509 PR508
0_0402_5% 10K_0402_1%
1 2
35,37 SYSON

2
Mode Level +0.675VSP VTTREF_1.35V L/S Rds(on): 9.9mohm(Typ), 13mohm(Max)
S5 L off off Idsm: 13.5A@Ta=25C, 11A@Ta=70C

1
@ PC514
S3 L off on 0.1U_0402_10V7K
S0 H on on Choke: 7x7x3

2
Rdc=8.3mohm(Typ), 10mohm(Max)
Note: S3 - sleep ; S5 - power off @ PR510
0_0402_5%
Switching Frequency: 285kHz 1 2 @ PJ501
Ipeak=10A 35,37,44 SUSP# 1 2
+1.5VP 1 2 +1.5V
Iocp~13A

1
JUMP_43X118
OVP: 110%~120% @ PC515 @ PJ502
VFB=0.75V, Vout=1.515V 0.1U_0402_10V7K 1 2

2
1 2
MOSFET footprint: SIS412DN JUMP_43X118

PJ503
@
1 2
+0.75VSP 1 2 +0.75VS
A
JUMP_43X39 A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2013/10/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VP/+0.75VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 12, 2014 Sheet 42 of 53
5 I'm from VIETNAM sualaptop365
4 3 2 1
 5 4 3 2 1

www.qdzbwx.com
EN pin don't floating Module model information
If have pull down resistor at HW side, pls delete PR2
D SY8208D_V1.mdd D

@ PR602
APL5930_V1.mdd
1 2 VR_ON 35,45
0_0402_5%

1
@ PC602
1M_0402_1%
0.22U_0402_10V6K PL602 from SH00000PJ00 change to

2
PR603
common part SH00000YE00

2
2013/10/23

@EMI@ PR604 @EMI@ PC603

4.7_1206_5% 680P_0603_50V7K
EMI@ PL601 1 2SNB_1.05V 1 2 PC609, PC610 from 47U_0603_6.3V6M change to
HCB2012KF-121T50_0805 PU601
22U_0603_6.3V6M 2013/10/23
B+ 1 2 B+_1.05V 8
IN EN
1 @ PR605
0_0603_5%
PC604
0.1U_0603_25V7K

10U_0805_25V6K

10U_0805_25V6K
6 BST_1.05V 1 2 1 2 PL602 TDC 8A

0.1U_0402_25V6
2200P_0402_50V7K
BS

1
1UH_11A_20%_7X7X3_M

@EMI@ PC605

PC606

PC607
1.05VS_LDO_3V 9 10 LX_1.05V 1 2
+1.05VSP
EMI@ PC601
GND LX

15.4K_0402_1%

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

330P_0402_50V7K
@

1
4

PR607
0_0402_5% FB

PC608

PC609

PC610

PC611

PC612
PR606 ILMT_1.05V3 7
Rup
+3VALW

2
ILMT BYP

4.7U_0603_6.3V6K

2
2

ILMT_1.05V 2 5 1.05VS_LDO_3V
PG LDO

PC614
4.7U_0603_6.3V6K
1

1
SY8208DQNC_QFN10_3X3

PC613
PR606 part count reduce FB = 0.6V

1
@ PR608

2
0_0402_5% PR609
20K_0402_1%
Rdown
2

C C

2
@ PJ601
Pin 7 BYP is for CS.
The current limit is set to 8A, 12A or 16A when this pin +1.05VSP 1 2
Common NB can delete +3VALW and PC714 1 2 +1.05VS
is pull low, floating or pull high JUMP_43X118

VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.062V

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/13 Deciphered Date 2013/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5 I'm from VIETNAM sualaptop365 4 3 2

Date: Wednesday, February 12, 2014
1
Sheet 43 of 53
 5 4 3 2 1

Module model information

www.qdzbwx.com EN pin don't floating
If have pull down resistor at HW side, pls delete PR2
SY8208D_V1.mdd
@ PR702
35 1.1V_EN
1 2
0_0402_5%

1
@ PC702
1M_0402_1%
0.22U_0402_10V6K PL702 from SH00000PJ00 change to

2
D PR703 D
common part SH00000YE00

2
2013/10/23

@EMI@ PR704 @EMI@ PC703

4.7_1206_5% 680P_0603_50V7K
EMI@ PL701 1 2SNB_1.1V 1 2
HCB2012KF-121T50_0805 PU701 PC709, PC710 from 47U_0603_6.3V6M change to
B+ 1 2 B+_1.1V 8
IN EN
1 @ PR705 PC706
22U_0603_6.3V6M 2013/10/23

10U_0805_25V6K

10U_0805_25V6K
0_0603_5% 0.1U_0603_25V7K

2200P_0402_50V7K
6 BST_1.1V 1 2 1 2

0.1U_0402_25V6
PL702 TDC 8A
BS

1
@EMI@ PC704

PC705

PC707
1UH_11A_20%_7X7X3_M
1.1VALW_LDO_3V
+1.1VALWP

EMI@ PC701
9 10 LX_1.1V 1 2
GND LX

100K_0402_1%

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

330P_0402_50V7K
@

1
PR707
4
0_0402_5% FB

PC708

PC709

PC710

PC711

PC712
PR706 ILMT_1.1V 3 7
Rup
+3VALW

2
ILMT BYP

4.7U_0603_6.3V6K

2
2

ILMT_1.1V 2 5 1.1VALW_LDO_3V
PG LDO

PC714
4.7U_0603_6.3V6K
PR706 part count reduce
1

PC713
SY8208DQNC_QFN10_3X3
FB = 0.6V

1
@ PR708

2
0_0402_5%
PR709
Rdown
2

115K_0402_1%

2
@ PJ701
Pin 7 BYP is for CS.
The current limit is set to 8A, 12A or 16A when this pin +1.1VALWP 1 2
C Common NB can delete +3VALW and PC714 1 2 +1.1VALW C
is pull low, floating or pull high JUMP_43X118

VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.12V

Module model information @ PJ703

1 2
SY8032_V2.mdd +1.8VSP 1 2 +1.8VS
JUMP_43X79

PC721
Imax= 2A, Ipeak= 3A
22U_0603_6.3V6M FB=0.6V
B 1 2 B
PL703
@ PJ702 JUMP_43X79
+3VALW 1 2 4 3 LX_1.8V 1 2
1 2 @ PR721 100K_0402_5% IN LX +1.8VSP

68P_0402_50V8J
1 2 5 2
+3VS PG GND 1UH_2.8A_30%_4X4X2_F

1
PC722

22U_0603_6.3V6M

22U_0603_6.3V6M
6 1
FB EN

1
PC723

PC724
1

2
@EMI@ PR722 PR723

2
SUSP# 35,37,42 @ PR724 4.7_0603_5% 20.5K_0402_1%
1 2+1.8VSP_ON

2
Rup

2
0_0402_5%
0.1U_0402_16V7K

PU702
1

PC725

SY8032ABC_SOT23-6
1

PR725 FB_1.8V
1M_0402_1%
2

1
@
2

@EMI@ PC726
680P_0402_50V7K PR726

2
10K_0402_1%
Rdown

2
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)=1.83V
A A

Security Classification Compal Secret Data

Issued Date 2011/06/15 Deciphered Date 2013/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.1VALWP/+1.8VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 12, 2014 Sheet 44 of 53
5 4 3 2 1

I'm from VIETNAM sualaptop365

 5 4 3 2 1

CPU_B+
EMI@ PL801
HCB2012KF-121T50_0805

www.qdzbwx.com 1 2 B+

10U_0805_25V6K

10U_0805_25V6K
PQ801 @EMI@ PL806
45,7 APU_VDD_SEN_L 7 APU_VDD_SEN_H 3 HCB2012KF-121T50_0805
S2

1
@ PR801 2 1 2

PC804

PC801
Module model information 0_0603_5% D1
S2
4

1
PC802 UGATE_NB1 1 2 1

2
0.01U_0402_50V7K G1 5
10_0402_5% 10_0402_5% RT8880A_V1A.mdd for IC portion 7 S2

2
1 2 1 2 PR805 S1/D2 6 PL802
+APU_CORE G2
RT8880A_V1B.mdd for SW portion 2.2_0603_1% PC806 0.36UH_PDME064T-R36MS_24A_20%
PR802 PR803 BOOT_NB1 1 2 BOOT_NB1-1 1 2 AON6932A_DFN5X6-8-7 1 4

680P_0402_50V7K
+APU_CORE_NB

1
0.22U_0603_25V7K 2 3

@ PC803

4.7_1206_5%
1
D D
PHASE_NB1 PR810

@EMI@ PC810 @EMI@ PR809

2.61K_0402_1%

2
layour area not enough, 1 2 1 2
chang H and L mos to Dual N MOS

1
1 2 PC808

2K_0402_1%

2
2013/10/19 .1U_0402_16V7K

@ PR804
@ PC805

1
330P_0402_50V7K LGATE_NB1 1 2

680P_0603_50V7K
PR806 PR807 @ PR811
APU_CORE_NB

2
10K_0402_1% 105K_0402_1% 0_0402_5%

0.1U_0402_25V6
2

1
1 2 1 2 PR808 TDC 27A

PC811
ISENA1N-1
CPU_B+
1 2
Peak Current 40 A ISENA1P

2
PC809 PC807 100K_0402_1% PR812 @
470P_0402_50V8J 68P_0402_50V8J OCP current > 48A 910_0402_1%
1 2 1 2 ISENA1N 1 2
Load line -2.1mV/A layour area not enough,
FSW=450kHz chang H and L mos to Dual N MOS CPU_B+
DCR 1.4mohm +/-5% 2013/10/19
TYP MAX

APU_VCC

TONSET

UGATE2
BOOT2
H/S Rds(on) :11.7mohm , 14mohm

COMP

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

2200P_0402_50V7K
FB

ISEN1N

ISEN2N
ISEN1P

ISEN2P
L/S Rds(on) :2.7mohm , 3.3mohm PQ802

@EMI@ PC838

EMI@ PC837
1

1
3
S2

1
@ PR849 2

PC836

PC833
0_0603_5% D1 4

2
PU801 APU_VCC UGATE_NB2 1 2 1 S2

13

12

11

10

2
G1

1
RT8880BGQW_WQFN52_6X6 5
PU802 7 S2

PWM3

BOOT2

UGATE2
VSEN

ISEN3N

ISEN1N

ISEN2N

TONSET
COMP

FB

ISEN3P

ISEN1P

ISEN2P
8 3 PR854 S1/D2 6 PL804
53 VCC UGATE 2.2_0603_1% PC834 G2 0.36UH_PDME064T-R36MS_24A_20%

1U_0603_16V6K
GND 1 4 BOOT_NB2 1 2 BOOT_NB2-1 1 2 AON6932A_DFN5X6-8-7 1 4
EN BOOT +APU_CORE_NB

1
14 52 PHASE2

4.7_1206_5%
RGND PHASE2

1
PWM_NB 5 2 0.22U_0603_25V7K 2 3

PC839

@EMI@ PC835 @EMI@ PR850

IMON 15 51 LGATE2 PWM PHASE PR853

2
C
IMON LGATE2 6 7 PHASE_NB2 2.61K_0402_1% C
VREF 16 50 APU_PVCC GND LGATE 1 2 1 2
V064 PVCC

TP

2
PC812 IMONA 17 49 LGATE1 PC832
1U_0402_6.3V6K+1.5VS IMONA LGATE1 RT9610BZQW_WDFN8_2X2 LGATE_NB2 .1U_0402_16V7K

1
1 2 VDDIO 18 48 PHASE1

680P_0603_50V7K
VDDIO PHASE1
20,7 APU_PWRGD 19 47 UGATE1 1 2

2
PWROK UGATE1 @ PR852

0.1U_0402_25V6
1
20 46 BOOT1 +5VS 0_0402_5%

PC831
ISENA1N-2
7 APU_SVC SVC BOOT1 PR813 ISENA2P
21 45 LGATE_NB1 2.2_0603_5% PR851
7 APU_SVD

2
SVD LGATEA1 APU_PVCC 1 2 910_0402_1% @
7 APU_SVT 22 44 PHASE_NB1 layour area not enough, ISENA2N 1 2
SVT PHASEA1
19.6K_0402_1%

6.04K_0402_1%

chang H and L mos to Dual N MOS

1

OFS 23 43 UGATE_NB1 APU_VCC 1 2

OFS UGATEA1 2013/10/19 CPU_B+
PR815

PR816

OFSA 24 42 BOOT_NB1 @ PR814

2.2U_0603_10V7K

2.2U_0603_10V7K
OFSA BOOTA1
1

1
2.2_0603_5%

PC813

PC814
0_0402_5%

SET1 25 41 PWM_NB
@ PR817

0_0402_5%

10U_0805_25V6K

10U_0805_25V6K
2

SET1 PWMA2 PR819 3

@ PR818

0.1U_0402_25V6

2200P_0402_50V7K
2

2
SET2 26 40 1 2 CPU_B+ 1 PQ803

@EMI@ PC818

EMI@ PC819
68U_25V_M
SET2 TONSETA

1
2 3 +

PC816

PC817
PGOODA
ISENA2N

ISENA1N
ISENA2P

ISENA1P
2

S2

PGOOD
COMPA

100K_0402_1% PD801 @ PR820 2

PC815
VSENA
OCP_L
2

D1
IBIAS

RB491D_SOT23-3 0_0603_5% 4
VCC

FBA

2
PR821 PR822 UGATE1 1 2 1 S2 2
EN

G1
100K_0402_1%_B25/50 4250K

6.8K_0402_1% 12K_0402_1% 5
18K_0402_1%

S2
100K_0402_1%_B25/50 4250K

1 2 1 2 7
Pull high at HW side
27

28

29

30

31

32

33

34

35

36

37

38

39

S1/D2 6 PL803
G2
1

0.36UH_PDME064T-R36MS_24A_20%
APU_VCC

PR825 35,7 PROCHOT# 35 VGATE 1 4

ISENA2N

ISENA1N

PHASE1 AON6932A_DFN5X6-8-7
PH801

PR824

PH802

ISENA2P

ISENA1P
COMPA

FBA

12.7K_0402_1% PR823
1 IBIAS

+APU_CORE
2.2_0603_1% 2 3

@EMI@ PR828
4.7_1206_5%
1 2 +3VS BOOT1 1 2 BOOT1-1 1 2
2

1
VREF PR829
PR826 PC820 2.61K_0402_1%
100K_0402_1%

100K_0402_5% 0.22U_0603_25V7K 1 2 1 2
PR827
0.1U_0402_25V6

0.1U_0402_25V6
1

B B
LGATE1 PC821
PC822

PC823

VR_ON 35,43
2

1 2
.1U_0402_16V7K

@EMI@ PC824
680P_0603_50V7K
2

1 2
@ PR831

2
4.12K_0402_1%
0.1U_0402_25V6

0.1U_0402_25V6
1

1
PC825 68P_0402_50V8J PC826
PC841

@ PC828
ISEN1N-1
PH801 and PH802 from SL200000U00 1 2 1 2 ISEN1P
change to common part SL200002H00 layour area not enough,
2

2
470P_0402_50V8J PR838
2013/10/23 chang H and L mos to Dual N MOS 910_0402_1%
PR832 PR833
2013/10/19 ISEN1N 1 2
OFS

@ PR834 @ PR835 @ PR836 1 2 1 2 CPU_B+

1

6.2K_0402_5% 120_0402_1% 20K_0402_5% @

1 2 1 2 1 2 PC827
10K_0402_1%
105K_0402_1% 1 2
@ PR839 @ PR840 @ PR841 @ PR837

10U_0805_25V6K

10U_0805_25V6K
APU_VCC
6.2K_0402_5% 120_0402_1% 20K_0402_5% 2K_0402_1% 330P_0402_50V7K PQ804
2

1 2 1 2 1 2 3
S2

1
@ PR860 2

PC848

PC845
OFSA

D1
1

0_0603_5% 4
@ PC829
APU_core UGATE2 1 2 1 S2

2
G1
680P_0402_50V7K TDC 25A 5
2

7 S2
PR842 Peak Current 38A S1/D2
G2
6 PL805
SET1

1 2 0.36UH_PDME064T-R36MS_24A_20%
PR843 PR845
+APU_CORE_NB OCP current > 46A PHASE2 1 4
1

20.5K_0402_1% 124K_0402_1% 10_0402_5% PR864 AON6932A_DFN5X6-8-7

1 2 1 2 PC830
Load line -2.1mV/A 2.2_0603_1% 2 3
+APU_CORE

@EMI@ PR863
4.7_1206_5%
0.01U_0402_50V7K FSW=450kHz BOOT2 1 2 BOOT2-1 1 2
2

1
PR846 PR848 APU_VCC PR861
470_0402_1% 124K_0402_1% DCR 1.4mohm +/-5% PC840 2.61K_0402_1%
1 2 1 2 7 APU_VDDNB_SEN_H
45,7 APU_VDD_SEN_L 0.22U_0603_25V7K 1 2 1 2
TYP MAX
SET2

LGATE2 PC843
H/S Rds(on) :11.7mohm , 14mohm

1 2
.1U_0402_16V7K
L/S Rds(on) :2.7mohm , 3.3mohm

@EMI@ PC842
680P_0603_50V7K
A 1 2 A
@ PR859

2
4.12K_0402_1%

0.1U_0402_25V6
1
ISEN2P

@ PC846
ISEN1N-2

2
PR862
910_0402_1%
ISEN2N 1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/10/15 Deciphered Date 2013/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_COREP/+CPU_CORE_NB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z5WAK
Date: Wednesday, February 12, 2014 Sheet 45 of 53
5 4 3 2 1

I'm from VIETNAM sualaptop365

 A
B
C
D

5
5

PC911 PC901
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

2
1
+
PC922 PC919 PC916 PC914
330U_D2_2VM_R9M 180P_0402_50V8J 0.01U_0402_25V7K 0.22U_0402_10V6K

+APU_CORE
PC912 PC902
22U_0603_6.3V6M 22U_0603_6.3V6M
+APU_CORE

2 1 2 1 2 1 2 1 2 1

2
1
+
PC923 PC920 PC917 PC915
330U_D2_2VM_R9M 180P_0402_50V8J 0.01U_0402_25V7K 0.22U_0402_10V6K
PC913 PC903
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

I'm from VIETNAM

2
1
+
PC924 PC921 PC918
330U_D2_2VM_R9M 180P_0402_50V8J 0.01U_0402_25V7K
PC904
22U_0603_6.3V6M
2 1

4
4

PC905
22U_0603_6.3V6M
2 1

PC906
+APU_CORE

22U_0603_6.3V6M
330uF*3

2 1

sualaptop365
APU_CORE

PC907
22U_0603_6.3V6M
2 1
0.01uF*3+180pF*3
22uF*13+0.22uF*2

PC908
22U_0603_6.3V6M
2 1

Issued Date
PC909
22U_0603_6.3V6M

Security Classification
2 1
www.qdzbwx.com

PC910

3
3

22U_0603_6.3V6M
2 1

2012/10/15
PC941 PC931
PC943 22U_0603_6.3V6M 22U_0603_6.3V6M
0.22U_0402_10V6K 2 1 2 1
2 1
2
1
+

PC950
330U_D2_2VM_R9M PC944 PC942 PC932
0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

Compal Secret Data

Deciphered Date
2
1
+

PC951
330U_D2_2VM_R9M
+APU_CORE_NB

PC945 PC933
0.22U_0402_10V6K 22U_0603_6.3V6M
2
1
+

2 1 2 1
PC952
330U_D2_2VM_R9M

2
2

PC946 PC934
180P_0402_50V8J 22U_0603_6.3V6M
2013/10/01

2 1 2 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PC947 PC935
180P_0402_50V8J 22U_0603_6.3V6M
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2 1 2 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+APU_CORE_NB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

PC948 PC936
180P_0402_50V8J 22U_0603_6.3V6M
Size
Title

Date:

2 1 2 1

PC949 PC937
180P_0402_50V8J 22U_0603_6.3V6M
180pF*4
330uF*3

2 1 2 1
Document Number

PC938
22U_0603_6.3V6M
APU_CORENB

2 1
22uF*12+0.22uF*3

W ednesday, February 12, 2014

PC939
22U_0603_6.3V6M
1
1

2 1
Sheet
VS50_AMD

PC940
46

22U_0603_6.3V6M
2 1
Processor Decoupling

of
Compal Electronics, Inc.

53
Rev
0.3
A
B
C
D
 5 4 3 2 1

www.qdzbwx.com
Module model information
TPS51212_V1.mdd for Single layer
TPS51212_V2.mdd for Dual layer
D D
VGA_EMI@ PL1001
HCB2012KF-121T50_0805
+1.5VSDGPUP_B+ 1 2
B+

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

@VGA@ PC1005
1

1
@VGA_EMI@ PC1002

VGA_EMI@ PC1003

VGA@ PC1004
2

2
5

PQ1001
AON7408L_DFN8-5
4

VGA@
PC1002 from SH00000MR00 change to
VGA@ VGA@ PR1001 VGA@ PC1001
PU1001 2.2_0603_5% 0.1U_0603_25V7K common part SH00000YV00
VGA@ PR1003 1 10 1
BST_+1.5VSDGPUP 2 1 2 2013/10/23 VRAM

3
2
1
105K_0402_1% PGOOD VBST
@VGA@ PR1004 1 2TRIP_+1.5VSDGPUP2 9 UG_+1.5VSDGPUP VGA@ PL1002
0_0402_5% TRIP DRVH 2.2UH_7.8A_20%_7X7X3_M
1 2 EN_+1.5VSDGPUP 3 8 SW _+1.5VSDGPUP 1 2
22,37,48,49 VGA_PG EN SW
+1.5VSDGPUP
FB_+1.5VSDGPUP 4 7
VFB V5IN
+5VALW

1
@VGA@ PC1006
0.1U_0402_16V7K

RF_+1.5VSDGPUP 5 6 LG_+1.5VSDGPUP @VGA_EMI@

VGA@ PQ1002
C C

AON7506_DFN33-8-5
TST DRVL
1

PR1005 1

330U_2.5V_ESR17M_6.3X4.5
1
11 4.7_1206_5%
TP

1
+

VGA@
Resistance(KΩ) Frequency(KHz) VGA@ VGA@

PC1009
2

2
PR1006 TPS51212DSCR_SON10_3X3 PC1007 4 ESR=17m ohm
1U_0603_6.3V6M
470 290 470K_0402_1%

1
PC1010 @VGA_EMI@ 2
2 680P_0402_50V7K
200 340

3
2
1

2
100 380
39 430
PC1009 from SF000002Z00 change to
VGA@ PR1007
11.5K_0402_1% common part SF000006S00
MOSFET: 3x3 DFN 1 2 2013/10/23
H/S Rds(on): 24mohm(Typ), 30mohm(Max)
Id: 8.7A@Ta=25C, 7A@Ta=70C
1

VGA@
PR1008
L/S Rds(on): 13.5mohm(Typ), 16.5mohm(Max) 10K_0402_1%
Idsm: 12A@Ta=25C, 9.5A@Ta=70C
2

B
Choke: 7x7x3 B
Rdc=15.5mohm +/-15% @VGA@ PJ1001
+1.5VSDGPUP 1 2 +1.5VSDGPU
1 2
JUMP_43X118
@VGA@ PJ1002
+1.2V +1.05V +1.5V 1
1 2
2

Switching Frequency: 290kHz Switching Frequency: 290kHz Switching Frequency: 290kHz JUMP_43X118
Imax=8A Imax=5.4A Imax=8A
OCP~10.5A Ipeak=6.5A OCP~10.5A
OVP: 120%~130% Iocp=7.8A OVP: 120%~130%
VFB=0.704V, Vout=1.207V OVP: 120%-130% VFB=0.704V, Vout=1.514V
VFB=0.704V, Vout=1.055V

Vout PR1007 PR1008 PR1003

+1.2V 7.15K 10k 105K

+1.05V 4.99k 10k 93.1k

A A

+1.5V 11.5K 10k 105K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/29 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VSDGPUP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, February 12, 2014 Sheet 47 of 53
I'm from VIETNAM
5 sualaptop365
4 3 2 1
 5 4 3 2 1

www.qdzbwx.com

Module model information

D D
SY8033_V1.mdd

@VGA@
PJ1102 JUMP_43X79
1 2
+0.95VSDGPUP 1 2 +0.95VSDGPU

FB=0.6V
Note:Iload(max)=3.5A
PC1101 from SH00000MN00 change to
common part SH00000YG00
C 2013/10/23 C

VGA@
@VGA@ PU1101 VGA@ PL1101

4
PJ1101 JUMP_43X79 1UH_2.8A_30%_4X4X2_F
+3VALW 1 2 10 2 LX_0.95V 1 2

PG
1 2 PVIN LX +0.95VSDGPUP
9 3

@VGA_EMI@ PR1102

VGA@ PC1102
4.7_0603_5%
Rup

68P_0402_50V8J
PVIN LX

1
VGA@ PC1101 8

22U_0603_6.3V6M

22U_0603_6.3V6M
SVIN

1
22U_0603_6.3V6M VGA@ PR1103

2
6

VGA@ PC1103

VGA@ PC1104
6.04K_0402_1%

2
5 FB

2
EN

NC

NC
@VGA@ PR1104

TP
0_0402_5% FB_0.95V
1 2+0.95V_ON
37,49 VGA_ON_R

11

1
Rdown

1
0.1U_0402_16V7K

1
VGA@ PC1105

@VGA_EMI@ PC1106
VGA@ PR1107

680P_0402_50V7K
1
0_0402_5% SY8033BDBC_DFN10_3X3 VGA@ PR1106
1 2 10K_0402_1%
22,37,47,49 VGA_PG

2
2

2
1

VGA@ PR1105
1M_0402_5%
HW request Add PR1107,
and unpop PR1104
2

B
Note: Vout=0.6V* (1+Rup/Rdown) B
When design Vin=5V, please stuff snubber
to prevent Vin damage

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/02 Deciphered Date 2013/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.95VSDGPU
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3

I'm from VIETNAM sualaptop365 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, February 12, 2014 Sheet 48 of 53
5 4 3 2 1
 A B C D E

GPIO21 GPIO29 GPIO30 GPIO20 GPIO15 AMD MARS series LP: DDR3 AMD SUN series UL: DDR3 Description
Pro/XT/XTX: GDDR5 Pro/XT/XTX: GDDR5
VID5 VID4 VID3 VID2 VID1 VDDC
0 1 1 1 1 1.125V GPU MARS XTX MARS XT MARS PRO MARS LP SUN UL SUN PRO SUN XT NA
1 0 0 0 0 1.100V
VDDC 0.775~1.175V 0.775~1.125V 0.775~1.050V 0.775~1.000V 0.775~1.125V 0.800~1.075V 0.800~1.150V NA
1 0 0 0 1 1.075V
1 0 0 1 0 1.050V TDC 32A (TDC) 25A (TDC) 21A (TDC) 17A (TDC) 16A (TDC) 19A (TDC) 25A (TDC) NA
H-side MOS:TPCA8065
1 0 0 1 1 1.025V Rds(on):
EDC 48A 37.5A 31.5A 26A 24A 28.5A 37.5A NA
1 0 1 0 0 1.000V 9.4mohm@Vgs=10V
1 0 1 0 1 0.975V OCP 57.6A 45A 37.8A 31.2A 28.8A 34.2A 45A NA 11.7mohm@Vgs=4.5V
Id :16A@Ta=25 degC
1
1 0 1 1 0 0.950V 1

Vboot 0.85V 0.85V 0.85V 0.85V 0.9V 0.9V 0.9V NA

1 0 1 1 1 0.925V L-side MOS:TPCA8057
1 1 0 0 0 0.900V Vboot Load line 1mohm 1mohm 1mohm --------- --------- --------- 1mohm NA Rds(on):
Remark: 2.0mohm@Vgs=10V
1 1 0 0 1 0.875V 2.6~3.2mohm@Vgs=4.5V
1. PWM3 (Pin24) tie to 5V & CLK# (Pin40) external pull high Ri for OCP and
1 1 0 1 0 0.850V PR1248 1.13K Ohm 887 Ohm 750 Ohm --------- --------- --------- 887 Ohm LoadLine Setting Id :42A@Ta=25 degC
=> 2 phase CPU VR config
PWM3 (Pin24) tie to 5V & CLK# (Pin40) tie to GND or floating 1 1 0 1 1 0.825V
=> 2 phase GPU VR config Rdroop for LoadLine Choke: 0.22uH (Size:7*7*4)
1 1 1 0 0 0.800V PR1229 1.43K Ohm 1.13K Ohm 953 Ohm --------- --------- --------- 1.13K Ohm Setting Rdc=0.98mohm +-5%
1 1 1 0 1 0.775V Heat Rating Current=28A
2. When 2 Phase GPU config PR1233 187K Ohm 147K Ohm 124K Ohm --------- --------- --------- 147K Ohm for Compensation Saturation Current=28A
a. DPSLPVR (Pin39)=0 PSI# (Pin2)=0

www.qdzbwx.com
=>1 phase CCM operation mode
b. DPSLPVR (Pin39)=0 PSI# (Pin2)=1 PR1236 51.1K Ohm 51.1K Ohm 51.1K Ohm --------- --------- --------- 51.1K Ohm for Positive offset
=>2 phase CCM operation mode
c. DPSLPVR (Pin39)=1 PSI# (Pin2)=0 or 1
=>1 phase DE operation mode Remark: MARS LP/ SUN UL/ SUN PRO
don't use this 2-phase solution
3. Rbias=147K =>overshoot reduction function disable
@VGA@ PR1201
Rbias=47k =>overshoot reduction function enable 0_0402_5% +3VSDGPU Vboot regulation
1 2 +VGA_B+ VGA_EMI@

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
37,48 VGA_ON_R PL1201

@VGA@ PC1235
.1U_0402_16V7K
1 2
.1U_0402_16V7K
1 B+

1
VGA@ PC1201

4. Thermal throttling:

1
HCB2012KF-121T50_0805

2200P_0402_50V7K

VGA@ 10U_0805_25V6K

VGA@ 10U_0805_25V6K
0.1U_0402_25V6
Protect: (6.98K+Rth)*60uA=1.2V
2

=> Rth=13.02K

@VGA_EMI@ PC1202

VGA_EMI@ PC1203
2

1
VGA@ PR1202

VGA@ PR1203

@VGA@ PR1204

@VGA@ PR1205

@VGA@ PR1206

@VGA@ PR1208

@VGA@ PR1209

VGA@ PR1210

VGA@ PR1211

VGA@ PR1212

PC1204

PC1205
=>Tp=110C (+-3C)

GPU_VID_5 2

GPU_VID_4 2

GPU_VID_3 2

GPU_VID_2 2

GPU_VID_1 2

GPU_VID_5 2

GPU_VID_4 2

GPU_VID_3 2

GPU_VID_2 2

GPU_VID_1 2
Recovery:(6.98K+Rth)*56uA=1.24V

2
=> Rth=15.16K VGA@ PR1214
Module model information:

5
1 2DPRSLPVR_VGA-1
=> Tr=105C (+-3C) 14 GPU_DPRSLPVR
ISL62883C_V1A for IC

VGA@ PQ1201
AON6552_DFN5X6-8-5
10K_0402_1% @VGA@
2
PR1226=6.98K PR1226=1.5K PR1216 ISL62883C_V1B for SW Choke/MOS on BTN 2

0_0603_5%
GPU_VID_5

GPU_VID_4

GPU_VID_3

GPU_VID_2

GPU_VID_1
14

14

14

14

14
protect T protect T +3VSDGPU 1 2 UGATE2_VGA 1 2 4 ISL62883C_V2B for SW Choke on BTN, MOS on TOP
@VGA@ PR1215
110C +-3 100C +-3 1.91K_0402_1% VGA@ PR1217 VGA@ PC1206
2.2_0603_5% 0.22U_0603_25V7K
Recovery T Recovery T BOOT2_VGA 1 2
BOOT2_2_VGA 1 2
22,37,47,48 VGA_PG

3
2
1
VGA@ PL1202
105C +-3 96C +-3 0.22UH_PCME064T-R22MS_28A_20% +VGA_CORE

5. Switching frequency set : PHASE2_VGA 1 4

GPU_VID_0
Rfset(kohm)=[period(us)-0.29]*2.65 1 2 2 3
+3VSDGPU

5
VRON_VGA

=5.9Kohm VGA@ PR1218

GPU_VID6

1
VGA@ PQ1202

@VGA_EMI@ PC1210 @VGA_EMI@ PR1219

100K_0402_5%

4.7_1206_5%
fsw=1/period(us)=400KHZ Rsum

AON6554_DFN5X6-8-5
Rbias VGA@ PR1220
PH1201 from SL200000J00 change to 147K_0402_1% Ro

3.65K_0402_1%
PSI#_VGA

1
1 2 LGATE2_VGA 4

1_0402_1%
VGA@ PR1222
10K_0402_1%

10K_0402_1%
common part SL200002E00

SNUB2_VGA
2

VGA@ PR1221

VGA@ PR1224
2013/10/23

VGA@ PR1223
RBIAS_VGA

3
2
1

2
VGA@ PR1225

680P_0603_50V7K
Layout Note:
40
39
38
37
36
35
34
33
32
31

100K_0402_5% PU1201
PH1201 should place near 1 2
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON

+3VSDGPU

1
phase1 H-side MOS
30 VSUM+_VGA ISEN2_VGA ISEN1_VGA VSUM-_VGA
BOOT2 29

2
1 UGATE2 28
RthVGA@ 2 PGOOD PHASE2 27
VGA@ PR1226 3 PSI# VSSP2 26
PH1201 RBIAS LGATE2
6.98K_0402_1% 4 25 +5VS
1 2 1 2 5 VR_TT# VCCP 24
VW_VGA 6 NTC PWM3 23

1U_0603_10V6K

1U_0603_10V6K
VW LGATE1

1
7 22

VGA@ PC1212

VGA@ PC1213
470K_0402_5%_B25/50 4700K COMP_VGA
FB_VGA 8 COMP VSSP1 21
1 2ISEN3_VGA 9 FB PHASE1 +VGA_CORE
Rfset
2

2
UGATE1

ISEN3
10 TDC 28A
1000P_0402_50V7K

BOOT1
ISUM+

ISEN2
1

ISEN1

ISUM-
VSEN

IMON

VGA@ PC1211
5.9K_0402_1%

VDD
RTN

Peak Current 40 A
VIN

41 +VGA_B+
VGA@ PR1227

VGA@ PC1214

22P_0402_50V8J
AGND
1

VGA@ ISL62883CHRTZ-T_TQFN40_5X5 OCP current > 48A

11
12
13
14
15
16
17
18
19
20

3 3
PR1228 VGA@ PC1215 VGA@
Load line 1mohm
2

499_0402_1% 390P_0402_50V7K
1 2FB1_VGA
1 2
FSW=400kHz
ISUM-_VGA

VDD_VGA
RTN_VGA

DCR 0.98mohm +/-5%

10U_0805_25V6K

10U_0805_25V6K
VGA@ PC1217

VGA@ PC1218
VGA@ PR1229
BOOT1_VGA

5
1.24K_0402_1% 1 2
+5VS TYP MAX

1
1 2

VGA@ PQ1203
VGA@ PC1216 VSEN_VGA @VGA@
PR1230

AON6552_DFN5X6-8-5
33P_0402_50V8J @VGA@
PR12310_0402_5% 10K_0402_1% @VGA@ H/S Rds(on) :11.7mohm , 14.5mohm
1 2 VIN_VGA 1 2 PR1232
Rdroop L/S Rds(on) :2.6mohm , 3.2mohm

2
ISEN2_VGA +VGA_B+ 0_0603_5%
VGA@ PC1219 VGA@ PR1233 VGA@ PR1234 PR1230 Pop: UGATE1_VGA 1 2 4
150P_0402_50V8J 147K_0402_1% ISEN1_VGA 1_0402_5%
1 2FB2_VGA1 2 1 2 for Loadline disable
0.22U_0402_16V7K

0.22U_0402_16V7K

PR1230 @: 1 2 BOOT1_1_VGA 1 2
VGA@ PC1221

VGA@ PC1222

VGA@ PC1223

0.22U_0603_25V7K

+5VS
1

1
VGA@ PR1236

VGA@ PC1224

VGA@ PR1235
51.1K_0402_1%

for Loadline enable

3
2
1
1

2.2_0603_5% VGA@ PC1220 VGA@ PL1203

1U_0603_10V6K

and LL=1mohm 0.22U_0603_25V7K 0.22UH_PCME064T-R22MS_28A_20% +VGA_CORE

2

PHASE1_VGA 1 4
for positive offset
2

2 3

PQ1204
AON6554_DFN5X6-8-5

1
VSUM-_VGA

4.7_1206_5%
PR1238
@VGA_EMI@
1 2
+VGA_CORE
LGATE1_VGA 4

SNUB1_VGA
VSUM+_VGA

2 PR1242 1
VGA@

1_0402_1%
VGA@ PR1237

10K_0402_1%

10K_0402_1%
3.65K_0402_1%
2

VGA@ PR1239

VGA@ PR1240
10_0402_1%

VGA@ PR1241
Cn
3
2
1
VGA@ PR1244

@VGA@ PR1243
2.61K_0402_1%

2
1

1 2
16 VCC_GPU_SENSE
1

VGA@
PC1229
@VGA_EMI@

680P_0603_50V7K
0_0402_5%

1
VGA@ PC1228
Rp Rntcs
0.033U_0402_16V7K

1000P_0402_50V7K
0.15U_0603_16V7K
2

330P_0402_50V7K

1NTC_VGA 2

2
1
VGA@ PC1231

VGA@ PC1232

VGA@ PR1245
11K_0402_1%
1

VSUM+_VGA ISEN1_VGA ISEN2_VGA

@VGA@ PC1230

Transient response : VSUM-_VGA

Rntcnet=(Rntcs+Rntc)*Rp/(Rntcs+Rntc+Rp)
2

4 4
2

VGA@ Cn=L*(Rntcnet+Rsum/N)/[Rntcnet*DCR*(Rsum/N)]
1

@VGA@ PR1246 VGA@ PC1233 PH1202

1 2 1000P_0402_50V7K 10K_0402_1%_B25/50 3370K N is the number of phases
16 VSS_GPU_SENSE
2

0_0402_5%
Rntc
2

Rdroop=Io*LL/Idroop
VGA@ PR1248
976_0402_1%
1 2 1 2
VSUM-_VGA
VGA@ PR1247
10_0402_1% Ri Layout Note:
1

VGA@ PC1234
.1U_0402_16V7K PH1202 should place near Security Classification Compal Secret Data Compal Electronics, Inc.
Phase1 Choke Issued Date 2013/01/03 Deciphered Date 2013/10/01 Title
2

PH1202 from SL200000W00 change to THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE
Size Document Number Rev
common part SL200002F00 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

I'm from VIETNAM sualaptop365 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
0.3
2013/10/23 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 12, 2014 Sheet 49 of 53
A B C D E
 A
B
C
D

5
5

2 1 2 1

VGA@ PC1339 VGA@ PC1328

+VGA_CORE
22U_0603_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1
+VGA_CORE

VGA@ PC1340 VGA@ PC1329 VGA@ PC1319 VGA@ PC1309 VGA@ PC1301
22U_0603_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1

VGA@ PC1341 VGA@ PC1330 VGA@ PC1320 VGA@ PC1310 VGA@ PC1302
22U_0603_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1

VGA@ PC1342 VGA@ PC1331 VGA@ PC1321 VGA@ PC1311 VGA@ PC1303
22U_0603_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1

I'm from VIETNAM

VGA@ PC1343 VGA@ PC1332 VGA@ PC1322 VGA@ PC1312 VGA@ PC1304
22U_0603_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 2 1 2 1

VGA@ PC1333 VGA@ PC1323 VGA@ PC1313 VGA@ PC1305

10U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1

4
4

VGA@ PC1334 VGA@ PC1324 VGA@ PC1314 VGA@ PC1306

10U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 2 1
2
1
+

VGA@ PC1335 VGA@ PC1325 VGA@ PC1315 VGA@ PC1307

2.2U_0402_6.3V6M 560U_2.5V_M 2.2U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1
2
1
+

Issued Date

sualaptop365
VGA@ PC1336 VGA@ PC1326 VGA@ PC1316 VGA@ PC1308
10U_0402_6.3V6M 560U_2.5V_M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1

Security Classification
2
1
+

VGA@ PC1337 @VGA@ PC1327 VGA@ PC1317

10U_0402_6.3V6M 330U_X_2VM_R6M 2.2U_0402_6.3V6M
2 1 2 1

VGA@ PC1338 VGA@ PC1318

10U_0402_6.3V6M 10U_0402_6.3V6M

2011/06/24
www.qdzbwx.com

3
3

meet ripple
AMD MARS
AMD MARS
GPU_CORE
560uF*2+330uF*1
10uF*11+2.2uF*13

Compal Secret Data

Deciphered Date
22uF*5+10uF*8+2.2uF*3

2013/10/01

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2
2

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Title

Date:
Custom
Size Document Number

Wednesday, February 12, 2014

VGA_CORE CAP

1
Sheet
1

50
Compal Electronics, Inc.

of
53
Rev
0.3
A
B
C
D
 5 4 3 2 1

Version change list (P.I.R. List) www.qdzbwx.com Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

PQ801;PQ803;PQ807;PQ808 FDMS7698 and PQ802;PQ804;PQ806;PQ809 MDU1511 10/09 EVT

1 layout area not enought APU_CORE change to Dual N AON6932A
D D

EMI bead "HCB2012KF-121T50_0805" derating 5A, Add PL806 EMI bead "HCB2012KF-121T50_0805" from 1pcs to 2pcs at B+, 10/15 EVT
2 need 2pcs for APU_CORE and APU_CORENB APU_CORE for APU_CORE and APU_CORENB

3 RT8880A FAE review APU_CORE PR813 from 0402 change to 0603, delete PR844, PR847 10/16 EVT
HW: EC share ROM, 3VALW change 3VALW enable net name from 3V5V_EN to 3V_EN
4 modify 3VALW and 1.1VALW enable net-name 5VALW change 1.1VALW enable net name from SUSP# to 1.1V_EN 10/17 EVT

5 Choke, OS-CON cap, Thermistor

change to standard part 10/23 EVT

6 CPU_CORE IC from RT8880A SA000066V00 change to 10/23 EVT

RT8880A vendor EOL, change to RT8880B APU_CORE RT8880B SA000066V10

7 Battery connector BATT+ bead,

1pcs for UMA, BATT Add PL202 HCB2012KF-121T50_0805 for DIS only 10/28 EVT
2pcs for DIS. CONN

+1.05VS PC609, PC610 and PC709, PC710 from

8 22U_0603_6.3V6M cheaper than 47U_0603_6.3V6M +1.1VALW 47U_0603_6.3V6M change to 22U_0603_6.3V6M 10/30 EVT
C C

HW request Add PR1107, and unpop PR1104,

9 VGA_PG is default setting for +0.95V Add location PR1107 0_0402_5%, and unpop PR1104 0_0402_5% 10/31 EVT
VGA sequence control

10 Add PR413 0_0402_5%, 10/31 EVT

HW request add RC at 3VALW enable +3VALW and PC428 0.1U_0402_10V7K _ un-pop

11 change PR607 from 100K ohm to 15.4K ohm, 12/02 DVT

adjust 1.05V output voltage
+1.05VSP change PR609 from 133K ohm to 20K ohm,
change 1.05V output from 1.05V to 1.062V

change PR723 from 20K ohm to 20.5K ohm, 12/10 DVT

12 adjust 1.8VSP output voltage +1.8VSP change 1.05V output from 1.8V to 1.83V

change PR709 from 118K ohm to 115K ohm, 12/10 DVT

13 adjust 1.1VALW output voltage +1.1VALW
B
change 1.1VALW output from 1.108V to 1.121V B

change enable resistor PR413, PR602, PR702, PR724 from 0 ohm to R-Short,
14 Part count reduce change EMI High side and Low side resistor PR308, PR407, PR605, 12/10 DVT
PR705, PR801, PR820, PR849, PR860, PR1216, PR1232 from 0 ohm to R-Short.

15 change PR1205 from pop to un-pop,

adjust VGA Vboot voltage VGA change PR1211 from un-pop to pop. 12/13 DVT

16 reserve PD801 for AMD CPU lekage voltage from APU_SVD 12/13 DVT
reserve PD801 CPU_CORE

change PR216 from 22.6K to 16K,

delete VCIN0 and VCIN1 hysteresis OTP change PR227 from 26.1K to un-pop,
17
change PR202 from UMA/10.5K and DIS/11.3K to 10K, 12/24 DVT
change PR223 from UMA/162K and DIS/100K to un-pop.

18 ABO request BI pin short to GND BATT CONN change PR210 from 1k to 0 ohm. 12/26 DVT MEMO

A A

19 65W and 40W VCIN0 set at the same voltage OTP change UMA SKU PR203 from 10K to 44.2K 12/26 DVT MEMO
active and recovery Add PC426

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/07/10 Deciphered Date 2013/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_PIR1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 51 of 53
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 2

www.qdzbwx.com for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

20 back to back damage, change to low Rds(on) Mos 0.3 Charger PQ303, PQ304 change from AON4466 to AON4406 01/08 PVT
D D

3VALW/
21 delete PD401 cost down 0.3 5VALW change PD301 to R-short PR415 01/08 PVT

22 change PD801 to low Vf diode 0.3 CPU_CORE change PD801 from RB751V-40_SOD323-2 to RB491D_SOT23-3 01/20 PVT

23

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/07/10 Deciphered Date 2013/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_PIR2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK
I'm from VIETNAM sualaptop365
Date: Wednesday, February 12, 2014 Sheet 52 of 53
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Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/07/10 Deciphered Date 2013/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR-HW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAK
Date: Wednesday, February 12, 2014 Sheet 53 of 53
I'm from VIETNAM
A
sualaptop365
B C D E