TPM5.1E
LA
18850_000_100107.eps
100209
©
Copyright 2010 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.
Published by MB/WS 1070 BU TV Consumer Care, the Netherlands Subject to modification EN 3122 785 18852
2010-Oct-15
EN 2 1. TPM5.1E LA Revision List
1. Revision List
Manual xxxx xxx xxxx.0 Manual xxxx xxx xxxx.2
• First release. • Added models 32HFL3232D/10 and 32PFL3205H/12 to
Manual xxxx xxx xxxx.1 the manual
• Added models 47PFL3605H/xx to the manual • Chapter 2: Added new models in Table 2-1.
• Chapter 2: Added new models to Table 2-1. • Chapter 5: Updated SAM contents.
• Chapter 4: added wiring diagrams and mechanical • Chapter 6: Add the panel codes in Table 6-3.
information of 47" sets.
• Chapter 4: added information on returning a defect LCD
panel.
• Chapter 5: Updated SAM contents.
• Chapter 6: Added table 6-2 White tone default settings and
updated table 6-3 Panel codes overview.
• Chapter 9: Added 47" Wiring Diagram.
• Chapter 11: Added 47" Styling Sheet.
For on-line product support please use the links in. Here is
product information available, as well as getting started, user
manuals, frequently asked questions and software & drivers.
2010-Oct-15
Technical Specifications, Connections TPM5.1E LA 2. EN 3
2.3 Connections
6 7 8
9
3
10
4
11
5
12
13
18850_001_100107.eps
100209
Note: The following connector colour abbreviations are used 6 - D1- Data channel j
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, 7 - D0+ Data channel j
Gy= Grey, Rd= Red, Wh= White, Ye= Yellow. 8 - Shield Gnd H
9 - D0- Data channel j
2.3.1 Side Connections 10 - CLK+ Data channel j
11 - Shield Gnd H
12 - CLK- Data channel j
1 - Cinch: Video CVBS - In, Audio - In
Ye - Video CVBS 1 VPP / 75 : jq 13 - n.c.
14 - n.c.
Rd - Audio R 0.5 VRMS / 10 k: jq
15 - DDC_SCL DDC clock j
Wh - Audio L 0.5 VRMS / 10 k: jq
16 - DDC_SDA DDC data jk
17 - Ground Gnd H
2 - USB2.0
18 - +5V j
19 - HPD Hot Plug Detect j
1 2 3 4 20 - Ground Gnd H
10000_022_090121.eps
090121 4 - Head phone (Output)
Bk - Head phone 80 - 600 : / 10 mW ot
Figure 2-2 USB (type A)
5 - Common Interface
1 - +5V k
68p - See diagram B08 SSB: CI card. jk
2 - Data (-) jk
3 - Data (+) jk
4 - Ground Gnd H 2.3.2 Rear Connections
10000_017_090121.eps
090428
2010-Oct-15
EN 4 2. TPM5.1E LA Technical Specifications, Connections
7 - EXT1 - 2: Video RGB/YC - In, CVBS - In/Out, Audio - In/ 3 - UART_RX Receive j
Out
20 2 10 - EXT3: Video YPbPr - In, Audio - In
Gn - Video - Y 1 VPP / 75 W jq
Bu - Video - Pb 0.7 VPP / 75 W jq
21 1
10000_001_090121.eps
Rd - Video - Pr 0.7 VPP / 75 W jq
090121
0.7 VPP / 75 : jk
10
7 - Video Blue/C-out 6
11 15
8 - Function Select 0 - 2 V: INT
10000_002_090121.eps
4.5 - 7 V: EXT 16:9 090127
9.5 - 12 V: EXT 4:3 j
9 - Ground Green Gnd H Figure 2-5 VGA connector
10 - n.c.
11 - Video Green 0.7 VPP / 75 : j 1 - Video Red 0.7 VPP / 75 : j
12 - n.c. 2 - Video Green 0.7 VPP / 75 : j
13 - Ground Red Gnd H 3 - Video Blue 0.7 VPP / 75 : j
14 - Ground P50 Gnd H 4 - n.c.
15 - Video Red/C 0.7 VPP / 75 : j 5 - Ground Gnd H
16 - Status/FBL 0 - 0.4 V: INT 6 - Ground Red Gnd H
1 - 3 V: EXT / 75 : j 7 - Ground Green Gnd H
17 - Ground Video Gnd H 8 - Ground Blue Gnd H
18 - Ground FBL Gnd H 9 - +5VDC +5 V j
19 - Video CVBS 1 VPP / 75 : k 10 - Ground Sync Gnd H
20 - Video CVBS/Y 1 VPP / 75 : j 11 - Ground Red Gnd H
21 - Shield Gnd H 12 - DDC_SDA DDC data j
13 - H-sync 0-5V j
8 - Cinch: S/PDIF - Out 14 - V-sync 0-5V j
Bk - Coaxial 0.4 - 0.6VPP / 75 ohm kq 15 - DDC_SCL DDC clock j
2010-Oct-15
Precautions, Notes, and Abbreviation List TPM5.1E LA 3. EN 5
2010-Oct-15
EN 6 3. TPM5.1E LA Precautions, Notes, and Abbreviation List
The third digit in the serial number (example: 3.4 Abbreviation List
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the 0/6/12 SCART switch control signal on A/V
specific TV set. In general, it is possible that the same TV
board. 0 = loop through (AUX to TV),
model on the market is produced with e.g. two different types
6 = play 16 : 9 format, 12 = play 4 : 3
of displays, coming from two different suppliers. This will then format
result in sets which have the same CTN (Commercial Type
AARA Automatic Aspect Ratio Adaptation:
Number; e.g. 28PW9515/12) but which have a different B.O.M.
algorithm that adapts aspect ratio to
number. remove horizontal black bars; keeps
By looking at the third digit of the serial number, one can
the original aspect ratio
identify which B.O.M. is used for the TV set he is working with.
ACI Automatic Channel Installation:
If the third digit of the serial number contains the number “1” algorithm that installs TV channels
(example: AG1B033500001), then the TV set has been
directly from a cable network by
manufactured according to B.O.M. number 1. If the third digit is
means of a predefined TXT page
a “2” (example: AG2B0335000001), then the set has been ADC Analogue to Digital Converter
produced according to B.O.M. no. 2. This is important for
AFC Automatic Frequency Control: control
ordering the correct spare parts!
signal used to tune to the correct
For the third digit, the numbers 1...9 and the characters A...Z frequency
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
AGC Automatic Gain Control: algorithm that
indicated by the third digit of the serial number.
controls the video input of the feature
box
Identification: The bottom line of a type plate gives a 14-digit AM Amplitude Modulation
serial number. Digits 1 and 2 refer to the production centre (e.g. AP Asia Pacific
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers AR Aspect Ratio: 4 by 3 or 16 by 9
to the Service version change code, digits 5 and 6 refer to the ASF Auto Screen Fit: algorithm that adapts
production year, and digits 7 and 8 refer to production week (in aspect ratio to remove horizontal black
example below it is 2006 week 17). The 6 last digits contain the bars without discarding video
serial number. information
ATSC Advanced Television Systems
MODEL : 32PF9968/10 MADE IN BELGIUM Committee, the digital TV standard in
220-240V ~ 50/60Hz the USA
128W
ATV See Auto TV
PROD.NO: AG 1A0617 000001 VHF+S+H+UHF
Auto TV A hardware and software control
S BJ3.0E LA system that measures picture content,
and adapts image parameters in a
10000_024_090121.eps dynamic way
100105
AV External Audio Video
AVC Audio Video Controller
Figure 3-1 Serial number (example)
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
3.3.7 Board Level Repair (BLR) or Component Level Repair carrier distance is 5.5 MHz
(CLR) BDS Business Display Solutions (iTV)
BLR Board-Level Repair
If a board is defective, consult your repair procedure to decide BTSC Broadcast Television Standard
if the board has to be exchanged or if it should be repaired on Committee. Multiplex FM stereo sound
component level. system, originating from the USA and
If your repair procedure says the board should be exchanged used e.g. in LATAM and AP-NTSC
completely, do not solder on the defective board. Otherwise, it countries
cannot be returned to the O.E.M. supplier for back charging! B-TXT Blue TeleteXT
C Centre channel (audio)
3.3.8 Practical Service Precautions CEC Consumer Electronics Control bus:
remote control bus on HDMI
• It makes sense to avoid exposure to electrical shock. connections
While some sources are expected to have a possible CL Constant Level: audio output to
dangerous impact, others of quite high potential are of connect with an external amplifier
limited current and are sometimes held in less regard. CLR Component Level Repair
• Always respect voltages. While some may not be ComPair Computer aided rePair
dangerous in themselves, they can cause unexpected CP Connected Planet / Copy Protection
reactions that are best avoided. Before reaching into a CSM Customer Service Mode
powered TV set, it is best to test the high voltage insulation. CTI Color Transient Improvement:
It is easy to do, and is a good service precaution. manipulates steepness of chroma
transients
CVBS Composite Video Blanking and
Synchronization
DAC Digital to Analogue Converter
DBE Dynamic Bass Enhancement: extra
low frequency amplification
DCM Data Communication Module. Also
referred to as System Card or
Smartcard (for iTV).
DDC See “E-DDC”
D/K Monochrome TV system. Sound
carrier distance is 6.5 MHz
DFI Dynamic Frame Insertion
2010-Oct-15
Precautions, Notes, and Abbreviation List TPM5.1E LA 3. EN 7
DFU Directions For Use: owner's manual SDI), is a digitized video format used
DMR Digital Media Reader: card reader for broadcast grade video.
DMSD Digital Multi Standard Decoding Uncompressed digital component or
DNM Digital Natural Motion digital composite signals can be used.
DNR Digital Noise Reduction: noise The SDI signal is self-synchronizing,
reduction feature of the set uses 8 bit or 10 bit data words, and has
DRAM Dynamic RAM a maximum data rate of 270 Mbit/s,
DRM Digital Rights Management with a minimum bandwidth of 135
DSP Digital Signal Processing MHz.
DST Dealer Service Tool: special remote ITV Institutional TeleVision; TV sets for
control designed for service hotels, hospitals etc.
technicians LS Last Status; The settings last chosen
DTCP Digital Transmission Content by the customer and read and stored
Protection; A protocol for protecting in RAM or in the NVM. They are called
digital audio/video content that is at start-up of the set to configure it
traversing a high speed serial bus, according to the customer's
such as IEEE-1394 preferences
DVB-C Digital Video Broadcast - Cable LATAM Latin America
DVB-T Digital Video Broadcast - Terrestrial LCD Liquid Crystal Display
DVD Digital Versatile Disc LED Light Emitting Diode
DVI(-d) Digital Visual Interface (d= digital only) L/L' Monochrome TV system. Sound
E-DDC Enhanced Display Data Channel carrier distance is 6.5 MHz. L' is Band
(VESA standard for communication I, L is all bands except for Band I
channel and display). Using E-DDC, LPL LG.Philips LCD (supplier)
the video source can read the EDID LS Loudspeaker
information form the display. LVDS Low Voltage Differential Signalling
EDID Extended Display Identification Data Mbps Mega bits per second
(VESA standard) M/N Monochrome TV system. Sound
EEPROM Electrically Erasable and carrier distance is 4.5 MHz
Programmable Read Only Memory MHEG Part of a set of international standards
EMI Electro Magnetic Interference related to the presentation of
EPG Electronic Program Guide multimedia information, standardised
EPLD Erasable Programmable Logic Device by the Multimedia and Hypermedia
EU Europe Experts Group. It is commonly used as
EXT EXTernal (source), entering the set by a language to describe interactive
SCART or by cinches (jacks) television services
FDS Full Dual Screen (same as FDW) MIPS Microprocessor without Interlocked
FDW Full Dual Window (same as FDS) Pipeline-Stages; A RISC-based
FLASH FLASH memory microprocessor
FM Field Memory or Frequency MOP Matrix Output Processor
Modulation MOSFET Metal Oxide Silicon Field Effect
FPGA Field-Programmable Gate Array Transistor, switching device
FTV Flat TeleVision MPEG Motion Pictures Experts Group
Gb/s Giga bits per second MPIF Multi Platform InterFace
G-TXT Green TeleteXT MUTE MUTE Line
H H_sync to the module MTV Mainstream TV: TV-mode with
HD High Definition Consumer TV features enabled (iTV)
HDD Hard Disk Drive NC Not Connected
HDCP High-bandwidth Digital Content NICAM Near Instantaneous Compounded
Protection: A “key” encoded into the Audio Multiplexing. This is a digital
HDMI/DVI signal that prevents video sound system, mainly used in Europe.
data piracy. If a source is HDCP coded NTC Negative Temperature Coefficient,
and connected via HDMI/DVI without non-linear resistor
the proper HDCP decoding, the NTSC National Television Standard
picture is put into a “snow vision” mode Committee. Color system mainly used
or changed to a low resolution. For in North America and Japan. Color
normal content distribution the source carrier NTSC M/N= 3.579545 MHz,
and the display device must be NTSC 4.43= 4.433619 MHz (this is a
enabled for HDCP “software key” VCR norm, it is not transmitted off-air)
decoding. NVM Non-Volatile Memory: IC containing
HDMI High Definition Multimedia Interface TV related data such as alignments
HP HeadPhone O/C Open Circuit
I Monochrome TV system. Sound OSD On Screen Display
carrier distance is 6.0 MHz OAD Over the Air Download. Method of
I2 C Inter IC bus software upgrade via RF transmission.
I2 D Inter IC Data bus Upgrade software is broadcasted in
I2 S Inter IC Sound bus TS with TV channels.
IF Intermediate Frequency OTC On screen display Teletext and
IR Infra Red Control; also called Artistic (SAA5800)
IRQ Interrupt Request P50 Project 50: communication protocol
ITU-656 The ITU Radio communication Sector between TV and peripherals
(ITU-R) is a standards body PAL Phase Alternating Line. Color system
subcommittee of the International mainly used in West Europe (color
Telecommunication Union relating to carrier= 4.433619 MHz) and South
radio communication. ITU-656 (a.k.a. America (color carrier PAL M=
2010-Oct-15
EN 8 3. TPM5.1E LA Precautions, Notes, and Abbreviation List
3.575612 MHz and PAL N= 3.582056 SVHS Super Video Home System
MHz) SW Software
PCB Printed Circuit Board (same as “PWB”) SWAN Spatial temporal Weighted Averaging
PCM Pulse Code Modulation Noise reduction
PDP Plasma Display Panel SXGA 1280 × 1024
PFC Power Factor Corrector (or Pre- TFT Thin Film Transistor
conditioner) THD Total Harmonic Distortion
PIP Picture In Picture TMDS Transmission Minimized Differential
PLL Phase Locked Loop. Used for e.g. Signalling
FST tuning systems. The customer TS Transport Stream
can give directly the desired frequency TXT TeleteXT
POD Point Of Deployment: a removable TXT-DW Dual Window with TeleteXT
CAM module, implementing the CA UI User Interface
system for a host (e.g. a TV-set) uP Microprocessor
POR Power On Reset, signal to reset the uP UXGA 1600 × 1200 (4:3)
PSDL Power Supply for Direct view LED V V-sync to the module
backlight with 2D-dimming VESA Video Electronics Standards
PSL Power Supply with integrated LED Association
drivers VGA 640 × 480 (4:3)
PSLS Power Supply with integrated LED VL Variable Level out: processed audio
drivers with added Scanning output toward external amplifier
functionality VSB Vestigial Side Band; modulation
PTC Positive Temperature Coefficient, method
non-linear resistor WYSIWYR What You See Is What You Record:
PWB Printed Wiring Board (same as “PCB”) record selection that follows main
PWM Pulse Width Modulation picture and sound
QRC Quasi Resonant Converter WXGA 1280 × 768 (15:9)
QTNR Quality Temporal Noise Reduction XTAL Quartz crystal
QVCP Quality Video Composition Processor XGA 1024 × 768 (4:3)
RAM Random Access Memory Y Luminance signal
RGB Red, Green, and Blue. The primary Y/C Luminance (Y) and Chrominance (C)
color signals for TV. By mixing levels signal
of R, G, and B, all colors (Y/C) are YPbPr Component video. Luminance and
reproduced. scaled color difference signals (B-Y
RC Remote Control and R-Y)
RC5 / RC6 Signal protocol from the remote YUV Component video
control receiver
RESET RESET signal
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs
SCL Serial Clock I2C
SCL-F CLock Signal on Fast I2C bus
SD Standard Definition
SDA Serial Data I2C
SDA-F DAta Signal on Fast I2C bus
SDI Serial Digital Interface, see “ITU-656”
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mémoire.
Color system mainly used in France
and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link
standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
reduce the effects of EMI
STB Set Top Box
STBY STand-BY
SVGA 800 × 600 (4:3)
2010-Oct-15
Mechanical Instructions TPM5.1E LA 4. EN 9
4. Mechanical Instructions
Index of this chapter: Notes:
4.1 Cable Dressing • Figures below can deviate slightly from the actual situation,
4.2 Service Positions due to the different set executions.
4.3 Assembly/Panel Removal 32"
4.4 Assembly/Panel Removal 42"
4.5 Returning a defect 32" or 42" LCD panel
4.6 Assembly/Panel Removal 47"
4.7 Set Re-assembly.
18850_101_100107.eps
100202
2010-Oct-15
EN 10 4. TPM5.1E LA Mechanical Instructions
18850_100_100107.eps
100209
18850_103_100505.eps
100505
2010-Oct-15
Mechanical Instructions TPM5.1E LA 4. EN 11
For easy servicing of a TV set, the set should be put face down
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the
display. Caution: Failure to follow these guidelines can
seriously damage the display!
Ensure that ESD safe measures are taken.
2010-Oct-15
EN 12 4. TPM5.1E LA Mechanical Instructions
1 1
18850_104_100203.eps
100203
2 2
3 Figure 4-5 Keyboard Control Panel (32")
2010-Oct-15
Mechanical Instructions TPM5.1E LA 4. EN 13
4.4.3 Power Supply Unit (PSU) 3. Remove the SSB as described earlier.
4. Remove the clips that secure the LCD panel with the bezel.
Caution: it is mandatory to remount all different screws at their 5. Remove the fixation screws that secure the LCD panel with
original position during re-assembly. Failure to do so may result the bezel.
in damaging the PSU. 6. Lift the LCD Panel from the bezel.
1. Unplug power connector from the SSB and take the cable 7. Unplug the connector [1] from the Keyboard Control Panel.
out of the cable clamp. 8. Release the clips that secure the Keyboard Control
2. Unplug all other connectors from the PSU. Panel [2].
3. Remove the fixation screw that connects the ground cable. When defective, replace the whole unit.
4. Remove all fixation screws from the PSU.
5. The PSU can now be taken out of the set.
When defective, replace the whole unit. 1 2
2010-Oct-15
EN 14 4. TPM5.1E LA Mechanical Instructions
Warning: Disconnect the mains power cord before removing To re-assemble the whole set, execute all processes in reverse
the rear cover. order.
1. Remove the fixation screws that secure the rear cover. Notes:
2. Lift the rear cover from the TV. Make sure that wires and • While re-assembling, make sure that all cables are placed
flat foils are not damaged while lifting the rear cover from and connected in their original position. See Figure 4-1
the set. and Figure 4-2.
• Pay special attention not to damage the EMC foams on the
4.6.3 Small Signal Board (SSB) SSB shields. Ensure that EMC foams are mounted
correctly.
Caution: it is mandatory to remount all different screws at their
original position during re-assembly. Failure to do so may result
in damaging the SSB.
1. Release the clips from both the LVDS Flat Foil connectors.
Caution: be careful, as these are very fragile connectors!
Take the flat foils out of their connectors.
2. Unplug all other connectors.
3. Remove all other fixation screws from the SSB.
4. Take out the SSB together with side I/O BKT.
5. Remove the screws near the HDMI and L/R audio
connectors.
4.6.6 Speakers
1. Release the clips that hold the board and take it out from
the bezel.
2. Unplug the connectors from the IR/LED board.
When defective, replace the whole unit.
2010-Oct-15
Service Modes, Error Codes, and Fault Finding TPM5.1E LA 5. EN 15
Purpose
The Customer Service Mode shows error codes and
information on the TV's operation settings.The call centre can
instruct the customer (by telephone) to enter CSM in order to
identify the status of the set.This helps the call centre to
diagnose problems and failures in the TV set before making a
service call.
The CSM is a read-only mode; therefore, modifications are not
possible in this mode. 18850_202_100107.eps
100107
General
• 1.1 Set Type NVM read/write (max. 16 characters).
• 1.2 Production code NVM read/write (max. 16
characters).
• 1.3 Installation date Date the software was installed.
• 1.4 Option Code Store in NVM (set feature grouping as
option) panel code.
• 1.5 Codes Error code Layer 2. Store in NVM. 10 error
buffers: 000 = No problem, 011 = I2C bus error,
012 = tuner error, 013 = panel.
• 1.6 SSB 12NC NVM read/write (12 characters).
18850_200_100107.eps • 1.7 Display 12NC NVM read/write (12 characters).
100107 • 1.8 PSU 12NC NVM read/write (12 characters).
• 2.1 Current Main SW Detects and displays software
Figure 5-1 CSM Menu 1 version.
• 2.2 Standby SW Detects and displays software version.
• 2.3 SW version of other PP Detects and displays software
version.
• 2.4 Reserved Not applicable.
• 2.5 Reserved Not applicable.
• 2.6 NVM version Detects and displays software version.
• 3.1 Signal Quality/Present analog/digital signal strength.
• 3.2 Child lock Detects and displays.
• 3.3 HDCP keys Detects and displays.
• 3.4 CI slot present Detects and displays.
• 3.5 HDMI input format per Supported format. e.g.
576i 50 Hz, 576p 50 Hz, 720p 50 Hz, 1080i 50 Hz,
1080p 50 Hz.
• 3.6 HDMI audio format input stream Per supported
format e.g. Dolby TrueHD, DTS-HD Master Audio, MPCM.
2010-Oct-15
EN 16 5. TPM5.1E LA Service Modes, Error Codes, and Fault Finding
How to enter
18850_203_100202.eps
To enter the factory mode, use the following method: 100506
• Press the following key sequence on the remote control
transmitter: “062596” directly followed by the “INFO” Figure 5-4 Example of SAM
button.
After entering the factory mode, the following screen is visible Press “OK” to check the Version information of the software
on the top and right of the panel. when you select the “F/W Version”.
18850_212_100506.eps
100512
2010-Oct-15
Service Modes, Error Codes, and Fault Finding TPM5.1E LA 5. EN 17
5.2.1 ComPair
Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following:
1. ComPair helps to quickly get an understanding on how to
repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. No
knowledge on I2C or UART commands is necessary,
because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the uP
is working) and all repair information is directly available.
4. ComPair features TV software upgrade possibilities.
2010-Oct-15
EN 18 5. TPM5.1E LA Service Modes, Error Codes, and Fault Finding
TO TV
TO TO TO
UART SERVICE I2C SERVICE UART SERVICE
CONNECTOR CONNECTOR CONNECTOR
ComPair II
Multi
RC in function
RC out
PC
Optional power
HDMI 5V DC
I2C only
10000_036_090121.eps
091118
How to Order
ComPair II order codes:
• ComPair II interface: 3122 785 90630.
• Programming software can be downloaded from the Philips
Service portal.
• ComPair UART interface cable for TPM5.1x xx.
3122 785 90630.
2010-Oct-15
Service Modes, Error Codes, and Fault Finding TPM5.1E LA 5. EN 19
5.3.1 Introduction
1. Point your web browser to http://www.philips.com/support. Figure 5-8 Update the TV software 2
2. Find information and software related to your TV.
3. Select the latest software update file and download it to
your PC.
4. Insert a USB flash drive into one of the USB ports of your
PC.
5. Decompress the downloaded ZIP file and copy the
“autorun.upg” to the root directory of the USB flash drive.
2010-Oct-15
EN 20 5. TPM5.1E LA Service Modes, Error Codes, and Fault Finding
The error code buffer contains all errors detected since the last
time the buffer was erased. The buffer is written from left to
right. When an error occurs that is not yet in the error code
buffer, it is displayed at the left side and all other errors shift one
position to the right.
5.5.1 Speakers
5.5.2 Tuner
2010-Oct-15
Alignments TPM5.1E LA 6. EN 21
6. Alignments
Index of this chapter: Alignment:
6.1 General Alignment Conditions 1. At SAM mode menu, select AUTO_COLOR item. Then
6.2 Hardware Alignments press “OK” key to adjust ADC_GAIN_R, ADC_GAIN_G,
6.3 YPbPr Mode display adjustment ADC_GAIN_B and ADC_OFFSET_R, ADC_OFFSET_G,
6.4 PC mode display adjustment ADC_OFFSET_B. Then store those values to NVM.
6.5 LCD Panel Flicker Adjustment 2. Apply 80% white pattern.
6.6 Option Settings 3. Set colour temperature to “NORMAL”.
6.7 Serial Number Definition 4. At FAC mode menu, adjust the CLR TEMP R, CLR TEMP
G, CLR TEMP B values to meet “NORMAL” colour
Note: The Service Alignment Mode (SAM) are described in coordinates specification below. Then store those values to
chapter 5. Service Modes, Error Codes, and Fault Finding. NVM (R/G/B gain value <= 128).
Menu navigation is done with the CURSOR UP, DOWN, LEFT 5. Set colour temperature to “COOL”.
or RIGHT keys of the remote control transmitter. 6. At FAC mode menu, adjust the CLR TEMP R, CLR TEMP
G, CLR TEMP B values to meet “COOL” colour
coordinates specification below. Then store those values to
6.1 General Alignment Conditions NVM (R/G/B gain value <= 128).
7. Set colour temperature to “WARM”.
Perform all electrical adjustments under the following 8. At FAC mode menu, adjust the CLR TEMP R, CLR TEMP
conditions: G, CLR TEMP B values to meet “WARM” colour
• Power supply voltage: 195 - 264 VAC, 50/ 60 ± 3 Hz. coordinates specification below. Then store those values to
• Connect the set to the mains via an isolation transformer NVM (R/G/B gain value <= 128).
with low internal resistance.
• Allow the set to warm up for approximately 15 minutes. Colour temperature Normal/Warm/Cool (x, y) co-ordinates
• Measure voltages and waveforms in relation to correct specification:
ground.
Caution: It is not allowed to use heatsinks as ground. Table 6-1 Reading with Minolta CA-210
• Test probe: Ri > 10 M:, Ci < 20 pF.
• Use an isolated trimmer/screwdriver to perform
alignments. Picture Mode Cool Normal
Normal (9000K) 0.287 r0.003 0.296 r0.003
Cool (11000K) 0.276 r0.003 0.282 r0.003
6.2 Hardware Alignments
Warm (6500K) 0.313 r0.003 0.329 r0.003
Not applicable.
If you do not have a colour analyser, you can use the default
values. This is the next best solution. The default values are
6.3 YPbPr Mode display adjustment average values coming from production.
• Select a COLOUR TEMPERATURE (e.g. COOL,
6.3.1 General set-up NORMAL, or WARM).
• Set the RED, GREEN and BLUE default values according
Equipment Requirements: to the values in Table 6-2
Minolta CA-110 or Equivalent Colour analyser. Quantum Data • When finished press OK on the RC, then press STORE (in
Pattern Generator 802G, 802BT or equivalent instrument. the SAM root menu) to store the aligned values to the NVM.
• Restore the initial picture settings after the alignments.
Input requirements:
Input Signal Type: YPbPr signal Table 6-2 White tone default settings
• 1080i mode, TVBar100 pattern by 802G or 802BT.
• Select Picture mode to User mode and check the x, y data. Screen Colour temperature
Picture mode size Red Green Blue
Input Signal Strength: Normal 32" 127 124 119
1 Vpp for Y signal; 700 mVpp for Pb & Pr signal
42" 127 126 113
47" 128 128 116
Input Injection Point:
YPbPr (RAC jack) Cool 32" 119 114 127
42" 125 121 127
6.3.2 Alignment method 47" 120 124 128
Warm 32" 127 114 73
Quantum Data Pattern Generator 802G or 802BT. Apply 1080i, 42" 127 118 72
and the pattern TVBAR100 shown as below. 47" 128 122 76
Initial Set-up:
Caution:
1. Select source as “EXT3”.
• Use Minolta CA-210 for colour coordinates and luminance
2. Set Smart Picture mode as “Vivid” and off the “Dynamic
check.
contrast/Dynamic backlight”.
• Luminance > 400 cd/m2 in the centre of the screen when
3. Apply “TVBar100” pattern with colour bar pattern by signal
Brightness/Contrast/Video Contrast setting at 100 and
generator.
CLR_TEMP_R/CLR_TEMP_G/CLR_TEMP_B = 128 for
4. Enter factory mode menu: press numeric keys
32"/42"/47" panels.
“062596” INFO key (FAC mode menu).
2010-Oct-15
EN 22 6. TPM5.1E LA Alignments
Use timing mode and use the POPO (pixel on pixel off) pattern
Input Signal Strength:
to adjust the clock until no stripe and adjust the phase until
clear picture (“Auto” will be done every time switching to PC 0.7 Vp-p linear voltage.
mode and mode change).
Input Injection Point:
PC D-SUB input.
6.4.2 WHITE-D adjustment
Row 4 0 gray
18850_207_100107.eps
100107
Initial Set-up:
1. Select source as “VGA”.
2. Apply “Pixel ON / OFF” pattern by signal generator or use
a factory cone and to enable built-in “Pixel ON / OFF”
pattern, see Figure 6-2.
3. Enter factory mode menu: press numeric keys “062596” +
18290_201_090330.eps INFO key (FAC mode menu).
090416
6.5.3 Alignment
Figure 6-1 Five white blocks pattern
1. At FAC mode menu, select V-COM item. Then press “OK”
Input Signal Strength: key to start adjusting panel flicker. By pressing “<-” or “->”
0.7 Vp-p linear voltage. key on RC to decrease or increase V-COM value, minimize
panel flicker.
Input Injection Point: 2. Once panel flicker is minimal, press “OK” key on RC to
PC D-SUB input. store V-COM value to V-COM IC’s MTP and NVM.
Caution: Please note that P Gamma IC is 100 times-write
6.4.3 Alignment method ONLY. Make sure you get the optimum result before press
“OK” to save the V-COM data.
Initial Set-up:
1. Select source as “PC”. 6.6 Option Settings
2. Set Contrast = 50 (Sharp) and Brightness=50 (Sharp), at
normal menu mode.
6.6.1 Introduction
3. Apply “5 white block” pattern by VGA pattern generator,
see Figure 6-1.
4. Enter factory mode menu: press numeric keys “062596” + The microprocessor communicates with a large number of I2C
INFO key (FAC mode menu). ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
which ICs to address. The presence/absence of these specific
6.4.4 Alignment
ICs (or functions) is made known by the option codes.
Equipment Requirements:
Chroma 2250 or equivalent PC signal generator.
2010-Oct-15
Alignments TPM5.1E LA 6. EN 23
2010-Oct-15
EN 24 7. TPM5.1E LA Circuit Descriptions
7. Circuit Descriptions
Index of this chapter: 7.1.1 Implementation
7.1 Introduction
7.2 Power Architecture Key components of this chassis are:
7.3 T-CON Architecture • TPA3110D2 Audio Amplifier
• NAND128W3A2BN6E NAND Flash
Notes: • TDTW-S810D Tuner
• Only new circuits (circuits that are not published recently) • NT5TU32M16CG-BD DDR Memory
are described. • TPA6132A2RTER Head phone Amplifier
• Figures can deviate slightly from the actual situation, due • TL2428MC T-CON IC
to different set executions.
• For a good understanding of the following circuit 7.1.2 TPM5.1E Architecture Overview
descriptions, please use the wiring, block (see chapter
9. Block Diagrams) and circuit diagrams (see chapter
For details about the chassis block diagrams refer to chapter 9.
10. Circuit Diagrams and PWB Layouts).Where necessary,
Block Diagrams. An overview of the TPM5.1E LA architecture
you will find a separate drawing for clarification. can be found in Figure 7-1.
7.1 Introduction
RF USB 2.0
MPEG2 TS
CI card SPDIF Out
Tuner slot
RC
I2C MT5363H UART (ISP & Factory alignment)
MCU
IFAT +/- (VIF/SIF) Key pad
DTV receiver/demodulator
SCART1 CVBS out
MPEG/video/audio decoder
CVI × 1 SCART2 CVBS out
Scaling
Audio Pre-amplifier SCART1 L/R out
CVBS × 1 (side) Video enhancement DRV603
3D comb
SCART2 L/R out
SCART1 RGB LVDS Transmitter
SCART1 CVBS/YC Audio AMP
HDMI 1.3
TPA3110
speakers
SCART2 CVBS/YC ADC
VGA H.264
HDMI Gamma
DC/DC suites
Side HDMI 12V / V-com
1. Max PF57
Max9668
2. G5657
EDID EDID EDID
24C02 24C02 24C02 Level shifter 3. AP1117E18
TPS65192
System NVM
System NVM
24C64 LVDS
24C64 I2C
18850_211_100222.eps
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2010-Oct-15
Circuit Descriptions TPM5.1E LA 7. EN 25
SERVICE
AUDIO CLASS - D ANALOG I/O CONNECTOR
TUNER
DC/DC
DIGITAL I/O
MT5363H
COMMON INTERFACE
TCON
18850_208_100204.eps
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2010-Oct-15
EN 26 7. TPM5.1E LA Circuit Descriptions
VGH
PANEL VCC(12V)
Q750 SI5441DC PANEL
+12V CMOS
VGL
U702 DV18_DDR
AP1117DL_13
HALF TCON_VDD
TCON_VCC
PANEL_VCC_ON/OFF U7053
TCON_VDD
PF57 U752 DV33 DDR
G1117-33T43Uf
TCON_1V8
U7050
U753 AV12
MP1484
TCON_VDD U411 STMPS2171 G1117T43Uf
-STR power switch
U7054
APM1117E-18LA
TCON_VCC
U602 TAP6132
5.3V HEADPHONE
+5V_STB U751 DV33SB Amplifier
PCMCIA
STB_PWR5V LC Circuit G1117-33T63Uf CI2_VCC
U750 AV33
G1117 -33T43UF MT5363
Q704 SI5441DC
switvh +5V_SW
DV11
STAND BY Jumper
OPWRSW
DC to DC Main Chip Audio Other chip
18850_209_100204.eps
100210
All power supplies are a black box for Service. When defective,
a new board must be ordered and the defective one must be
returned, unless the main fuse of the board is broken. Always
replace a defective fuse with one with the correct
specifications! This part is available in the regular market.
Consult the Service website for the order codes of the boards.
2010-Oct-15
Circuit Descriptions TPM5.1E LA 7. EN 27
U7051
GAMMA
I2C Gamma / V-con
Gamma / V-con
MAX9668ETP
MAX9668ETP
VCOM
I2C
TCON NVM
TCON NVM
24C32
24C32
U7001
18850_210_100204.eps
100210
The T-CON section includes the T-CON IC, a Level shift IC, a
DC to DC conversion IC and a correction Gamma IC. The
T-CON IC will transform the LVDS signal into a mini-LVDS
signal with a 6 pairs Level shifter IC. This is a 9 channel
level-shifter intended for use in LCD display applications such
as TVs and monitors. The device converts the logic-level
signals generated by the Timing Controller (T-CON) to the
high-level signals used by the display panel. The gamma IC
outputs eight voltage references for gamma correction in TFT
LCDs and one voltage reference for VCOM. Each gamma
reference voltage has its own 10-bit digital-to-analog converter
(DAC) and buffer to ensure a stable voltage. The VCOM
reference voltage has its own 10-bit DAC and an amplifier to
ensure a stable voltage when critical levels and patterns are
displayed. The DC to DC IC multiple-output power-supply
controller generates all the supply rails for thin-film transistor
(TFT) liquid-crystal display (LCD) panels in TVs and monitors
operating from a regulated 12 V input. It includes a step-down
and a step-up regulator, a positive and a negative charge
pump, a dual-mode logic controlled high-voltage switch control
block, and an adjustable timing power-good output. The
positive and negative charge-pump regulators provide the TFT
gate driver supply voltages.
2010-Oct-15
EN 28 8. TPM5.1E LA IC Data Sheets
8. IC Data Sheets
This section shows the internal block diagrams and pin
configurations of ICs that are drawn as “black boxes” in the
electrical diagrams (with the exception of “memory” and “logic”
ICs).
8.1 Diagram B04 SSB: MT5363 By-pass/Trap, MT5363LICG BGA-522 (IC U401)
Block diagram
CVBS/ HDMI Audio
YC Input Rx Input Panel CVBS
Audio DAC BScan PVR RTC UART MS,SD PWM NAND Flash
SPDIF, I2S
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2010-Oct-15
IC Data Sheets TPM5.1E LA 8. EN 29
Pinning information
LT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
B VCC2IO RCLK0 RDQ8 RDQS1 RDQS0 RDQ11 VCC2IO AO0N AO2N AO3N
D RA9 VCC2IO RDQ5 RDQ0 DVSS RDQ9 VCC2IO AO0P AO2P AO3P
F RA5 AVDD33_L
RA7 VCC2IO RDQ7 DVSS RDQ6 VCC2IO AE1N AECKN
VDS
AVDD33_L
H RBA2 RBA0 RA1 VCC2IO RDQ1 RDQ4 AE1P AECKP
VDS
J AVSS33_L
RBA1 DVSS DVSS VCC2IO
VDS
AVSS12_M
T RDQ19 RDQ20 RDQ30 RDQ25 DVSS DVSS DVSS
EMPLL
AVSS33_U AVSS33_U
AT POCE0_ POWE_ PARB_ PDD5 RX2_0B RX2_2B RX1_0B RX1_2B
SB SB
AV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
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2010-Oct-15
EN 30 8. TPM5.1E LA IC Data Sheets
Pinning information
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 RT
CI_MOSTR
AE4N GPIO33 GPIO24 GPIO16 GPIO8 ETPHYCLK CI_MCLKO CI_MCLKI F
T
TUNER_DA TUNER_CL
DVSS VCCK VCCK AOSDATA4 N
TA K
AVDD33_A VCXO T
DVSS DVSS VCCK OPWM2 U1TX
DAC1
AVSS33_A U
DVSS DVSS DVSS AL1 AR2 AR3
DAC1
AIN0_L_AA AIN2_L_AA
DVSS DVSS DVSS AD
DC DC
AVSS33_A
VCCK VCCK DVSS AR0 AE
DAC0
AVDD12_T AVDD33_
AVICM AL0 AF
VDPLL ADAC0
VDAC_OUT TUNER_BY
U0TX SOG SOY1 PR1P PB0P SY0 CVBS2P
1 AP
PASS
AVSS33_V AVSS33_C
OPCTRL3 HSYNC COM COM1 Y0P SY1 CVBS0N AR
DAC VBS
VDAC_OUT
U0RX BP RP PB1P COM0 SC0 CVBS3P CVBS0P AT
2
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 RB
18850_302_100107.eps
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2010-Oct-15
IC Data Sheets TPM5.1E LA 8. EN 31
8.2 Diagram B14 SSB: T-CON power, PF57 TQFN-40 (IC U7053)
Block diagram
VIN
(12V)
BST LX1
VL
IN2
3.3V
STEP-
2A STEP- UP
LX2 DOWN PGND
OSC
FB1
COMP 100k
330pF
GND2 AGND
FSEL VL
OUT
SWI
FB2
P
150
mV AVDD
SWO
VIN VIN 16V
3.3V 1.5A
VL VL
VL
PGOOD
RESET PGOOD
REF REF CRST
REF
AGND
DRN
Step-down, Negative
ON/OFF EN1
SEQUENCE
POWER-UP
DRVP
VGOFF NEGATIVE POSITIVE
DRVN
REG
-6V REG
100mA CPGND
CPGND FBN FBP
AVDD
REF
Pinning information
PGOOD
AGND
COMP
PGND
CRST
SWO
SWI
FB1
LX1
LX1
40 39 38 37 36 35 34 33 32 31
THR 1 30 PGND
DRVP 2 29 EN2
GND2 3 28 VL
SRC 4 27 DEL2
GON 5 26 EN1
DRN 6 25 FSEL
MODE 7 24 VIN
DLP 8 23 IN2
FBP 9 22 IN2
CPGND 10 21 OUT
11 12 13 14 15 16 17 18 19 20
DEL1
FB2
LX2
BST
LX2
CTL
AGND
REF
DRVN
FBN
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2010-Oct-15
EN 32 8. TPM5.1E LA IC Data Sheets
8.3 Diagram B06 SSB: DDR2 memory, NT5TU32M16CG-BD (IC U402, U403)
10000_090121_038.eps
CKE
CK
CK
CS
Command
Control Logic
Decode
WE
CAS
RAS Bank3
Bank2
AP Bank1 CK, CK
Row-Address MUX
DLL
Row-Address Latch
Mode
15
& Decoder
Registers
Bank0
13 8192 Bank0
Memory Data
Read Latch
Drivers
15 Array
(8192 x 256 x 64) 16
64 16 16
13
MUX
Sense Amplifiers 16
16 DQS 1
Refresh Counter
16384
Generator
Bank Control Logic
DQS LDQ0-LDQ7
Address Register
Receivers
UDQS
Column
Decoder 16 16
8 16 16
Column-Address 64 16
10 16 16
Counter/Latch COL0 Data
2 16 16
CK,
CK
COL0,1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation
of the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the
bidirectional DQ and DQS signals.
Pinning information
× 16
1 2 3 7 8 9
A10/AP A1 M A2 A0 VDD
VSS A3 A5 N A6 A4
A7 A9 P A11 A8 VSS
VDD A12 NC R NC NC
18291_300_090609.eps
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2010-Oct-15
IC Data Sheets TPM5.1E LA 8. EN 33
8.4 Diagram B12 SSB: Audio Amp/Headphone out, TPA6132A2RTER 25mW QFN-16 (IC U602)
Block diagram
VDD
HPVDD
Supply 2.2 F
Control
PGND
HPVDD
INL- Resistor
–
Array + OUTL
INL+
Short-Circuit
HPVSS Protection
Thermal
HPVDD Protection
–
INR-
Resistor
Array + OUTR
INR+
HPVSS HPVDD
CPP
G0 Charge 1 F
Gain Click-and-Pop
Suppression Pump
Select
G1
CPN
HPVSS
1 F
SGND EN
Pinning information
SGND
OUTL
VDD
EN
16
15
14
13
INL- 1 12 HPVDD
INL+ 2 11 CPP
INR+ 3 10 PGND
INR- 4 9 CPN
7
6
8
5
OUTR
G0
G1
HPVSS
18850_304_100107.eps
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2010-Oct-15
EN 34 8. TPM5.1E LA IC Data Sheets
8.5 Diagram B15 SSB: T-CON main chip, TL2428MC LQPF-176 (IC U7000)
Frame Memory
SDRAM
Gate Gate in
(16Mbit)
Driver panel
2 2
TFT LCD ARRAY
SDA
SCL
EEPROM
Gate Gate in
(LUT)
Driver panel
16Kbit
n n
or 32Kbit
Pinning information
RMLVDS
GIP_EN
MPVDD
MPVDD
MLVDD
MLVDD
MLVDD
MLVDD
MLVDD
MPVSS
MPVSS
MLVSS
MLVSS
MLVSS
MLVSS
MLVSS
RLV0+
RLV1+
RLV2+
RLV5+
RLV3+
RLV4+
RLV6+
LLV2+
LLV0+
LLV4+
LLV6+
LLV1+
LLV3+
LLV5+
RLV0-
RLV2-
RLV4-
RLV3-
RLV5-
RLV1-
RLV6-
LLV0-
LLV2-
LLV4-
LLV6-
LLV1-
LLV3-
LLV5-
129
128
127
123
122
121
117
116
115
111
110
109
105
104
103
132
131
130
126
125
124
120
119
118
114
113
112
108
107
106
102
101
100
99
94
93
98
97
96
95
92
91
90
89
16
22
28
34
39
40
12
13
14
15
17
18
19
20
21
23
24
25
26
27
29
30
31
32
33
35
36
37
38
41
42
43
44
1
2
3
4
5
6
7
8
9
OGND
OVDD
PWM_TIN
PWM_TOUT
OPC_EN
CVDD
CGND
LGND
LVDD
R1AM
R1AP
R1BM
R1BP
LVDD
R1CM
R1CP
R1CLKM
R1CLKP
LGND
R1DM
R1DP
R1EM
R1EP
R2AM
R2AP
R2BM
R2BP
LVDD
R2CM
R2CP
R2CLKM
R2CLKP
LGND
R2DM
R2DP
R2EM
R2EP
CGND
CVDD
BIT_SEL
FSEL
RBF
OVDD
OGND
18850_305_100107.eps
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2010-Oct-15
IC Data Sheets TPM5.1E LA 8. EN 35
8.6 Diagram B14 SSB: T-CON power, TPS65192RHDR QFN-28 (IC U7052)
Block diagram
FLK1
FLK2
VGH1 FLK3
RE
IN1 OUT1
IN2 OUT2
IN3 OUT3
IN4 OUT4
IN5 OUT5
IN6 OUT6
IN7 OUT7
VSENSE -
DISCHARGE
V REF +
GND VGL
VGH2
IN8 OUT8
IN9 OUT9
Pinning information
D IS C H A R G E
V S E NS E
FLK 1
FLK 2
FLK 3
G ND
RE
25
28
26
27
24
23
22
IN9 1 21 OUT9
IN8 2 20 OUT8
IN7 3 19 OUT7
IN6 4
Exposed 18 OUT6
IN5 5 17 OUT5
IN4 6 16 OUT4
IN3 7 15 OUT3
12
11
13
14
10
8
V G H1
OUT 1
IN 1
IN 2
V G H2
OUT 2
VGL
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2010-Oct-15
EN 36 8. TPM5.1E LA IC Data Sheets
8.7 Diagram B14 SSB: T-CON power, MAX9668ETP+ TQFN-EP-20 (IC U7051)
Block diagram
AVDD
10 10 10-BIT
GMA1
DAC
10 10 10-BIT
GMA2
DAC
10 10 10-BIT
GMA3
DAC
10 10 10-BIT
GMA4
DAC
MTP I2C '$&
MEMORY REGISTERS10 REGISTERS
10 10-BIT
GMA5
DAC
10 10 10-BIT
GMA6
DAC
10 10 10-BIT
GMA7
DAC
10 10 10-BIT
GMA8
DAC
10 10 10-BIT AVDD_AMP
DAC
VCOM
VCOM_FB
DVDD GND_AMP
SDA
I2C
SCL
INTERFACE MAX9668
A0
GND
Pinning information
GMA6
GMA5
GMA4
GMA3
GMA2
15 14 13 12 11
AVDD 16 10 GMA1
N.C. 17 9 N.C.
MAX9668
GMA7 18 8 AVDD
GMA8 19 7 AVDD_AMP
EP*
SCL 20 + 6 VCOM_FB
1 2 3 4 5
DVDD
VCOM
SDA
AGND_AMP
A0
18850_307_100107.eps
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2010-Oct-15
Block Diagrams TPM5.1E LA 9. EN 37
9. Block Diagrams
Wiring Diagram 32"
WIRING DIAGRAM 32" (Dali)
CN902
2. ROUT+
1. ENA
4. LOUT+
HIGH VOLTAGE
CN601
1. ROUT-
3. LOUT-
DANGEROUS
CN803 2. DIM
1. HV2 3. +12V
4. +12V
2. N.C. 5. GND
3. HV2 6. GND
7. GND CN401
8. +24V 9. KEY2
9. +24V 8. KEY1
10. S/B
HIGH VOLTAGE
7. GND
DANGEROUS
2. LED_G
1. LED_R
CN701
13. LED_ON
12. STB_PWR5V
11. STB_PWR5V
10. STANDBY
9. +24V
8. +24V
MAIN POWER SUPPLY 7. GND
SSB
A (1054)
6. GND
5. GND B (1053)
4. +12V
3. +12V
(1057)
2. BRIGHT_ADJ
1. INVERTER_ON_OFF
CN7050
1. GND
2. GMA1
3. GMA3
87050
3. CLK1_TCON
4. GMA4
5. GMA6
CN7051
6. GMA7
2. Z_OUT
60. GND
4. CLK2
5. CLK3
6. CLK4
7. CLK5
8. CLK6
1. GND
7. GMA9
CN1
8. GMA10
1. N
2. L
...
...
60. GND
TO
BACKLIGHT 87051
8001
8401
2010-Oct-15
Block Diagrams TPM5.1E LA 9. EN 38
CN903
1. ENA
HIGH VOLTAGE
DANGEROUS
CN803 2. DIM
1. HV2 3. +12V
4. +12V
2. N.C. 5. GND
3. HV2 6. GND
2. ROUT+
4. LOUT+
CN601
1. ROUT-
3. LOUT-
7. GND
8. +24V
9. +24V
10. S/B
HIGH VOLTAGE
DANGEROUS
5. DV33SB
4. GND
3. RC6
2. LED_G
1. LED_R
CN701
13. LED_ON
MAIN POWER SUPPLY
A (1054)
12. STB_PWR5V
11. STB_PWR5V
10. STANDBY
9. +24V
8. +24V
7. GND
SSB
6. GND
B
(1057)
5. GND (1053)
4. +12V
3. +12V
2. BRIGHT_ADJ
1. INVERTER_ON_OFF
87051
CN7050
1. GND
2. GMA1
3. GMA3
CN1
1. N
4. GMA4
2. L
87050 5. GMA6
3. CLK1_TCON
6. GMA7
CN7051
7. GMA9
2. Z_OUT
60. GND
8. GMA10
4. CLK2
5. CLK3
6. CLK4
7. CLK5
8. CLK6
1. GND
...
TO 60. GND
...
BACKLIGHT
8001
8401
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2010-Oct-15
Block Diagrams TPM5.1E LA 9. EN 39
CN903
1. ENA
HIGH VOLTAGE
DANGEROUS
CN803 2. DIM
1. HV2 3. +12V
4. +12V
2. N.C. 5. GND
3. HV2 6. GND
KEYBOARD CONTROL PANEL
7. GND
8. +24V
9. +24V
10. S/B
HIGH VOLTAGE
DANGEROUS
4. LOUT+
CN601
1. ROUT-
3. LOUT-
(1057)
CN401
9. KEY2
8. KEY1
7. GND
6. DV33SB
5. DV33SB
4. GND
3. RC6
2. LED_G
1. LED_R
CN701
13. LED_ON
12. STB_PWR5V
11. STB_PWR5V
10. STANDBY
CN1
9. +24V
1. N
2. L
8. +24V
7. GND
6. GND
5. GND
4. +12V
3. +12V
2. BRIGHT_ADJ
1. INVERTER_ON_OFF
87051
CN7050
1. GND
2. GMA1
B SSB
3. GMA3
4. GMA4
5. GMA6
(1053)
87050 6. GMA7
7. GMA9
8. GMA10
...
60. GND
CN7051
1. GND
2. Z_OUT
3. CLK1_TCON
4. CLK2
5. CLK3
6. CLK4
7. CLK5
8. CLK6
8401 ...
60. GND
IR/LED BOARD
(1056) CN001
4P
CN301
7P J RIGHT SPEAKER LCD DISPLAY LEFT SPEAKER
18850_402_100506.eps
100506
2010-Oct-15
Block Diagrams TPM5.1E LA 9. EN 40
Block Diagram
RF USB 2.0
MPEG2 TS
CI card SPDIF Out
Tuner slot
RC
I2C MT5363H UART (ISP & Factory alignment)
MCU
IFAT +/- (VIF/SIF) Key pad
DTV receiver/demodulator
SCART1 CVBS out
MPEG/video/audio decoder
CVI × 1 SCART2 CVBS out
Scaling
Audio Pre-amplifier SCART1 L/R out
CVBS × 1 (side) Video enhancement DRV603
3D comb
SCART2 L/R out
SCART1 RGB LVDS Transmitter
SCART1 CVBS/YC Audio AMP
HDMI 1.3
TPA3110
speakers
SCART2 CVBS/YC ADC
VGA H.264
HDMI Gamma
DC/DC suites
Side HDMI 12V / V-com
1. Max PF57
Max9668
2. G5657
EDID EDID EDID
24C02 24C02 24C02 Level shifter 3. AP1117E18
TPS65192
System NVM
System NVM
24C64 LVDS
24C64 I2C
2010-Oct-15
Circuit Diagrams and PWB Layouts TPM5.1E LA 10. EN 41
!
1
0.0022uF/500V
31DF6
1
100K_NC
C924
PBHV9040T_NC
P6KE200A 1
4
8
7
6
2
Q911
1.5NF/1KV
0R
7
1 8 R930
2
D910 100 OHM 100 OHM
R954 R955 R956 R931
HER303G-18
3
1
R973
3.3M_NC
Q905 2 24V
BC857C D909 L903
FB904 1M 1/4W 1% 1M 1/4W 1% UF1007 9 + 0.8uH + C927
BEAD 1MOHM +-1% 1/4W R974 C926 R934 47uF/50V
18.7K 620R 1/8W 1%
10 R932
R957
HQ904
R917
2
0.01uF
560PF 5 C928
C919
2
330P 50V
3.3M_NC
C917
1.5K 1/4W
2 12
R958
R920
330N 50V
BZX79-B18 + 100 OHM 1/4W
47UF 50V_NC
C948
C920
Q904 6 1 2 12V
1
1
IC909 FMV11N60ES Q910 L904
1
33K_NC
R964 3 6 R922
CS VCC
C944
R923
R921 C906 D1 C907 A3 C908 D1 C909 A1
1
1
B 33K MTZJ T-72 3.3B_NC C918 B4 C919 A3 C920 B4 C921 B3 B
! R924
! C922 B4
C926 A5
C923 B3 C924 A4 C925 A5
C927 A5 C928 A5 C929 B5
2
1
TS4B06G C945 0R15 1W 1%
C942 A1 C943 B1 C944 B1 C945 B1
+
10N 50V
RGP10D
2
2
1U 25V
C922
22uF/50V
RGP10D
3 2 C931 22nF25V
Q904 B2 Q905 A4 Q907 C5 Q909 E4
R967 R939 Q910 B2 Q911 A3 Q912 C2 RV901 E1
1
MTZJT-7213B
22K 1/8W
22R 1/6W 5%
R914
FB901 FB902
220R 1/8W 5%
! !
R968
C949
C932
1
D915
3 4 0.0022uF/500V
2
! !
Q912 1 BF-L25030W-768 R941
2
1 0.8uH
1M 1/8W 5%
10 2 +5VSB
C901 C902 3
D905 3
R970
12K
BZX79-C15
ZD903
TNY274PN-TL
4
R949 R945
D
R901 1M2 5% 1/2W_NC ! 5 4 IC906 3.3K 12K 1/8W 1%
D
1
S D EL817MA
6 S
7 2
3
S BP/M
! 8 S EN/UV 1
!
2
C935
BZX79-C9V1
3 4 KIA431A-AT/P R947
10K5 1/8W 1%
1
C906
0.47uF/275V
!
1
R910 CN902
! 15K OHM 2W HOT COLD
FB905
BEAD ! R906 D902 1 ENA
Q902
BC857C
C910 1K 1/4W 5% 4
1500pF Q909 5 C940
2
0.1uF
BZX79-C9V1
3 1 1 2
11
12 +5VSB
715G3816-P01
4
F901
2 13
14 INV_OK
C941
0.1uF
32" LIPS
T5.0AH 250V CN901
SOCKET
1 2 3 4 5
18850_504_100107.eps
100107
2010-Oct-15
Circuit Diagrams and PWB Layouts TPM5.1E LA 10. EN 42
Inverter 32"
1 2 3 4 5
5
CN802 C4 CN803 A3 C801 A2 C802 B2
CN803 C803 A2 C804 B2 C805 A4 C806 A3
B+ ! 3
2
CONN C807 A3
C811 A1
C808 C3 C809 C3 C810 C4
C812 A1 C813 B1 C814 B1
1 C815 B1 C816 B1 C817 E3 C819 C1
C803 C821 D3 C823 B1 C824 E2 C825 C4
10nF C826 A3 C827 B4 C828 C3 C829 D4
A A A
C807 C830 E4 C831 D4 C832 C5 C833 C2
4
15pF/6KV C834 D2 D801 A4 D802 C4 D803 C4
R801 C805 D804 D5 D805 E5 D806 E3 IC801 A1
INVERTER IC801 22R 1/8W 5% Q801
FQPF8N60C
470P 50V IC803 C2 IC804 C2 IC805 D2 IC806 E2
1 IFB GH 24 Q801 A2 Q802 B2 Q803 D4 Q804 D4
3
C826
C811 2 CIFB FS 23 C801 6 ! C806 100P 50V_NC
Q805 E4
Q809 C4
Q806 B2 Q807 D2 Q808 E2
Q810 C2 Q811 C2 R801 A2
15N 50V 100N 50V R834 1 T803 D801
R802 B2 R803 B4 R804 B2 R805 E3
3 22 10K 1/8W 1% TRF-UU28 1N2 50V BAV99
VFB SH R806 B1 R807 C1 R808 B2 R809 C1
R810 B1 R811 B2 R812 C2 R813 C2
C812 4 21 2 5
2
220N 50V CVFB NC R814 D2 R815 E2 R816 E2 R817 E2
C813 R802 R818 E2 R819 C5 R820 D3 R821 C4
5 CSWP NC 20
2N7 50V 22R 1/8W 5% Q802 R822 B3 R823 B3 R824 D2 R825 B3
3 8
C814 FQPF8N60C C827 R826 D3 R827 B1 R828 D5 R829 E5
6 CT NC 19
220N 50V 22N 50V R830 D4 R831 E4 R832 D4 R834 A2
C815 7 18 4 R835 B2 R836 C5 R837 C3 R838 C2
56P 50V CF GL
R835 7
R806 33K 1/8W 1% 8 17 10K 1/8W 1% R803
IREF PGND C802 68K 1/8W 1%
R810 Vdd 330NF 450V
B 9 CPWM VDD 16 T801 B
0 OHM +-5% 1/8W 4 3 D
10 15 C804 2U2 25V
24R 1/8W 1%
R823
56P 50V 6 1
C823 NF 12 13 R804
N,FAULT PWMd 470R 1/8W 1%
470P 50V
TRF-UU9.8 C
UBA2071
2
100K 1/8W 1%
R827
100K 1/8W 1%
MTZJT-7213B Vdd-S
R808
2
1
HOT COLD
1
C819 3 R819
100N 50V C808 BAV99 Q809 390KOHM +-5% 1/4W_NC
R809 ! 12V
1N2 50V C828 D802 1 KIA431A-AT/P
4
32
3 CONN
IC804 R813 2
EL817MA 2K7 1/8W 1% 1
3
3 2
R838
10K 1/8W 1% 12V
4
1 C
DIM
Q811 C834
2
R814 R832
2K7 1/8W 1% 10K 1/6W 5%
12V
4
Q803
D
! IC805 RK7002 D
EL817MA
R828
D804
3
! R817
2K7 1/8W 1%
D806
C830
R831
56K 1/8W +/-1% 1N4148
R816 2 100N 50V
47K 1/8W 1% IC806 C817
3
EL817MA 3 D
E E
1 56P 50V
Q808 R805
KIA431A-AT/P 330K 1/8W 1%
BAV99
R815 R818
3K6 1/8W 1% C824 150K 1/8W +/-1%
10N 50V
1 2 3 4 5
18850_525_100107.eps
100107
2010-Oct-15
Circuit Diagrams and PWB Layouts TPM5.1E LA 10. EN 43
D804
Q808
D805
CN803 J912 IC806
J922
Q801
IC805
R824
IC803
J901
Q809 Q807
T803
R832
Q802
J921
J919
J904
J905
ZD907
ZD801
C930
IC804 IC904
R967
C803
C949 D916 J906 ZD906
CN802
J918
IC903
L904
CN902
C928
C809
C924
T901
R953
C920 D908 D910 L903
J930
C925 C927
ZD905
Q901
J910
R925
J913
D906 C926
ZD909 IC905
J909
C921 J920
C905
D913 ZD904
C947 C911
D905 HD912 L905
D912
J931
J928
J926
J925
FB903
D917 C934
J915
Q904
IC901
ZD903
T902 C932
D914
D904 C933
L906
J927
J908
ZD910
J907
J929
IC906
R966FB906
J911
ZD912
R915
IC907
R916 C912 C904
ZD908
R909
J916
D902
C938
J903
ZD902 FB905
R956
TH901
C906
L901 F901
RV901
R910
C907 C910 L902
R901
C908
FB901
J902
C909
BD901FB902
CN901
C950
C902
C901
FB904 C903
y18850_526_100107.eps
100308
2010-Oct-15
Circuit Diagrams and PWB Layouts TPM5.1E LA 10. EN 44
C810
C808 C817 R822
C828 R818
R805
R828
D806
C825 C806 C827 C824
C805
R830
R821 C826 R803
C829
D803 D801 D802
Q804
C821 Q803 R825 C811 R801
C812
R834
R816
R826
R819
C813
R836 IC801
R815
C814
R829
C830
C831
R802
R810
C816
C823
C833
R827
R835
RJ904
R809
R838
C834 D915 C804
R936 LED901
Q806
C940
Q811
R969
R968
R939
C931
R938
RJ903
C939
R937
R940
R970
C918
R933
R932
R920
R919
R924 IC902
C923
R942
C936
R921
D907
C917
R922
Q905
C916
Q907 R941
R943
C945 R965
R918
R962
R911
C914
C913 IC909 R960
R959
C944
R914 R907
R949
R961
R945 C942
R963
R947
Q903 R954
R948 R950
R955
R976
Q910 R975
R972
R974
R971
Q911
R906
R973
C937
Q909
18850_527_100107.eps
100107
2010-Oct-15
Circuit Diagrams and PWB Layouts TPM5.1E LA 10. EN 45
! C910 G3 C911 A2
1
82K OHM 1W
0.0022uF/500V
1 C914 D4 C915 D6
270PF 1KV
R910
C911 +
PBHV9040T_NC
R923
C921
R931 1
5
270PF 1KV_NC
100 OHM 1/4W 10
R939
C919
B MTZJ T-72 16B 22K 1/8W 5% + D921 B
4.7K 1/8W
22uF 50V_NC
2 7 1 C949 E7 C950 E7
Comp Driver
R932
C917
C927
R916 1 2 HQ903 6 C951 E9 C952 F8
0.01uF
Mult GND
1
C912
C928
C925
1U 25V
1
BEAD SG6961 22K OHM 1/8W 330P 50V_NC
1uF/25V_NC
! ! D904 G3 D910 B4
39K 1/8W
R914
Q903
10K 1/8W
R919 2 FQPF3N80C
FB D922 A8 D923 B7
0.22OHM 2W 3 6 R915
CS VCC 0.001uF/250V D926 G10 D927 G9
150PF 1KV
C955 C954 4 5 47R 1/6W 5%
GND DRV FB901 B1 FB902 F1
C936
33P 50V R906 470P 50V R927
! 3M3 1/4W_NC D913
1N4148 10 OHM FB903 F2 FB904 C1
1
C 1K 1/4W 1R2 5% 2W C
C918
IC907 F6 IC908 G7
1
FB904 FB906
PMBTA45_NC ! R958
LED902 G9 L901 E1
L902 D1 L907 E8
4
1
4K7 +-5% 1/8W Q902 B4 Q903 C7
IC903 Q905 B6 Q907 D4
2
1N5 50V
C915
1U 25V
R911 A2 R912 B6
1
R927 C7 R928 C7
EL817MA R929 B4 R930 C7
C901 C902 IC904 R931 A5 R932 B5
470pF/250V 470pF/250V C914 R934 G3 R935 A9
3
R959
1
15K 1/8W 4
t
1
5
F 6 F
ZD912 TNY277PN-TL
2
FB903 BZX79-C9V1 7
BEAD 5 4 ZD908 8
!
1
S D MTZJ15B
1
6 R953 24V 9
1
BEAD +5VSB 12
2
330N 25V
G
BZX79-C9V1 G
LED902 R974
1
HOT COLD
2
2
t
1 2 + C958
R934 TH903 10UF/50V
15K 5% 3W PTC R946 Q920
1K 1/8W RK7002
Q918
PMBTA45
R948 D926
2.2K R976
1M 1/8W 5% BAV21P
H H
1 2 3 4 5 6 7 8 9 10 11
18850_500_100107.eps
100107
2010-Oct-15
Circuit Diagrams and PWB Layouts TPM5.1E LA 10. EN 46
A
1
COLD C801 B4
C803 B4
C805 B8
C802 C6
C804 C4
C806 B7
A
2 6 C807 B7 C808 D7
C809 D7 C810 D8
C811 B2 C812 B2
3 7 C813 B2 C814 C2
C815 C2 C816 C2
C817 F7 C818 B2
4 C819 D4 C821 E6
5
HQ801 8 C823 C2 C824 F5
CN803 C825 B7 C826 D7
395V
3 CONN C827 C8 C828 D8
2 C829 G6 C830 F3
C803 1
10nF NC
C831 D5 C832 E5
R805 T803
! D806 F6 D807 B8
2
2
4
C818 Q801 1 C807
47N 50V IC801 10 OHM +-5% 1/8W 15PF 6KV IC803 D5 IC804 D5
1 AOTF10N60
B R801 IC805 E5 IC806 F5 B
1 IFB GH 24 IC808 F5 IC809 G6
2 6 VS1 C805
3
3
Q801 B5 Q802 B5
470P 25V_NC
3 VFB SH 22 3 7
Q806 C5 Q808 D5
2
C825
220N 50V 4 1.8NF 50V BAV99
C813 5 20 Q802 8 R805 B3 R806 C2
4N7 50V CSWP NC AOTF10N60 C827 R807 D4 R808 C4
1
2
C814 6 19 R809 D4 R810 C2
220N 50V CT NC R802 C802 R811 C4 R812 D5
3
12V
4
C819 D808 3
IC803 C808
330P_NC
1K 1/4W 5% BAV99
EL817MA
C826
32
D D
10N 50V
R807 R835
100K C809
15PF 6KV C828
12V
2
32
PMBS3904 R813 1
1
1 470R
DIM
JR902 C832
0 OHM 1/4W 10N 50V
2
12V
4
R827
IC805 1K
E ! EL817MA
E
3
R824
10K 1/6W IC810 R826
KIA431A-AT/P 330K 1/8W 1%_NC
R820 C821
30K 1/8W 1%
1U 25V
R814
470R
12V
4
R816
47K ! IC806
EL817MA
3
F F
IC808 R819
KIA431A-AT/P 390K 1/6W 5%
1
C830 R815
1N 50V_NC 5K6 1/8W 5% C824 R818 C817
100N 50V
30K 1/8W 1%
J919 56P 50V COLD HOT
3
D806
2
BAV99 R830
330K 1/8W 1%
IC809
KIA431A-AT/P
2
H H
1 2 3 4 5 6 7 8 9 10 11
18850_501_100107.eps
100308
2010-Oct-15
Circuit Diagrams and PWB Layouts TPM5.1E LA 10. EN 47
R819 IC808
C807
J938
J929
J937
IC809
J930
T801 J902
J936 IC810
J926
J927
Q801 IC806 C958
J934
CN803
J935
IC921
R824 IC805
R809
ZD925
T802
T803 IC803 C937 CN903
J933
R828
R835
J924
IC804
L922
J940