VLSI Design

Lecture 19: Memory and Data

path

Shaahin Hessabi
Department of Computer Engineering
Sharif University of Technology
Adapted, with modifications, from lecture notes
prepared by the author (from Prentice Hall PTR)
 Topics
™ Memories:
¾ ROM;
¾ SRAM;
¾ DRAM.
™ Datapaths.
™ PLAs.

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High-density memory architecture
™ Address is divided into
row, column.
¾ Row may contain full word
or more than one word.
™ Selected row
drives/senses bit lines in
columns.
™ Amplifiers/drivers
read/write bit lines.

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 Read-only memory (ROM)
™ ROM core is organized as NOR gates
¾ pulldown transistors of NOR determine programming.
™ Erasable ROMs require special processing that
is not typically available.
™ ROMs on digital ICs are generally mask-
programmed
¾ placement of pulldowns determines ROM contents.

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 ROM core circuit

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 Static RAM (SRAM)
™ Core cell uses six-transistor circuit to store
value.
™ Value is stored symmetrically: both true and
complement are stored on cross-coupled
transistors.
™ SRAM retains value as long as power is applied
to circuit.

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 SRAM core cell

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 SRAM core operation
™ Read:
¾ precharge bit and bit’ high (the two PMOS transistors
for precharge not shown: source=VDD, drain=bit/bit’,
gate=precharge’);
¾ set select line high from row decoder;
¾ one bit line will be pulled down.
™ Write:
¾ set bit/bit’ to desired (complementary) values;
¾ set select line high;
¾ drive on bit lines will flip state (charge sharing) if
necessary.

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 SRAM sense amplifier
™ Differential pair: takes
advantage of complementarity
of bit lines.
™ When one bit line goes low,
that arm of differential pair
reduces its current, causing
compensating increase in
current in other arm.
™ Sense amplifier can be cross-coupled to increase
speed.

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 3-Transistor Dynamic RAM (DRAM)
™ First form of DRAM
¾ modern commercial
DRAMs use one-transistor
cell (requires poly-poly).
™ 3-transistor cell can easily
be made with a digital
process.
™ Dynamic RAM loses
value due to charge
leakage
¾ must be refreshed.

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 3-T DRAM operation
™ Value is stored on gate capacitance
of t1.
™ Read:
¾ read = 1, write = 0, read_data’ is
precharged;
¾ t1 will pull down read_data’ if 1 is stored.
™ Write:
¾ read = 0, write = 1, write_data = value;
¾ guard transistor writes value onto gate
capacitance.

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 Data paths
™ A data path is a logical and a physical structure:
¾ bitwise logical organization;
¾ bitwise physical design.
™ Datapath often has ALU, registers, some other
function units.
™ Data is generally passed via busses.

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 Typical data path structure
Slice includes one bit of function units, connected
by busses:

bus
registers shift ALU

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 Bit-slice structure
™ Many arithmetic and logical functions can be
defined recursively on bits of word.
™ A bit-slice is a one-bit (or n-bit) segment of an
operation of minimum size to ensure regularity.
™ Regular logical structure allows regular physical
structure.

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 Abutting and pitch-matching
™ Cells in bit-slice may be abutted together
¾ requires matching positions on terminals.
™ Pitch-matching is designing cells to ensure that
pins are at proper positions for abutting.

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 Wiring plans
™ A wiring plan shows layer assignments and
directions for major signals.
™ Put most important signals on lowest-impedance
accessible layers.

VDD

VSS
cell1 cell2 cell3

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 Bus circuits
™ Cannot support full connectivity between all data
path elements
¾ must choose number of transfers per cycle allowed.
™ A bus circuit is a specialized multiplexer circuit.
™ Two major choices:
¾ pseudo-nMOS,
¾ precharged.

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 Pseudo-nMOS bus circuit

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 Precharged bus circuit

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 Programmable logic array (PLA)
™ Used to implement specialized logic functions.
™ A PLA decodes only some addresses (input
values); a ROM decodes all addresses.
™ PLA not as common in CMOS as in NMOS, but
is used for some logic functions.

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 PLA organization and structure
™ AND plane, OR plane, inverters together form
complete two-level logic functions.
™ Both AND and OR planes p1
are implemented as NOR p2
circuits. AND plane p3 OR plane
™ Pulldown transistors form p4
programming (personality)
of PLA. Transistors may
i0 i0’ i1 i1’ f0 f1
be referred to as
programming tabs. product term

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 PLA AND/OR cell

input 1 input 2
programming
output 1 tab

output 2
no tab

VSS

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