Retiming: Sequential digital circuit optimization

Theerayod Wiangtong
25/01/05
Introduction

Synchronous Digital Circuits

arrival time si T arrival time sj

register i combinational logic with register j

propagation delay x
Approaches to synchronous logic
optimization

• Optimize combinational logic only.

• Optimize register position only:
– Retiming.
• Optimize overall circuit:
– Peripheral retiming.
Example: Minimize delay

si = sj A 5 B
5
j
i

D 6 12 C

23

A B C D
max 5 5 12 6
Retiming

Shift registers around to improve circuit performance.

A 5 5 B A 5 5 B
j j
i i
D 6 12 C D 6 12 C
Optimal Retiming

A 5 5 B

j
i si = sj

D 6 12 C

Minimum clock period

with zero skew
16

D A B C
max 6 5 5 12
Retiming

• Allow synthesis tool to automatically move register

stages delay on each side of the F/Fs
• Does not change total delay of the circuit – Just
improves the balance of delays
Example: Minimize Registers
Fundamental criteria
u w(u,v) v

r(u) r(v)

w(u,v): original nonnegative register count of wire (u,v)

After retiming, every wire must have nonnegative register

count: w(u,v) + r(v) - r(u) > 0
O(E) linear constraints
E : # wires
Structural constraints
u 1 v

2 1

w(u,v): original nonnegative register count of wire (u,v)

After retiming, every wire must have nonnegative register

count: 1 + r(v) - r(u) > 0
O(E) linear constraints
E : # wires
Structural constraints
u v

2 1

w(u,v): original nonnegative register count of wire (u,v)

After retiming, every wire must have nonnegative register

count: 1 + 1 - r(u) > 0
O(E) linear constraints
E : # wires
Structural constraints
u v

2 1

w(u,v): original nonnegative register count of wire (u,v)

After retiming, every wire must have nonnegative register

count: 1 + 1 - 2 >0
O(E) linear constraints
E : # wires
Legal register moves

• Retiming Lag/Lead
So, what is retiming?

• Structural optimization methods.

• Retiming.
– Modeling:
– Retiming for minimum delay.
– Retiming for minimum area.
Synchronous logic modeling

• State-based model:
– Transition diagrams or tables.
– Explicit notion of state.
– Implicit notion of area and delay.
• Structural model:
– Synchronous logic network.
– Implicit notion of state.
– Explicit notion of area and delay
Synchronous network graph

• Synchronous network graph:

– Vertices <-> equations <-> I/O , gates.
– Edges <-> dependencies <-> nets.
– Weights <-> synch. delays <-> registers.
Example
Example
Rules of retiming

• Move register position.

• Do not modify combinational logic.
• Preserve network structure:
– Modify weights.
– Do not modify graph structure.
Example
Retiming

• Global optimization technique [Leiserson].

• Changes register positions:
– affects area:
• changes register count.
– affects cycle-time:
• changes path delays between register pairs.
• Solvable in polynomial time.
Assumptions

• Vertex delay is constant:

– No fan-out delay dependency.
• Graph topology is invariant:
– No logic transformations.
• Synchronous implementation:
– Cycles have positive weights.
– Edges have non-negative weights.
• Consider topological paths:
– No false path analysis.
Example

• Retiming of a vertex:
– Integer.
– Lag: registers moved from output to input (+).
– Lead: registers moved from input to output (-).
• Retiming of a network:
– Vector of vertex retiming.
Example

r = -[11222100]T
Definitions and properties

See example
9.3.9 pp 465
Legal retiming
Refined analysis

• Least register path:

–.
– Over all paths between vi and vj.
• Critical delay:
–.
– Over all the paths from vi to vj with weight W(vi, vj).
• There exists a vertex pair vi, vj whose D(vi, vj)
bounds the cycle-time.
Example
Minimum cycle-time retiming

• Find minimum value of the clock period such that there

exist a retiming vector where:

• Solution:
– Given a value of :
• solve linear constraints.
– methods:
• Bellman-Ford or derivate.
• MILP.
• Relaxation.
Example

See 9.3.10 pp 466

Minimum area retiming problem

• Find a retiming vector that minimizes the

number of registers.
• Simple area modeling:
– Every pos.-weighted edge -> register.
– Total register area cost equals total of weights.
• Register sharing model:
– Every set of positively-weighted edges with
common tail -> shift-register.
– Register area cost equals maximum of weights on
outgoing edges.
Example
Summary of retiming

• Sequential optimization technique for:

– Cycle time or register area.
• Applicable to:
– Synchronous logic models.
– Architectural data-path models:
• Resources with delays.
• Exact algorithm in polynomial time.
• Problems:
– Delay modeling.
– Network granularity.