ABOUT ELECTRONICS & ICT ACADEMIC ORGANIZING COMMITTEE NKN Winter Faculty Development

AT PDPM IIITDM JABALPUR Programme

CHIEF PATRON
The Ministry of Electronics and
Information Technology, Government of India, Prof. M. K. Surappa, FNA, FNAE VLSI Chip Design Hands on using open
has instituted seven Electronics and ICT Hon'ble Vice Chancellor source EDA
Academies with one academy at PDPM IIITDM Anna University
Jabalpur. The primary objective of the Academy Chennai. December 16th - 20th, 2019
is to prepare manpower for two important
missions - ‘Digital India’ and ‘Make in India’. PATRON
The Academy aims at scalable training
programmes in niche areas of Electronics and Prof. L. Karunamoorthy, Ph.D.
ICT for the development of required knowledge Registrar
base, skills, and tools to unleash the talent of the Anna University
Indian population. In addition to the faculty Chennai.
development programmes on fundamental and
advanced topics, the Academy conducts CHAIRMAN Seamless Learning Opportunities
customized training programmes for the Prof. S. Selladurai At
corporate sector and research promotion Electronics and ICT Academy
workshops in emerging areas. The Academy is
Additional Registrar
Centre for Constituent Colleges An Initiative and Sponsored by
envisioned to become a central hub of activities Ministry of Electronics and Information
on training, research, consultancy work, and Anna University
Chennai. Technology (MeitY)
entrepreneurship programmes.
Government of India
ABOUT PDPM IIITDM JABALPUR NODAL CENTRE
PDPM IIITDM Jabalpur was Prof. T. Senthilkumar
established in 2005 with a focus on education Dean & Nodal Centre Head
and research in IT-enabled Design and University College of Engineering
Manufacturing. Since its inception, PDPM Anna University, BIT Campus
ITTDM Jabalpur has been playing a vital role Tiruchirappalli.
in producing quality human resources for
contribution in India’s mission of inclusive and Dr. P. Vaishnavi
sustainable growth. The Institute offers Assistant Professor &
undergraduate, postgraduate and PhD Nodal Centre Coordinator
programmes in Computer Science and Department of Computer Applications
Engineering, Electronics and Communication University College of Engineering
Engineering, Mechanical Engineering, Design Anna University, Tiruchirappalli.
and PhD programmes in Mathematics, Physics
and Literature. Under IIIT act, the Institute has Organized by in association with
been declared as an Institute of National Dr. P. Ramadevi
Importance in January 2015. The Institute Assistant Professor &
PDPM University College of
campus is being developed on 250 acres of land Nodal Centre Programme Coordinator
Indian Institute of Information Engineering
close to Dumna Airport, Jabalpur. The Institute Department of Electronics and BIT Campus,
Tehcnology,
is 10 km from the main railway station and 5.5 Communications Engineering Design and Manufacturing Tiruchirappalli
km from Dumna Airport, Jabalpur. University College of Engineering Jabalpur
Anna University, Tiruchirappalli.
ABOUT UCE, BIT CAMPUS,
ANNA UNIVERSITY, TRICHY
University College of Engineering, BIT Campus,
Anna University, Tiruchirappalli is a technical
university department of Anna University. The
Vision of the Institute is to transform students into
competent professional and responsible citizen by
focusing on assimilation, analysis, synthesis and
dissemination of knowledge to meet the societal
needs. It offers higher education in Engineering,
Technology, Management and allied sciences at
undergraduate, postgraduate and doctorate level.
The main campus is situated in the southern part of
Tiruchirappalli and extends over 354 acres (1.43
km2).
FACULTY DEVELOPMENT PROGRAMME
VLSI CHIP DESIGN HANDS ON USING
OPEN SOURCE EDA
Who can attend: Programme is open to faculty from
all colleges and universities preferably from the
states of Madhya Pradesh, Chartisgarh, and
Maharashtra. Faculty members from other states are
also eligible. Industry personnel working in the
concerned/allied discipline may also apply. Limited
sears are available for research scholars.
How to apply:
Application format may be downloaded from the
website (Also given in this brochure). Print out of
the filled-in application form duly endorsed by the
forwarding authority, and a demand draft of the
applicable amount (as given below) in favour of
'Electronics and ICT Academy, IIITDMJ' payable at
Jabalpur may be sent to the address given below.
No Travelling Allowance will be paid by the
Academy.
Important Dates:
Last Date of Registration:
Spot Registration also available if seats are available
Course Dates: Dec. 16th - 20th, 2019.
Registration Fee and Accommodation:
Faculty and Research Scholars (Ph.D.): Nil and free
accommodation on sharing basis.
Others: Rs.3000 and extra nominal charges
accommodation and food
COURSE CONTENTS APPLICATION FORM
1. Study various components of RISC-V microprocessor
Name of the Course / Programme: VLSI Chip
based SoC and review all components using MAGIC Layout
Design Hands on using open source EDA
tool:
Name of the Applicant (first, last) : ....................
Brief introduction RISC-V ISA, Overview of RISC-V based
.......................................................................
micro-processor and its related SoC, Overview of QFN48
package, pads, macros and memory in MAGIC, Idea of chip-
Gender : M / F / T Category: GEN/SC/ST/OBC
planning, aspect ratio, utilization factor, power planning,
decoupling capacitor, pads/memory and macro placement.
Designation: ...................................................
2. Study the importance of standard cell library and design &
Organization / Institute / College:
characterize one cell using MAGIC Layout tool and
ngSPICE for SPICE simulations: .......................................................................
Pros and cons of good-bad floorplan, Introduction to lab to
Contact Address:
create floorplan for small design, which will be covered in
detail on Day 4), System-on-Chip (SoC) planning and design
........................................................................
concepts overview, Physical design overview, Why Libraries
are called the soul and heart of semi-conductor industry?,
.......................................................................
Standard cells library overview.
E-mail:
Mobile Number:
3. Pre-layout timing analysis of SoC using OpenSTA, chip
planning using MAGIC and block-level placement/routing
Do you need accommodation? (Yes/No):
using qflow RTL2GDS opensource EDA toolchain: Note: Accommodation facility will be available
Art of layout – Stick diagram + Euler’s path using MAGIC, th
from the evening of Dec 16 to the morning of
Characterization of important parameters using ngSPICE, th
Dec 20 , 2019.
Introduction to 16-Mask CMOS process and its significance
to chip design flow, Logic synthesis and high fanout net Paymet Details:
synthesis interactive tutorial using Yosys opensource DD Number: ................... Date: ...............
synthesis tool Bank: ...................... Payable at: ...................
4. Hierarchical placement/routing using pads and blocks, and
perform sign-off checks viz. LVS/DRC using Magic:
Introduction to static timing analysis and the related Industry Signature of the Applicant
standard reporting formats, Pre-layout timing analysis of a
design using OpenSTA opensource STA tool, which includes I hereby agree to relieve Mr./Ms./Dr...................
setup timing analysis for reg2reg and IO, Introduction to ................................................... in case she/he
clock tree synthesis (CTS) and its related checks viz. skew, is selected to attend the programme.
latency, pulse-width, duty cycle, Placement/Routing/CTS of
a design using qflow opensource RTL2GDS tool, Perform
CTS quality and routing quality checks using OpenSTA0020.
Signature & Seal of the Forwarding Authority
5. Post-layout timing analysis using OpenSTA and
engineering change order (ECO) using Tritonsizer:
Full chip integration using MAGIC for a design with blocks Name:......................... Designation: ..................
and pads, Revise floorplan from Day 2, Populate layout from
library manager in MAGIC, select digital core block and Contact us
additional pads, Arrange pads and create a pad-frame Dr. P: Ramadevi: +91 - 97881 - 70012
hierarchy, Project work using SiFive E31 RISC-V design Email: ramadevi.mohan@gmail.com
blocks .