Institut für Integrierte Systeme

Integrated Systems Laboratory

Department of Information Technology and Electrical Engineering

VLSI II:
Design of Very Large Scale Integration Circuits
227-0147-00L

Sample Solution Exercise 2

Introduction to Innovus
Prof. L. Benini
F. Gürkaynak

Last Changed: 2019-02-28 14:07:35 +0100

Reminder:
With the execution of this training you declare that you understand and accept the regulations about using
CAE/CAD software installations at the ETH Zurich. These regulations can be read anytime at
http://eda.ee.ethz.ch/index.php/Regulations.
1 Overview
This exercise will allow you to see a completed back-end design flow of an actual manufactured ASIC, and get
familiar with the back-end tool that we use, Innovus (formerly SoC Encounter) of Cadence Design Systems.
It is meant as an introduction to the back-end design flow. We will cover the individual steps of the back-end
design flow in a series of exercises. The Exercise 3 will cover preparation of input files and Floorplaning. Power
analysis and IR drop effects will be discussed in Exercise 6 and 7, and the placement and routing steps will
be the topic of Exercise 9. Finally, in Exercise 9 we will see chip finishing steps. It is the end product of these
exercises that you will see today.

Student Task: Parts of the text that have a gray background, like the current paragraph, indicate steps
required to complete the exercise.

2 Using Innovus
First a warning: Innovus is a state-of-the-art EDA package used in the industry. It contains many features that
we will not require (or we have not yet included in our design flow), don’t be overwhelmed by them.
To get familiar with Innovus, let us take a look at a completed design first.

Student Task 1:
• Copy the files required for this exercise by using the following command:
/home/vlsi2/ex02/install.sh

• This should create a directory named ex02/ . Enter this directory and start cockpit:
cd ex02
icdesign umcL65 &

• Start Encounter/Innovus using cockpit.

You will see an xterm and the Innovus GUI appear. The xterm contains the console for Innovus. While the GUI
looks fancy, you will be using the console more than you think. Make sure that it remains accessible and visible
at all times1 . Figure 1 shows the main Innovus window with the most important functions highlighted2 .

2.1 Terminology
Before we start to explore the example design, some notes about the terminology used in Innovus:
Module Is equivalent to the entities in VHDL or modules in Verilog. It contains a level of design hierarchy.
Standard Cell / StdCell Building block that implements a logic gate (and, or, flip flop, latch, etc.) and will be
placed (aligned in rows) in the core area.
Macro-cell / Block Building block that is typically larger and more complex than the standard cells. This could
be a sub-design that has been completed previously or a full-custom block like the RAMs used in this
example. Typically placed somewhere in the core area.
Pad Building block that is used to connect the core of the chip to the external world. Placed in the IO region
around the core.
1 You could also start Innovus from the command line by changing into the ’encounter’ directory and running the command
cds innovus innovus
In this case, the xterm you start Innovus from will act as your console. Don’t use a ’&’ character to put the process in the
background, as this will suspend Innovus. If you accidentally do this, you could use the fg command to resume.
2 Innovus uses tool tips: if you leave the cursor on buttons for a short while, a label will appear.

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Figure 1: Important elements of a fresh Innovus window.

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Cell [Type] A building block available from a library, e.g. AN2B1S, ND2, SHKA65 8192X32X1CM16 etc. Note:
Also used for Verilog modules defined in your design netlist.
Instance One specific copy of a building block that is part of your design netlist. Identified by a unique instance
name, e.g. ’i top/U68’ or ’i top/DataxD reg 0 ]’. Note: Also used for Verilog modules used in your
design netlist.
Row All standard cells have the same height. This allows them to be placed in (horizontal) rows. In back-end
terms, a row defines a region where standard cells can be placed.
Term A logical connection point (port) of a module or cell, e.g. the buffer ’BUF1’ has two terminals (’I’ and ’O’).
[Inst] Pin A physical connection point/shape of an instance, i.e. where the router contacts the instance.
Net The logical/signal interconnection between instances.
Special Net All instances need to be connected to power and ground. Technically these connections are also
nets, but they are treated differently from regular nets. These nets are called special nets.

2.2 Basic Shortcuts

Although most of the functionality is available through menus, you will realize that keyboard (mouse) shortcuts
make life much easier. You can press ’b’ to view (and edit) the keyboard shortcuts. The following is a short list
of the most popular shortcuts:
’z’ : Zoom In
’Z’ : Zoom Out
’f’ : Zoom to fit the design
’q’ : Query properties of selected object
’u’ : Undo
’b’ : Edit keyboard bindings

2.3 Exploring the Design

Now let us restore a completed database. We use a design specifically created for these exercises. However,
it uses the same technology and shares the same dimensions as our student projects.

Student Task 2:
• Select File→Restore Design... from the menu. The design is stored in Innovus’ own format,
it is stored as ’filter chip final.enc’ inside the ’save’ directory.

After loading the design you will be in the Floorplan View of Innovus (see Figure 2). We will use this view
mostly during floorplaning. This view shows you the power connections for the entire chip and all instances
with a placement status of ’FIXED’, i.e. pads, pre-placed macro-cells (the RAM) and standard cells that are
part of a clock tree (including the registers).

Student Task 3:
• To get an impression how small the chip is let us try to measure the chip dimensions. First we will
have to select the ’ruler’ tool by either clicking on its icon (fourth from left in the second row) on
the tool panel of Innovus, or by calling the function by its keyboard shortcut ’k’. The units are in
micrometers. How long is one side of the chip?

Sample solution: l = 1200 µm

Note that you can zoom in by using the right mouse button, pan by pushing SHIFT-RIGHTMOUSE
and moving the cursor, and you can remove all the rulers by pressing ’SHIFT-K’. To see (or change)
keyboard shortcuts go to the menu ”Design →Preferences...” You will see a button called

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Figure 2: Innovus in floorplaning mode with a design loaded.

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 Binding Key, that will enable you to view or modify the keyboard short-cuts, or simply press its
shortcut ’b’. You can auto-adjust the view to fit the design by pushing ’f’
• When you look at the chip, you realize that the area used for the pads is not very small. The
remaining area in the center is called core area. How many percent larger would the core area be,
if there were no pads?

Sample solution: Atotal /Acore = 1.44 mm2 /0.9262 mm2 = 1.555 ⇒ 55.5% larger

• The RAM block is placed in the upper left corner. What is the area of such a RAM module? In this
example, the RAM holds 8192 words of 32 bit each. What is the bit density in this technology, in
other words how many bits can you store per mm2 ?

Sample solution: A = 0.1906 mm2

Sample solution: ρ = 1.375 Mbit/mm2

Normally, we would use the ’Floorplan View’ to start our design. The design we have loaded, however, is
completely finished – some parts are just not visible yet. To see all standard cell placements and the routing
you will have to change the view to Physical (see Figure 3).

Student Task 4:
• Click on the ’Physical View’ button on the right side of the Innovus toolbar.

The physical view will literally show you a jungle of connections. You will need to zoom in really close to
differentiate individual connections. A modern IC manufacturing technology provides several metal layers for
routing, the technology we use for semester projects has eight. Each metal layer is separated by an insulating
layer. In this way separate signals can be carried on different metal layers. To move a signal from one metal
layer to another a special connection named ’via’ is used. Each via connects two adjacent metal layers. In this
technology multiple vias can also be stacked (placed on top of each other), so that it is possible to move from
the top most metal (Metal-8) to the bottom most metal layer (Metal-1) at one point3 .
There are several colored squares on the right hand side of the Innovus window. Each square shows the color
of an object category in the design. The object category is written on the left side of the colored square. On
the right side of the squares you can see two (red) check boxes. The first check box is used to toggle the
visibility of an object category. Let us take the object category ’Net’. This category contains all normal signal
connections between the standard cells. Click on the first check box so that the box is not selected (the box
turns gray). You will see all interconnections disappear. You can now see the placement of the standard cells
on the chip. The second box determines whether or not you will be able to select objects belonging to that
category. Remember that you can only select objects that are visible. We will not explain all object categories
(you can consult the user manual for that). The category ’Instance’ will control all instances in your design, and
’Special Net’ controls all power connections (that are treated differently from signal interconnections).

Student Task 5:
• There are eight metal layers in this process. Typically, each metal layer is used predominantly in one
direction (either horizontal or vertical). For the metal layers 1 to 4, find out in which direction it is
running.
You will need the section ’Wire&Via’ in the layer control area on the right to switch the physical layers
on and off. You can also use the keyboard shortcuts 1,2,. . . ,8 to toggle the visibility of Metal-1 to
Metal-8. The via layers are automatically switched on if both adjacent metal layers are toggled on
using the keyboard shortcuts.
3 Note that there will be 7 separate vias that are placed on top of each other for this to happen. This will block all in-between
metal layers (Metal-2, Metal-3, ..., Metal-7) at this point as well.

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Figure 3: Innovus in physical mode with a design loaded.

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 M4 vertical
M3 horizontal
Sample solution:
M2 vertical
M1 horizontal

• When looking at the individual metal layers, do you notice any exceptions in the direction of the
wiring? Why or why not?

Sample solution: Small short-distance adjustments are made in non-typical direction for local
wiring

• Follow the power connections of the RAM. On which metal layer is the connection, where does it
connect to?
Hint: You can switch off the visibility of the majority of connections (’Net’) to see only the power
connections (’Net-Power’, ’Net-Ground’). You might also want to toggle the pins of the RAM block
(’Cell-Pin Shapes’).

Sample solution: M3 and M4. The power pins of the RAM are rings around the macro, how-
ever (for as yet unknown reasons) the power pins are not actually connected to the power
nets...

• Switch on a single metal layer in vertical direction, e.g. M6. You should notice a very distinctive,
regular pattern all across the chip (you need to make the ’Net’ visible again if you have switched it
off before). You probably have noticed that the main power distribution grid is on layers M7 and M8
with very wide tracks on M8. Yet it clearly also seems to influence the routing on other metal layers.
Can you explain this?

Sample solution: Very little routing directly below the power lines on M7/M8 to reduce capac-
itive coupling. Also, the rows of vias from the thick power lines block the layers below.

• Besides the vertical pattern, it seems that there are other areas with almost no routing. To analyze
the source of this, switch to the amoeba view on the top right of the main window. Besides the RAM
block and the pads, there is one large block called i filter top. You can select it and click on the
’group’ (G) and ’ungroup’ (shift-G) buttons to get more detailed view of your design. Can you now
explain these areas with almost no wiring on the metal layers?

Sample solution: Areas that form boundaries between blocks (instances) are sparsely routed.
Hierarchical designs usually have blocks with very dense routing/logic and relatively few con-
nections between them.

A very helpful feature of Innovus is the Design Browser than can be accessed through the ”Tools → Design\

Browser”, or by clicking on its icon on the upper part of the Innovus toolbar.
This tool allows you to browse through the logical hierarchy of the design and lets you highlight and select
instances and nets. For each hierarchy, the number of terminals (pins), nets and standard cells within the
hierarchy will be shown. In addition the number of sub-modules will be given. By clicking on the ’+’ sign you
can expand further hierarchies. Selecting one or more objects will cause them to be cross highlighted on the
main Innovus window as well.
Obviously, it is necessary to be able to find components of your design within Innovus. However, often you
need more than just finding individual components, but you need to be able to see their connectivity to the next
few components. We examine one option to do so with the next task.
Figure 4 shows the schematic of the filter design we have just loaded. The top-level filter top consists
of a data memory, and the main operational block filter. The filter is built from eight filter stages

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 RamWE_S
RamTest_TI
DataIn_DI 14 32 RamWD_D
permutator SHKA65_8192X32X1CM16
DataInReq_SI RamAddr_D
DataInAck_SO r256x72tb300xo
RamRD_D
32

ScanEn_TI

filter_stage0

filter_stage1

filter_stage2

filter_stage7

permutator
Clk_CI
32 32 14 DataOut_DO
’0’
Reset_RBI

DataOutAck_SI

DataOutReq_SO

filter
fiter_top
filter_chip

DataIn_DI 32
permutator
64
64 64 Next_DI
Prev_DI 32
LUT 32 32

D_DI 32
32 D_DO
A_DI 10 32
LUT
pipe_stage0

pipe_stage1

pipe_stage7

32

filter_stage pipe_stage

Figure 4: Schematic diagram of the filter design.

and some control logic for the memory. There are permutators at the input and output, which were intro-
duced when scaling up an old design to fill a chip with the same dimensions as used for the current semester
projects.

Student Task 6:
• Use the Design Browser to find pad DataOut DO 0. Select it and click on the ’Show Cone Schematic’
button. In the new window, you should be able to see this instance with its name, all its pins, etc.
You can switch the visibility of the pin names, . . . in the ’Preference’ window.
• You can right-click on the DO pin and select ’Open Fan-In Cone’. Repeat this for a few levels of fan-in
and you should be able to see the buffers and multiplexer driving this output pin to the schematic.
You can also right-click on the component instance to open the fan-in of all input pins.
Using this newly acquired knowledge, explore further to find the use of this multiplexer. It is not a
functional part of the circuit, but has been inserted later on. What does it do?

Sample solution: This Multiplexer is driven directly by the ScanEn TI pin of the chip. This
enables the scan chain used for testing, where all registers in the design are hooked up to
each other without logic in between.

• Use the hierarchy browser to identify the individual components of the filter. What is the instance
name of the memory? What type of cell drives most bits of the RAM address (setup proper view,
track the wires)? What is the function of this cell? If you can’t tell from its name and inputs/outputs,
check the standard cell datasheet in the doc folder located in the exercise root folder.

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 Figure 5: Close-up of the filter design loaded in Innovus.

Sample solution: The memory instance name is u ram. The address pins are driven by ADF
cells, which are full adders.

Figure 5 is a close-up of the filter design we have just loaded. It shows one standard cell (ND2) with three
pins (’A’, ’B’ and ’Z’). The instance name is i filter top/U69. You can find this instance with the design
browser as well (cf. Figure 6).

Student Task 7:
• Find the above mentioned instance in your design. You can use the design browser as shown in the
figure.

To find instances it is also possible to use wild cards (’*’ and ’?’: the ‘*‘ matches any number of characters, a
’?’ can be used to match exactly one character. ).
It is also possible to find other objects than just ’Instance’s. By clicking on the box near ’Find’ in the ’Design
Browser’ window, it is possible to choose between ’Instance’, ’Net’, ’Group’ and ’Cell’.

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 Figure 6: The Innovus design browser.

By clicking the ’Zoom Selected’ button you can easily zoom to the selected instance. You can use the ‘F9’ button
to dim the remaining elements on the screen, enabling you to see the selected components much more easily.
There are 2 different dimming settings, pressing ’F9’ two more times will revert back to the original display
setting.
In Figure 2, two special nets VDD and VSS are shown. These special nets follow through the rows where the
cells are placed and assure each cell is connected to them.
The following is the line in the Verilog netlist that describes the same cell. This is the Verilog netlist obtained
from Synposys DC which has originally been imported into Innovus. It is located at ’synopsys/netlists/fil-
ter top.v’, feel free to also have a look at the file itself.
ND2M16WA U69 ( .A(RamTest_TI), .B(RamWrite_D[2]), .Z(n46) );

ND2M16WA is the cell, U69 is the instance name, RamTest TI, RamWrite D[2], and n46 are net names. A,
B and Z are pins of the cell. Note that there are no pins and connections for special nets in this description.
The attribute field4 at the lower left of the main Innovus window reports some information about the selected
object. Also note that the cell name is not exactly the same in the netlist obtained using Synopsys DC. Innovus
can resize the cells depending on the load. In this case the load was significantly smaller than Synopsys DC
expected it to be. This is one of the reasons why the area figures obtained through Synopsys DC should only
be treated as rough estimates.

Student Task 8:
• Use the Design Browser to select all nets that form the clock tree in this design. The nets have a
name that contains ’CTS’. Can you see the different clock tree levels (L1, L2, etc.) ? Check both: the
Instances (they have names containing ’Clk’) and the Nets. How many levels are there ?

4 if it is not visible, you can enable it under ”Options → Show/hide windows → Property”.

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 Sample solution: There’s 5 levels of buffers in the design (L2-L6)

• Innovus features dedicated tools for interacting with the clock tree. Verify that your previous answer is
correct by launching the clock tree debugger through ”Clock → CCOpt Clock Tree Debugger”
and pressing OK in the following configuration window. If CCOpt runs for the first time, it will ask to
run the clock tree extraction, which can take a few minutes. Can you see the expected amount of
clock tree levels?

To get additional information about an instance or a net, you can open up the attribute editor. Select an
instance, and open the attribute editor by pressing ’q’. You can also double click on the instance. In addition to
the attribute editor, all connections of the instance will be highlighted. The source of a connection is denoted
by a ’O’ and the sinks by ’X’.
Most modern standard cell libraries contain cells with different driving strengths. These cells are identical
in functionality but have different output stages and are suited to drive different capacitive loads. The drive
strength is a normalized value that shows how much load a given standard cell can drive at the same speed.
In the technology we use for this training, there are (at least) 4 different drive strengths for all functions. The
cell names reflect both the function and the drive strength. There are no accepted standards for naming the
cells, and every standard cell manufacturer chooses a different naming scheme5 .
There is more information hidden in the name of a cell. For umcL65, the name consists of four fields:
• field 1 (cell index): high speed (H), low power (L), scan (S)
• field 2 (cell function name): e.g., ND2 for a 2-input NAND
• field 3 (cell driving strength index): M0, M1, M2, ...
• field 4 (device type): e.g., W,WA for low-threshold and low-leakage
Example: SDFEQRM1WA describes a scan-enabled (S), D-type flip-flop (DF) with enable signal (E), single
output (Q) and reset (R). It has drive strength 1 (M1) and is designed for the low-threshold, low-leakage
process (WA).
All the details about the cells can be found in the process documentation. The databook for the standard cell
for umcL65 can be found at docs/stdcell low vt b03 databook.pdf, relative to the root of your cockpit
directory. On page 21 there is a more detailed explanation of the cell naming conventions, but there is also
the definition of how the setup time has been determined or a listing of the power dissipation for every cell,
depending on the load.
Let us investigate the standard cells in more detail. All cells of a standard cell library have the same height.
Some standard cells contain more (or larger) transistors than others, which requires more area. These cells
are wider than others.

Student Task 9:
• Determine the height of the standard cells for this technology.

Sample solution: h = 1.8 µm

• Find a ‘INV‘ (inverter), ‘SDFEQR‘ (scanable flip-flop with reset), ‘ND2‘ (2-input NAND gate), and ‘OR2‘
(2-input OR gate) in the example design and compare their sizes. You can use the Design Browser
to find cells of this type and then use ’Zoom Selected’ to find it in the main window. In order to get
a meaningful comparison, choose similar sizes (e.g., M2W for the logic gates and M1WA for the
flip-flop).

5 Using a ’M’, ’D’ or ’X’ followed by a number is pretty common practice, i.e. AN2D4 or AN2X4

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 INV 0.6 µm × 1.8 µm
SDFEQR 7.4 µm × 1.8 µm
Sample solution:
ND2 0.8 µm × 1.8 µm
OR2 1.2 µm × 1.8 µm

Student Task 10: Let us have a look at the 2-input NAND gate. For how many different drive strengths is
it available?

Sample solution: 10: M0W, M1W, M2W, M3W, M4W, M5W, M6W, M8W, M12WA, M16WA

Assume that the output of a NAND gate is connected to five 2-input NAND gates of drive strength M2.
You want a propagation delay of less than 0.042 ns. Which drive strength would you choose? Why?

Sample solution: Use drive strength M2W. We need to drive 5 × 0.001 29 pF = 0.006 45 pF. The
closest drive strength that should suffice is M2W, as it drives 0.0072 pF in 0.0425 ns.

Although this gives you a rough estimate, it does not account for the capacitance of the wiring. The capacitance
of the wiring is quite often not negligible, but hopefully you have still obtained some rough idea of the capability
of different drive strengths.

Student Task 11: One of the few details missing in the databook is the size of the cells. In order to get an
impression, complete the following table and compare the sizes.a

Cell driving strengthmin size (µm2 ) driving strengthmax size (µm2 )

MUX2 M0 A = 3.24 M12 A = 8.64
Sample solution:
INV M0 A = 1.08 M48 A = 11.88
ND2 M0 A = 1.44 (= 1GE) M16 A = 7.92
a If you can not find the cell in your design make use of the Cell Viewer (Tools → Cell Viewer).

2.4 Further Help

This training will only explain the basic functionality of Innovus, for additional help please use the ’Help’ menu.
Note that each sub-window has its own ’Help’ button. Pressing this button will show you directly the relevant
help page.
Most of the commands that can be used in the command line window have a man page that can be accessed
by issuing the command
man command_name

Sometimes, you just need to know the command options, and are not looking for a lengthy description. In such
cases use
help command_name

to get brief usage information. If you are not running Innovus, but would like to access the help system, you
can also start the Innovus help (which will displayed in a web browser) by issuing the following command from
a shell by typing:
cds_innovus cdnshelp

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2.5 A Last Note
Back-end design is an iterative process. The decisions you will make at the beginning of back-end design
may have a profound impact on the outcome. However, you will not always be able to predict this. You will
have to complete individual stages of back-end design (floorplaning, placement, routing etc) and then assess
the quality of the result. If you are not satisfied with this result you will have to repeat the stage or even the
entire process. This is normal, be prepared for it. This iterative nature of the backend process also makes it a
necessity to capture your flow in a TCL script - this helps you in two ways:
• It makes a once-established process easily reproducible
• It makes it easy to modify individual steps of the backend process
Notice that each time you repeat a certain stage, you will gain more experience and will be able to work
faster.

E You are done with Exercise 2. Discuss your results with an assistant.
E

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