MIT Art’s, Commerce & Science College, Alandi (D)

Department of Electronics

F.Y.B.Sc (Computer Science)

Electronics Practical Manual

SEM-II

Year 2019 - 2019

MIT Art’s, Commerce & Science College, Alandi (D)
Department of Electronics
F.Y.B.Sc Electronics Practical Sheet

Title: Study of LDR based system.

Aim: To built, test and study LDR based system.

Objectives:
1. To learn working relays.
2. To study the operation of LDR.
3. To understand the concept of photoelectric effect is used in LDR.

Components: Transistor, resistors, LDR, Relay, Diode, LED etc.

Instruments: Digital multimeter, Experimental Board with inbuilt power supply.

Circuit Diagram:

PROCEDURE:
1. Make the circuit connections according to circuit diagram shown on board using Patch Chord.
Carefully look the polarities of the power supply.
2. Enlist the components with their specifications and values using DMM.
 3. Test the circuits under different light conditions so that relay switches ON and OFF and
measure the voltages at base and collector of the transistors used for both conditions
4. From the above readings comment whether the transistors are in cut off or saturation or in
active region

Observation Table:

Transistors T1 T2
Light Condition Max Intensity Min Intensity Max Intensity Min Intensity
LED ON OFF ON OFF

State of
Saturated Cut off Saturated Cut off
Transistor

Working Principle of LDR :

This resistor works on the principle of photo conductivity. It is nothing but, when the light falls on its
surface, then the material conductivity reduces and also the electrons in the valence band of the device
are excited to the conduction band. These photons in the incident light must have energy greater than the
band gap of the semiconductor material. This makes the electrons to jump from the valence band to
conduction

These devices depend on the light, when light falls on the LDR then the resistance decreases, and
increases in the dark. When a LDR is kept in the dark place, its resistance is high and, when the LDR is
kept in the light its resistance will decrease.

If a constant “V’ is applied to the LDR, the intensity of the light increased and current increases. The
figure below shows the curve between resistance Vs illumination curve for a particular light dependent
resistor.
Result:

Conclusion:

Questions:
1. Explain the construction of LDR. Which photoelectric effect is used in LDR
2. Which type of pair is formed by T1 and T2? What is its use?
3. What will happen if position of LDR and potentiometer are interchanged?
4. What are the uses of photo relay using LDR?
5. Explain the working of circuit when light falls on LDR.
 MIT Art’s, Commerce & Science College, Alandi (D)
Department of Electronics
F.Y.B.Sc Electronics Practical Sheet

Title: Study of Stepper Motor.

 MIT Art’s, Commerce & Science College, Alandi (D)
Department of Electronics
F.Y.B.Sc Electronics Practical Sheet
Aim:

To design and study the open loop gain from Non-Inverting Amplifier circuit.
Components required:

Function generator, CRO, Regulated Power supply, resistor, capacitor, 741 IC, connecting wires.

The operational amplifier can also be used to construct a non-inverting amplifier with the circuit indicated
below. The input signal is applied to the positive or non-inverting input terminal of the operational amplifier,
and a portion of the output signal is fed back to the negative input terminal. Analysis of the circuit is performed
by relating the voltage at V 2 to both the input voltage V in and the output voltage Vo.
The output is applied back to the inverting (-) input through the feedback circuit (closed loop) formed by the
input resistor R1 and the feedback resistor R2. This creates ve feedback as follows. Resistors R 1 and R2 form a
voltage-divider circuit, which reduces V o and connects the reduced voltage V 2 to the inverting input.

Figure 1: Non-Inverting Amplifier configuration of an op-amp

Procedure:

1. Connect the circuit as shown in the circuit diagram.

2. Measure the input and output voltage from the input and output waveform in the CRO.
3. Switch on the power supply.
4. Note down the outputs from the CRO
5. Draw the necessary waveforms on the graph sheet.

Observations:

1. Observe the output waveform from CRO. A non-inverted and amplified waveform will be observed.
2. Measure the input and output voltage from the input and output waveform in the CRO.
3. Calculate

4. Compare the theoretical voltage gain from the above equation with the experimental value obtained by
dividing output voltage by input voltages observed.
5. Observe outputs of the inverting amplifier circuit using different input waveforms.
For example, a case has been taken and the required parameters values is being noted down below:
1. Input Voltage: 1.94VV
2. Frequency: 50Hz
3. Output Voltage: 17.3V

Calculations:

1. Calculate experimentally observed voltage gain A v using observed Vo & Vin from CRO.

2. Theoretically voltage gain is given by:

Result:

Hence the opamp can configure as non-inverting amplifier circuit as observed from the output waveforms.
Precautions:

1. Connections should be verified before clicking run button.

2. The resistance to be choosen should be in Kohm range.
3. Best performance is being obtained within 50Hz to 1Mhz.
Objectives:

(I) Study of the inverting amplifier configuration and to find its gain
(II) Study of the non-inverting amplifier configuration and to find its gain

Apparatus:

1. OPAMP IC 741
2. Resistors: 1K (2 nos), 10K, 50K
3. D.C. power supply
4. Digital multimeter
5. Bread board
6. Connecting wires

Theory:

Please refer the supplementary note.

Circuit Diagram:

Inverting amplifier
 Non-inverting amplifier

Procedure:

(I) Inverting amplifier

1. Configure the circuit as shown in the circuit diagram. Connect the pins 7 and 4 of the
IC to the ±15V output terminals of the D.C. power supply. Connect the 0V terminal to
ground. Choose Rin = 1K and Rf = 10K. Measure the resistance values with multimeter
and calculate gain, -(Rf/Rin). Connect a resistor R3 (= Rin║Rf ≈ Rin) as shown in the
circuit diagram so as to minimize offset due to input bias current.
2. Connect one of the output terminals of the D.C. power supply (0-30V) at the
inverting input (pin no. 2).
3. Switch on the power supply and apply different voltages in the range 0- 1.5V (why?)
in steps of 0.2 V at the inverting terminal. Measure this input using a digital multimeter.
4. Measure the corresponding output voltages with the multimeter and calculate gain
Vo/Vin. Note the sign of the output voltage.
5. Now, replace Rf by 50K. Measure the resistance value with multimeter and calculate
gain, -(Rf/Rin).
6. Apply different voltages in the range 0- 0.5V in steps of 0.1 V at the inverting
terminal. Measure this input using a digital multimeter.
7. Measure the corresponding output voltages with the multimeter and calculate gain
Vo/Vin.
8. Plot graphs for V in ~ Vo for both the values of RF.
9. You may also use a function generator to give a sinusoidal input and notice the output
waveform using an oscilloscope.

(II) Non-inverting amplifier

1. Configure the circuit as shown in the circuit diagram with Rin = 1K and Rf = 10K.
using the measured value of resistance calculate gain, 1+ (Rf/Rin).
2. Connect one of the output terminals of the D.C. power supply (0-30V) at the non-
inverting input (pin no. 3).
 3. Repeat steps 3 onwards of procedure (I) with inputs applied at non-inverting terminal.

Observ

ations

Obs. Input Rf Rf
Table (V)
No. − = ------ − = ------
Rin Rin
Output Gain Average Output Gain Average
(I): (V) Vo/Vin (V) Vo/Vin
0.2
0.4
…

Table (For II):

Obs. Input Rf Rf
No. (V) 1+ = ------ 1+ = ------
Rin Rin
Output Gain Average Output Gain Average
(V) Vo/Vin (V) Vo/Vin
1 0.1
2 0.2
.. …

Graph:

Calculate gain from graph in

each case. Discussions:

Conclusions/precautions:
 MIT Art’s, Commerce & Science College, Alandi (D)
Department of Electronics
F.Y.B.Sc(CS) Electronics Practical Sheet

Title: Opamp as adder & subs tractor.

Aim: To study opamp as adder and sub tractor circuit

Apparatus: Experimental kit, connecting wires, DMM etc.

Components: IC 741, R1=R2=R3=Rf=10kΩ

Symbol of Opamp: Pin diagram Of IC741

Circuit Diagram:
Opamp as Adder
Rf=10kΩ

R1=10kΩ

Vo=-(V1+V2)
R2=10kΩ

Observation table:

Obs. No. Inputs Outputs Error

V1 (volts) V2(volts) Calculated Observed
1
2
3
4
5
Procedure:

1. Connect the circuit as shown in the diagram.

2. Apply +/- 15V dual power supply to the circuit.
3. Apply different input voltages V1 and V2 .Measure the output voltage Vo &
record it.
4. Note that the input voltages V1 and V2 are must be precisely measured and
then connect to the input.
5. Comment on error in the measurement.

Opamp as Subs tractor

Circuit Diagram:

Vo= (V2 - V1)

Observation table:

Obs. Inputs Outputs Vo= V2 - V1 Error

No. V1 (volts) V2(volts) Calculated Observed
1
2
3
4
5
Result & Conclusion:

Questions:

1. What is opamp? Draw the symbol of opamp?

2. What are the types of opamp?
3. What are the ideal characteristics of opamp?
4. What are the applications of opamp?
 MIT Art’s, Commerce & Science College, Alandi (D)
Department of Electronics
F.Y.B.Sc (CS)Electronics Practical Sheet

Title: RS, JK & D flip flop.

Aim: To study RS, JK and D flip flops.

Components: Experimental kit, connecting wires etc.

RS Flip flop
Block Diagram: Circuit Diagram:

Truth Table:

Inputs Output State

CLK S R Q
0 x x NC Previous
1 0 0 NC Previous
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 - Forbidden

Theory:

The SR flip-flop, also known as a SR Latch, can be considered as one of the most
basic sequential logic circuit possible. This simple flip-flop is basically a one-bit
memory bistable device that has two inputs, one which will “SET” the device
(meaning the output = “1”), and is labeled S and another which will “RESET” the
device (meaning the output = “0”), labeled R.
Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop
back to its original state with an output Q that will be either at a logic level “1” or
logic “0” depending upon this set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs
back to its opposing inputs and is commonly used in memory circuits to store a single
data bit. Then the SR flip-flop actually has three inputs, Set, Reset and its current
output Q relating to its current state or history. The term “Flip-flop” relates to the
actual operation of the device, as it can be “flipped” into one logic Set state or
“flopped” back into the opposing logic Reset state.

JK Flip flop
Block Diagram: Circuit Diagram:

Truth Table:

Inputs Output State

CLK S R Q
0 x x NC Previous
1 0 0 NC Previous
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 - Toggle

Theory:

The JK flip-flop is basically an SR flip flop with feedback which enables only one of
its two input terminals, either SET or RESET to be active at any one time thereby
eliminating the invalid condition seen previously in the SR flip flop circuit.
Also when both the J and the K inputs are at logic level “1” at the same time, and the
clock input is pulsed “HIGH”, the circuit will “toggle” from its SET state to a RESET
state, or visa-versa. This results in the JK flip flop acting more like a T-type toggle
flip-flop when both terminals are “HIGH”.
Although this circuit is an improvement on the clocked SR flip-flop it still suffers
from timing problems called “race” if the output Q changes state before the timing
pulse of the clock input has time to go “OFF”. To avoid this the timing pulse period
( T ) must be kept as short as possible (high frequency). As this is sometimes not
possible with modern TTL IC’s the much improved Master-Slave JK Flip-flop was
developed.

D Flip flop

D flip flop using SR: Truth Table:

D flip flop using JK:

Theory:

We remember that a simple SR flip-flop requires two inputs, one to “SET” the output
and one to “RESET” the output. By connecting an inverter (NOT gate) to the SR flip-
flop we can “SET” and “RESET” the flip-flop using just one input as now the two
input signals are complements of each other. This complement avoids the ambiguity
inherent in the SR latch when both inputs are LOW, since that state is no longer
possible.
Thus this single input is called the “DATA” input. If this data input is held HIGH the
flip flop would be “SET” and when it is LOW the flip flop would change and become
“RESET”. However, this would be rather pointless since the output of the flip flop
would always change on every pulse applied to this data input.
To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to
isolate the data input from the flip flop’s latching circuitry after the desired data has
been stored. The effect is that D input condition is only copied to the output Q when
the clock input is active. This then forms the basis of another sequential device called
a D Flip Flop.
The “D flip flop” will store and output whatever logic level is applied to its data
terminal so long as the clock input is HIGH. Once the clock input goes LOW the “set”
and “reset” inputs of the flip-flop are both held at logic level “1” so it will not change
state and store whatever data was present on its output before the clock transition
occurred. In other words the output is “latched” at either logic “0” or logic “1”.

Result & Conclusion:

Questions:

1. What is Flip-flop?
2. What are the types of flip flop?
3. What is race around condition?
4. What is drawback of SR flip flop?
5. What is difference between combinational & sequential circuits?
 MIT Art’s, Commerce & Science College, Alandi (D)
Department of Electronics
F.Y.B.Sc (CS)Electronics Practical Sheet

Title: Decade Counter (Scaling circuit)

Aim: To study decade counter.

Apparatus: Experimental kit, Connecting wires, DMM etc.

Pin diagram of IC7490:

Pin Description
CKA Clock input to the inernal MOD-5 counter.
CKB Clock input to FF-A
R0(1),R0(2) Gated zero reset input
R9(1),R9(2) Gated set nine input
QA,QB,QC,QD Outputs
QA Output of internal MOD-2 Counter
QB,QC,QD Output of internal MOD-5 Counter
 MOD 10 Counter
Circuit Diagram:
Clock i/p

State Diagram:

MOD 8 Counter
Circuit Diagram
+5V (VCC)
State Diagram:

14 5
CLK QA 12
0
1 QB 9
7
QC 8 1
F/8
10 IC7490 11
QD
6
2
3 R0(1) 2
R0(1)
6
R9(1) 5
7 3
R9(2) 4
Clock QD QC QB QA
input
 0 0 0 0 0 Truth Table: Procedure:
1 0 0 0 1
2 0 0 1 0 1. Clock input is given to CLKA
3 0 0 1 1 2. QA is connected to CLKB
4 0 1 0 0 3. R9(1) and R9(2) are connected to ground.
5 0 1 0 1 4. Last counted state is 0111.To reset the counter
6 0 1 1 0 at the next state 1000, QD is connected to
7 0 1 1 1 R0(1)&R0(2).
8 0 0 0 0 5. Output is seen at QC

MOD 5 Counters
Circuit Diagram +5V (VCC) State Diagram:

14 5
QA 12
QB 9
0
1
CLKB QC
8
10 IC7490
4 1
11 QD
F/5
2
R0(1)
3
R0(2)
6 R9(1) 3 2
7 R9(2)

Truth Table: Procedure:

Clock QD QC QB QA
input

0 0 0 0 0
1 0 0 0 1
 2 0 0 1 0
3 0 0 1 1
4 0 1 0 0 1. Clock input is given to pin no.1 CLKB
5 0 0 0 0 2. R9(1) and R9(2) are connected to ground.
3. R0(1)&R0(2) are connected to ground.
4. Output is seen at QD

MOD 2 Counter

Circuit Diagram: State Diagram:

+5V (VCC)

14 0 1
5
CLKB QA 12 F/2
1 QB 9
QC
8
10 IC7490 QD

R0(1)
3
R0(2)
6 R9(1)
7 R9(2)

Truth Table: Procedure:

Clock QD QC QB QA
input
1. In this only one flipflop is used.
2. Clock input is given to pin no.14 CLKB
0 0 0 0 0
3. R9(1) and R9(2) are connected to ground.
1 0 0 0 1
4. R0(1)&R0(2) are connected to ground.
2 0 0 0 0
5. Output is seen at QA
Result & Conclusion:

MIT Art’s, Commerce & Science College, Alandi (D)

Department of Electronics
F.Y.B.Sc (CS)Electronics Practical Sheet
Title: Study of 4 bit Shift Register.

Aim: To study various mode of shift register using IC 7495 & it’s use as a ring counter .

Apparatus: Experimental kit, connecting wires etc.

Pin diagram of IC 7495:

Logic Diagram:

Observation Table:

1) SISO Data: 1001

Sr.no. CLK pulse Serial I/p Serial O/P

1 1 X
2 0 X
3 0 X
4 1 1
5 X 0
6 X 0
7 X 1

2) SIPO Data: 1001

Sr.no CLK pulse Serial I/p Parallel O/P

Q3 Q2 Q1 Q0
1 1 x x x X
2 0 x x x x
3 0 x x x X
 4 1 1 0 0 1

3) PIPO: Data: 1001

Sr.no CLK Parallel I/P Parallel O/P

pulse D3 D2 D1 D0 Q3 Q2 Q1 Q0

1 1 0 0 1 1 0 0 1

Procedure:

1. Identify the pin configuration of IC.

2. Connect the +5V to the VCC terminal (14) and negative terminal to ground
(7) of the IC 7495.
3. In order to observe the stages of outputs connect to Q0, Q1, Q2, Q3

Part1: Serial Mode:

1. Connect the mode selection input M to ground (logic 0)

2. Connect clock cp1& cp2 to logic 1.
3. For serial shift in operation consider 4 bit word.
4. Set LSB at the serial data input. Apply clock pulse & observe the outputs.
5. Apply signal corresponding to the next higher bit, apply the clock pulse
& observe the output.
6. Repeat the procedure till all 4 bits are entered. Note that it should be
same as the 4 bit input word.
7. Write the no of clock pulses required for serial shift in operation.
8. Now connect serial input to the ground. (logic 0)
9. Determine the no. of clock pulses requires to shift the data out parallel
and serially.
Part2: Parallel Mode:

1. Connect the mode selection input M to +VCC (logic 1)

2. Connect clock cp1& cp2 to logic 1.
3. For parallel in parallel out operation consider 4 bit word.
4. Set this 4 bit to parallel data inputs(D0=1, D1= 0, D2=0, D3= 1)
5. Apply the clock pulse and observe the output.
6. For paprallel data out no clock pulse is required.
7. To shift data serially out, change the mode select input to low & serial input
to 0.
8. Apply clock to cp0 and connect to 1.
9. Determine the no of clock pulses required to shift out data serially.

Result :

Mode of operation Number of clock pulses

Serial shift mode
1. Serial in serial out

2. Serial in Parallel out

Parallel operation
1. Parallel in Parallel out

2. Parallel in Serial out

Conclusion:

Questions:

1. What is a shift register?

2. What are the types of shift register?
3. Give the applications of shift register.
 MIT Art’s, Commerce & Science College, Alandi (D)
Department of Electronics
F.Y.B.Sc (CS)Electronics Practical Sheet
Title: Diode Matrix ROM.

Aim: To study Diode Matrix ROM.

Components: Experimental kit, IC 74138, connecting wires etc.

Pin diagram of IC 74138:

IC 74138
 Truth table of IC 74138:

Address inputs Outputs

C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 0 1 1 1 1 1 1 1
0 0 1 1 0 1 1 1 1 1 1
0 1 0 1 1 0 1 1 1 1 1
0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 1 1 1 0 1 1 1
1 0 1 1 1 1 1 1 0 1 1
1 1 0 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 0

Circuit Diagram: +5V

+Vcc(5V)

6 16 15
Y0
14
Y1
13
Y2
C 3
Address 12
Y3
Inputs B 2 IC 11
74138 Y4
A 1 10
Y5
9
4 Y6
7
Y7
5 8

D3 D2 D1 D0
Observation table:

Address inputs Output Hex

C B A D3 D2 D1 D0 Value
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Test Procedure:

1. Construct the circuit as shown in figure and set +5V power supplky to the
circuit.’
2. Provide the address input 000 to 111 and observe the output voltage at data
lines and record the logic level.
3. Comment on the performance of diode.

Result:

Theory:

Diode matrix ROM is the heart of the ROM array. It is formed by connecting diode
between each row and column.

ROM having 8 location each with 3 bit diode i.e. 3 x 8 that to select 8 locations
the number of address lines must satisfy condition 2n=8 so n=3. Hence three
address lines A B C select the location.
Here IC 74138 is used as 3 to 8 line decoder. That means there are 3 address
inputs and 8 outputs are present. The output of decoder is active low.

Ex. For input 000 we get the output Y0 = 0. And other outputs are high.

A ROM can be constructed by diode matrix array. The string of the data is done
manufacturer level and not as user level. A ROM consists of an array of cell each
can be read. But the modification of the data is not possible at the user level.

Hence presence of diode indicates storage of 1 bit and absence of diode of bit 0 in
particular selected cell. A diode is placed in such a way that it shorts a particular
row with column when conducted.

Questions:

1. Explain the working of diode matrix ROM.

2. Explain 3 to 8 line decoder,
3. What is ROM? How data is stored in ROM?
4. Give the classification of memory.
5. Give the features of IC 74138.
6. What is decoder?