A NOVEL HIGH SPEED DYNAMIC COMPARATOR

WITH LOW POWER DISSIPATION FOR HIGH SPEED ADC

By

B K MOHARANA

The Department of Electronics and Communication Engineering

Abstract:
The continuous speed enhancement of the wireless communication systems brings out huge
demands in speed and power specifications of high-speed low-resolution analog-to - digital
converters. This paper proposed a design of new CMOS dynamic comparator using dual input
single output differential amplifier as latch stage suitable for high speed, low power and noise
immune analog-to-digital converters. Back-to-back inverter in the latch stage is replaced with
dual-input single output differential amplifier. This topology is used to remove the noise that is
present in the input completely. The structure shows lower power dissipation and higher speed
than the conventional comparators. The circuit is simulated with 1V DC supply voltage and
250 MHz clock frequency. The proposed topology is based on two cross coupled differential
pairs positive feedback and switchable current sources, has a lower power dissipation, higher
speed, less area, and it is shown to be very robust against transistor mismatch, noise
immunity.

Keywords: Dynamic comparator, CMOS, cadence, ADC, latch stage, differential amplifier

Introduction:
Comparators are the 2nd most widely used electronic components as compared to operational
amplifiers in this world. Comparators are also known as 1-bit analog to digital converter(ADC)
and for that is the reason why they are mostly used in A/D converter. In the process of analog
to digital conversion, first the input is sampled. The sampled output signal is then applied to a
combinational block of comparators which is used to determine the digital equivalent of the
analog input signal. The conversion speed of comparator is mostly dependant on the decision
making time of the comparator. Apart from this uses, comparators are also found in other
applications like zero-crossing and peak detectors, switching power regulators, data
transmission, BLDC operating motors, and others. The basic function of a CMOS comparator
is to detect whether a signal is greater or smaller than zero or to compare an input analog
signal with a reference signal and generates a digital signal based on comparison. The output
from the comparator is mainly a special type of digital code, called thermometer code.
 Fig-1. Schematic symbol and operation of a basic comparator

Comparator Design:
The comparator is a crucial part of almost all kind of analog-to-digital (ADC) converters.
Speed, gain, power dissipation, offset and resolution are the important parameters of any type
of comparators. The type and architecture of the comparator is having a considerable impact
on the performance of the target application. The fundamental aim of the comparator is to
compare an input signal (Vin) with a reference signal (Vref) and to produce an output logic low
or logic high depending on whether the input signal is greater or smaller than reference.
Comparator can be considered as a decision making circuit because it makes a decision
based on the value of input signal and reference signal.

Designed comparator components:

There are two comparators those have been designed. One without the clock and another
with clock. Both the comparators have 3 stages namely preamplifier, decision making and
output buffer. The preamplifier amplifies the input signal difference voltage into a higher
voltage level, in order to get better sensitivity of the comparator. It also separates the
comparator input from the decision making stage. The decision making stage generally uses
positive feedback mechanism for the operation. Positive feedback mechanism is used to
determine the larger input signal from the two inputs. The output buffer amplifies the signal
coming out from the decision making stage and generate the final digital output.
Regenerative comparators
Regenerative comparators are mainly divided into non-clocked and clocked comparators
which are briefly discussed in the following paragraphs.

Fig-2. Block diagram of designed comparator

Non-clocked comparators

In this type of comparators clock is not present. Non-clocked comparator comprises of three
stages such as preamplifier, decision making and output buffer. The preamplifier is used to
amplify the input voltage signal difference into a higher voltage level, so that better sensitivity
for the comparator can be obtained. It also blocks the comparator input from directly
connecting to the decision making stage. The decision making stage normally uses positive
feedback mechanism for the operation. Positive feedback mechanism is used to detect the
high input signal from the two input signals. The output buffer is used to amplify the signal
coming out from the decision making stage and gives the final digital output. Fig.3 shows the
circuital representation of the non-clocked comparator designed.

Clocked Comparators

Clocked comparators are often called dynamic Comparators. The speed of clocked
comparators is very high because regenerative feedback mechanism is frequently used in
these types of comparators. A clocked comparator normally consists of two stages. The first
stage interfaces input signal with reference signal. This stage determines whether the input
signal is below or above the reference signal. The second (regenerative) stage contains two
cross coupled inverters, where each input is attached to the other output. Any symmetric
structure with this cross coupling creates regenerative feedback. The clock is used to reset
the circuit and also used to get a balanced state earlier to regeneration. Clocked comparators
 are widely used in the design of high speed ADCs. The designed clocked comparator is shown
in Fig.4.

Conclusion and future work:

Modern communication systems necessitate higher data rates which have increased the
demand for the high speed transceivers. For a system to work efficiently, all blocks of that system
should be fast. It can be seen that the analog interfaces are main bottleneck in the whole system
in terms of speed and power. This fact has led researchers to develop and implement high speed
analog-to-digital converters (ADCs) with low power consumption.
The work till now demonstrates the design of the clocked and non-clocked comparator and
calculation of their parameters. The clocked comparator has less propagation delay than that of
the non-clocked one, so the speed of the clocked comparator is high. The latch circuit of the
clocked comparator is to be optimized properly so that we can get better speed than this. The
clocked comparator dissipates more power as compare to non-clocked one.

References:
[1] Philip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, 2nd ed., Oxford
Indian Edition, 2006
[2] G. T. Verghese, K.K. Mahapatra, “Design AND IMPLEMENTATION OF a Novel flash adc
for ultra wide band applications,” Ph. D Report for NIT Rourkela, India,May 2014.
[3] Prasun Bhattacharyya, K.K. Mahapatra , "Design of a novel high speed dynamic comparator
with low power dissipation for high speed ADCs," M. Tech Report for NIT Rourkela, India, May,
2011