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SCAN INSERTION

LAB OBSERVATION

SUBMITTED BY

K.S.K.S.SARMA
TEST CASE – 1
PROBLEM DEFINITION: Design has S1 violations and it should be on all inputs (clk, set, and
reset) of the flop. Fix the violation using command and also by manual edits to the netlist.

INPUTS:

 Synthesis Netlist
 Library Model
 Dofile Commands

OUTPUTS:

 Scan Inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def

What is the issue?

Design is having S1 violations. S1 violation is one in which the clocks (sets and resets included)
of non scan elements cannot be turned to off state.

How it is resolved?

It can be fixed by adding a MUX which selects between clocks in test mode and functional
mode.

OBSERVATIONS:

1) Write block diagram with all DFT inputs?


2) How many clock domains?

1 clock domain

3) How many resets?

2 resets

4) Number of scan chains

4 scan chains

5) Clock mixing or not clock mixing?

No clock mixing.

6) How many lock-up latches are added during scan insertion?

Zero lock-up latches were added during scan insertion.

7) Is it top-down or bottom-up approach?

It is Top-Down approach.

8) How many terminal lock-up latches are added?

Zero terminal lock-up latches were added.

9) Number of non-scan flops in the design?

4 non-scan flops

10) Chain length?

10 is the longest scan chain

11) Number of DRC violations?

4 S1 violations and 4 D5 violations


12) Write diagram with issues

S1 violations:

Issue: Unstable non-scan


scan cells when clocks are off.

D5 violations:

Issue: Non-scan
scan memory element

13) Write diagram with solution

After fixing S1 violation:


After fixing D5 violation:
TEST CASE -2
PROBLEM DEFINITION: Design has S2 violations and fix the violation using command and also
by manual edits to the netlist.

INPUTS:

 Synthesis Netlist
 Library model
 Dofile commands

OUTPUTS:

 Scan Inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def

What is the issue?

Design is having S2 violation. S2 violation is one in which the data at input of flop cannot be
captured with the clock due to some conditions like when the clock pin is tied to some value.

How it is resolved?

It can be fixed by connecting the clock input of flop to output of mux which selects test clock
when test enable is high and the functional clock when it is low.

OBSERVATIONS:

1) Write block diagram with all DFT inputs?


2) How many clock domains?

1 clock domain

3) How many resets?

2 resets

4) Number of scan chains

4 scan chains

5) Clock mixing or not clock mixing?

No clock mixing.

6) How many lock-up latches are added during scan insertion?

Zero lock-up latches were added during scan insertion.

7) Is it top-down or bottom-up approach?

It is Top-Down approach.

8) How many terminal lock-up latches are added?

Zero terminal lock-up latches were added.

9) Number of non-scan flops in the design?

4 non-scan flops

10) Chain length?

10 is the longest scan chain

11) Number of DRC violations?

3 C7 violations, 3 D5 violations and 3 S2 violations


12) Write diagram with issues

C7 violations:

Issue: Scan cell capture ability


lity check
check.

D5 violations:

Issue: Non-scan
scan memory element

S2 violations:

Issue: Clock capture ability check


13) Write diagram with solution

After fixing C7 violation:

After fixing D5 violation:

After fixing S2 violation:


TEST CASE – 4
PROBLEM DEFINITION: Design has bus contention. Fix the violation using command and also by
manual edits to the netlist.

INPUTS:

 Synthesis Netlist
 Library model
 Dofile commands

OUTPUTS:

 Scan Inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def

What is the issue?

Design has Bus Contention violation. Bus contention arises when there are multiple drivers
(usually with tristate buffers) disabling all drivers of the bus except 1 of the drivers.

How it is resolved?

With the command “insert test logic –tristate on” it can be resolved. This command will make
any two tristate buffers enabled with gating.

OBSERVATIONS:

1) Write block diagram with all DFT inputs?

2) How many clock domains?

1 clock domain
3) How many resets?

1 resets

4) Number of scan chains

2 scan chains

5) Clock mixing or not clock mixing?

No clock mixing.

6) How many lock-up latches are added during scan insertion?

Zero lock-up latches were added during scan insertion.

7) Is it top-down or bottom-up approach?

It is Top-Down approach.

8) How many terminal lock-up latches are added?

Zero terminal lock-up latches were added.

9) Number of non-scan flops in the design?

18 non-scan flops

10) Chain length?

10 is the longest scan chain

11) Number of DRC violations?

5 DRC violations which includes E4 and E10. E10 can’t be fixed and it won’t affect the design.
12) Write diagram with issues

E4 violation:

Issue: Bus contention during test procedure

E10 violation:

Issue: Possible bus contention

13) Write diagram with solution

These
ese violations can be ignored.
TEST CASE – 5
PROBLEM DEFINITION: Design has 1 clock domain with DFFs and latches and insert 2 scan
chains in the design.

INPUTS:

 Synthesis Netlist
 Library model
 Dofile commands

OUTPUTS:

 Scan Inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def

What is the issue?

Latches are present in the design which leads to reduced coverage.

How it is resolved?

Usually if the design is having latches, it is advisable to go for LSSD style. In this case latches are
ignored.

OBSERVATIONS:

1) Write block diagram with all DFT inputs?

No DFT pins are inserted in this case.

2) How many clock domains?

2 clock domains

3) How many resets?

1 reset

4) Number of scan chains

2 scan chains
5) Clock mixing or not clock mixing?

clock mixing.

6) How many lock-up latches are added during scan insertion?

Zero lock-up latches were added during scan insertion.

7) Is it top-down or bottom-up approach?

It is Top-Down approach.

8) How many terminal lock-up latches are added?

Zero terminal lock-up latches were added.

9) Number of non-scan flops in the design?

56 non-scan flops are available in the design and 2 non-scan flops are ignored for scannable
check.

10) Chain length?

27 is the longest scan chain

11) Number of DRC violations?

34 DRC violations which include C8, C9 and D5 but these violations can be ignored.

12) Write diagram with issues

These violations can be ignored.

13) Write diagram with solution

These violations can be ignored.


TEST CASE – 6
PROBLEM DEFINITION: Design has 1 clock domain with only Scan FFs and insert 3 scan chains in
the design.

INPUTS:

 Synthesis Netlist
 Library model
 Dofile commands

OUTPUTS:

 Scan Inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def

What is the issue?

The number of scan chains should be made equal to 3.

How it is resolved?

With the command “insert_test_logic –number 3” it can be done.

OBSERVATIONS:

1) Write block diagram with all DFT inputs?

2) How many clock domains?

1 clock domain
3) How many resets?

1 reset

4) Number of scan chains

3 scan chains

5) Clock mixing or not clock mixing?

No clock mixing.

6) How many lock-up latches are added during scan insertion?

Zero lock-up latches were added during scan insertion.

7) Is it top-down or bottom-up approach?

It is Top-Down approach.

8) How many terminal lock-up latches are added?

Zero terminal lock-up latches were added.

9) Number of non-scan flops in the design?

102 non-scan flops

10) Chain length?

34 is the longest scan chain

11) Number of DRC violations?

Zero DRC violations.

12) Write diagram with issues

Zero DRC violations.

13) Write diagram with solution

Zero DRC violations.


TEST CASE – 7
PROBLEM DEFINITION: Design has no ATPG model for a Flip flop used in the netlist, later create
the model and insert scan with 2 scan chains.

INPUTS:

 Synthesis Netlist
 Library model
 Dofile commands

OUTPUTS:

 Scan Inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def

What is the issue?

The design has no ATPG model for a Flip-Flop used in the netlist.

How it is resolved?

The library team should provide the library model files. Then the problem can be resolved.

OBSERVATIONS:

1) Write block diagram with all DFT inputs?

2) How many clock domains?

1 clock domain

3) How many resets?

No reset in the design.


4) Number of scan chains

2 scan chains

5) Clock mixing or not clock mixing?

No clock mixing.

6) How many lock-up latches are added during scan insertion?

Zero lock-up latches were added during scan insertion.

7) Is it top-down or bottom-up approach?

It is Top-Down approach.

8) How many terminal lock-up latches are added?

Zero terminal lock-up latches were added.

9) Number of non-scan flops in the design?

14 non-scan flops

10) Chain length?

7 is the longest scan chain.

11) Number of DRC violations?

Zero DRC violations.

12) Write diagram with issues

Zero DRC violations

13) Write diagram with solution

Zero DRC violations


TEST CASE – 8
PROBLEM DEFINITION: Design has 1 clock domain and a 10bit shift register. Insert scan for the
design and make the 10bit shift register has part of the scan chain without converting it to Scan
FFs. Use 2 scan chains with new ports for scan in and scan out.

INPUTS:

 Synthesis Netlist
 Library model
 Dofile commands

OUTPUTS:

 Scan Inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def

What is the issue?

The shift register should be added in the scan chain with converting it into scan Flip-Flop.

How it is resolved?

If the entire design is a shift register with no combo logic then the scan insertion chain and only
continuity has to be verified in this case.

OBSERVATIONS:

1) Write block diagram with all DFT inputs?

2) How many clock domains?

1 clock domain
3) How many resets?

1 reset

4) Number of scan chains

2 scan chains

5) Clock mixing or not clock mixing?

No clock mixing.

6) How many lock-up latches are added during scan insertion?

Zero lock-up latches were added during scan insertion.

7) Is it top-down or bottom-up approach?

It is Top-Down approach.

8) How many terminal lock-up latches are added?

Zero terminal lock-up latches were added.

9) Number of non-scan flops in the design?

Zero non-scan flops

10) Chain length?

41 is the longest scan chain

11) Number of DRC violations?

Zero DRC violations.

12) Write diagram with issues

Zero DRC violations.

13) Write diagram with solutions

Zero DRC violations.


TEST CASE – 9
PROBLEM STATEMENT: Design has 1 clock domain, insert 2 scan chains for design containing 2
memories but no memory BIST or collar around the memory

INPUTS:

 Synthesis Netlist
 Library model
 Dofile commands

OUTPUTS:

 Scan Inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def

What is the issue?

During scan insertion, memories are to be black boxed.

How it is resolved?

By using the command, “add_black_boxes –auto”, it can be resolved.

OBSERVATIONS:

1) Write block diagram with all DFT inputs?

2) How many clock domains?

1 clock domain

3) How many resets?

0 resets
4) Number of scan chains

2 scan chains

5) Clock mixing or not clock mixing?

No clock mixing.

6) How many lock-up


up latches are added during scan insert
insertion?

Zero lock-up
up latches were added during scan insertion.

7) Is it top-down or bottom-up
up approach?

It is Top-Down approach.

8) How many terminal lock-up


up latches are added?

Zero terminal lock-up


up latches were added.

9) Number of non-scan
scan flops in the desig
design?

77 non-scan flops

10) Chain length?

39 is the longest scan chain

11) Number of DRC violations?

77 D7 DRC violations.

12) Write diagram with issues

Issue: Set and Reset pins of Flip-Flops


Flops are connected to ground.

13) Write diagram with solutions

These violations can be ignored.


TEST CASE – 10
PROBLEM DEFINITION: Design has modules where in block1 is already scan inserted with 4 scan
chains. Insert scan for other blocks with 4 chains. Balance the scan chains for the entire design
from the top module using 4 chains.

INPUTS:

 Synthesis Netlist
 Library model
 Dofile commands

OUTPUTS:

 Scan Inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def

What is the issue?

The specific block which is already scan-inserted should be re-inserted again.

How it is resolved?

Specify the sub chains (with add subchains) which are already present in the modules with their
length, scan-in, scan-out so that tool won’t touch these chains and just include them in the new
scan chains.

OBSERVATIONS:

1) Write block diagram with all DFT inputs?

2) How many clock domains?

1 clock domain
3) How many resets?

2 resets

4) Number of scan chains

4 scan chains

5) Clock mixing or not clock mixing?

clock mixing.

6) How many lock-up latches are added during scan insertion?

Two lock-up latches were added during scan insertion.

7) Is it top-down or bottom-up approach?

It is Bottom-Up approach.

8) How many terminal lock-up latches are added?

Zero terminal lock-up latches were added.

9) Number of non-scan flops in the design?

17 non-scan flops

10) Chain length?

53 is the longest scan chain

11) Number of DRC violations?

2 C2, 2 T24 and 2 D5 DRC violations.

12) Write diagram with issues

D5 violations:

Issue: Non-scan memory element


C2 violations:

Issue: Clock reachability check

13) Write diagram with solutions

D5 violations can be ignored.


TEST CASE – 11
PROBLEM DEFINITION: Design has 2 modules block1 and block2. Insert 4 scan chains for the
design by ignoring block2 and insert lockup latches at end of chains

Top

|___block1

|___block2

INPUTS:

 Synthesis Netlist
 Library model
 Dofile commands

OUTPUTS:

 Scan Inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def

What is the issue?

A block should be ignored during scan insertion.

How it is resolved?

By using the command “add nonscan instance –module [module name]”, it can be resolved.

OBSERVATIONS:

1) Write block diagram with all DFT inputs?


2) How many clock domains?

1 clock domain

3) How many resets?

0 resets

4) Number of scan chains

4 scan chains

5) Clock mixing or not clock mixing?

No clock mixing.

6) How many lock-up latches are added during scan insertion?

Zero lock-up latches were added during scan insertion.

7) Is it top-down or bottom-up approach?

It is Bottom-Up approach.

8) How many terminal lock-up latches are added?

Four terminal lock-up latches were added.

9) Number of non-scan flops in the design?

183 non-scan flops

10) Chain length?

38 is the longest scan chain

11) Number of DRC violations?

4 D5 DRC violations.
12) Write diagram with issues

D5 violations:

Issue: Non-scan memory element

13) Write diagram with solutions

D5 violations can be ignored.


TEST CASE – 12
PROBLEM DEFINITION: Design has 3 clocks (one +ve, one –ve, one using both edges)

a) Use default scan insertion

b) Mix clock domains and insert scan

c) Mix edges, clock domains and insert scan

d) Use a single test clock and insert 4 scan chains

INPUTS:

 Synthesis Netlist
 Library model
 Dofile commands

OUTPUTS:

 Scan Inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def

What is the issue?

For 12(a): Normal scan insertion should be done for the given netlist.

For 12(b): The clock domains should be mixed and the scan should be done.

For 12(c): Along with clock mixing and inserting scan, edge mixing should also be done.

For 12(d): With single clock, all the 4 scan chains should be stitched.

How it is resolved?

For 12(a): By using the command, “set test logic -set on -reset on -clock on -ram on -bidi off”,
the scan insertion was done.

For 12(b): By using the commands, “set lockup latch on “and “insert test logic -ram on -clock
merge” clock mixing was done.

For 12(c): By using the commands, “set lockup latch on” and “insert test logic -ram on -clock
merge -edge merge”, clock mixing and edge mixing are done.
For 12(d): By using a single clock for the whole design and with the command, “insert test logic
–number 4”, all the 4 scan chains were stitched.

OBSERVATIONS:

1) Write block diagram with all DFT inputs?

For 12(a):

For 12(b):

For 12(c):

For 12(d):
2) How many clock domains?

For 12(a): 4 clock domains

For 12(b): 2 clock domains

For 12(c): 1 clock domain

For 12(d): 2 clock domains

3) How many resets?

For 12(a): 2 resets

For 12(b): 2 resets

For 12(c): 2 resets

For 12(d): 2 resets

4) Number of scan chains

For 12(a): 4 scan chains

For 12(b): 2 scan chains

For 12(c): 1 scan chain

For 12(d): 4 scan chains

5) Clock mixing or not clock mixing?

For 12(a): clock mixing

For 12(b): clock mixing

For 12(c): non clock mixing

For 12(d): clock mixing


6) How many lock-up latches are added during scan insertion?

For 12(a): Zero lockup latches

For 12(b): 2 lockup latches

For 12(c): 2 lockup latches

For 12(d): Zero lockup latches

7) Is it top-down or bottom-up approach?

For 12(a): Top-Down Approach

For 12(b): Top-Down Approach

For 12(c): Top-Down Approach

For 12(d): Top-Down Approach

8) How many terminal lock-up latches are added?

For 12(a): Zero terminal lockup latches

For 12(b): Zero terminal lockup latches

For 12(c): Zero terminal lockup latches

For 12(d): Zero terminal lockup latches

9) Number of non-scan flops in the design?

For 12(a): 2 non-scan flops

For 12(b): 2 non-scan flops

For 12(c): 2 non-scan flops

For 12(d): 67 non-scan flops


10) Chain length?

For 12(a): Longest scan chain has 63 scan cells

For 12(b): Longest scan chain has 87 scan cells

For 12(c): Longest scan chain has 128 scan cells

For 12(d): Longest scan chain has 41 scan cells

11) Number of DRC violations?

For 12(a): 17 C3, 16 C8, 16 C9, 2 D5 and 41 D7 DRC violations

For 12(b): 17 C3, 16 C8, 16 C9, 4 D5 and 41 D7 DRC violations

For 12(c): 17 C3, 16 C8, 16 C9, 4 D5 and 41 D7 DRC violations

For 12(d): 6 C3, 16 C8, 16 C9, 2 D5 and 7 D7 DRC violations

12) Write diagram with issues

For 12(a): These DRC violations can be ignored.

For 12(b): These DRC violations can be ignored.

For 12(c): These DRC violations can be ignored.

For 12(d): These DRC violations can be ignored.

13) Write diagram with solutions

For 12(a): These DRC violations can be ignored.

For 12(b): These DRC violations can be ignored.

For 12(c): These DRC violations can be ignored.

For 12(d): These DRC violations can be ignored.