By Chunping Song, IC Design Engineer,
National Semiconductor, Santa Clara, Calif.
In voltage-mode, hysteretic-controlled dc-dc
converters, output capacitor-induced ripple and
loop delay are the key sources of error in output
voltage regulation.
H
ysteretic control, also known as bang-bang
control or ripple regulator control, maintains
the converter output voltage within the
hysteresis band centered about the reference
voltage. The hysteretic-controlled regulator
is popular because of its inexpensive, simple and easy-to-use
architecture. The greatest benefits of hysteretic control are
that it offers fast load transient response and eliminates the
need for feedback-loop compensation. The other well-known
characteristic is the varying operating frequency.[1-4]
However, the regulation inaccuracy issue of the hysteretic-
controlled converter is almost unknown to engineers.
Until now, research on hysteretic regulators has mainly
focused on transient analysis and transient modeling.[1-3]
The first analysis of accuracy was performed on a current-
mode hysteretic regulator specifically designed to power
microprocessors.[5] However, the regulation accuracy of
the more widely used voltage-mode hysteretic-controlled
regulators is still unknown.
By analyzing operation of the voltage-mode hysteretic-
controlled regulator, the root cause of its inaccuracy can
be identified. This analysis also reveals how operating
conditions (input voltage [VIN]; output voltage [VOUT];
and loop delay [tD]), component sizes (inductor L, output
capacitor C) and parasitic parameters (ESR, ESL, RDS(ON),
DCR, etc.) affect the accuracy of dc regulation. Most
importantly, this analysis influences the design process for
hysteretic-controlled dc-dc converters and enables practical
design tradeoffs to be made.
Sources of Inaccuracy
Fig. 1 shows a simplified hysteretic-controlled voltage
regulator and its ideal operating waveforms with only ESR-
caused output voltage ripple considered. If output voltage
VO(t) is at or below the level of the reference VREF minus the
hysteresis VHYS, output of the hysteretic comparator is high and
Power Electronics Technology February 2006
then Q2 is turned off and Q1 is turned on. This is the power
stage on-state and it causes the output voltage to increase.
When the output voltage VO(t) reaches or exceeds the
reference VREF plus the hysteresis VHYS, the output of the
hysteretic comparator turns low and then Q1 is turned off
and Q2 is turned on. This is the power stage off-state, and it
causes the output voltage to decrease. This hysteretic method
of control keeps output voltage within the hysteresis band
around the reference voltage, which leads the dc value of
output voltage to be the reference voltage, namely VO=VREF ,
without any dc offset.
This conclusion is based on the assumptions that there
is only ESR-caused output voltage ripple and that all
components used are ideal. However, in practical applications,
these assumptions are wrong. Output voltage ripple also
includes output capacitor CO-caused ripple and ESL-caused
ripple. And all components used are not ideal, so there will
be delay in the whole control loop. Given these realities, can
the dc regulation accuracy of a typical hysteretic-controlled
regulator used in real applications be guaranteed?
Effects of ESL-Caused and CO-Caused Ripple
It is well known that output voltage ripple has three
elements. The three elements of the output capacitor
that contribute to output voltage ripple are ESR, ESL and
capacitor CO. Assume that all three elements are in series
and there are no other parasitic components to consider.
Fig. 2 shows the voltage waveforms across each component
of the output capacitor. These waveforms are described by
the following equations. These equations define the ESR
voltage components differently depending on whether the
high-side MOSFET Q1 is turned on or the low-side MOSFET
Q2 is turned on.
The voltage waveform across ESR with Q1 turned on is:
 ∆I × t ∆I 
VESR = E
ESR  −
 D × TS 2 
14 www.powerelectronics.com
 HYSTERETIC CONTROL

VIN
Driver
Q1 -V
ESR O
L VO V –V L
ESR IN O
SW L
Q2 iL VO(t) VHYS
CO
VREF
ESR VHYS
Hysteretic
Comparator tON tOFF
ESL
OUT – TS
+
VREF

(a) (b)

Fig. 1. A simplified schematic demonstrates operation of the hysteretic voltage-mode voltage regulator (a) with waveforms (b) depicting
ideal operation.

With Q2 turned on, that value becomes:

iCO tD
 ∆I ∆I × t 
VESR = ESR
ESR  −
VHYS  2 (1 − D)TS 
∆I
tD VHYS t
Similarly, the voltage waveform across the ESL when Q1
(a)
is on is: ESL L × ∆I
VESL =
VESR
D × TS
which, when Q2 is on, becomes:
ESLL × ∆I
t
VESL =
(b) (1 − D)TS
The last component of the ripple voltage waveform is the
VESL voltage waveform across an ideal capacitor with an initial
value at the beginning of high-side Q1 on-time of:
∆I × t 2 ∆I × t
(c)
t VCO = −
2C O × D × TS 2C O
VCO which, at the beginning of low-side Q2 turn on,
becomes: ∆I × t ∆I × t 2
t
VCO = −
(d) 2C O 2C O (1 − D)TS

VO tD From those components, the output voltage ripple

waveform can be described as:
VO = VESR + VESL + VCO
tD t The ripple component from ESL causes the voltage steps;
(e)
ESR causes the ramps; and capacitance causes the curvature
tON tOFF in the ripple voltage during the switching transitions.[4]
TS First, let’s consider the effect of ESL-caused ripple on the
dc accuracy. Assume that ESL-caused voltage step is smaller
than VHYS and Fig. 3 shows the output voltage waveform with
Fig. 2. A current through the output capacitor (a) produces three
separate ripple voltage waveforms—the voltage across the ESR (b), only ESR- and ESL-caused ripple considered. From this figure,
the voltage across the ESL (c) and the voltage across an ideal capacitor we can see that the output voltage’s peak ripple above VREF
with an initial value at the beginning of the high-side Q1 on-time (d). is equal to VHYS, and the output voltage’s valley ripple below
The sum of these three voltages is the composite output voltage VREF is equal to VHYS, too. Then the dc value of output voltage
ripple (e). is still regulated at VREF without any offset. So ESL-caused

Power Electronics Technology February 2006 16 www.powerelectronics.com

 HYSTERETIC CONTROL
ripple has no effect on the dc regulation accuracy as long as
it is smaller than the hysteresis band.
Next, let’s consider the output capacitor C O-caused
ripple’s effect on the dc accuracy. There are two cases that
need to be considered. The first case is that CO is big and
so CO-caused output ripple is small compared with ESR-
caused ripple. The output voltage waveform in this case is
shown in Fig. 4. Here we can see that output ripple is not a
ramp anymore and it has second-order curvature caused by
CO-caused ripple. But the output voltage’s peak and valley
value is still decided by ESR-caused ripple.
Achieve higher performance from transformers with
In this case, the output voltage’s peak ripple above VREF is
equal to VHYS, and the output voltage’s valley ripple below VREF
is equal to VHYS , too. So, the dc value of the output voltage
is still regulated at VREF without any offset. That means CO-
caused ripple has no effect on the dc regulation accuracy
as long as it does not change the ESR-caused peak value of
output ripple voltage.
In the second case, where CO is not very big, CO-caused
output ripple cannot be ignored when compared with
ESR-caused output ripple. The output voltage waveform
in this case is shown in Fig. 5. From this figure, we can
see the curvature of ripple is obvious and
the output voltage’s peak ripple does not
happen at the end of on-time anymore. Now
the output voltage’s peak ripple happens
at the same time during off-time, and it is
decided by both CO-caused and ESR-caused
ripple. In this case, the output voltage’s peak

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ripple above VREF is higher than VHYS, and the
output voltage’s valley ripple below VREF is
still equal to VHYS. Therefore, the dc value
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BRIDGE TRANSFORMER
VOS=0.5(VPEAK_OFF - VHYS).
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Surprisingly for the hysteretic-controlled regulator, CO
may influence the dc regulation accuracy
powerful depending on CO’s value. In the following
analysis, the range of CO’s value for the
360 watts
second case and the output voltage dc offset
RESONANT TRANSFORMER in this case are provided.
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power supplies using ON Semiconductor From the ripple equations given for
MC34067 resonant mode controller
Fig. 2, the ripple of output voltage during
off-time when only ESR- and CO-caused
ripple are considered is:
VO _ OFF (t) = VESR (t) + VCO (t) =
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From Eq. 2, we get:

(1 − D)TS
t OFF _ MAX = − ESR
ESR × C O (Eq. 3)
2

Power Electronics Technology February 2006 18 www.powerelectronics.com

 HYSTERETIC CONTROL EXACTING
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PROTECTION

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TS

Fig. 4. For large values of output capacitance, CO-caused ripple has no

effect on the dc regulation accuracy.

Inserting Eq. 3 into Eq. 1, we can get the peak value of

output voltage ripple during off-time:
Astronics is the leader in advanced electrical
VPEAK _ OFF = VO _ OFF (t OFF _ MAX)=
MAX
power systems for the very light jet market
∆I × ESR
ESR 2 × C O ∆I(1 − D)TS (Eq. 4) and other aircraft power subsystems.
+
2(1 − D)TS 8C O Our company is built around power supply
Therefore, the case where the output ripple voltage’s expertise. We are continually looking for the
peak value occurs during the off-time happens when best power supply engineers. Bring your skills
to our team and see how your contribution can
V P E A K _ O F F is higher than the upper hysteresis band
make a real difference.
VHYS(VHYS0.5ESRI). Then from Eqs. 3, 4 and 0 t 
(1-D)TS , we can derive the boundary of CO when VPEAK_OFF
is higher than VHYS : Be a part of a
CO ≤ CB =
(1 − D)TS (Eq. 5) company
2ESR
The dc offset of output voltage under this condition is:
1  ESRR × CO (1 − D)TS 
VOS ≈ VHYS
HYS  + − 1 (Eq. 6)
2  (1 − D)TS 4C O × EESR 

The Effect of Delay

In a hysteretic-controlled regulator, one important Visit our website
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nonideal factor is the loop delay. Fig. 6 shows the output for job opportunities
voltage waveform with only delay and ESR-caused ripple

www.powerelectronics.com 19 Power Electronics Technology February 2006

 HYSTERETIC CONTROL

VOV
VO (t)

VO (t)
VPEAK _ OFF tDR
VHYS VHYS

VREF t VREF t
VOS _ TD
VOS VHYS tDF VHYS

tON tOFF VUV

tON tOFF
TS
TS

Fig. 5. When the value of CO is too low, CO-caused ripple degrades the Fig. 6. Loop delay produces an offset in the output voltage ripple
dc regulation accuracy by producing an offset in the output voltage waveform.
ripple waveform.
VHYS = 21 mV and load current IO = 1 A.
considered. From this figure, we can see that the output The operating frequency (fSW) and other performance
voltage’s peak ripple above VREF is greater than VHYS, and the characteristics of a hysteretic-controlled regulator depend
magnitude of the output voltage’s valley ripple below VREF on external conditions and components. The best approach
is also greater than VHYS. From Fig. 6,, we can see that VOV, is first to determine what operating frequency is desirable
the overshoot over upper hysteresis band VHYs, and VUV, the in the application. In this example, we assume the accepted
undershoot over lower hysteresis band VHYS, are: operating frequency range is 200 kHz  fSW  400 kHz.
From the operating frequency estimation equation given
VIN − VO V
VOV = ESR × t DR , VUV = O ESR × t DF (Eq. 7) in reference 4 at the end of this article:
L L t
Then the dc value of output voltage, VOS_DELAY , is: (
VO VIN − VO ESR )(
ESR − d
CO
)
1 f SW = (Eq. 10)
VOS _ DELAY =
DELAY (VOV − VUUVV ) = VIN (VIN × ESR × t D + VHHYS
ESR YS × L − ES L × VIN )
ESL
2
1 ESR((VIN − VO )t DR − VO × t DF ) (Eq. 8) It is important that ESL meet the following condition:
× ESL<ESRtD+VHYSL/VIN. If it does not, the switching
2 L
frequency becomes too high and uncontrollable. If CO is big
If we assume the rising delay time and the falling delay enough and ESL is small enough, Eq. 10 can be simplified
time are the same, namely tDR=tDF=tD , then: to be:
1 ESR × t D (VIN − 2 VO ) (Eq. 9) f SW =
(
VO VIN − VO E ESR)
Y = ×
VOS _ DELA (Eq. 10a)
DELAY
2 L VIN (VIN × ESR × t D + VHHYS
ESR YS × L)

From Eq. 9, we can see that the only time there is no dc The peak-to-peak voltage ripple estimation is:
offset is when VIN=2VVO, namely when the duty cycle is 50%.
Under any other operating conditions, there will always be VIN
VPK − PK = VHYS + R × tD
ESR
dc regulation offset caused by loop delay. And this offset is L
higher for lower inductance L, higher ESR, delay and the Assume in this example that the peak-to-peak voltage
difference between VIN and VO. ripple estimation is smaller than VRIPPLE_SPEC=40 mV. Then
we have:
Design Flow V
VPK − PK = VHYS + IN ESR
R × t D ≤ VRIPPLE _ SPEC = 40 mV
From the previous analysis, we can see that hysteretic- L
controlled regulators may have inaccuracy issues in real (Eq. 11)
applications. This inaccuracy is caused mainly by output Eqs. 10 and 11 show that the switching frequency and the
voltage ripple elements other than ESR-caused ripple and by output ripple strongly depend on L, ESR and ESL.
loop delay. In this section, a design example is presented to The minimum inductance can be calculated using the
demonstrate a design flow for hysteretic voltage regulators following equation:
that accounts for sources of dc error. VIN − VD − VO VO
In this example, the hysteretic voltage regulator shown L= × (Eq. 12)
in Fig. 1a is used. And because the LM3475 hysteretic PFET ∆I VIN × f SW
buck controller is used, Q1 and Q2 in Fig. 1a should be where I is the allowable inductor ripple current and
changed to a PFET and a diode, respectively.[6] The design VD is the forward voltage drop of the diode. The maximum
condition and target is: 5 V < VIN < 10 V, VO = VREF = 0.8 V, allowable inductor ripple current should be calculated as a

Power Electronics Technology February 2006 20 www.powerelectronics.com

 HYSTERETIC CONTROL

Tek Stop [ ]
input capacitor, diode and MOSFET, it is the same as that
: 30.4 mV in the normal selection process. Bench test results for the
@ : 795 mV
component values selected previously are presented in Fig.
7. In Fig. 7, channel 1 is the switch node waveform and
channel 3 is the output voltage. From Fig. 7, we can see circuit
operation meets the design goal. PETech
1

Ch1 Freq References

344.0 kHz
1. Miftakhutdinov, R. “An Analytical Comparison of
Alternative Control Techniques for Powering Next
3 Generation Microprocessors,” TI Seminar, 2002.
2. Yan, Liu, and Sen, P.C. “Large-Signal Modeling of
Hysteretic Current-Programmed Converters,” IEEE Trans.
on Power Electronics, Vol. 11, No. 3, 1996, pp. 423-430.
Ch1 5.00 V BW M 1.00 µs A Ch1 4.20 V 3. Tso, C., and Wu, J. “A Ripple Control Buck Regulator with
Ch3 20.0 mV BW
16 Jan 2006
4.000% 16:48:26 Fixed Output Frequency,” IEEE Power Electronics Letters,
Fig. 7. Measurements of the switch node waveform (Ch1) and the output
Vol. 1, No. 3, 2003, pp. 61-63.
voltage (Ch3) of the test circuit confirm that the selected component 4. “Designing Fast Response Synchronous Buck Regulators
values satisfy the design requirements. Using the TPS5211,” User’s Guide, Texas Instruments, June
2000.
function of output current as shown here: 5. Song, C., and Nilles, J. “Accuracy Analysis of Hysteretic
IMAX=IOUT0.3=0.3 A Current-Mode Voltage Regulator,” Proc. IEEE APEC, 2005,
Then, by Eq. 12 with fSW=300 kHz, the inductance L is pp. 276-280.
chosen to be L=10 H. 6. “LM3475 Datasheet,” National Semiconductor Corp.,
Once the inductance value and the desired operating January 2005.
frequency are selected, ESR must be selected based on
Eq. 10 or 10a. By using Eq. 10a and tD100 ns for the
required operating frequency range, ESR needs to be 70
m  ESR  170 m. Here we choose ESR=100 m.
And this ESR value also needs to satisfy the ripple requirement
given in Eq. 11.
Based on the previous analysis of CO-caused ripple, CO’s
affect on the dc regulation accuracy and operating frequency
can be eliminated, if for duty cycle D < 0.5:
(1 − D) Astronics is the leader in aircraft cabin power
CO ≥ CB = (Eq. 13)
2ESR × f SW systems and other aircraft power subsystems.
This equation dictates that C O 23 F F for f SW =200 Our company is built around power supply
kHz and CO11 F F for fSW=400 kHz. Here we can choose expertise. We are continually looking for the
CO=47 F, CO=100 F or CO=22 F. Eq. 13 is a conservative best power supply engineers. Bring your skills
estimation of the critical output capacitance because its to our team and see how your contribution can
make a real difference.
derivation does not consider the turn-on and turn-off delay.
So in real application, CO can be 22 µF without any affect
on dc accuracy.
Be a part of a
Once CO’s choice satisfies Eq. 13, the dc regulation company
inaccuracy is mainly caused by the loop delay. In this case,
the dc output voltage offset is:
1 0.5 VIN − VO
VOS = VHYS + ESR × t D ≤ 15 mV (Eq. 14)
2 L
This offset will be higher when L is lower, ESR is higher,
delay is longer, and the difference between VIN and VO is
greater. If this inaccuracy is not tolerable, the above design
steps need to be repeated. Sometimes, it may take several Visit our website
www.astronics.com
iterations to satisfy all requirements. for job opportunities
As for the selection of other components, such as the

www.powerelectronics.com 21 Power Electronics Technology February 2006