Power Lab Manual Jigar Original Last Pe PDF

POWER ELECTRONICS DEVICE AND CIRCUIT (2161006) YEAR 2019
EXPERIMENT: 1
V-I Characteristic and Measurement of latching/holding current of SCR.
 AIM: Study the V-I characteristic and measurement of latching and holding current of SCR.
 APPARATUS: Trainer kit, Connecting probes, Multi-meter (3 Nos.).
 THEORY:
The circuit symbol in the left hand side inset defines the polarity conventions of the variables
used in figure 2.1. With ig = 0, VAK has to increase up to forward break over voltage VBRF
before significant anode current starts flowing. However at VBRF forward break over takes
place and the voltage across the SCR drops to VH (holding voltage). Beyond this point
voltage across the SCR (VAK) remains almost constant at VH (1-1.5v) while the anode
current is determined by the external load.
Figure 1.1: Characteristic of THYRISTOR
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The magnitude of gate current has a very strong effect on the value of the break over
voltage as shown in the figure 1.1 above. After “Turn ON” the SCR is no more affected
by the gate current.
Hence, any current pulse (of required magnitude) which is longer than the minimum
needed for “Turn ON” is sufficient to effect control. The minimum gate pulse width is
decided by the external circuit and should be long enough to allow the anode current to
rise above the latching current (IH) level. The left hand side of figure above shows the
reverse i-v characteristics of the SCR. Once the SCR is ON the only way to turn it OFF is
by bringing the SCR current below holding current (IH). The gate terminal has no control
over the turn OFF process. In ac circuits with resistive load this happens automatically
during negative zero crossing of the supply voltage. This is called “natural commutation ”
or“ line commutation”. However, in dc circuits some arrangement has to be made to
ensure this condition. This process is called “forced commutation”. During reverse
blocking if ig= 0 then only reverse saturation current Is flows until the reverse voltage
reaches reverse break down voltage (VBRR). At this point current starts rising sharply.
Large reverse voltage and current generates excessive heat and destroys the device. If Ig>
0 during reverse bias condition the reverse saturation current rises. This can be avoided
by removing the gate current while the SCR is reverse biased. Following definitions are
useful in studying the characteristic of THYRISTOR.
1. Break Over Current (IBO) - Principle current at the break over point.
2. Break Over Voltage (VBO) - Principle voltage at the break over point.
3. Gate Trigger Current (IGT) - Minimum gate current required to maintain the SCR in
the on state.
4. Holding Current (IH) - Minimum principle current required to maintain the SCR in
the on state.
5. Latching Current (IL) - Minimum principal current required to maintain the SCR in
the on state. Immediately after the switching from off state to on state has occurred and
the triggering signal has been removed.
6. On-state Voltage (VT) - Principle voltage when the SCR is in the on state.
7. Gate Trigger Voltage (VGT) - Gate voltage required to produce the gate trigger
current.
8. On-state Current (IT) - Principle current when the SCR is in the on state.
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Figure 1.2: Pictorial view
 PROCEDURE:
1. Connect voltmeter across anode-cathode terminal, ammeter in series with gate supply and
anode supply as shown by the dotted terminal on the trainer kit.
2. Vary the POT3 and set the gate current IG.
3. Now gradually increase the anode-cathode voltage VAK by varying the POT4 till the
SCR get turned on, note down the ammeter current IA, Anode-cathode voltage VAK
readings. Also find BREAK-OVER voltage VBR.
4. For different values of gate current IG note the values of VAK, IA and tabulate them.
5. For measuring latching current, put both POT3 and POT4 in minimum condition and
switch ON the switch. Increase anode cathode voltage VAK slightly, and apply gate
voltage. Some anode current will flow. If this current is less then latching current
removing gate voltage will make this anode current zero.
6. Apply more VAK and apply gate and remove gate and check whether SCR is latched or
not. Increase VAK further in small steps, at some value of anode current after removing
of gate voltage also the SCR will remain in on state; this minimum value of anode current
is the latching current of the SCR.
7. For measuring holding current, apply maximum VAK and apply gate voltage. High value
of anode current which is more than latching current will flow. Remove gate voltage, as
the SCR is latched anode current will continue to flow.
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 MULTISIM SIMULATION:
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 OBSERVATION TABLE:
Gate current: 𝐈𝐆 Anode to cathode voltage : 𝐕𝐀𝐊 Anode current: 𝐈𝐀

4 mA 1.809 V 16 mA
4.8 mA 1.800 V 16 mA
24 mA 1.774 V 08 mA
 Latching Current IL = 23 mA  Holding current IH = 21.5 mA

 Gate current IG = 23 mA  Break over voltage VBRO = 2.5V
 CONCLUSION: After performing this practical we are learning that the SCR is
becomes turn on since gate voltage is applied to it. And we have measured holding
current and latching current.
SIGNATURE
DATE
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EXPERIMENT: 2
To Study the V-I characteristic of TRIAC.
 AIM: Study the V-I characteristic of TRIAC.

 THEORY :
From a functional point of view a TRIAC is similar to two THYRISTORS connected in

anti-parallel. Therefore, it is expected that the V-I characteristics of TRIAC in the 1st and
3rdquadrant of the V-I plane will be similar to the forward characteristics of a
THYRISTORS.
(a)
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(b)
Figure 2.1: Characteristic of TRIAC
Figure 2.2: Operation of TRIAC in four quadrants
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As shown in figure 2.2, with no signal to the gate the TRIAC will block both half cycle of
the applied ac voltage provided its peak value is lower than the break over voltage (VBO)
of the device.
However, the turning on of the TRIAC can be controlled by applying the gate trigger
pulse at the desired instance.
Mode-1triggering is used in the first quadrant where as Mode-3 triggering is used in the
third quadrant. As such, most of the THYRISTORS characteristics apply to the TRIAC
(i.e. latching and holding current). However, in a TRIAC the two conducting paths (from
MT1 to MT2 or from MT2 to MT1) interact with each other in the structure of the
TRIACS. Therefore, the voltage, current and frequency ratings of TRIACS are
considerably lower than THYRISTORS.
At present TRIACS with voltage and current ratings of 1200V and300A (rms) are
available. TRIACS also have a larger on state voltage drop compared to a THYRISTOR.
Manufacturers usually specify characteristics curves relating rms device current and
maximum allowable case temperature.
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 PROCEDURE:
1. Follow the general practical procedure as given in section 3.4. Do not connect supply and
connect TRIAC for characteristic study. Now switch ON the circuit.
2. For observing characteristic in 1st quadrant put the MODE selection switch on 1st
quadrant side.
3. Vary the POT3 and set the gate current IG to some value.
4. Gradually increase the MT2-MT1 voltage VMT2MT1by varying the POT4 till the TRIAC
is turned on, note the voltage VMT2MT1, Current IMT2 reading and tabulate them.
5. Now measure the BREAKOVER voltage VB01.
6. Further increase the VMT2 MT1 voltage and note the current IMT2.
7. To measure the reverse characteristic of TRIAC alternate the switch 1ST quadrant to 3RD
quadrant on the trainer kit and repeat the steps 3 to 6..
8. To measure the latching current IL, holding current IH repeat the same step as performed
in the practical 5.
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 OBSERVATION:
 IN FORWARD CONDITION:
𝐈𝐆 𝐕𝐌𝐓𝟐−𝐌𝐓𝟏 𝐈𝐀
12 mA 1.931 V 160 mA
24 mA 1.895 V 80 mA
 IN REVERSE CONDITION:
𝐈𝐆 𝐕𝐌𝐓𝟏−𝐌𝐓𝟏 𝐈𝐀
4.8 mA 971.108 mV 8 mA
24 mA 965.077 mV 40 mA
 Latching Current I L = 12 mA  Holding current IH = 10 mA

 Gate current IG= 12 mA  Break over voltage VBRO = 2.5V
 CONCLUSION: After performing this practical we are learning the V-I characteristics
of TRIAC in 1St And 3rd quadrant of V-I plan.
Signature
Date
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EXPERIMENT: 3
Study of the V-I Characteristic of DIAC.
 AIM: Study of the V-I characteristic of DIAC.

 THEORY:
A DIAC is an important member of the THYRISTOR family and is usually employed for
triggering. A DIAC is a two-electrode bidirectional avalanche diode which can be
switched from off-state to the on-state for either polarity of the applied voltage. This is
just like a TRIAC without gate terminal, as shown in figure 2.4. Again the terminal
designations are arbitrary since the DIAC, like TRIAC, is also a bilateral device. The
switching from off-state to on-state is achieved by simply exceeding the avalanche break
down voltage in either direction.
Figure 3.1 Symbol & Characteristics of Diac
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Volt-ampere characteristic of a DIAC is shown in figure2.4. It resembles the English

letter Z because of the symmetrical switching characteristics for either polarity of the
applied voltage. The DIAC acts like an open-circuit until its switching or break-over
voltage is exceeded. At that point the DIAC conducts until its current reduces toward
zero (below the level of the holding current of the device). The DIAC, because of its
peculiar construction, does not switch sharply into a low voltage condition at a low
current level like the SCR or TRIAC. Instead, once it goes into PE LAB MANUAL Page
12.
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Figure 3.2 Pictorial view
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 PROCEDURE:
connect DIAC for characteristic study; and switch ON the circuit.
2. Vary the POT7 value till the DIAC get turn on. Note these values of VMT2MT1and
current IMT2.Note the BREAKOVER voltage VBO1.
3. Now interchange the MT2 and MT1terminal and repeat the step2 to obtain the VBO2.
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 OBSERVATION:
 IN FORWARD CONDITION:
𝐕𝐌𝐓𝟐−𝐌𝐓𝟏 𝐈𝐌𝐓𝟐
2.25 V 94.372mA
2.28 V 150.847 mA
 IN REVERSE CONDITION:
𝐕𝐌𝐓𝟏−𝐌𝐓𝟐 𝐈𝐌𝐓𝟏
-2.23 V -75.532 mA
-2.28 V -150.84 mA
 CONCLUSION: After performing this practical we are learning that V-I characteristics
of DIAC in both direction (Forward & Reverse).
SIGNATURE
DATE
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EXPERIMENT: 4
Study of the switching characteristic of MOSFET.
 AIM: Study of the switching characteristic of MOSFET.

 APPARATUS: Trainer kit, Connecting probes, Oscilloscope.
 THEORY :
The MOSFET, like the BJT is a three terminal device where the voltage on the gate terminal
controls the flow of current between the output terminals, Source and Drain. The source
terminal is common between the input and the output of a MOSFET. The output characteristic
of a MOSFET is then a plot of drain current ID as a function of the Drain – Source voltage
(VDS) with gate source voltage VGS as a parameter. Figure 4.1 (a) shows such a
characteristic.
(a) (b)
Figure 4.1: Characteristic of MOSFET
(a) Drain characteristics
(b) Trans-conductance characteristics
With gate-source voltage VGS below the threshold voltage VGS(TH) the MOSFET operates
in the cut-off mode. No drain current flows in this mode and the applied drain–source voltage
VDS is supported by the body-collector p-n junction. Therefore, the maximum applied voltage
should be below the avalanche break down voltage of this junction. VDSS to avoid destruction
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of the device. When VGS is increased beyond VGS(TH) drain current starts flowing. For small
values of VDS(VDS< (VGS – VGS(TH)) drain current is almost proportional to VDS.
Consequently this mode of operation is called “Ohmic mode” of operation. In power electronic
applications a MOSFET is operated either in the cut off or in the ohmic mode. The slope of the
VDS– iD characteristics in PE LAB MANUAL Page 15
this mode is called the ON state resistance of the MOSFET (RDS(ON)). RDS(ON) reduces with
increase in VGS. This is mainly due to reduction of the channel resistance at higher value of
VGS. Hence, it is desirable in power electron ic applications, to use as large a gate-source
voltage as possible subject to the dielectric break down limit of the gate-oxide layer. At still
higher value of VDS(VDS>(VGS–VGS(TH)) the I – VDS characteristics deviates from the
linear relationship of the Ohmic region and for a given VGS, I, tends to saturate with increase in
VDS. The exact mechanism behind this is rather complex. It will suffice to state that, at higher
drain current the voltage drop across the channel resistance tends to decrease the channel width
at the drain drift layer end. In addition, at large value of the electric field, produced by the large
Drain – Source voltage, the drift velocity of free electrons in the channel tends to saturate. As a
result the drain current becomes independent of VDS and determined solely by the gate – source
voltage VGS. This is the active mode of operation of a MOSFET. For power MOSFETs the
transfer characteristics ( I, Vs VGS) is more linear. At this point the similarity of the output
characteristics of a MOSFET with that of a BJT should be apparent. Both of them have three
distinct modes of operation, namely, (i) Cut off, (ii) Active and (iii) Ohmic(saturation for BJT)
modes. However, unlike BJT a power MOSFET does not undergo second break down. For safe
operation of a MOSFET, the maximum limit on the gate source voltage (VGS(Max)) must be
observed. Exceeding this voltage limit will cause dielectric break down of the thin gate oxide
layer and permanent failure of the device. It should be noted that even static charge inadvertently
put on the gate oxide by careless handling may destroy it. The device user should ground itself
before handling any MOSFET to avoid any static charge related problem.
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 PROCEDURE:
use MOSFET SWITCHING section of trainer.
2. Connect MOSFET between G-D-S terminal and short dotted terminal in series with load.
Connect oscilloscope across D-S terminal of MOSFET.
3. Switch on the circuit and observer the switching waveform across the drain-source
terminal of MOSFET.
4. Now connect the inductor L (120mH) as stray inductor in series with load and MOSFET
and observe the switching waveform across the drain-source terminal of MOSFET. Note the
spike coming in the switching waveform because of stray inductance.
5. Now connect the Snubber Circuit (R = 330Ω, C= 470μF, 400V) across the MOSFET.
Observe the reduction in voltage spikes across the drain-source terminal voltage of the
MOSFET.
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 OBSERVATION:
 DRAIN CHARACTERISTICS:
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 TRANSCONDUCTANCE CHARACTERISTICS :
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 CONCLUSION: After performing this practical we are learning the MOSFET Switching
characteristics.
SIGNATURE
DATE
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EXPERIMENT: 5
Study of triggering circuit of an SCR.
 AIM: Study of triggering circuit of an SCR.

 APPARATUS: Gate-Base drive circuit trainer kit, Oscilloscope, Connecting probes,
Multi-meter.
 THEORY:
 TRIGGERING CIRCUITS FOR SCR (LATCHING DEVICES) :
SCR can be switched from off state to on state in several ways. These are forward voltage
triggering, dv/dt triggering, temperature triggering, light triggering and gate triggering. Gate
triggering is, however the most common method of turning on the SCRs, because this method
lends itself accurately for turning on the SCR at the desired instant of time. In addition, gate
triggering is an efficient and reliable method. With this set up the following four methods of
gate triggering circuits are studied:
1. DC triggering circuit
2. Resistance triggering circuit
3. RC (phase shift) triggering circuit
4. Synchronized UJT triggering circuit (Relaxation oscillator)
 DC TRIGGERING :
SCR conducts when it is forward biased and required gate current to turn on the device is
provided. These basic facts can be demonstrated with the help of this circuit. Once the SCR
is turned on, even the gate is removed; the device remains in on state. The same can be
turned off by momentarily bringing down the anode current below holding current level. This
circuit is very rarely used in useful applications, as the gate power dissipation is one of the
major disadvantages of this system.
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Figure 5.1: Dc triggering
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 RESISTANCE TRIGGERING (R-TRIGGERING) :
Resistance trigger circuits are the simplest and most economical. They however, suffer from
a limited range of firing angle control (0 to 90 degrees).Figure 2.1 shows the basic resistance
triggering circuit. R2 Is the variable resistance, R is the stabilizing resistance. As resistance
R1, R2 are large, gate trigger circuit draws small current. Diode D allows the flow of current
during positive half cycle only i.e. gate voltage is half wave DC pulse. The amplitude of this
DC pulse can be controlled by varying R2.
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Figure 5.2: R triggering
 RC TRIGGERING :
The limited range of firing angle control by resistance firing circuit can be overcome by RC
firing circuit. A simple RC trigger circuit giving full wave output voltage is shown in Figure
2.5. In this circuit, the initial voltage from which the capacitor "C" charges is almost zero.
The capacitor "C" is set to this low positive voltage by the clamping action of SCR gate.
When capacitor charges to a voltage equal to V SCR triggers and rectified voltage V appears
across load as Vo. In figure, the waveforms are shown for alpha is more than 90 degrees and
alpha is less than 90 degrees.
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Figure 5.3: RC triggering
 UJT TRIGGERING:
A synchronized UJT trigger circuit using an UJT is shown in figure 2.6. Diodes D1-D4
rectifies AC to DC. Resistance R1lowersVdcto a suitable value for the zener diode and UJT.
7
Zener diode "Z" functions to clip the rectified voltage to a standard level V which remains
constant except near the V zero, as shown in figure.
This voltage V is applied to the charging circuit RC. Current i1 charges capacitor C at a rate
determined by R. Voltage across capacitor C is marked by V in figure2.6.When voltage V
reaches the uni junction threshold voltage , the E-B1 junction of UJT breaks down and the
capacitor C discharges as shown in figure 2.7.
which produces the gate trigger voltage. So the SCR fires during each half cycle. As soon as
the capacitor discharges, it starts to recharge.
Rate of rise of capacitor voltage is controlled by varying R2. The firing angle can be
controlled up to about 150 degrees.
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This method of controlling the output power by varying the charging resistance R2 is called
ramp control, manual control or open loop control As the zener voltage goes to zero at the
end of each cycle, the synchronization of the trigger circuit with supply voltage across SCR
is achieved Thus the time T =𝛼/𝜔, when the pulse is applied to SCR for the first time, will
remain constant for the same value of R. Small variation in supply voltage and frequency are
not going to effect the circuit operation.
In case R is reduced, so that V reaches UJT threshold voltage twice in each half cycle as
shown in figure 2.7, then there will be 2 pulses in each half cycle. As the first pulse will be
able to turn on the SCR, second pulse in each cycle is redundant.
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Figure 5.4: UJT triggering
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 DC TRIGGERING CIRCUIT:
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 R TRIGGERING CIRCUIT:
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 RC TRIGGERING CIRCUIT:
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 UJT TRIGGERING CIRCUIT:
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 GENERAL PROCEDURE FOR PRACTICAL :
1. Before making connection makes sure that the supply switch is in OFF position.
2. Connect the kit power cord to the single phase 230V AC supply. Do not switch on the
firing circuit switch.
3. Keep the potentiometer position to the minimum value.
4. Make Switch to the ON condition of the firing circuit section.
5. Connect required firing circuit section at the power circuit i.e. G(gate) and K(cathode)
(connect R,DC,RC,UJT firing pulses at the SCR power circuit and MOSFET/IGBT gate
driver pulses to the MOSFET/IGBT power circuit section)to the G and K points of the power
control circuit under experiment.
6. Connect oscilloscope across the power circuit terminals to observe the load voltage
waveform.
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 OBSERVATION:
 OUTPUT WAVEFORM OF DC TRIGGERING:
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 OUTPUT WAVEFORMS OF R TRIGGERING:
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 OUTPUT WAVEFORMS OF RC TRIGGERING:
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 OUTPUT WAVEFORM OF UJT TRIGGERING:
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 CONCLUSION: After performing this practical we are observed different triggering

circuits of SCR.
SIGNATURE
DATE
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EXPERIMENT: 6
To study about UJT relaxation oscillator
 AIM: To study about UJT relaxation oscillator.

 APPARATUS:
1. Power Supply.
2. Patch cords.
3. Multi-meter
 THEORY:
Many devices such as transistor, UJT and FET can be used as a switch. Here UJT issued as a
switch to obtain the sweep voltage. Capacitor C charges through the resistor, R towards
supply Voltage, Vbb . As long as the capacitor voltage is less than peak Voltage, Vp ,the
emitter appears as an open circuit.
Vp =h Vbb + Vγ where, h = standoff ratio of UJT,

Vγ = Cut in voltage of diode.
When the voltage Vo exceeds voltage Vp , the UJT fires. The Capacitor starts discharging
through R1 + Rb1. Where, Rb1 is the internal base resistance. This process is repeated until
the power supply is available.
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Figure 6.1 : Connection of UJT relaxation oscillator
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 PROCEDURE:
1. Make the connections as shown in the practical circuit diagram on TAT-01

board using patch cord.
2. Switch on the power supply.
3. Set supply voltage as shown in figure.
4. Observe the voltage waveform across the capacitor, C.
5. Change the time constant by changing the capacitor values to 0.1μF and
0.001 μF and observe the wave forms. Note down the parameters, amplitude, charging and
Discharging periods of the wave forms.
6. Compare the theoretical and practical time periods.
7. Plot the graph between voltages across capacitor with respect to time.
 CALCULATION OF DESIGN EQUATIONS:
Theoretical Calculations:
VP = Vγ + (R1/ R1 R2 )Vbb
When C=0.01μF
TC =RC ln(Vbb - Vv / Vbb- VP )
Td =R1C
 OBSERVATION:
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 CONCLUSION: After studying this practical we are learning that is able to work as
relaxation oscillator.
SIGNATURE
DATE
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EXPERIMENT:7
Study of chopper circuit with R-load.
 AIM: Study of chopper circuit with R load.

 APPARATUS: Trainer kit, Oscilloscope, connecting probes, Multi-meter.
 THEORY:
 CLASS-A CHOPPER:
Figure shows a Class A Chopper circuit with inductive load and free-wheeling diode. When
chopper is ON, supply voltage V is connected across the load i.e.v0=V, and current i0 flows
as shown in figure. When chopper is OFF, v0 = 0 and the load current continues to flow in
the same direction through the freewheeling diode. Therefore the average values of output
voltage and current i.e., O v and O i are always positive. Hence, Class A Chopper is a first
quadrant chopper (or single quadrant chopper).
 PROCEDURE:
1. Connect 24VDC supply to +Vs and –Vs terminal of the CLASS A CHOPPER‟ section.
2. Connect „R load‟ from LOAD BANK across the load terminal.
3. Connect oscilloscope and multi-meter as DC Voltmeter across load terminal.
4. Kept control switch in upper position i.e. frequency control method.
5. Start trainer kit and select “CLASS A” mode from menu on the LCD. Press START to
start gate circuit. Observe gate pulse G1 on oscilloscope.
6. Make supply switch ON and observer the load voltage output waveform on Oscilloscope.
By changing frequency Observe load current waveform.
7. Press STOP to stop gate circuit. Change the control switch position i.e. lower (duty ratio
control) & follow the same procedure and observations for duty ratio control method.
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 OBSERVATION:
 OUTPUT WAVEFORMS OF CHOPPER:
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 SUPPLY VOLTAGE (DC) VS= 24 V.
 FREQUENCY CONTROL:
Frequency Output Voltage
40 kHZ 22.872 V
50 kHZ 22.877 V
 DUTY RATIO CONTROL:
Duty ratio Output Voltage
50 % 22.872 V
60 % 22.865 V
 CONCLUSION: After performing these practical we are learning about CLASS-A

chopper with observation of its output waveforms.
SIGNATURE
DATE
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EXPERIMENT: 8
Study of Gate triggering circuit for DC-DC converter.

 AIM: Study of gate triggering circuits for DC-DC converter.
 APPARATUS: Trainer kit, Oscilloscope, Connecting probes, Multi-meter.
 THEORY:
DC-DC converter is a class of power conversion circuits that operates from an unregulated
dc voltage source and converts it into a regulated dc voltage. They work at a very high
frequency which reduced into a reduced size of magnetic components required in this
configuration. There are various classes of switch mode converters, out of them this trainer
intended for learning basic topologies and their working. Academic procedure of learning
this subject is to understand the operation of converter under continuous current mode
(CCM)and discontinuous current mode (DCM) and then to find boundary between CCM
and DCM. It is easy to maintain the regulation of the converter while it works in CCM as a
result factors that may lead to DCM mode of operation from CCM are normally analyzed.
Keeping in view of these academic aspects this trainer is designed to demonstrate basic
switch mode dc-dc converter topology like Buck, Boost and Buck-Boost converters. For all
three converters their working under CCM and DCM can be experimented and analyzed
with this trainer.
 FEATURES:
1. Basic topologies i.e. Buck, Boost and Buck-Boost configuration are possible.
2. Open loop and close loop operation possible.
3. Operation of converter in CCM and DCM can be experimented.
4. Control circuit test points are available for observation of intermediate stage waveforms.
5. Kit works directly from line AC supply and circuit low voltages are generated internally.
6. Inductor voltage and current waveform observation is possible.
7. Necessary fuse is provided for protection.
8. Firing circuit loading and power circuit are in the same kit with proper isolation.
9. Many more then listed experiments are possible due to flexible design of the kit.
The DC-DC converters are widely used in regulated switch-mode dc power supplies. The
input to these converters is unregulated dc voltage. Switch mode dc-to-dc converters are
used to convert the unregulated dc input into a controlled dc output at a desired voltage
level. Figure 8.1 shows the typical block diagram of dc-dc converter system.
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Figure 8.1: Block Diagram of DC-DC Converter
The following non isolated DC-DC converters are presented in this manual.
1. Buck (Step-down) Converter
2. Boost (Step-up) Converter
3. Buck-Boost (Step-down / Step-up) Converter
 BUCK (STEP-DOWN) DC-DC CONVERTER:
The step-down dc–dc converter, commonly known as a buck converter, is shown in figure
2.2. It consists of dc input voltage source VS , controlled switch S, diode D, filter inductor L,
filter capacitor C, and load resistance R. Typical waveforms in the converter are shown in
figure 2.3 under assumption that the inductor current is always positive. The state of the
converter in which the inductor current is never zero for any period of time is called the
continuous conduction mode (CCM). It can be seen from the circuit that when the switch S is
commanded to the on state, the diode D is reverse biased. When the switch S is off, the diode
conducts to support an uninterrupted current in the inductor.
 BOOST (STEP-UP) DC-DC CONVERTER:
Figure 2.8 depicts a step-up or boost converter. It is comprised of dc input voltage source VS
, boost inductor L, controlled switch S, diode D, filter capacitor C, and load resistance R. The
converter waveforms in the CCM are presented in figure 2.9.
 BUCK-BOOST (STEP-DOWN/UP) DC-DC CONVERTER:
Topology of the buck–boost converter is shown in figure2.14. The converter consists of dc

input voltage source VS, controlled switch S, inductor L, diode D, filter capacitor C, and load
resistance R. With the switch on, the inductor current increases while the diode is maintained
off. When the switch is turned off, the diode provides a path for the inductor current.
Page | 40
160220111081(J.A.P)
Page | 41
 PROCEDURE:
load to converter power configuration; only make control circuit ON.
2. Start the trainer kit and select “BUCK” converter mode from menu on the LCD.
3. Select Open loop mode.
4. Press START to start gate control circuit.
5. Observe 40 kHz gate pulses on oscilloscope. Vary duty ratio and observer gate pulses.
6. Start the trainer kit in “BOOST” converter open loop and observe gate pulses on
oscilloscope. Vary duty ratio and observer gate pulses.
7. Start the trainer kit in “BUCK-BOOST” converter open loop and observe gate pulses on
oscilloscope. Vary duty ratio and observer gate pulses.
 BUCK DC-DC CONVERTER:
160220111081(J.A.P)
Page | 42
 BOOST DC-DC CONVERTER:
160220111081(J.A.P)
 OBSERVATION:
 BUCK CONVERTER WAVEFORM:
160220111081(J.A.P)
Page | 43
 BOOST CONVERTER WAVEFORMS:
160220111081(J.A.P)
 CONCLUSION: After performing these practical we are learning that by gate

triggering of thyristor we can make DC to DC buck and boost type converters.
SIGNATURE
DATE
Page | 44
EXPERIMENT: 9
Single phase rectifier

 AIM: To Study about the Single phase rectifier.
 APPARATUS: Single phase rectifier trainer kit, Oscilloscope, Connecting probes, DC
voltmeter, External battery (E).
 THEORY:
 SINGLE-PHASE HALF-WAVE UNCONTROLLED RECTIFIERS:
1) WITH R LOAD:
VS is the source voltage represented by 𝑉𝑚 sin ωm t in which 𝑉𝑚 is the peak value; 𝑉𝑙𝑑 , IL
dare the load voltage and load current respectively; 𝑉𝑑 , Id are the mean DC output
voltage and current respectively. The average DC output voltage and current can be
expresses with:
𝜋
𝑉𝑑 = 1/2𝜋 0
Vmsin at dat= 𝑉𝑚/𝜋 𝜋 0 Id = Vd /R = Vm /𝜋R
160220111081(J.A.P)
Figure 9.1 Single-phase half-wave uncontrolled circuit with R load
2) WITH RL LOAD:
The average DC output voltage and current can be expresses with
𝛽
Vd = 1/2𝜋 0
Vm sinωtdωt=𝑉𝑚/2𝜋(1−cos𝛽𝛽0) Id = Vd /R= Vm (1−cos𝛽)
Page | 45
160220111081(J.A.P)
Figure 9.2 Single-phase half-wave uncontrolled circuit with R-L load
 SINGLE-PHASE HALF-WAVE CONTROLLED RECTIFIERS
1) WITH R LOAD
Assume the element is thyristor and its leakage current and conduction drop is negligible.
160220111081(J.A.P)
Figure 9.3 Single-phase half-wave controlled circuit with R load
Page | 46
2) WITH RL LOAD:
160220111081(J.A.P)
Figure 9.4 Single-phase half-wave controlled circuit with R-L load
 SINGLE-PHASE FULL-WAVE UNCONTROLLED RECTIFIERS
When 0 ≤ 𝜔𝑡 ≤ 𝜋, D1 & D2 are forward-biased and hence turned on. At 𝜔𝑡 = 𝜋, D3 &

D4 start to turn on due to the rising forward-bias voltage across them, and take up the
load current from D1 & D2.
160220111081(J.A.P)
Figure 9.5 Single-phase full-wave uncontrolled circuit with R load
Page | 47
 SINGLE-PHASE FULL-WAVE CONTROLLED RECTIFIERS
When0 ≤ 𝜔𝑡 ≤ 𝜋 + 𝛼, , although T3 & T4 are forward-biased, they remain off until the
triggering signal appears at 𝜔𝑡 = 𝜋 + 𝛼.
160220111081(J.A.P)
Figure 9.6 Single-phase full-wave controlled circuit with R load
 GENERAL PROCEDURE FOR PRACTICAL
1. Before making connection make sure that control supply switch is OFF.
2. Connect the kit to the single phase 230V AC supply through power cord.
3. Connect single phase 230V AC supply between „P‟ and „N‟ on the kit.
4. Switch ON the control circuit supply and study the various waveforms of control
circuit on oscilloscope.
5. Connect „P1‟ and „N1‟ terminal to rectifier configuration section (Half wave / Full
wave and Controlled / Uncontrolled rectifier) to connect 30V AC supply. And also
connect load (R, R-L) from LOAD BANK across the load of rectifier configuration
section circuit.
6. Connect the DC voltmeter and oscilloscope across load terminal and turn ON MCB.
7. Observe the output voltage (Vd ) waveform on oscilloscope also measure it on
voltmeter.
8. Calculate the output voltage (Vd ) using formula according to corresponding rectifier
configuration.
9. Match practical output voltage and theoretically calculated output voltage.
10. Observer and study load voltage, device voltage waveform on oscilloscope.
11. For observing load current waveform on oscilloscope either observer voltage across R
and divide it with R or connect 1ohm, 10W resistor in series with R and observe voltage
across.
Page | 48
160220111081(J.A.P)
Figure 9: Pictorial view
Page | 49
 OUTPUT WAVEFORMS OF HALF-WAVE UNCONTROLLED WITH R:
160220111081(J.A.P)
 OUTPUT WAVEFORMS OF HALF-WAVE UNCONTROLLED WITH RL:
160220111081(J.A.P)
 OUTPUT WAVEFORMS OF HALF-WAVE CONTROLLED WITH R:
160220111081(J.A.P)
Page | 50
 OUTPUT WAVEFORMS OF HALF-WAVE CONTROLLED WITH RL:
160220111081(J.A.P)
 FULL-WAVE UNCONTROLLED RECTIFIER WITH R:
160220111081(J.A.P)
 FULL-WAVE CONTROLLED RECTIFIER WITH R:
160220111081(J.A.P)
Page | 51
 OBSERVATION:
 OUTPUT WAVE OF HALF-WAVE UNCONTROLLED RECTIFIER WITH R:
160220111081(J.A.P)
 OUTPUT WAVE OF HALF-WAVE UNCONTROLLED RECTIFIER WITH RL:
160220111081(J.A.P)
Page | 52
 OUTPUT WAVE OF HALF-WAVE CONTROLLED RECTIFIER WITH R:
160220111081(J.A.P)
 OUTPUT WAVE OF HALF-WAVE CONTROLLED RECTIFIER WITH RL:
160220111081(J.A.P)
Page | 53
 OUTPUT WAVE OF FULL-WAVE CONTROLLED RECTIFIER WITH R:
160220111081(J.A.P)
 OUTPUT WAVE OF FULL-WAVE UNCONTROLLED RECTIFIER WITH R:
160220111081(J.A.P)
Page | 54
 CONCLUSION: After performing this practical we are learning the controlled and
Uncontrolled Rectifier with different loads along output waveforms.
SIGNATURE
DATE
Page | 55
EXPERIMENT: 10
Single phase inverter
 AIM: To study about the single phase inverter.

 APPARATUS: Single phase inverter trainer kit, Oscilloscope, Connecting probes,
Multi-meter.
 THEORY:
 SINGLE-PHASE HALF-BRIDGE VOLTAGE SOURCE INVERTER (VSI) :

In half bridge topology the single-phase load is connected between the mid-point of the
input dc supply and the junction point of the two switches.Fig2.1 shows the basic
configuration of single phase half-bridge voltage source inverter. Square wave load
voltage output by half-bridge inverter is as shown in fig. 2.2
160220111081(J.A.P)
Fig 10.1Single-Phase Half-Bridge Voltage Source Inverter
Page | 56
 SINGLE-PHASE FULL-BRIDGE VOLTAGE SOURCE INVERTER (VSI)
The single-phase full bridge circuit can be thought of as two half- bridge circuits sharing
the same dc bus. The full bridge circuit will have two pole-voltages (VAO and VBO),
which are similar to the pole voltage VAO of the half- bridge circuit. Both VAO and
VBO of the full bridge circuit are square waves but they will have some phase difference.
Figure 2.3 shows the circuit configuration and figure 2.4 shows the pole voltages
staggered in time by „t‟ seconds. The output voltage in this case can be expresses with
following mathematical expressions:
160220111081(J.A.P)
Fig. 10.2 Single-Phase Full-Bridge Voltage Source Inverter
Page | 57
160220111081(J.A.P)
Figure: 10.3 Pictorial view
Page | 58
 GENERAL PROCEDURE FOR PRACTICAL:
1. Before making connection makes sure that the supply switch is in OFF position.
2. Connect the kit power code to the single phase 230V AC supply. Do not switch on the
supply.
3. Connect DC supply„ +Vs‟ and „-Vs‟ terminal to the input of inverter configuration
under experiment (HALF BRIDGE VSI / FULL BRIDGE VSI).
4. Connect required load from LOAD BANK at the load points of the inverter under
experimentation.
5. Connect oscilloscope and Multi-meter(in AC-RMS mode) across the inverter load
terminals. Moving iron analogue multi-meter is more preferred.
6. Switch on the 230V mains and check DC supply at „+Vs‟ and „-Vs‟ supply terminal.
If DC input voltage is coming properly switch on the inverter under experimentation.
7. Observe the output voltage waveform on oscilloscope and its value on meter. Also
measure its frequency and RMS/Peak value.
8. For observing load current waveform on oscilloscope either observer voltage across R
and divide it with R or connect 1ohm, 10W resistor in series with R and observe voltage
across it. (While connecting load voltage and load current simultaneously on
oscilloscope, make sure that common points of both the signals are connected with the
reference point of channels.)
 SINGLE-PHASE HALF-WAVE VOLTAGE INVERTER:
160220111081(J.A.P)
Page | 59
 SINGLE-PHASE FULL-BRIDGE VOLTAGE INVERTER:
160220111081(J.A.P)
 OBSERVATION:
 OUTPUT WAVEFORMS HALF-BRIDGE INVERTER:
160220111081(J.A.P)
Page | 60
 OUTPUT WAVEFORM FULL-BRIDGE INVERTER:
160220111081(J.A.P)
 CONCLUSION: After performing this practical we are study about Half-Bridge

and Full-Bridge Inverter along with Output waveforms.
SIGNATURE
DATE
Page | 61

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POWER ELECTRONICS DEVICE AND CIRCUIT (2161006) YEAR 2019

V-I Characteristic and Measurement of latching/holding current of SCR.

Figure 1.1: Characteristic of THYRISTOR

Figure 1.2: Pictorial view

2. Vary the POT3 and set the gate current IG.

Gate current: 𝐈𝐆 Anode to cathode voltage : 𝐕𝐀𝐊 Anode current: 𝐈𝐀

 Latching Current IL = 23 mA  Holding current IH = 21.5 mA

 AIM: Study the V-I characteristic of TRIAC.

From a functional point of view a TRIAC is similar to two THYRISTORS connected in

Figure 2.2: Operation of TRIAC in four quadrants

Figure 2.3: Pictorial view

5. Now measure the BREAKOVER voltage VB01.

 Latching Current I L = 12 mA  Holding current IH = 10 mA

Study of the V-I Characteristic of DIAC.

 AIM: Study of the V-I characteristic of DIAC.

Figure 3.1 Symbol & Characteristics of Diac

Volt-ampere characteristic of a DIAC is shown in figure2.4. It resembles the English

Figure 3.2 Pictorial view

Study of the switching characteristic of MOSFET.

 AIM: Study of the switching characteristic of MOSFET.

Figure 4.2: Pictorial view

Study of triggering circuit of an SCR.

 AIM: Study of triggering circuit of an SCR.

 TRIGGERING CIRCUITS FOR SCR (LATCHING DEVICES) :

Figure 5.1: Dc triggering

 RESISTANCE TRIGGERING (R-TRIGGERING) :

Figure 5.2: R triggering

Figure 5.3: RC triggering

Figure 5.4: UJT triggering

Figure 5.5: Pictorial view

 UJT TRIGGERING CIRCUIT:

 GENERAL PROCEDURE FOR PRACTICAL :

3. Keep the potentiometer position to the minimum value.

4. Make Switch to the ON condition of the firing circuit section.

 OUTPUT WAVEFORM OF DC TRIGGERING:

 OUTPUT WAVEFORMS OF R TRIGGERING:

 OUTPUT WAVEFORMS OF RC TRIGGERING:

 OUTPUT WAVEFORM OF UJT TRIGGERING:

 CONCLUSION: After performing this practical we are observed different triggering

To study about UJT relaxation oscillator

 AIM: To study about UJT relaxation oscillator.

Vp =h Vbb + Vγ where, h = standoff ratio of UJT,

Figure 6.1 : Connection of UJT relaxation oscillator

1. Make the connections as shown in the practical circuit diagram on TAT-01

2. Switch on the power supply.

3. Set supply voltage as shown in figure.

4. Observe the voltage waveform across the capacitor, C.

6. Compare the theoretical and practical time periods.

 CALCULATION OF DESIGN EQUATIONS:

Study of chopper circuit with R-load.

 AIM: Study of chopper circuit with R load.

2. Connect „R load‟ from LOAD BANK across the load terminal.

3. Connect oscilloscope and multi-meter as DC Voltmeter across load terminal.

4. Kept control switch in upper position i.e. frequency control method.

Figure 7.1: Pictorial view

 OUTPUT WAVEFORMS OF CHOPPER:

 SUPPLY VOLTAGE (DC) VS= 24 V.

Frequency Output Voltage

 DUTY RATIO CONTROL:

Duty ratio Output Voltage

 CONCLUSION: After performing these practical we are learning about CLASS-A

Study of Gate triggering circuit for DC-DC converter.