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Digital Electronic Circuits


Assignment- Week 8
TYPE OF QUESTION: MCQ/Short answer
Number of questions: 20 Total mark: 20 X 1 = 20
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QUESTION 1:
Which of the following points must be considered before selecting any kind of register?
a. Sufficient no. of input-output pins depending upon requirement
b. Time taken for reading from and writingto the register
c. Destructive or non-destructive output of register
d. All of the above

Correct answer: d
Detailed Solution: Refer to slide 4, Lecture-36 (Register and Shift Register: PIPO and
SISO), NPTEL online certification courses and reference books.

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QUESTION 2:
In the given IC74175 circuit, the input at pins 1, 4, 5, 12, 13 is 11010. What will be the output at
pins 3, 6, 11 and 14 after one clock pulse?

a. 0101
b. 1010
c. 0111
d. 1110

Correct Answer: a

Detailed Solution: IC74175 is a PIPO register with asynchronous clear input (pin 1)and 4-bit
input at pins 4, 5, 12 and 13. Since the clear input is inactive, the pins 3, 6, 11 and 14 provide the
complement value of the output of corresponding flip-flops.

Refer to Lecture-36 (Register and Shift Register: PIPO and SISO), NPTEL online
certification courses and reference books.

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QUESTION3:
In the given circuit diagram of IC 74166, which of the following is correct?

a) Circuit acts as SISO when shift/load =1


b) Circuit acts as SIPO when shift/load =0
c) Circuit acts as PIPO when shift/load =0
d) Circuit acts as PISO when shift/load =1

Correct Answer: a

Detailed solution:

Let C denote the shift/load control input. Here, the S input of different flip-flops is given as:

S= C.Serialin + C’.A.

When Shift/Load is HIGH, S=Serialin and output of one flip-flop is connected to input of other
flip-flop through AND-NOR gate combination. Hence, it acts as a shift register with serial
input/output i.e. SISO.

Thus, correct answer is (a)

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QUESTION4:

For the given circuit diagram of IC7495A, left shift register operation can be performed by:

a) Applying 1 at ‘Mode Control’ pin and using Clock 2 for clock input

b) Applying 0 at ‘Mode Control’ pin and using Clock 1 for clock input

c) Applying 1 or 0 at ‘Mode Control’ pin and using Clock 1 for clock input

d) Applying 0 at ‘Mode Control’ pin and using Clock 2 for clock input

Correct Answer: a)

Detailed Solution:

Mode Control = 1/0 corresponds to left/right shift operations respectively.

Clock 2 is the left shift clock and Clock 1 is the right shift clock. When Mode Control input is 1,
the AND gate of connected to A, B, C and D get 1 at one of its input. Also with Mode Control as
1, AND gate at clock 2 gets 1 as input such that, clock 2 is connected to clock input of every flip-
flop.
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Refer to Lecture-37 (Shift Register: SIPO, PISO and Universal Shift Register), NPTEL
online certification courses and reference books.

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QUESTION 5:
A microprocessor makes use of registers to store the data before providing them to the ALU for
calculation. Consider the two registers in figure below. Both are 8 bit SIPO registers. Two 8 bit
data are to be serially shifted into the registers to perform addition between them. Also consider
the clock cycle of CPU to be 2.5GHz. The ALU takes 2 clock cycles to perform addition once
data is available at its input. Calculate the time required to load and perform addition of two 8-bit
numbers.(The data from both registers isavailable parallelly at the input of ALU).

Reg B Reg A
Serial Input Serial Input

ALU

Output

a. 3.2ns
b. 4ns
c. 3.2us
d. 4us

Correct Answer: b

Detailed Solution:

Given frequency is 2.5GHz

= 4x10-10 s.
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Since the registers are of 8 bit, it will take 8 clock cycles to enter data into both the registers.
Hence, total time to load registers is,

4x10-10 x8= 32x10-10seconds

The ALU take 2 clock cycles to operate over data from registers. So, total time that would take to
input data into register and get output from ALU is,

32x10-10 + (2x4x10-10)seconds

= 40x10-10 seconds.

= 4ns

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QUESTION 6:
A delay line circuit is to be generated to create a delay of 0.32ms between input and output. How
many numbers of flip-flops are required in SISO register to produce the required delay? (Given:
clock frequency fc = 1.25 MHz)

a. 40

b. 400

c. 4000

d. 40000

Correct Answer: b

Detailed Solution:

We have,

∆𝑡𝑡 = 𝑁𝑁𝑇𝑇𝐶𝐶

Where, ∆t= Total delay required,

N= Number of flip-flops,

TC= Clock time cycle.

From equation we can write,


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∆𝑡𝑡
𝑁𝑁 =
𝑇𝑇𝐶𝐶

32∗10 −5
𝑁𝑁 = = 400
8∗10 −7

Hence, 400 flip-flops would be required to produce the required delay.

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QUESTION 7:
If there are N number of Flip-flops in a PISO shift register circuit, maximum clock delay of
serial output is ________________ clock cycles.

a. N
b. N+1
c. N/2
d. 2N

Correct Answer: b

Detailed Solution:

PISO register requires 1 clock cycle to load the data into flip-flops and N clock cycles to output
the data serially. Hence, a total of (N+1) clock cycles are required.

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QUESTION 8:
In the diagram shown below, find the logic gates required to get ‘Y=1’ output when bit sequence
in registers A and B are same.

Reg. A

B E
D

Reg. B

a) A-AND, B-OR, C-AND, D-OR, E-AND

b) A-XOR, B-XNOR, C-XOR, D-XNOR, E-BUBBLED INPUT AND

c) A-XOR, B-XOR, C-XOR, D-XOR, E-BUBBLED INPUT AND

d) A-XNOR, B-XNOR, C-XNOR, D-XNOR, E- OR

Answer: c

Detailed Solution:
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The circuit diagram of a bit checker is shown as below,

Reg. A

YY=1

Reg. B

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QUESTION 9:

The number of unused states in an n-stage ring counter is:

a. 𝑛𝑛
b. 2𝑛𝑛
c. 2𝑛𝑛 − 𝑛𝑛
d. 2𝑛𝑛 − 2𝑛𝑛

Correct answer: c
Detailed Solution:
The ring counter cycles through n states. Hence, the number of unused states is 2𝑛𝑛 − 𝑛𝑛.
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QUESTION 10:
Consider the Ring counter shown in figure below:

Q1 Q2 Q3 Q4
J1 J2 J3 J4

Clk

Let the initial state of counter before the clock is applied is 1010. What will be the output
waveform of counter circuit?

a.

b.

c.

d.

Correct Answer: a

Detailed Solution:
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The initial state is:

Q1 1 Q2 0 Q3 1 Q4 0
J1 J2 J3 J4

After first clock pulse:

Q1 0 Q2 1 Q3 0 Q4 1
J1 J2 J3 J4

After second clock pulse:

Q1 1 Q2 0 Q3 1 Q4 0
J1 J2 J3 J4

After third clock pulse:

Q1 0 Q2 1 Q3 0 Q4 1
J1 J2 J3 J4

The sequence repeats at further cycles. Hence, option (a) is correct.

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QUESTION 11:
Consider the Johnson Counter and the clock timing diagram as shown in the figure below.

Q1 Q2 Q3
T1 T2 T3 T4
Q’4

CLK

Clk:
1ms
t=0

Let the initial state of Johnson Counter be 0000. Consider the delay from i/p to o/p of each flip-
flop is0.1ms. After, how much time the o/p of the counter will be all zero again?

a. 13ms

b. 8ms

c. 9ms

d. 15ms

Correct Answer: d

Detailed Solution:

Since the delay of the flip-flops is much less than the clock cycle duration, the given Johnson
counter operates correctly. The state of the counter changes at each negative transition of the
clock input (i.e., negative edge-triggered).

The states of the counter are listed below along with the time elapsed (with reference to t = 0):

Clock Q1 Q2 Q3 Q4 Time elapsed


(ms)

0 0 0 0 0 0
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1 1 0 0 0 1

2 1 1 0 0 3

3 1 1 1 0 5

4 1 1 1 1 7

5 0 1 1 1 9

6 0 0 1 1 11

7 0 0 0 1 13

8 0 0 0 0 15

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QUESTION 12:
In the following circuit, consider initial value of allflip-flops to be zero. The outputs will again
be zero after ____________ clock cycles ?

Q1 Q2 Q3 Q4
T1 T2 T3 T4

CLK

Correct Answer: 15

Detailed Solution:

State of the given circuit at different clock cycles is given below:

Clock Q1 Q2 Q3 Q4
Pulses

0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 0 1 1 1

5 1 0 1 1

6 1 1 0 1

7 0 1 1 0

8 0 0 1 1

9 1 0 0 1

10 0 1 0 0
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11 1 0 1 0

12 0 1 0 1

13 0 0 1 0

14 0 0 0 1

15 0 0 0 0

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QUESTION 13:

What is the polynomial representing the following LFSR? Is it maximal (Yes/No)?

a. 𝑥𝑥 4 + 𝑥𝑥 3 + 1, Yes
b. 𝑥𝑥 4 + 𝑥𝑥 3 + 1, No
c. 𝑥𝑥 4 + 𝑥𝑥 + 1, Yes
d. 𝑥𝑥 4 + 𝑥𝑥 + 1, No
Correct answer: a
Detailed Solution: The polynomial representation is 𝑥𝑥 4 + 𝑥𝑥 3 + 1
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It is seen that the LFSR cycles through 24 − 1 = 15 states, which is the maximum possible
number of states for 4-bit LFSR (excluding the trivial state 0000). Hence, the sequence generated
by the given LFSR is maximal length.

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QUESTION 14:
Which of the following statements are TRUE about pseudorandom noise (pn) sequences and
Linear Feedback Shift Registers (LFSRs)?

I. A pn sequence is deterministic and periodic.


II. A pn sequence with sufficiently long period exhibits properties of random sequences.
III. A 𝑚𝑚-bit LFSR is needed to generate a maximal length sequence of 2𝑚𝑚 − 1.
IV. In a LFSR, it is not always possible to find a set of connections from flip-flop outputs to
parity generator which will yield a maximal length sequence.
V. In a m-bit LFSR, a necessary and sufficient condition for obtaining maximal length
sequences is to choose even number of taps which are coprime with respect to each other.

a. All the above


b. I, II, III only
c. II, III, V only
d. I, II, IV, V only
Correct answer: b
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Detailed Solution:

Statement IV is not true, because it is always possible to determine the appropriate feedback
connections so that the sequence length is maximal.

Statement V is not true, because having even number of taps which are coprime is necessary but
not sufficient condition to yield maximum length sequences.

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QUESTION 15:

A 4-bit LFSR with external feedback has the polynomial representation 𝑥𝑥 3 + 𝑥𝑥 2 + 1. Let the
LFSR be initialized with 1111. The generated pseudorandom sequence has period:
a. 4
b. 7
c. 8
d. 15
Correct answer: b
Detailed Solution:

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QUESTION 16:
In CRC-4 coding with generator polynomial, 𝑥𝑥 4 + 𝑥𝑥 3 + 1, determine the transmitted code if the
message is 1100111.

a. 0011000111
b. 11001110110
c. 1100111010
d. 11001110010

Correct answer: d

Detailed solution:

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QUESTION 17:
The number of clock cycles required by serial and parallel adder to perform sum of two N-bit
inputs is _________ and ___________.Assuming that the two N-bit inputs are preloaded into the
registers, determine the answer considering only time taken for addition operation.

a. N, 1
b. N, N/2
c. 2N, N
d. N2, N

Correct Answer: a

Detailed Solution:

Serial adder performs one 2-bit summation operation in 1 clock cycle. So it will take N clock
cycles to sum two binary numbers containing N bits each.

Parallel cascaded adders and can perform addition operation of two N bit numbers in single
clock cycle.

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QUESTION 18:

Determine the inputs to the JK flip-flop so that the circuit below functions as a 𝑛𝑛-bit serial adder.
Here, the 𝑛𝑛-bit sum is stored in register A after 𝑛𝑛 clock cycles.

a. 𝐽𝐽𝑖𝑖𝑖𝑖 = 𝑥𝑥𝑥𝑥, 𝐾𝐾𝑖𝑖𝑖𝑖 = 𝑥𝑥 ′ 𝑦𝑦 ′


b. 𝐽𝐽𝑖𝑖𝑖𝑖 = 𝑥𝑥 + 𝑦𝑦, 𝐾𝐾𝑖𝑖𝑖𝑖 = 𝑥𝑥 ′ + 𝑦𝑦 ′
c. 𝐽𝐽𝑖𝑖𝑖𝑖 = 𝑥𝑥𝑥𝑥, 𝐾𝐾𝑖𝑖𝑖𝑖 = 𝑥𝑥 ′ 𝑄𝑄 + 𝑦𝑦 ′ 𝑄𝑄′
d. 𝐽𝐽𝑖𝑖𝑖𝑖 = 1, 𝐾𝐾𝑖𝑖𝑖𝑖 = 1

Correct answer: a
Detailed Solution:

In this implementation of the serial adder, the JK flip-flop stores the previous carry in the output
Q. Let 𝑄𝑄𝑛𝑛 and 𝑄𝑄𝑛𝑛 + 1 denote the previous and next carry out respectively. Hence, we have:
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Solving using K-maps, we get:

𝐽𝐽𝑖𝑖𝑖𝑖 = 𝑥𝑥𝑥𝑥

𝐾𝐾𝑖𝑖𝑖𝑖 = 𝑥𝑥 ′ 𝑦𝑦 ′ = (𝑥𝑥 + 𝑦𝑦)′

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QUESTION 19:
Perform serial multiplication of the following 4 bit numbers using the given circuit and find the
value of M after 3 clock pulses.Assume that the initial value of M is all zeros.
X= 1110 and Y=1101

a. 01010100
b. 00001110
c. 00101010
d. 01010101

Correct Answer: a

Detailed Solution:

X= 1110 and Y=1101

X4X3X2X1 1110 1110 1110

i/p to AND gates Y3=1 Y2=1 Y1=0

AND Output 1110 1110 0000


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Previous M 00000000 00001110 00101010

Adder input (A7-1) 0000000 0001110 0101010

Adder input (B7-1) 0000111 0000111 0000000

Adder output (m7-m1) 0000111 0010101 0101010

M at clock trigger 00001110 00101010 01010100

Clock Clock1 Clock2 Clock3

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QUESTION 20:
In the given divider circuit, assume D7 = 0, D6-0= 1011010 and d= 1010. What will be the state
of the shift-register (D3D2D1D0) after 3 clock cycles?

a) 0100
b) 1000
c) 1010
d) 0000

Correct Answer: a

Detailed Solution:

The division operation for the given value of D and d can be performed as,
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D=1011010; d=1010

11 00 11 10

1 0 0 0 0 1

00 01 00 11 00

0 1 1 1 0 0 0

00 01 10 01 10

0 1 1 1 0 1 0

00 11 00 11 00

1 0 0 0 0 0 0

bout

Initially, value of the shift-register D3-D0 is 1010. The quotient value generated after first clock
is 1 which moves to D0 and previous values in the register shifts left. After second clock,
generated quotient value (0) is shifted to D0 and previous value of D0 is shifted to D1. Similarly,
after third clock, D0 contains third quotient value (0) and previous values after shifted left.
Hence after 3 clocks, value of shift register D3,D2,D1,D0 is 0100 or option (a).

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