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# Sr No

## Question OptionA OptionB

accepts many inputs
accepts one input and gives several and gives many
1 A multiplexer is a logic circuit that output output
In order to implement a n variable switching function,
2 a MUX must have 2n inputs 2n+1 inputs
A combinational logic circuit which sends data coming
from a single source to two or more separate
3 destinations is called Decoder Encoder
4 EPROM contents can be erased by exposing it to Ultraviolet rays Infrared rays
The output of a logic gate is 1 when all its inputs are at
5 logic 0. the gate is either A NAND or an XOR An OR or an XNOR
A three input NOR gate gives logic high output only
6 when One input is high One input is low
Which of the following logic families is well suited for
7 high-speed operations ? TTL ECL
8 The absorption law in Boolean algebra says that X+X=X X.X=X
The digital logic family which has minimum power
9 dissipation is TTL RTL

10 Negative numbers cannot be represented in Signed magnitude form 1’s complement form
11 8-bit 1’s complement form of –77.25 is 1001101.01 1001101.001

## 12 In computers, subtraction is generally carried out by 9’s complement 10’s complement

13 X – = Y + 1 means X=X–Y+1 X = –X – Y – 1
Shifting a register content to left by one bit position is
14 equivalent to Division by two Addition by two
The 2s compliment form (Use 6 bit word) of the
15 number 1010 is 111100 110110
The answer of the operation (10111)2*(1110)2 in hex
16 equivalence is 150 241
17 The gray code equivalent of (1011)2 is 1101 1010
18 12-bit 2’s complement of –73.75 is 1001001.11 11001001.11
The negative numbers in the binary system can be
19 represented by Sign magnitude 1s complement
20 The 2’s complement of the number 1101101 is 101110 111110
The number of 1’s present in the binary
21 representation of 10 × 256 + 5 × 16 + 5 is 5 6

## 22 The hexadecimal number equivalent to (1762.46)8 is 3F2.89 3F2.98

How many 1’s are present in the binary representation
23 of 3 × 512 + 7 × 64 + 5 × 8 + 3 8 9
24 What is decimal equivalent of BCD 11011.1100 ? 22 22.2
What is the binary equivalent of the decimal number
25 368 101110000 110110000
26 The ASCII code for letter A is 1100011 1111111
27 Floating point representation is used to store Boolean values Whole numbers

## 28 The Gray code for decimal number 6 is equivalent to 1100 1001

29 The decimal equivalent of hex number 1A53 is 6793 6739
(001011111010 0000
30 (2FAOC)16 is equivalent to 195 084)10 1100)2
31 The octal equivalent of hexadecimal (A.B)16 is 47.21 12.74

## Page Shift Keying (PSK) Method is used to modulate

digital signal at 9600 bps using 16 level. (Find the line
33 signals and speed (i.e. modulation rate). ) 2400 bauds 1200 bauds
The simplified form of the Boolean expression
34 (X+Y+XY)(X+Z) is X + Y + ZX + Y XY – YZ
What is the transitive voltage for the voltage input of a
35 CMOS operating from 10V supply ? 1V 5V
36 The highest noise margin is offered by BICMOS TTL
The branch logic that provides making capabilities in
37 the control unit is known as Controlled transfer Conditional transfer
The digital logic family which has the lowest
38 propagation delay time is ECL TTL

39 In a positive logic system, logic state 1 corresponds to Positive voltage Higher voltage level
40 AB+(A+B)’ is equivalent to A*B A+B
The NAND gate output will be low if the two inputs
41 are 00 01

## 42 The Boolean expression x’y’z+yz+xz is equivalent to x y

Which one of the following expressions does NOT
43 represent exclusive NOR of x and y? xy + x ' y ' x ex-or y '
ease of avoiding
Advantage of synchronous sequential circuits over problems due to
44 asynchronous ones is faster operation hazard
A reduced state table has 18 rows. The minimum
number of flip flops needed to implement the
45 sequential machine is 18 9
Which of the following is the fastest logic TTL ECL
46

## 47 CMOS circuits consume power Equal to TTL Less than TTL

The commercially available 8-input multiplexer integrated
48 circuit in the TTL family is 7495 74153
CMOS circuits are extensively used for ON-chip computers
49 mainly because of their extremely low power dissipation. high noise immunity.
The time difference between the instant of application of
input & the instant at which output responds to it, is called
50 as_________ propagation delay delay time
Reduced power dissipation may lead to ___ in propagation
51 delay Increase Decrease
52 Noise immunity of TTL is _____ CMOS More than Less than

53 TTL tristate inverter consists of ______ 2 transistors & 2 diodes 4 transistors & 2 diodes
54 ___ digital Ics have highest packing density PMOS NMOS
only p channel Mos
55 CMOS consist of______ only n channel Mos devices devices
56 Recommended Fan out for TTL gate is_____ 10 4
57 ___ is operated in ohamic or cut-off regions CMOS ECL
58 _____ is operated in saturation or cut-off regions. CMOS ECL
Dual edge triggered D
59 The MSI chip 7474 is Dual edge triggered JK flip-flop (TTL). flip-flop (CMOS).

60 The logic 0 level of a CMOS logic device is approximately 1.2 volts 0.4 volts

## _________ transistors are used as a switch & operated in

61 saturation region unipolar bipolar
The product of power dissipation and propagation time is
62 always___________ High Low

## Partially the value of figure of merit should be

63 as_________ as possible Low High
______ is always a compromise between speed & power
64 dissipation Figure of merit Fan-In
_____is used as a common means for measuring &
65 comparing the overall performance of different IC family. Speed power product Propagation dealy
The TTL Ics known as _________ TTL are not available now
66 a days. Fast Standard
Totem pole output have a very low output impedance
67 typically______ 10ohm 20ohm

## 68 For a TTL IC any floating input is equivalent to a______ Logic 0 Logic 1

Typically the Fan out of a CMOS device is ____ below 1
69 MHz 10 25

## 70 Input capacitance of each CMOS device gate is ______ 50pF 50nF

decreases with
increases with increased reverse-bise increased forword-bise
71 The storage time of a trnasistor___ voltage of BC junction of BC junction

72 for fastest switching operation it is preferred to use______ normal p-n junction diodes schottky diodes
The average supply current,Icc is determined based on____
73 duty cycle 100% 75%
______ diodes are used in all TTL gates to suppress the
74 ringing caused from the fast voltage transitions Zener Free wheeling
which one of the following logic families can be operated
75 using a supply voltage from 3V to 15V? 74TTL 74LS

76 If a logic circuit has a fan-out of 10 then the circuit _____ has 10 inputs has 10 outputs

77 The temprature range for devices in 74XX series is from 0 to 70° 55 to 125°
78 Voltage range of CMOS Ics are from_____ 3 to 5V 4 to 6V
79 Noise margin is calculated as VOH(min)-VIH(min) VOH(max)-VIH(max)
80 Low level noise margin for CMOS is____ & TTL is ___ 0.5V,1.5V 0.4V,1.45V
Propagation delay of CMOS & TTL is _________
81 respectively 10ns,105ns 105ns,70ns

## 82 VNL is equals to VIL(max)—VOL(max) VOH(max) — VIH(max)

It is possible to use an incandesnt lamp of rating 10V, 40mA TTL gate with passive
83 as load in a____ TTL gate with totem-pole output pull-up
For standard TTL, voltage levels for VOL(max) and
84 VOH(min) are _____ & _ respectively 0.4V,2.4V 0.4,0.8V

## the current drawn from

If the output of a TTL gate with active pull-up gets a large current will be drawn from the the supply voltage will
85 connected to positive 5V accidently supply causing damage to the gate not be affected at all

## a standard TTL gate has

lower fan out while
a standard TTL gate has higher fan out driving low power
while driving low power Schottky TTL Schottky TTL gates than
gates than while driving standard TTL while driving standard
86 Which of the following statement is true? gates. TTL gates.

## for TTL 74LS series, IOL= 8MA, IOH=-400µA,IIH=20µA & IIL=

87 -.36mA. Its fan out is 1 10

## The thrshold voltage of an n channel enhancement mode

MOSFET is 2v. The gate voltage required for conduction is
88 ________ 0.7V 1V
(FA)16 is the ________ one’s complement representation of
89 -5 4-bit 8-bit

## If sign bit (MSB) of

When adding two positive numbers result and sign bit of
Which of the following condition is true for determining gives a negative result or when two two operands are of
90 overflow condition in 2’s complement? negatives give a positive result different signs.
How -5 is represented in hex format in 2’s complement in
91 8-bits? (FB)16 (7F)16

## 92 value of B in 2’s complement binary?

93 How will you represent −42 in hexadecimal? D6 26

## If there is a carry out of the least If there is a carry out of

94 Which one of these will cause overflow in signed addition? significant bit. the most significant bit.
How many decimal nos are represented by an 8-bit string,
95 assuming 2’s complement binary? 255 256
What is the representation of the sign binary string 0111 0x8A4, -1883 in base
96 0101 1011 in hexadecimal and decimal? 0x75B, -1883 in base 10 10
The 4-variable Karnaugh Map (K-Map) has ______rows and
97 ____colums 2,2 4,2

## Eliminate one variable

98 By pairing two adjucent 1's in K-map we can__________ Add one variable in resulting term in original term
The maxterm corresponding to the combination 011
99 is_____ Ā+Ē+Ō A+Ē+O

## 100 An Octet in K-map eliminates_______________ variable One Two

101 In K-map groups may be________________ Horizontal Vertical

## Simplification of Y = Σm(1,3,7,11,15) + d(0,2,5) using K-map

102 results into_______.(Consider A,E,I and O as literals) Y = IO+ĀĒ Y = IO+AE
What will be the result of minimising the logical expression
103 Y = ĀĒĪ + ĀEĪ + ĀEI + AĒI using K-map. ĀE + ĀI + AĒI AE + ĀĪ + AĒI

104 Identify the slowest of the logic families listed below LSTTL TTL

## In case of CMOS and TTL devices operating at same power

supply voltage of +5 volts, no additional interface IC is
105 required for________ TTL to CMOS interface CMOS to TTL interface
The basic CMOS 2-input NAND gate two N-channel and two
106 requires____________. two N-channel MOSFETS P-channel MOSFETS

## It is recommended that unused inputs of AND and NAND

107 gates of TTL family are not left open and are tied to logic High logic LOW
_______________ if the circuit which connects or isolates
108 it's input from it's output. Tristate buffer Wired AND
109 In TTL _______________ is lower than CMOS. Propogation delay Fan-out
CMOS IC can operate on higher power supply voltages,
110 when ______ noise margin is required. Lower Moderate
The ___________ devices are preferred for battery
111 operated systems. CMOS ECL
We have to use a _____________ network to protect the
112 CMOS IC against electrostatic discharge. Resistive Resistor Diode
Higher Operating
113 Due to __________ CMOS may get damaged permanently. Latch ups frequency

## 114 __________ are used as buffer/driver. Open collector TTL

The _______ operator represents complementary
115 function. NOT NOR
From the truth table below, determine the standard
116 SOP expression.
An OR gate with "bubbles" on its inputs performs the
117 same functions as ________ gate. NAND NOR
The expression Y=AB+(A+B)(ĀB+BB) is simplified
118 as Y= _____ A+B ĀB

## 119 Find the equivalent of ∑m(2,4,7). ∑M(0,1,3,5,-6) ∏m(0,1,3,5,6)

The expression Y=∑m(0,1) can also be represented as
120 Y=______ A B+A B AB+AB
The output of an OR gate with three inputs, A, B, and
121 C, is LOW when ________. A = 0, B = 0, C = 0 A = 0, B = 0, C = 1
Which of the examples below express the commutative
122 law of multiplication? A+ B= B+A AB = BA
Which is the correct logic function for this PAL
123 diagram?

## Derive the Boolean expression for the logic circuit

124 shown below:
The Boolean expression is logically
125 equivalent to which single gate? NAND NOR
Which of the following gates is described by the
126 expression X=ABCD ? OR AND
How many truth table entries are necessary for a four-
127 input circuit? 4 16
128 EX-OR gate is ______ gate. Derived Basic
How many AND gates are required to implement
129 Y=AB+CDE 1 2
130 The expression Y=ABC+ABC is in which form? Standard SOP Standard POS
131 0110 represnts which minterm? ABCD ABCD

## 132 The maxterm A+B+C is represented as ____. M4 m4

How many gates would be required to implement the
following Boolean expression after simplification? XY
133 + X(X + Z) + Y(X + Z) 1 2

## The Standard POS expression Y=(A+B+C)(A+B+C)

134 (A+B+C) is also expressed as Y=______. ∑M(0,6,2) ∏m(0,6,2)
135 The logic expression for a NOR gate is ________.
Find the most simplified SOP expression
136 for F = ABD + CD +ACD + ABC + ABCD. F = ABD + ABC + CD F = CD + AD
can be found in
The NAND or NOR gates are referred to as can be used to build all the other almost all digital
137 "universal" gates because either: types of gates circuits
The basic types of programmable arrays are made up
138 of ________. AND gates OR gates
139 How many AND gates are used in a 7408 IC? 1 2
Converting the Boolean expression LM + M(NO +
140 PQ) to SOP form, answer is ________. LM + MNOPQ L + MNO + MPQ
141 ASCII code is 4 bit code 6 bit code
Decoder Encoder
142 Decimal digits can be converted to binary format using
The output of gate is LOW when at least one of its AND OR
143 inputs is HIGH. It is true for
144 The BCD number for decimal 473 is 11101101 111011110101001
Which of the following rules states that if one input of
an AND gate is always 1 , the output is equal to the A+1=1 A+A=A
145 other input ?
the minimum number of NOR gates required to realize 2 3
146 X-NOR gate is
In a combinational circuit the ouputs at any instant only on past input only on past output
147 depend
The format used to present the logic output for the Boolean constant Boolean variable
148 various combinations of logic inputs to a gate is called
if a 3-input OR gate has eight input possibilities, how
many of those possibilities will result in a HIGH 1 2
149 output?

0 1

## 150 the output of the circuit shown is equal to:

Gate No.1 Gate No.2

## 151 In the above gate network which gate is redundant

signed 16 bit integer
floating point multiplication
152 Sign extension is a step in addition

81 72
153 the Octal equivalent of 111010 is
154 Which code is a weigthed code Gray Excess-3
155 The digital systems usually operate on ........system binary decimal
156 The binary system uses powers of ........for positional va 2 10
157 After counting 0, 1, 10, 11, the next binary number is 12 100
158 The number 10002 is equivalent to decimal number one thousand eight
159 In binary numbers, shifting the binary point one place tomultiplies by 2 divides by 2
160 The binary addition 1 + 1 + 1 gives 111 10
161 The cumulative addition of the four binary bits ( 1 + 1 + 1111 111
162 The result of binary subtraction (100 − 011) is −111 111
163 The chief reason why digital computers use complemental simplifies their circuitry is a very simple proces
164 The result of binary multiplication 1111 × 102 is 1101 110
165 The binary division 110002 ÷ 1002 gives 110 1100
166 Hexadecimal number system is used as a shorthand langua
decimal binary
167 Octal coding involves grouping the bits in 5's 7's
168 In Excess-3 code each coded number is .......than in BC four larger three smaller
169 Base 10 refers to which number system? binary coded decimal decimal
170 Which numbering system uses numbers and letters as s decimal binary
171 The number of bits used to store a BCD digit is 8 4
172 Sample-and-hold circuits in ADCs are designed to: sample and hold the output of the binastabilize the ADCs thres
Difficulty
OptionC OptionD Answer Marks Level

accepts many inputs and accepts one input and gives one
gives one output output C

## 2n-1 inputs 2n-1 inputs A

Multiplexer Demultiplexer D
Burst of microwaves Intense heat radiations A

## Two input are low All input are high D

MOS CMOS B
x+x.y=x None of the above C

DTL CMOS D

## 2’s complement form None of the above D

10110010.1011 10110010.1101 C

## 1’s complement 2’s complement D

X = –X + Y + 1 X= X – Y – 1 A

## Multiplication by two Subtraction by two A

110111 1011 B
142 101011110 C
1110 1111 D
10110110.01 10110110.11 C

## 2s complement All of the above C

110010 10011 D

7 8B

2F3.89 2F3.98 B

10 11 B
20.2 21.2 B

111010000 111100000 A
1000001 10011 C
Real no with fraction Integers C

101 110 C
6973 6379 B

12.71 17.21 B

FFFF ABCD C

X + YZ XZ + Y C

10V 20V B
ECL CMOS B

CMOS PMOS A

(A+B)A (A+B)B A

10 11 D

z x+y+z C

## x 'ex-or y x 'ex-or y ' D

lower hardware
requirement better noise immunity A

5 4C
CMOS LSI B 1

74154 74151 B 1

## large packing density. low cost. C 1

rise time fall time A 1

## constant None of these A 1

Equal to Extremely less than B 1

CMOS TTL B 1

## MOS devices p channel & n channel Mos devices D 1

20 50 A 1
TTL PMOS A 1
TTL PMOS C 1
Dual edge triggered D flip-
flop (TTL). Dual edge triggered JK flip-flop (CMOS). C 2

5 volts 0 volts D 2

One Constant D 2

## Fan-Out Noise Margin A 2

Noise margin Figure of merit A 2

40ohm 50ohm A 2

50 100 C 2

50µF 50mF A 2

## increases with increased

forward bias of BC junction None of these C 2

50% 25% C 2

## Clamping None of these C 2

74AS CMOS D 2
can drive maximum of 10
inputs can drive maximum of 10 outputs C 3

0 to 125° 0 to 55° A 3
2 to 6V 4 to 8V C 3
VIL(max)-VOL(max) VOH(min)-VIH(max) A 3
0.45V,1.5V 0.45V,2.5V A 3
105ns,10ns 10ns,70ns C 3

## VIL(max) — VOL(max) VOH(min)— VIH(max) A 3

normal open-collector TTL
gate open-collector buffer/driver TTL gate D 3

2.0,2.4V 0.2V,0.4V A 3

## the output transistor of a

TTL gate will not be
damaged nothing will happen to the gate A 3

## A low power schottky TTL

gate has higher fan out
while driving standard TTL
gates than while driving A low power schokkty gate has same fan
low power schottky TTL out while driving standard TTL gates &
gates low power schottky TTL gates. A 3

20 30 C 3

2V more than 2V D 3

16-bit 2-bit B 2

## The ‘1’ in the MSB position

indicates a negative
number after adding two
positive numbers. All of the above D 1
(FF)16 (FA)16 A 4
two possible encodings of
the decimal 0.
D4 24 A 2

## If adding two negative If the magnitude of the result is smaller

numbers results in a than the magnitude of the smaller add
positive result. end. C 2

8 128 B 2

4,4 2,4 C 1

## Eliminate both variables in Add both variables in resulting resulting

resulting resulting term term D 1

A+Ē+Ō Ā+E+O C 1

Three Eight C 1
Diagonal Both horizontal and vertical D 1

Y=ĀŌ + ĒI Y = IŌ + AĒ A 4

AE + AĪ + AĒI ĀE + ĀĪ + AĒI D 2

## either CMOS to TTL or TTL

to CMOS interface none of these A 1
one N-channel and one P-channel
two P-channel MOSFETS MOSFET B 1

LOW ground A 1

## open collector TTL TTL inverter A 1

Power dissipation Fan-in B 1

## Higher Extremely Low C 1

TTL RTL A 1

Capacitive Inductive B 1

## Open drain output CMOS Tristate buffer C 1

NAND EXNOR A 1 1

D 1 1
NOT OR A 1 1

B AB C 2 1

∑m(0,1,3,5,6) ∏m(0,1,3,5,-6) B 1 1

A B+A B A B+A B A 1 1

## A = 0, B = 1, C = 1 A=1 , B=1 ,C=1 A 1 1

AB = B + A AB = A * B B 1 1

C 4 4

A 1 1
AND OR A 1 1

NOR NAND B 1 1

8 12 B 1 1
Universal Complementary A 1 1

3 4C 1 1
SOP and POS POS A 1 1
ABCD ABCD C 1 1

M3 m3 C 1 1

4 5B 2 2

∑m(7,1,5) ∏M(7,1,5) A 2 2
D 1 1

F = BC + AB F = AC + AD A 2 2

## can be used in all types

of Combinational gates were the first gates to be integrated A 1 1

## NAND and NOR gates AND gates and OR gates D 2 2

3 4D 1 1
LM + M + NO + MPQ LM + MNO + MPQ D 1 1
8 bit code 7 bit code D 1 EASY
Mux Demux B 1 EASY

NOR OR A 1 EASY
010001110011 010011110011 C 1 EASY

4 5 D 1 EASY

## only on the inputs

past as well as present inputs C 1 EASY
present at that instant

7 8 C medium

## A B+A B ( A*B) * ( A*B) A 2 medium

Gate No.3 Gate No.4 B 2 medium

## 71 none of these B 1 easy

BCD 5111 C
octal hexadecimal A
8 16 A
101 110 B
four sixteen B
decreases by 10 increases by 10 A
110 11 D
100 1001 B
11 1D
can handle negative numbeavoids direct subtraction A
1001 1110 A
11 101 D
octal large D
4's 3's D
three larger much larger C
octal hexadecimal B
octal hexadecimal D
1 2B
stabilize the input analog s sample and hold the ADC staircase wavefoC
Explanation
(High speeds are possible in ECL because the transistors are
used in difference amplifier configuration, in which they are
never driven into saturation and thereby the storage time is
As in CMOS one device is ON & one is Always OFF so
eliminated.
power consumption is low

## Because CMOS circuits have large packing density.

MSI chip 7474 dual edge triggered D Flip-Flop

## In the bipolar saturated ligic families,the bipolar

transistors are used as the main device. It is used as a
switch & operated in the saturation or cutoff regions.

## Practically,the value of figure of merit should be as low

as possible. Figure of merit is always a compromise
beteen speed & power dissipation. That means if we try
to reduce the propagation delay then the power
dissipation will increase & vice-versa.
The speed power product is used as a common means
for measuring & comparing the overall performance of
different IC family.
TTL Ics were first developed in 1965 & they were known
as standard TTL.

## open or floating input acts extly same as if a logical 1 is

applied to that input.

## the temprature range for the series in 7400 is from 0 to

70°C, over a supply voltage range of 4.75 to 5.25V
NOT represents inversion or complementary

## Outputs which are 1 are taken for SOP.

Draw the truth table and then verify it.

## Use Rules : AB+AB=AB , BB=B, AĀ=0 ,A+1=1

Given function contains minterms and hence answer
should have remainig as maxterms

## First two combinations are to be considered for this

As OR gate is having its ouput 1 even if any of the
input is 1 therefore 1st option.
As cumulative law of multiplication therefore
second option
X sign indicates valid input considred for this
example.

## Trace the diagram according to gates.

As given expression is equivalent to ABC
Observing the expression , it is product and then
inversion

As 2^4=16
As it is formed from other basic gates.

## One for AB and two for CDE.

As both terms contains all variables.
As it is represented in Minterms.
ABC=011 amd minterm is ABCand therefore
maxterm is A+B+C

## Use Rule 1+A=1.

Find out from table and as its maxterm answer will
have for example A+B+C as 0,0,0 and which is 0th
term.
From truth table we will have the answer D

## NAND and NOR are used for buliding all other

types of gates.
Programmable arrays are combination of both AND
and OR gates
As according to structure only 4 gates are their.
Only SOP so solve brackets.

## encoder converts decimal information from n input

lines to n ouput lines
for AND operation if any of the input is LOW the
OUPUT is Low else it is High
4= 0100, 7= 0111, 3= 0011 => 010001110011

## if A=0 then, 0.0=0 ie A itself and if A=1 then, 1.1=1

ie again A itself

## because for input ABC when 000 then 0+0+0=0

making the group of 3 bits from LSB towards MSB
111=7 010=2=> 72

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