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10 Negative numbers cannot be represented in Signed magnitude form 1’s complement form
11 8-bit 1’s complement form of –77.25 is 1001101.01 1001101.001
39 In a positive logic system, logic state 1 corresponds to Positive voltage Higher voltage level
40 AB+(A+B)’ is equivalent to A*B A+B
The NAND gate output will be low if the two inputs
41 are 00 01
53 TTL tristate inverter consists of ______ 2 transistors & 2 diodes 4 transistors & 2 diodes
54 ___ digital Ics have highest packing density PMOS NMOS
only p channel Mos
55 CMOS consist of______ only n channel Mos devices devices
56 Recommended Fan out for TTL gate is_____ 10 4
57 ___ is operated in ohamic or cut-off regions CMOS ECL
58 _____ is operated in saturation or cut-off regions. CMOS ECL
Dual edge triggered D
59 The MSI chip 7474 is Dual edge triggered JK flip-flop (TTL). flip-flop (CMOS).
60 The logic 0 level of a CMOS logic device is approximately 1.2 volts 0.4 volts
decreases with
increases with increased reverse-bise increased forword-bise
71 The storage time of a trnasistor___ voltage of BC junction of BC junction
72 for fastest switching operation it is preferred to use______ normal p-n junction diodes schottky diodes
The average supply current,Icc is determined based on____
73 duty cycle 100% 75%
______ diodes are used in all TTL gates to suppress the
74 ringing caused from the fast voltage transitions Zener Free wheeling
which one of the following logic families can be operated
75 using a supply voltage from 3V to 15V? 74TTL 74LS
76 If a logic circuit has a fan-out of 10 then the circuit _____ has 10 inputs has 10 outputs
77 The temprature range for devices in 74XX series is from 0 to 70° 55 to 125°
78 Voltage range of CMOS Ics are from_____ 3 to 5V 4 to 6V
79 Noise margin is calculated as VOH(min)-VIH(min) VOH(max)-VIH(max)
80 Low level noise margin for CMOS is____ & TTL is ___ 0.5V,1.5V 0.4V,1.45V
Propagation delay of CMOS & TTL is _________
81 respectively 10ns,105ns 105ns,70ns
104 Identify the slowest of the logic families listed below LSTTL TTL
0 1
81 72
153 the Octal equivalent of 111010 is
154 Which code is a weigthed code Gray Excess-3
155 The digital systems usually operate on ........system binary decimal
156 The binary system uses powers of ........for positional va 2 10
157 After counting 0, 1, 10, 11, the next binary number is 12 100
158 The number 10002 is equivalent to decimal number one thousand eight
159 In binary numbers, shifting the binary point one place tomultiplies by 2 divides by 2
160 The binary addition 1 + 1 + 1 gives 111 10
161 The cumulative addition of the four binary bits ( 1 + 1 + 1111 111
162 The result of binary subtraction (100 − 011) is −111 111
163 The chief reason why digital computers use complemental simplifies their circuitry is a very simple proces
164 The result of binary multiplication 1111 × 102 is 1101 110
165 The binary division 110002 ÷ 1002 gives 110 1100
166 Hexadecimal number system is used as a shorthand langua
decimal binary
167 Octal coding involves grouping the bits in 5's 7's
168 In Excess-3 code each coded number is .......than in BC four larger three smaller
169 Base 10 refers to which number system? binary coded decimal decimal
170 Which numbering system uses numbers and letters as s decimal binary
171 The number of bits used to store a BCD digit is 8 4
172 Sample-and-hold circuits in ADCs are designed to: sample and hold the output of the binastabilize the ADCs thres
Difficulty
OptionC OptionD Answer Marks Level
accepts many inputs and accepts one input and gives one
gives one output output C
Multiplexer Demultiplexer D
Burst of microwaves Intense heat radiations A
MOS CMOS B
x+x.y=x None of the above C
DTL CMOS D
110111 1011 B
142 101011110 C
1110 1111 D
10110110.01 10110110.11 C
7 8B
2F3.89 2F3.98 B
10 11 B
20.2 21.2 B
111010000 111100000 A
1000001 10011 C
Real no with fraction Integers C
101 110 C
6973 6379 B
FFFF ABCD C
10V 20V B
ECL CMOS B
CMOS PMOS A
10 11 D
z x+y+z C
lower hardware
requirement better noise immunity A
5 4C
CMOS LSI B 1
74154 74151 B 1
5 volts 0 volts D 2
One Constant D 2
40ohm 50ohm A 2
50 100 C 2
50µF 50mF A 2
50% 25% C 2
74AS CMOS D 2
can drive maximum of 10
inputs can drive maximum of 10 outputs C 3
0 to 125° 0 to 55° A 3
2 to 6V 4 to 8V C 3
VIL(max)-VOL(max) VOH(min)-VIH(max) A 3
0.45V,1.5V 0.45V,2.5V A 3
105ns,10ns 10ns,70ns C 3
2.0,2.4V 0.2V,0.4V A 3
20 30 C 3
2V more than 2V D 3
16-bit 2-bit B 2
8 128 B 2
4,4 2,4 C 1
A+Ē+Ō Ā+E+O C 1
Three Eight C 1
Diagonal Both horizontal and vertical D 1
Y=ĀŌ + ĒI Y = IŌ + AĒ A 4
AE + AĪ + AĒI ĀE + ĀĪ + AĒI D 2
TTL RTL A 1
Capacitive Inductive B 1
NAND EXNOR A 1 1
D 1 1
NOT OR A 1 1
B AB C 2 1
∑m(0,1,3,5,6) ∏m(0,1,3,5,-6) B 1 1
A B+A B A B+A B A 1 1
AB = B + A AB = A * B B 1 1
C 4 4
A 1 1
AND OR A 1 1
NOR NAND B 1 1
8 12 B 1 1
Universal Complementary A 1 1
3 4C 1 1
SOP and POS POS A 1 1
ABCD ABCD C 1 1
M3 m3 C 1 1
4 5B 2 2
∑m(7,1,5) ∏M(7,1,5) A 2 2
D 1 1
F = BC + AB F = AC + AD A 2 2
NOR OR A 1 EASY
010001110011 010011110011 C 1 EASY
4 5 D 1 EASY
7 8 C medium
As 2^4=16
As it is formed from other basic gates.