MULTIPLE CHOCE QUESTIONS

SUBJECT : DIGITAL ELECTRONICS

GROUP NO. : 1
1. Low power dissipation is desired in large systems as it leads to
a. Lower cooling costs
b. Lower power supply and distribution costs,
c. Reduction in mechanical design problems
d. All of above

2. Which of the following logic families has the shortest propagation delay?
a. CMOS b. BiCMOS c. ECL d. RTL

3. Power dissipation increases linearly as a function of the

a. frequency of switching b. current
c. input voltage d. None of above

4. The noise margin of a logic gate is a measure of its noise immunity, a gate’s ability to withstand
a. output signal variations b. input signal variations
c. Power supply variations d. None of above

5. The shorter the propagation delay

a. higher is the speed of the circuit b. slower is the speed of the circuit
c. Depends on the logic family d. None of above

6. There are ___ number of propagation delays associated with a logic gate
a. 1 b. 2 c. 4 d. 5

7. The reference points on the wave forms with respect to which the time delays are measured can be chosen as
a. the 40% of the leading and trailing edges of the wave forms
b. the 50% of the leading and trailing edges of the wave forms
c. the 60% of the leading and trailing edges of the wave forms
d. the 100% of the leading and trailing edges of the wave forms

8. The military IC series has a universal requirement for operability from

a. -30oC to 55oC b. -30o C to 85oC
o o
c. 0 C to 55 C d. -55oC to 125o C

9. Consider the following statements regarding ICs:

1. ECL has the least propagation delay
2. TTL has the largest fanout
3. CMOS has the biggest noise margin
4. TTL has the lowest power consumption

Which of these statements are correct?

a. 1 and 3 b. 2 and 4
c. 3 and 4 d. 1 and 2

10. For a logic family

1. VOH is the minimum output high level voltage.

2. VOL is the maximum output low level voltage.
3. VIH is the minimum acceptable input high level voltage.
4. VIL is the maximum acceptable input low level voltage.
 Which of the following statement is correct,
a.1&2 b. 2&3
c. 2&4 d. 3&4

11. The time taken for the output of a gate to change after the inputs have changed is called
a. transient response b. propagation delay
c. noise immunity d. None of above

12. The delay conditions tPHL and tPLH are not necessarily equal and vary depending on
a. Load conditions b. input conditions
c. supply d. none of above

13. Fan in of a gate is defined as:

a. Number of inputs connected to the gate without degradation in voltage levels
b. Number of outputs connected to the gate without degradation in voltage levels
c. Number of inputs connected to the gate with degradation in voltage levels
d. Number of outputs connected to the gate with degradation in voltage levels

14. Fanout of a gate is defined as

a. Maximum number of similar logic gates that a gate can drive without degradation in voltage levels
b. Minimum number of similar logic gates that a gate can drive without degradation in voltage levels
c. Maximum number of dissimilar logic gates that a gate can drive without degradation in voltage levels
d. Minimum number of dissimilar logic gates that a gate can drive without degradation in voltage levels

15. __________ is the function of output impedance of the driving gate and the input impedance of driven gate
a. Fan- in b. Fan- out
c. Propagation delay d. None of above

16. The difference between operation input voltage level and threshold voltage is called _____________ of the
circuit
a. Noise margin b. Noise
c. Noise voltage d. None of above

17. Which family of logic circuits uses field effect transistors?

a. TTL b. CMOS
c. Both TTL and CMOS d. Neither TTL nor CMOS

18. The fan out of a 7400 NAND gate is

a. 2 TTL b. 5 TTL
c. 8 TTL d. 10 TTL

19. The maximum propagation value in case of 7400 NAND gate is

a. 1 second b. 20 milli-seconds
c. Less than 20 nano-seconds d. Less than 20 pico-seconds

20. The voltage needed for a TTL IC power supply is

a. 5 V dc b. 10 V dc
c. 2 V dc d. 20 V dc

21. The digital logic family which has minimum power dissipation is
a. TTL b. RTL
c. DTL d. CMOS

22. In digital ICs, Schottky transistors are preferred over normal transistors because of their
a. Lower Propagation delay b. Higher Propagation delay
c. Lower Power dissipation. d. Higher Power dissipation.
23. CMOS circuits consume power
a. Equal to TTL b. Less than TTL
c. Twice of TTL d. Thrice of TTL
24. In a positive logic system, logic state 1 corresponds to
a. positive voltage b. higher voltage level
c. zero voltage level d. lower voltage level

25. The logic 0 level of a CMOS logic device is approximately

a. 1.2 volts b. 0.4 volts
c. 5 volts d. 0 volts

26. Which among them is faster?

a. Saturated b. Non-saturated
c.Both d. None

27. An SSI device has circuit complexity of

a.12 to 99 equivalent gates b. Up to 12
c. 1000 to 9999 d.2000 t0 5000

28. An MSI device has complexity of

a.12 to 99 b.100 to 999
c .2000 to 5000 d.10000 to 00000

29. An LSI device has circuit complexity of

a. 100 to 9999 b. 10000 to 99999
c. 2000 to 5000 d.100 to 999

30. An VLSI device has circuit complexity of

a. 100 to 9999 b.2000 to 5000
c. 10000 to 99999 d.100 to 999

31. An ULSI devices has circuit complexity of

a.10000 to 99999 b.2000 to 5000
c. above 100000 d.1000 to 9999

32. A +ve going pulse is applied to an inverter. The time interval from the leading edge of the I/P to the leading edge
of O/P is 7nsec .This parameter is
a.Speed –Power product b. Propagation delay
c)power dissipation d)pulse width

33. When frequency of I/P signal to CMOS gate is increased the power dissipation
a.Decreases b.Increases
c.does not change d.decrease exponentially

34. CMOS operates more reliably than TTL in a high noise environment because of its
a. Low noise margin b.i/p capacitance
c.High noise margin d. Smaller power dissipation

35. Proper handling of a CMOS device is necessary because of its

a.Fragile construction b.High noise immunity
c.Susceptibility to electrostatic discharge d. Low power dissipation

36 .which of the following IC is not belong to TTL Family.

a.74F00 b.74AS00
c.74HC00 d.74AL500
37. The main advantage of the ECL over TTL or CMOS is
a.ECL is less expensive b.ECL consumes less power
c.ECL is available in greater variety of circuit types d. ECL is faster
38. ECL cannot be used in
a.High noise b. damp environment
c.high frequency application d.none

39. SSI & MSI circuits are available in

a.TTL b.CMOS
c.both a & b d.None

40. LSI ,VLSI & ULSI are implemented with

a.TTL b. CMOS
c. both a&b d).none

41. Prefix 74 in IC number indicates

a. Used in military application b. used in severe environment
c. used for general purpose d.None

42. Prefix 54 indicate in IC number indicates

a. Used for commercial grade b. Used for general purpose
c) used for military grade d. none

43. Speed of operation is

a. Directly proportional to propagation delay

b. Inversely proportional to propagation delay
c. Inversely proportional to power dissipation
d. Directly proportional to power dissipation

44.Which of the following logic families has the highest maximum clock frequency?
a. S-TTL b. HS-TTL
c. AS-TTL d. HCMOS
45. Which of the following logic families has the shortest propagation delay?
a .S-TTL b. AS-TTL c. HS-TTL d. HCMOS

46.Which TTL logic gate is used for wired ANDing

a.Open collector output b.Totem Pole

c.Tri state output d.ECL gates

47.The high input impedance of MOSFETs:

a. allows faster switching b. reduces input current and power dissipation

c. prevents dense packing d. creates low-noise reactions

48.The digital logic family which has minimum power dissipation is

a.TTL b.DTL
 c.RTL d.CMOS

49. Ten TTL loads per TTL driver is indicating:

a. noise immunity b. fan-out

c. power dissipation d.propagation delay

50. Why is a pull-up resistor needed for an open collector gate?

a. To provide Vcc for the IC b. To provide ground for the IC

c. To provide the HIGH voltage d. To provide the LOW voltage

51. The correct relationship among these is

a. VIH > VOH > VIL > VOL
b. VOH > VIH > VIL > VOL
c. VIH > VOH > VOL > VIL
d. VOH > VIH > VOL > VIL