CYRILL - Digital Electronics PDF

ACTP
ACTP -- FOUNDATION
FOUNDATION COURSE
COURSE
DIGITAL ELECTRONICS
Lecture By
CYRIL PRASANNA RAJ.P
Asst.Professor & Programme Manager
VLSI System Design Center
MSRSAS, Bangalore
MSRSAS VSD Center Cyril Prasanna Raj.P
Lecture Overview
z Introduction
z Boolean Algebra
z Logic Gates
z Karnaugh Maps
z Logic Circuits
z Examples

Why Digital?
z We live in an Analog world!
z BUT, digital processing gives us greater
freedom and performance
z Must move between Analog & Digital domains
Analog Domain
Digital Domain
A/D ..01001101.. D/A
DSP

Applications
z Consumer Electronics
» Video/Audio
» Control (Appliances, Automotive)
z Communications
» Wireless transceivers
» Modems
z Instrumentation
» Industrial & Scientific Test Equipment

A/D Conversion
Analog Digital Digital

In Filter Out
Anti-alias Sampling Quantization Digital

Filtering Coding
D/A Conversion
Digital Digital Analog
In DÆA Out
Filter
Digital DAC Analog Reconstruction

Decoding Hold Filtering

Boolean Algebra
z Number system
z Base Conversions
z Codes
z Logic Gates
z Boolean Algebra

Number System
z Basis for counting various items.

z Generally used NS is Decimal NS.
z Decimal No. can be expressed in units, tens,
hundreds, thousands & so on.
z Position of the digit w.r.t the decimal point determines
its value/weight.
z Example:
2 7 43.8
2 x 103 + 7 x 102 + 4 x 101 + 3 x 100 + 8 x 10-1 = 2743.81

Different Number System
z Decimal Number System (Base 10 system)

z Binary Number System (Base 2 system)
z Octal Number System (Base 8 system)
z Hexadecimal Number System (Base 16 system)

Binary Number System
z Contains only 2 nos. i.e., 0 & 1

z As in decimal system, each binary digit commonly
known as bit, has its own value or weight.
z Weight is expressed as a power of 2.
23 22 21 20 2-1 2-2 2-3 2-4

MSB ...... .. …... LSB

Decimal to binary Conversion
z Two Methods
» Repeated Division by 2 Method
» Sum of Weights Method

z Example of Repeated Division by 2 Method:
Number Divided by 2 Remainder

249 124 1
124 62 0
62 31 0
31 15 1
15 7 1
7 3 1
3 1 1
1 0 1
1 1 1 1 1 0 0 1

z Example of Sum of Weights Method
Convert 249 into its binary equivalent:
249 = 128 + 64 + 32 + 16 + 8 + 4 + 2 + 1
= 1 1 1 1 1 0 0 1
= (1 1 1 1 1 0 0 1)2

z Example of Fractional Decimal to binary Conversion
Convert 0.8125 into its binary equivalent:
Fraction Base Result

0.8125 x 2 = 1.625 = 0.625 with a carry of 1 MSB
0.625 x 2 = 1.25 = 0.25 with a carry of 1
0.25 x 2 = 0.50 = 0.50 with a carry of 0
0.50 x 2 = 1.00 = 0.00 with a carry of 1 LSB
So (0.8125)10 = (1101)2

Conversion of Binary to Decimal
z Multiply each bit of the binary no. with its

corresponding positional weight and add together.
z Convert (1101.01)2 into its Decimal equivalent
1 1 0 1.0 1
1 x 23 + 1 x 22 + 0 x 21 + 1 x 20 + 0 x 2-1 + 1 x 2-2 =13.25

Octal Number System
z Uses first eight digit of the decimal Number system:

0,1,2,3,4,5,6 & 7.
z Positional Weights are …. 83, 82, 81, 80, 8-1, 8-2, 8-3,
…..
z Conversion
» Convert (567.34)8 into decimal
» Convert (317.328)10 into Octal
» Convert (1011001111.0011)2 into Octal
» Convert (3456.7)8 into binary

Hexadecimal Number System
z Uses first 10 digit of the decimal Number system and

first 6 alphabets: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E & F.
z Positional Weights are …. 163, 162, 161, 160, 16-1,
16-2, 16-3, …..
z Conversion
» Convert (7E4)16 into decimal
» Convert (317.328)10 into Hexadecimal
» Convert (1011001111.00111)2 into Hexadecimal
» Convert (5A9.B4)16 into binary

Other Conversions
z Relationship between decimal, binary, octal, and hex
The other base

systems make it
easy to group
collections
of binary bits
i.e. Hex is just a collection

of 4 binary bits
1100 1010 0001

C A 1

Binary Codes

Binary Coded Decimal (BCD)
z Is a numeric code in which each digit of a decimal

number is represented by a separate group of bits.
z Most common is 8-4-2-1 BCD
z Easy to convert it to decimal (it is useful to represent
decimal numbers in some way other than binary)
z BCD is less efficient
z Arithmetic operations are more complex

Binary Coded Decimal (BCD)
Decimal Digits BCD Code

8 4 2 1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Logic Gates

Logic Signals
z Logic signals are signals with two possible ranges

correspond to logic 0 and logic 1
z There is undefined region between logic 0 range and
logic 1 range
z Positive logic :
- Logic 0 is assigned to the low voltage range “LOW”
- Logic 1 is assigned to the high voltage range
“HIGH”
z Negative logic :
- Logic 1 is assigned to the low voltage range “LOW”
- Logic 0 is assigned to the high voltage range
“HIGH”

Positive and Negative Logic
z General Concept
» Positive Logic
– High Voltage => Logic 1
– Low Voltage => Logic 0
» Negative Logic
– High Voltage => Logic 0
– Low Voltage => Logic 1

Logic Gates
z Basic elements that makes up the digital System.

z Circuit that is able to operate on a number of binary
i/ps to perform logical function.
z Many i/ps and only one o/ps.
z Basic gates are NOT, OR & AND.
z Universal gates are NAND & NOR.
z Other gates are XOR & XNOR.

Basic logic Gates
AND Gate OR Gate NOT Gate

X X
Z Z X Z
Y Y
X Y Z X Y Z X Z
0 0 0 0 0 0
0 1 0 0 1 1 0 1
1 0 0 1 0 1 1 0
1 1 1 1 1 1

Logic Gates
NAND Gate NOR Gate

X X
Z Z
Y Y
X Y Z X Y Z
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0

Logic Gates
XOR Gate XNOR Gate

X X
Z Z
Y Y
X Y Z X Y Z
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1

Timing Diagram
z 3 inputs NAND Gate Truth table

X
Y w X Y Z W
Z
0 0 0 1
0 0 1 1
X 0 1 0 1
0 1 1 1
Y
1 0 0 1
1 0 1 1
Z
1 1 0 1
W 1 1 1 0

Boolean Algebra
z Boolean Algebra defines the relationships between

binary variables (variables whose values are
restricted to 0 and 1).
z Used to simplify or re-arrange Boolean Equation to

make simple logical circuits.
z Operations
» AND (*): A AND B = 1 if and only if both A and B are 1
» OR (+): A OR B = 1 if and only if either A or B are 1
» NOT (¯¯): NOT A = 1 if and only if A = 0

Boolean Algebra
z Logical Expressions
» NOT gate: Y=A

» AND gate: Y = AB
» OR gate: Y=A+B
» NAND gate: Y = AB
» NOR gate: Y=A+B
» XOR gate: Y=A+B
» XNOR gate: Y=A B

Laws of Boolean Algebra
z Commutative Law:
» A+B=B+A
» AB = BA
z Associative Law:
» A + (B + C) = (A + B) + C
» A(BC) = (AB)C
z Distributive Law:
» A(B + C) = AB + AC

Postulates of Boolean Algebra
z Identities
» A+0=A
» A+1=1
» A*0=0
» A*1=A
z Idempotence
» A+A=A
» A*A=A
z Complements
» A+A=1
» A*A=0

Postulates of Boolean Algebra
z Involution
» (A)=A
z Absorption
» A + AB = A
» A(A + B) = A
z Others
» A + AB = A + B
» AB + AB = B
» (A + B) (A + C) = A + BC

DeMorgan’s Law
z Theorem 1
The complement of a product is equal to the sum of
complements.
AB = A + B
z Theorem 2
The complement of a sum is equal to the product of
complements.
A+B=A B

DeMorgan’s Theorem
z Symbolic DeMorgan’s duals exist for all gate

primitives
NAND
NOR
AND
OR
NOT
Logic Minimization
z Boolean Simplification
» Motivation
– Simpler logic
– Smaller delays
» Essence
– A*B + A*B = B;
– A*B + A*B = B etc.,
z Given a Boolean Expression it can be reduced using
the theorems of Boolean Algebra

Simplify Example 1
z Use the theorems of Boolean Algebra to simplify
Y = AC + (A + C)D
DeMorgan’s Law
Y = (A + C) + (A + C)D
Factor
Y = (A + C) (1 + D)
=1
Y=A+C
Simplify Example 2
z Use Boolean Algebra to simplify:
Y = A + C + ACD First, regroup

Y = A + A(CD) + C
Use: a + ab = a + b
Y = A + CD + C
Use it again
Y=A+D+C

Logic Minimization
z Can save you time in evaluating/designing

combinatorial logic – Align bubbles and non-bubbles
whenever possible
a d
c
f
!c e
b
a d
c
f
!c e
b

Minimization related Problems

Problem 1
Y = ABC’ + AB’C
Y = A(B + C)

Problem 2
z Y = AB’CD + A’BCD’ + A’B’C’D’

Problem 3
z Y = AB + CD

Universal Gates
z NAND & NOR gates are called as Universal Gates as

any function can be implemented using these gates.
z Realize basic gates using NAND & NOR gates.
z Realize XOR & XNOR using universal gates.

Universal Gates
Implementation using NAND Gates
z STEP 1: Draw the Logic circuit using basic gates

alone.
z STEP 2: If NAND hardware has been chosen, add
bubbles on the output of each AND gate and bubbles
on input sides of all OR gates.
z STEP 3: Add inverters on each line that received a
bubble in step 2.
z STEP 4: Replace bubbled OR by NAND .
z STEP 5: Eliminate double inversion.

Universal Gates
Implementation using NOR Gates
z STEP 1: Draw the Logic circuit using basic gates

alone.
z STEP 2: If NOR hardware has been chosen, add
bubbles on the output of each OR gate and bubbles
on input sides of all AND gates.
z STEP 3: Add inverters on each line that received a
bubble in step 2.
z STEP 4: Replace bubbled AND by NOR .
z STEP 5: Eliminate double inversion.

Universal Gates
z NAND NOR Equivalent
NAND
NOR

Venn Diagram
z Way of representing a Boolean equation.

z Visualizes the relationships among the variables of a
Boolean expression.
z AND operation is equivalent to Intersection of the 2
variables.
A.B↔ A∩B
z OR operation is equivalent to Union of the 2
variables.
A+B↔ AUB

Venn Diagram
A’
1 - Variable

Venn Diagram
A B
A’B
AB’
A’B’
AB
2 - Variable
Venn Diagram
A’B’C’ A
AB’C’
ABC’ AB’C
B C
ABC
A’B’C
A’BC
A’BC’
3 - Variable
Venn Diagram
z Realize using Venn diagram.
1. Y = A (B + C)
2. Y = XY + XYZ +XYZ’ + X’YZ

Part B : Karnaugh Map & Combinational
Circuits
z Karnaugh Map
z Combinational Circuits
» Half Adder
» Full Adder
» Parallel Adder
» Adders/Subtractors
» Magnitude Comparators
» Decoders
» Multiplexer
» Tristate Buffers
» Encoders

Karnaugh Map

K-Maps
z Array of cells in which each cell represents a binary
value of the input variables (minterm).
z Provides a systematic method for simplifying a

Boolean expression.
z If properly used, will produce the simplest SOP form.
z For n variable function, K-map consists of 2n cells
z Each cells can be represented by Minterm or

Maxterm.

K-Maps
z Adjacent cells are cells that differ by only a single

variable.
z Can be used for 4,5,6 variables, but beyond

6variables it is quite impractical to manipulate
manually.
z Boolean expression in SOP form can be plotted on K-

map by placing a 1 in each cell corresponding to a
term in SOP expression.

Procedure for grouping
z 1’s in adjacent cells must be combined in groups of
1’s, 2’s, 4’s, 8’s, 16’s ….(called as sub-cubes).
z Each group of 1’s should be maximized to include the

largest no of adjacent cells as possible in accordance
to the previous rule.
z Every 1’s on the map must be included in at least one

group.
z There can be overlapping groups if they include non

common 1’s.

Procedure for Simplification
z Each group of 1’s create a product term composed of

all variables that appear in only one form within the
group. Variables that appear both complemented and
uncomplemented are eliminated.
z Care should be taken, so that all 1’s are covered &

no repetitions is done.
z The final simplified expression is formed by summing

the product terms of all the groups.

2 Variable Karnaugh Map
A
B 0 1
0 A=1, B=0
A=O, B=0 1
A=1, B=1
A=O, B=1

A
A B F
B 0 1
0 0 1
0
0 1 1
1 0 0
1
1 1 0

A
A B F
B 0 1
0 0 1
0 1
0 1 1
1 0 0
1 1
1 1 0

A
A B F
B 0 1
0 0 1
0 1 0
0 1 1
1 0 0
1 1 0
1 1 0

A
A B F
B 0 1
0 0 1
0 1 0
0 1 1
1 0 0
1 1 0
1 1 0 A’ B’
A’ B F = A’B’ + A’B
F = A’

A
A B F
B 0 1
0 0 1
0 1 0
0 1 1
1 0 0
1 1 0
1 1 0
A=0
B = 0 or 1
F = A’B’ + A’B
F = A’

A
BC 0 1
Note the order of 00
the B C variables: 01
00
01 11
ABC=101
11 10
10
ABC=010

Truth Table to Karnaugh Map
A
A B C F
BC 0 1
0 0 0 0
0 0 1 0 00 0
0 1 0 1
0 1 1 1 01
1 0 0 0
1 0 1 1 11
1 1 0 0
1 1 1 1
10

A
A B C F
BC 0 1
0 0 0 0
0 0 1 0 00 0
0 1 0 1
0 1 1 1 01 0
1 0 0 0
1 0 1 1 11
1 1 0 0
1 1 1 1
10 1

A
A B C F
BC 0 1
0 0 0 0
0 0 1 0 00 0 0
0 1 0 1
0 1 1 1 01 0
1 0 0 0
1 0 1 1 11 1
1 1 0 0
1 1 1 1
10 1

A
A B C F
BC 0 1
0 0 0 0
0 0 1 0 00 0 0
0 1 0 1
0 1 1 1 01 0 1
1 0 0 0
1 0 1 1 11 1 1
1 1 0 0
1 1 1 1
10 1 0

Karnaugh Map to Boolean
Algebra
A
F = AC
BC 0 1
00 0 0
01 0 1
11 1 1
A = 1, C = 1, B = don’t care(0 or 1) 10 1 0

Karnaugh Map to Boolean
Algebra
A
F = AC + A’B
BC 0 1
00 0 0
01 0 1
A = 0, B = 1, C = don’t care
11 1 1
A = 1, C = 1, B = don’t care 10 1 0

K-Map: Key Idea
z Physical adjacency Ù
AB’ + AB = A
z A graphical way of finding these

Minterm Expression to
Karnaugh Map
A
BC 0 1
Σ m ( 1, 4, 5, 6 )
00 1
F (A,B,C) =
01 1
11
001
10
100

Karnaugh Map
A
BC 0 1
Σ m ( 1, 4, 5, 6 )
00 1
F (A,B,C) =
01 1 1
110
11
101
10 1

Karnaugh Map
A
BC 0 1
Σ m ( 1, 4, 5, 6 )
00 0 1
F (A,B,C) =
01 1 1
Remaining maps 11
spaces are 0.
0 0
10 0 1

Karnaugh Map
A
BC 0 1
Each minterm 00
0 4
corresponds to a 01
1 5
location on the
11
Karnaugh Map 3 7
10
2 6
m0 … m7

Maxterm Expression to
Karnaugh Map
A
Each maxterm in the BC 0 1
expression 00
0 4
corresponds to a 0 on
01
the Karnaugh Map 1 5
11
3 7
M0 … M7 10
2 6

Karnaugh Map
A
F (A,B,C) = Π M(2, 3, 4 ) BC 0 1
00 0
0 4
100 01
1 5
11 0
3 7
011 10 0
2 6
010

Karnaugh Map
A
BC 0 1
F (A,B,C) = Π M(2, 3, 4 )
00 1
0
0
4
01 1 1
Remaining maps 1 5
spaces are 1
11 0 1
3 7
10 0 1
2 6

Adjacent Spaces
A
BC 0 1
00 AB'C' Adjacent spaces on the

map differ by
01 A'B'C AB'C complementing exactly
one variable.
11 ABC
10

Adjacent Spaces
A
BC 0 1
00 AB'C' Note that the map

“wraps around” so edge
01
spaces are also
11 adjacent.
10 ABC'

Combining Terms
A Adjacent spaces can be
BC 0 1 combined using:
00 AB'C' XY + XY’ = X
01 A'B'C AB'C
A’B’C + AB’C = B’C
11
10 ABC' AB’C’ + ABC’ = AC’

Combining Terms
A Adjacent spaces can be
combined using:
BC 0 1
XY + XY’ = X
00 A'B'C' AB'C'
01 A'B'C AB'C A’B’C’ + AB’C’ + A’B’C + AB’C

B’C’(A + A’) + B’C (A + A’)
11 B’(C + C’)
B’
10
Can do multiple
applications of
theorem at once

Combining Terms
z Can do multiple applications of

AB’+AB=A at once
» Circle 2, 4, 8, 16, … squares at a time
» Must be a power of 2

Boolean Algebra to Karnaugh
Map
a
Plot:
bc 0 1
ab’c’ + bc + a’
00 1
01
11 1 1
10

Map
a
Plot:
bc 0 1
00 1 1
01 1
11 1 1
10 1

Map
a
bc 0 1
00 1 1
Plot:
01 1 0
Remaining map
11 1 1 spaces are 0
10 1 0

Mapping Sum of Product
Terms
The 3 variable map has 12 possible groups of 2 spaces
These become terms with 2 literals

X X X
YZ 0 1 YZ 0 1 YZ 0 1
00 00 00
01 01 01
11 11 11
10 10 10
Y’Z
X Z’

Mapping Sum of Product
Terms
The 3 variable map has 6 possible groups of 4 spaces
These become terms with 1 literal

X X X
YZ 0 1 YZ 0 1 YZ 0 1
00 00 00
01 01 01
11 11 11
10 10 10
Y
X Z’

WX
YZ 00 01 11 10
00
WXY’Z
01
11
10
Note strange row

and column orderings
WXYZ=0110
Required for adjacency

Map
AB
Plot:
CD 00 01 11 10
A’B + BD + AB’C’D + B’CD
00 1
01 1
11 1
10 1

Map
AB
Plot:
CD 00 01 11 10
00 1
01 1 1
11 1 1
10 1

Map
AB
Plot:
CD 00 01 11 10
00 1
01 1 1 1
11 1 1
10 1

Map
AB
Plot:
CD 00 01 11 10
00 1
01 1 1 1
11 1 1 1 1
10 1

Map
AB
Plot:
CD 00 01 11 10
00 0 1 0 0
01 0 1 1 1
Remaining map 11 1 1 1 1
spaces are 0
10 0 1 0 0

Karnaugh Map to Boolean Algebra
(Simplification)
AB
Plot:
CD 00 01 11 10
00 0 1 0 0
Generate:
01 0 1 1 1
11 1 1 1 1
10 0 1 0 0

(Simplification)
AB
Plot:
CD 00 01 11 10
00 0 1 0 0
Generate:
01 0 1 1 1
A’B
11 1 1 1 1
10 0 1 0 0

(Simplification)
AB
Plot:
CD 00 01 11 10
00 0 1 0 0
Generate:
01 0 1 1 1
A’B
11 1 1 1 1
10 0 1 0 0

(Simplification)
AB
Plot:
CD 00 01 11 10
00 0 1 0 0
Generate:
01 0 1 1 1
A’B + CD
11 1 1 1 1
10 0 1 0 0

(Simplification)
AB
Plot:
CD 00 01 11 10
00 0 1 0 0
Generate:
01 0 1 1 1
A’B + CD
11 1 1 1 1
10 0 1 0 0

(Simplification)
AB
Plot:
CD 00 01 11 10
00 0 1 0 0
Generate:
01 0 1 1 1
A’B + CD + AD
11 1 1 1 1
10 0 1 0 0
Smallest expressions result from choosing largest sized groups of 1’s.

Will learn exact procedure that guarantees minimal solution later.

Finding a Product of Sums
Solution
Circle the 0’s and write F’ LM

NP 00 01 11 10
00 1 0 0 1
01 1 1 1 1
11 1 1 1 0
10 1 1 1 1

Finding a Function through
Product of Sums

NP 00 01 11 10
F’ = MN’P’ 00 1 0 0 1
01 1 1 1 1
11 1 1 1 0
10 1 1 1 1

Finding a Function through
Product of Sums

NP 00 01 11 10
F’ = MN’P’ + LM’NP 00 1 0 0 1
01 1 1 1 1
11 1 1 1 0
10 1 1 1 1

Finding a Product of Sums
Expression

NP 00 01 11 10
F’ = MN’P’ + LM’NP 00 1 0 0 1
01 1 1 1 1
Now invert: 11 1 1 1 0
10 1 1 1 1
F = (M’+N+P)(L’+M+N’+P’)
Piece of cake…

Finding a Product of Sums Expression
Do It Directly
Circle the 0’s and write F directly LM

NP 00 01 11 10
F = (M’+N+P)(L’+M+N’+P’) 00 1 0 0 1
01 1 1 1 1
11 1 1 1 0
10 1 1 1 1
Piece of cake…

Combinational Circuit

Combinational vs. Sequential logic
z Input /Output representation of logic circuits :
x
Inputs y Logic Circuit F Output
Z
z Combinational logic circuits:

- The output depends only on the current input
- Input/Output relationship is described by the Truth Table
z Sequential logic circuits :
- The output depends on the current input and the previous
outputs
- Input/Output relationship is described by the State Table

Combinational Logic
z Half Adder
z Full Adder
z Adders/Subtractors
z Decoders
z Multiplexer
z Encoders

Design Steps of Combinational Ckt
1. Problem is stated
2. The no of available input variables & output

variables is determined.
3. The i/p & o/p variables are assigned letter symbols.
4. Truth table that defines the required relationship

between i/p & o/p is derived.
5. Simplified Boolean function for each o/p is obtained.
6. Logic diagram is drawn.

Half Adder
z Combinational circuit that adds 2 binary nos.

z HA accepts 2 binary digits on its input & produces 2
binary digits on its output, a Sum bit & a Carry bit.
A B C S
S=A+B
0 0 0 0
0 1 0 1
A
1 0 0 1
C = AB
B
1 1 1 0

Full Adder
z FA accepts 2 input bits & an input carry & generates

a sum output and an output carry.
z Basic difference between FA & HA is that FA accepts
an input carry.

Full Adder
BCin
A 00 01 11 10
A B Cin Sum Cout
0 0 1 0 1
0 0 0 0 0
1 1 0 1 0
0 0 1 0 1
Sum = A + B + Cin
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1 BCin
A 00 01 11 10
1 0 1 1 0
0 0 0 1 0
1 1 0 1 0
1 0 1 1 1
1 1 1 1 1
Cout = AB + BC + CA

Full Adder
A
B
Sum = A + B
C
Cout = (A + B)Cin +AB

Adder/Subtractors
z Binary subtraction is performed by adding the

minuend to the 2’s complement of the subtrahend.
z 2’s complement is obtained by complementing every

bit in the subtrahend and then adding 1 to LSB.
z This addition of 1 is accomplished by setting the input

carry Co to 1.

Adder/Subtractors
z An Adder/subtractor has 2 inputs, A = an-1 ….. a0 and

B = bn-1 … b0 and 1 output, F = fn-1 … f0 as well as
one select signal, S.
z When S = 0 then the circuit performs addition and

when S = 1, it performs subtraction.
z The below shown example is an 8 bit

adder/subtractor and represents a ripple-carry adder.

Adder/Subtractors

Adder/Subtractors

Decoder
z In general, an m-to-n decoder has m = log2n input

lines, Am-1, ….., A0, and n output lines Cn-1, …. C0, as
well as a control input, E.
z Whenever E = 0 all the outputs are 0 and whenever

E = 1 only the output Ci will be 1, where i is the
integer whose value is equal to the binary value on
the inputs Am-1, …., A0.

1-to-2 decoder
Fig1: Symbol Fig2: Truth table
Boolean Expression
C 0 = EA 0'
C1 = EA 0 Fig3: Logic Diagram

2-to-4 decoder
Boolean Expression
C 0 = EA 1' A 0'
C 1 = EA 1' A 0
C 2 = EA 1 A 0' Fig3: Logic Diagram
C 3 = EA 1 A 0

Multiplexer
z Multiplexer is a combinational component that can

select one of several data sources to be used.
z In general, mux will have n inputs, one output, and

log2n select signals that will select data from any one
of the n inputs to be passed to the output.
z Mostly available multiplexers are 2-to1 and 4-to-1.
z Using these multiplexers with larger no of inputs can

be easily be constructed.

2-to-1 Multiplexer
Fig1: 2-to1 mux Fig2: Truth table
Fig3: Logic Diagram

4-to-1 Multiplexer
Fig1: 4-to1 mux Fig2: Truth table
Fig3: Logic Diagram

Encoders
z An encoder is a digital circuit that performs the

inverse operation of a decoder.
z It has 2n(or lesser) input lines and n output lines.
z The output lines generates the binary code

corresponding to the input value.
z Octal to binary encoder has 8 i/p’s one for each octal

digit, and 3 o/p’s that generate the corresponding
code.

Priority Encoders
z A priority encoder has n inputs, Dn-1,…,D0, where

n = 2m for some m and log2n = m outputs, Am-1,…,A0.
z It also has an additional output called Any, which will
be 1 whenever any of the inputs has a value that is
different from 0.
z A 2-to-1 priority encoder has 2 inputs, D1 & D0, and
one output, A0, in addition to the Any output.
z Whenever D1 = 0 and D0 = 1, then A0 = 0, and
conversely, whenever D1 = 1 and D0 is a don’t care,
then A0 = 1.

2-to-1 Priority Encoders
Boolean Expression
A0 = D1
Any = D 0 + D1 Fig3: Logic Diagram

Part C: Sequential Circuits
z Sequential Circuits
z Binary Cell
z Latch (SR, gated SR, D)
z Flip-Flops (SR, D, JK)

Sequential circuits
z Circuits that depend on present inputs and past

outputs.
z Depending on the timing of the signals, Sequential
circuit is classified as
» Synchronous sequential circuit.
It is a system whose behavior can be defined from the
knowledge of its signals at discrete instants of time.
» Asynchronous sequential circuit.
It is a system whose behavior depends upon the order in
which its input signals change and can be affected at any
instant of time.

Sequential circuits

Binary Cell
z It is the fundamental building block of memory.

z It is meant to store one bit of binary information and it
must be SET to store a 1 and RESET to store a 0.
z They differ in construction but are identical in
functional properties.
z Examples of binary cell are Cross coupled NAND /
NOR gate cell.
z Basic property of the sequential circuit is preserved.

Binary Cell
z If SET input is Asserted and RESET
line is Not-asserted, Q will go to an
asserted condition.
z Asserted condition on Q, together with
(RESET) ‘ condition, drives Q’ to its
asserted condition, which comes back
Fig1: Cross-coupled NAND gate
around and reinforces the SET
condition.
z After this reinforcement the SET
condition can be removed and the
circuit will remain stable.
z Now the cell is said to be loaded with
the binary bit 1.
Fig2: Cross-coupled NOR gate

Binary Cell
Fig3: Cross-coupled NAND gate
Fig4: Truth-table

Latch
z A Latch is a temporary storage device which has 2

stable states.
z The basic difference between a Flip-flop and a Latch
is in the method used for changing their state.
z The input is passed to output when clock is true -
output follows input.
z The output is stable when clock is false - output
cannot change.
z It is a level sensitive operation, device operation is
transparent.

SR - Latch
z Often used to debounce a switch, or as a building

block for other memory devices.
z Output of each gate is connected to an input of the
opposite gate.
z For proper operation of an SR – flip-flop, only one
input should be low at a time.
z SR – latch goes into an undefined state when both
the inputs go HIGH simultaneously.

SR - Latch
1
0 S (set) S R Q Q’
1 Q
1 0 0 1
1 1 0 1 (after S = 1, R = 0)
1 0 1 1 0
1 1 1 0 (after S = 0, R = 1)
0 R (reset) 2 Q’
’ 0 0 1 1
(a) Logic diagram (b) Truth table

Flip - Flops
z Flip-flops are synchronous bistable devices, also

known as bistable multivibrator.
z Synchronous means, the output changes the state

only at a specified point on a triggering input called
as clock which is designated as the control input.
z An edge triggered flip-flop changes the state either at

the positive edge or at the negative edge of the clock
pulse.
z It is sensitive to its inputs only at the transition of the

clock.

Flip - Flops
z Reading inputs and writing outputs are two separate

operations of a Flip-flop.
z Input read is done at one clock edge and output is

written on the other clock edge.
z The device operation is not transparent.

SR Flip - Flops
z Often required to set or reset the memory cell in

synchronism with a train of pulses known as clock.
Such circuits are referred as clocked set-reset Flip-
Flop.
z In SR Flip-Flop, if clock pulse is present, its operation
is exactly the same as SR latch.
z If the clock pulse is not present, the first 2 NAND
gates are inhibited, which means that the circuit
responds to the inputs S & R only when the clock is
present.

SR Flip - Flops
Fig1: Schematic symbol Fig2: Logic diagram of SR flip-flop
Only one input should be low at a time.

Clock 0Î1Î0 transition causes input to be transferred to output.
Clock allows user control of transfer time.
Clock allows for input settling time prior to data read.

SR Flip - Flops
Fig3: Characteristic table Fig4: Excitation table

JK Flip - Flops
z JK flip-flop is a refinement of the SR Flip-Flop.

z The uncertainty in the state of an SR Flip-Flop when
S = R = 1 is eliminated by converting it into a JK Flip-
Flop.
z JK Flip-Flop constructed with 4 cross-coupled NAND
gates is shown in the next slide.
z It differs from SR flip-flop in that Q output is
connected back to the input of gate G2, and the Q’
output is connected back to the input of gate G1.
z JK flip-flop can be negative edge triggered type, in
which case the clock input is inverted.

JK Flip - Flops
Fig1: Schematic symbol Fig2: Logic diagram of JK flip-flop

JK Flip - Flops

JK Master - Slave Flip-Flop
z A master slave JK Flip-Flop is a cascade of 2 SR

Flip-Flops, with feedback from the outputs of the
second to the input of the first.
z Positive clock pulse are applied to the first Flip-Flop
and the clock pulses are inverted before these are
applied to the second.
z When Clk = 1, the first Flip-Flop is enabled and the
outputs Qm &Q’m respond to the inputs J & K
accordingly.
z At the same time, the second Flip-Flop is inhibited.

z When Clk = 0 the first Flip-Flop is inhibited and the

second is enabled. Therefore, the outputs Qout & Q’out
follow Qm & Q’m.
z Since the second Flip-Flop simply follows the first
one, it is referred as Slave and the first one as
Master, Hence the configuration is referred as
Master-Slave Flip-Flop.

Qm
Jin Qout
J Q J Q
Clk enable enable
Kin K Q/ K Q/ Q/out
Q’m

D Flip-Flop
z A D flip-flop is a bistable device that changes state on

a clock pulse.
z – “bistable” means that it remains stable in either a ‘0’
state or a ‘1’ state until it is explicitly changed.
z This enables us to store a single bit of information.
z It has only one input referred as D-input or data input.
z It is constructed using a SR or JK Flip-Flop.

D Flip-Flop
Fig1: Schematic symbol Fig2: Logic diagram of D flip-flop

D Flip-Flop

T Flip-Flop
z In a JK Flip-Flop, if J = K the resulting Flip-Flop is

referred to as a T Flip-Flop.
z It has only one input called as T-input.
z If T = 1 it acts as a toggle switch.
z For every clock pulse the output Q changes.
z It can be constructed using a JK Flip-Flop by shorting
the inputs to give a common input called as T-input.

T Flip-Flop
Fig1: Schematic symbol Fig2: Logic diagram of T flip-flop

T Flip-Flop
0 RESET cell
0 SET cell
SET cell
RESET cell

Thank You
Summary
&
Question Hour

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ACTP

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A/D ..01001101.. D/A

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Analog Digital Digital

Anti-alias Sampling Quantization Digital

Digital DAC Analog Reconstruction

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z Basis for counting various items.

2 x 103 + 7 x 102 + 4 x 101 + 3 x 100 + 8 x 10-1 = 2743.81

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z Decimal Number System (Base 10 system)

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z Contains only 2 nos. i.e., 0 & 1

23 22 21 20 2-1 2-2 2-3 2-4

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MSRSAS VSD Center Cyril Prasanna Raj.P

z Example of Repeated Division by 2 Method:

Number Divided by 2 Remainder

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z Example of Sum of Weights Method

Convert 249 into its binary equivalent:

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z Example of Fractional Decimal to binary Conversion

Convert 0.8125 into its binary equivalent:

Fraction Base Result

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z Multiply each bit of the binary no. with its

z Convert (1101.01)2 into its Decimal equivalent

1 x 23 + 1 x 22 + 0 x 21 + 1 x 20 + 0 x 2-1 + 1 x 2-2 =13.25

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z Uses first eight digit of the decimal Number system:

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z Uses first 10 digit of the decimal Number system and

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The other base

i.e. Hex is just a collection

1100 1010 0001

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MSRSAS VSD Center Cyril Prasanna Raj.P

z Is a numeric code in which each digit of a decimal

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Decimal Digits BCD Code

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MSRSAS VSD Center Cyril Prasanna Raj.P

z Logic signals are signals with two possible ranges

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MSRSAS VSD Center Cyril Prasanna Raj.P

z Basic elements that makes up the digital System.

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AND Gate OR Gate NOT Gate

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NAND Gate NOR Gate

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XOR Gate XNOR Gate

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z 3 inputs NAND Gate Truth table

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z Boolean Algebra defines the relationships between

z Used to simplify or re-arrange Boolean Equation to

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