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#ifndef __STM32F401xC_H
#define __STM32F401xC_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
*/
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/**
* @brief STM32F4XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers
****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable
Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management
Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault
Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault
Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call
Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor
Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV
Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick
Interrupt */
/****** STM32 specific Interrupt Numbers
**********************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog
Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection
Interrupt */
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI
line */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI
line */
FLASH_IRQn = 4, /*!< FLASH global
Interrupt */
RCC_IRQn = 5, /*!< RCC global
Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0
Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1
Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2
Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3
Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4
Interrupt */
DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global
Interrupt */
DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global
Interrupt */
DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global
Interrupt */
DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global
Interrupt */
DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global
Interrupt */
DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global
Interrupt */
DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global
Interrupt */
ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global
Interrupts */
EXTI9_5_IRQn = 23, /*!< External Line[9:5]
Interrupts */
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global
interrupt */
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global
interrupt */
TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global
interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare
Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global
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Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global
Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global
Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event
Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error
Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event
Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error
Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global
Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global
Interrupt */
USART1_IRQn = 37, /*!< USART1 global
Interrupt */
USART2_IRQn = 38, /*!< USART2 global
Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10]
Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line
Interrupt */
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line
interrupt */
DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7
Interrupt */
SDIO_IRQn = 49, /*!< SDIO global
Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global
Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global
Interrupt */
DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global
Interrupt */
DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global
Interrupt */
DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global
Interrupt */
DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global
Interrupt */
DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global
Interrupt */
OTG_FS_IRQn = 67, /*!< USB OTG FS global
Interrupt */
DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global
interrupt */
DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global
interrupt */
DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global
interrupt */
USART6_IRQn = 71, /*!< USART6 global
interrupt */
I2C3_EV_IRQn = 72, /*!< I2C3 event
interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error
interrupt */
FPU_IRQn = 81, /*!< FPU global
interrupt */
SPI4_IRQn = 84 /*!< SPI4 global
Interrupt */
} IRQn_Type;
/**
* @}
*/
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/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
__IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
__IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address
+ 0x300 */
__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address
+ 0x304 */
__IO uint32_t CDR; /*!< ADC common regular data register for dual
AND triple modes, Address offset: ADC1 base address
+ 0x308 */
} ADC_Common_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
} CRC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
}DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
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__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;
typedef struct
{
__IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
__IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
__IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
__IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
__IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
} FLASH_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset:
0x00 */
__IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset:
0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset:
0x08-0x14 */
uint32_t RESERVED[2]; /*!< Reserved,
0x18-0x1C */
__IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset:
0x20 */
} SYSCFG_TypeDef;
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/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
__IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
__IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
__IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
__IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
__IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
__IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
} IWDG_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
__IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address
offset: 0x00 */
__IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address
offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address
offset: 0x08 */
__IO uint32_t CIR; /*!< RCC clock interrupt register, Address
offset: 0x0C */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address
offset: 0x10 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address
offset: 0x14 */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address
offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved,
0x1C */
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address
offset: 0x20 */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address
offset: 0x24 */
uint32_t RESERVED1[2]; /*!< Reserved,
0x28-0x2C */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address
offset: 0x30 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address
offset: 0x34 */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address
offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved,
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0x3C */
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address
offset: 0x40 */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address
offset: 0x44 */
uint32_t RESERVED3[2]; /*!< Reserved,
0x48-0x4C */
__IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address
offset: 0x50 */
__IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address
offset: 0x54 */
__IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address
offset: 0x58 */
uint32_t RESERVED4; /*!< Reserved,
0x5C */
__IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address
offset: 0x60 */
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address
offset: 0x64 */
uint32_t RESERVED5[2]; /*!< Reserved,
0x68-0x6C */
__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address
offset: 0x70 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address
offset: 0x74 */
uint32_t RESERVED6[2]; /*!< Reserved,
0x78-0x7C */
__IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address
offset: 0x80 */
__IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address
offset: 0x84 */
uint32_t RESERVED7[1]; /*!< Reserved,
0x88 */
__IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address
offset: 0x8C */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00
*/
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04
*/
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08
*/
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C
*/
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10
*/
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14
*/
__IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18
*/
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C
*/
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20
*/
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24
*/
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28
*/
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C
*/
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30
*/
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34
*/
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38
*/
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C
*/
__IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40
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*/
__IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44
*/
__IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48
*/
uint32_t RESERVED7; /*!< Reserved, 0x4C
*/
__IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50
*/
__IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54
*/
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58
*/
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C
*/
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60
*/
__IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64
*/
__IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68
*/
__IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C
*/
__IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70
*/
__IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74
*/
__IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78
*/
__IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C
*/
__IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80
*/
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84
*/
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88
*/
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C
*/
__IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90
*/
__IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94
*/
__IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98
*/
__IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C
*/
} RTC_TypeDef;
/**
* @brief SD host Interface
*/
typedef struct
{
__IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00
*/
__IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04
*/
__IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08
*/
__IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C
*/
__IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10
*/
__IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14
*/
__IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18
*/
__IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C
*/
__IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20
*/
__IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24
*/
__IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28
*/
__IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C
*/
__IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30
*/
__IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34
*/
__IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38
*/
__IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C
*/
uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
__IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
__IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
} SDIO_TypeDef;
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/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
__IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
} USART_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief USB_OTG_Core_Registers
*/
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typedef struct
{
__IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
__IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
__IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
__IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
__IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
__IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
__IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
__IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
__IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
__IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
__IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
uint32_t Reserved30[2]; /*!< Reserved 030h */
__IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
__IO uint32_t CID; /*!< User ID Register 03Ch */
uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
__IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
} USB_OTG_GlobalTypeDef;
/**
* @brief USB_OTG_device_Registers
*/
typedef struct
{
__IO uint32_t DCFG; /*!< dev Configuration Register 800h */
__IO uint32_t DCTL; /*!< dev Control Register 804h */
__IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
uint32_t Reserved0C; /*!< Reserved 80Ch */
__IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
__IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
__IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
__IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
uint32_t Reserved20; /*!< Reserved 820h */
uint32_t Reserved9; /*!< Reserved 824h */
__IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
__IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
__IO uint32_t DTHRCTL; /*!< dev threshold 830h */
__IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
__IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
__IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
uint32_t Reserved40; /*!< dedicated EP mask 840h */
__IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
__IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
} USB_OTG_DeviceTypeDef;
/**
* @brief USB_OTG_IN_Endpoint-Specific_Register
*/
typedef struct
{
__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
__IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
__IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
__IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
} USB_OTG_INEndpointTypeDef;
/**
* @brief USB_OTG_OUT_Endpoint-Specific_Registers
*/
typedef struct
{
__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
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} USB_OTG_OUTEndpointTypeDef;
/**
* @brief USB_OTG_Host_Mode_Register_Structures
*/
typedef struct
{
__IO uint32_t HCFG; /*!< Host Configuration Register 400h */
__IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
__IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
uint32_t Reserved40C; /*!< Reserved 40Ch */
__IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
__IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
__IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
} USB_OTG_HostTypeDef;
/**
* @brief USB_OTG_Host_Channel_Specific_Registers
*/
typedef struct
{
__IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
__IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
__IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
__IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
__IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
__IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
uint32_t Reserved[2]; /*!< Reserved */
} USB_OTG_HostChannelTypeDef;
/**
* @}
*/
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
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#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
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/**
* @}
*/
/**
* @}
*/
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/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
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injected channels */
#define ADC_CR1_DISCNUM_Pos (13U)
#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits
(Discontinuous mode channel count) */
#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
#define ADC_CR1_JAWDEN_Pos (22U)
#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on
injected channels */
#define ADC_CR1_AWDEN_Pos (23U)
#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on
regular channels */
#define ADC_CR1_RES_Pos (24U)
#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */
#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits
(Resolution) */
#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */
#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */
#define ADC_CR1_OVRIE_Pos (26U)
#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
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#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External
Trigger Conversion mode for regular channelsp) */
#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
#define ADC_CR2_SWSTART_Pos (30U)
#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of
regular channels */
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#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0
Sample time selection) */
#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP1_Pos (3U)
#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1
Sample time selection) */
#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP2_Pos (6U)
#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2
Sample time selection) */
#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP3_Pos (9U)
#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3
Sample time selection) */
#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP4_Pos (12U)
#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4
Sample time selection) */
#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP5_Pos (15U)
#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5
Sample time selection) */
#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP6_Pos (18U)
#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6
Sample time selection) */
#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP7_Pos (21U)
#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7
Sample time selection) */
#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP8_Pos (24U)
#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8
Sample time selection) */
#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR2_SMP9_Pos (27U)
#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9
Sample time selection) */
#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
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/****************** Bit definition for ADC_JOFR2 register *******************/
#define ADC_JOFR2_JOFFSET2_Pos (0U)
#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected
channel 2 */
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/******************* Bit definition for ADC_SQR2 register *******************/
#define ADC_SQR2_SQ7_Pos (0U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th
conversion in regular sequence) */
#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ8_Pos (5U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th
conversion in regular sequence) */
#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ9_Pos (10U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th
conversion in regular sequence) */
#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ10_Pos (15U)
#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th
conversion in regular sequence) */
#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ11_Pos (20U)
#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th
conversion in regular sequence) */
#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ12_Pos (25U)
#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th
conversion in regular sequence) */
#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
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#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd
conversion in regular sequence) */
#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ4_Pos (15U)
#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th
conversion in regular sequence) */
#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ5_Pos (20U)
#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th
conversion in regular sequence) */
#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ6_Pos (25U)
#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th
conversion in regular sequence) */
#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
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Sequence length) */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
/* Legacy defines */
#define ADC_CSR_DOVR1 ADC_CSR_OVR1
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#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DDS_Pos (13U)
#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection
(Multi-ADC mode) */
#define ADC_CCR_DMA_Pos (14U)
#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct
Memory Access mode for multimode) */
#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
#define ADC_CCR_ADCPRE_Pos (16U)
#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC
prescaler) */
#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
#define ADC_CCR_VBATE_Pos (22U)
#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
#define ADC_CCR_TSVREFE_Pos (23U)
#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and
VREFINT Enable */
/* Legacy defines */
#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************************************************************************/
/* */
/* DMA Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMA_SxCR register *****************/
#define DMA_SxCR_CHSEL_Pos (25U)
#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
#define DMA_SxCR_CHSEL_0 0x02000000U
#define DMA_SxCR_CHSEL_1 0x04000000U
#define DMA_SxCR_CHSEL_2 0x08000000U
#define DMA_SxCR_MBURST_Pos (23U)
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#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
#define DMA_SxCR_PBURST_Pos (21U)
#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk
#define DMA_SxCR_DBM_Pos (18U)
#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
#define DMA_SxCR_PL_Pos (16U)
#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
#define DMA_SxCR_PL DMA_SxCR_PL_Msk
#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
#define DMA_SxCR_PINCOS_Pos (15U)
#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
#define DMA_SxCR_MSIZE_Pos (13U)
#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
#define DMA_SxCR_PSIZE_Pos (11U)
#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
#define DMA_SxCR_MINC_Pos (10U)
#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
#define DMA_SxCR_PINC_Pos (9U)
#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
#define DMA_SxCR_CIRC_Pos (8U)
#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
#define DMA_SxCR_DIR_Pos (6U)
#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
#define DMA_SxCR_PFCTRL_Pos (5U)
#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
#define DMA_SxCR_TCIE_Pos (4U)
#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
#define DMA_SxCR_HTIE_Pos (3U)
#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
#define DMA_SxCR_TEIE_Pos (2U)
#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
#define DMA_SxCR_DMEIE_Pos (1U)
#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
#define DMA_SxCR_EN_Pos (0U)
#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
#define DMA_SxCR_EN DMA_SxCR_EN_Msk
/* Legacy defines */
#define DMA_SxCR_ACK_Pos (20U)
#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
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#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
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#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
#define DMA_LISR_FEIF1_Pos (6U)
#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
#define DMA_LISR_TCIF0_Pos (5U)
#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
#define DMA_LISR_HTIF0_Pos (4U)
#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
#define DMA_LISR_TEIF0_Pos (3U)
#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
#define DMA_LISR_DMEIF0_Pos (2U)
#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
#define DMA_LISR_FEIF0_Pos (0U)
#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
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#define DMA_HISR_DMEIF4_Pos (2U)
#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
#define DMA_HISR_FEIF4_Pos (0U)
#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
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#define DMA_HIFCR_CTEIF7_Pos (25U)
#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
#define DMA_HIFCR_CDMEIF7_Pos (24U)
#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
#define DMA_HIFCR_CFEIF7_Pos (22U)
#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
#define DMA_HIFCR_CTCIF6_Pos (21U)
#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
#define DMA_HIFCR_CHTIF6_Pos (20U)
#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
#define DMA_HIFCR_CTEIF6_Pos (19U)
#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
#define DMA_HIFCR_CDMEIF6_Pos (18U)
#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
#define DMA_HIFCR_CFEIF6_Pos (16U)
#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
#define DMA_HIFCR_CTCIF5_Pos (11U)
#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
#define DMA_HIFCR_CHTIF5_Pos (10U)
#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
#define DMA_HIFCR_CTEIF5_Pos (9U)
#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
#define DMA_HIFCR_CDMEIF5_Pos (8U)
#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
#define DMA_HIFCR_CFEIF5_Pos (6U)
#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
#define DMA_HIFCR_CTCIF4_Pos (5U)
#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
#define DMA_HIFCR_CHTIF4_Pos (4U)
#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
#define DMA_HIFCR_CTEIF4_Pos (3U)
#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
#define DMA_HIFCR_CDMEIF4_Pos (2U)
#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
#define DMA_HIFCR_CFEIF4_Pos (0U)
#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
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/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0_Pos (0U)
#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0
*/
#define EXTI_IMR_MR1_Pos (1U)
#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1
*/
#define EXTI_IMR_MR2_Pos (2U)
#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2
*/
#define EXTI_IMR_MR3_Pos (3U)
#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3
*/
#define EXTI_IMR_MR4_Pos (4U)
#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4
*/
#define EXTI_IMR_MR5_Pos (5U)
#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5
*/
#define EXTI_IMR_MR6_Pos (6U)
#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6
*/
#define EXTI_IMR_MR7_Pos (7U)
#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7
*/
#define EXTI_IMR_MR8_Pos (8U)
#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8
*/
#define EXTI_IMR_MR9_Pos (9U)
#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9
*/
#define EXTI_IMR_MR10_Pos (10U)
#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line
10 */
#define EXTI_IMR_MR11_Pos (11U)
#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line
11 */
#define EXTI_IMR_MR12_Pos (12U)
#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line
12 */
#define EXTI_IMR_MR13_Pos (13U)
#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line
13 */
#define EXTI_IMR_MR14_Pos (14U)
#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line
14 */
#define EXTI_IMR_MR15_Pos (15U)
#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line
15 */
#define EXTI_IMR_MR16_Pos (16U)
#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line
16 */
#define EXTI_IMR_MR17_Pos (17U)
#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line
17 */
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line
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stm32f401xc.h - Printed on 09/12/2019 22:19:36
18 */
#define EXTI_IMR_MR19_Pos (19U)
#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line
19 */
#define EXTI_IMR_MR20_Pos (20U)
#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line
20 */
#define EXTI_IMR_MR21_Pos (21U)
#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line
21 */
#define EXTI_IMR_MR22_Pos (22U)
#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line
22 */
/* Reference Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
#define EXTI_IMR_IM1 EXTI_IMR_MR1
#define EXTI_IMR_IM2 EXTI_IMR_MR2
#define EXTI_IMR_IM3 EXTI_IMR_MR3
#define EXTI_IMR_IM4 EXTI_IMR_MR4
#define EXTI_IMR_IM5 EXTI_IMR_MR5
#define EXTI_IMR_IM6 EXTI_IMR_MR6
#define EXTI_IMR_IM7 EXTI_IMR_MR7
#define EXTI_IMR_IM8 EXTI_IMR_MR8
#define EXTI_IMR_IM9 EXTI_IMR_MR9
#define EXTI_IMR_IM10 EXTI_IMR_MR10
#define EXTI_IMR_IM11 EXTI_IMR_MR11
#define EXTI_IMR_IM12 EXTI_IMR_MR12
#define EXTI_IMR_IM13 EXTI_IMR_MR13
#define EXTI_IMR_IM14 EXTI_IMR_MR14
#define EXTI_IMR_IM15 EXTI_IMR_MR15
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
#define EXTI_IMR_IM19 EXTI_IMR_MR19
#define EXTI_IMR_IM20 EXTI_IMR_MR20
#define EXTI_IMR_IM21 EXTI_IMR_MR21
#define EXTI_IMR_IM22 EXTI_IMR_MR22
#define EXTI_IMR_IM_Pos (0U)
#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
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#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR_MR10_Pos (10U)
#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR_MR11_Pos (11U)
#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR_MR12_Pos (12U)
#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR_MR13_Pos (13U)
#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR_MR14_Pos (14U)
#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR_MR15_Pos (15U)
#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR_MR16_Pos (16U)
#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
#define EXTI_EMR_MR17_Pos (17U)
#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19_Pos (19U)
#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20_Pos (20U)
#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21_Pos (21U)
#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22_Pos (22U)
#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
/* Reference Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
#define EXTI_EMR_EM1 EXTI_EMR_MR1
#define EXTI_EMR_EM2 EXTI_EMR_MR2
#define EXTI_EMR_EM3 EXTI_EMR_MR3
#define EXTI_EMR_EM4 EXTI_EMR_MR4
#define EXTI_EMR_EM5 EXTI_EMR_MR5
#define EXTI_EMR_EM6 EXTI_EMR_MR6
#define EXTI_EMR_EM7 EXTI_EMR_MR7
#define EXTI_EMR_EM8 EXTI_EMR_MR8
#define EXTI_EMR_EM9 EXTI_EMR_MR9
#define EXTI_EMR_EM10 EXTI_EMR_MR10
#define EXTI_EMR_EM11 EXTI_EMR_MR11
#define EXTI_EMR_EM12 EXTI_EMR_MR12
#define EXTI_EMR_EM13 EXTI_EMR_MR13
#define EXTI_EMR_EM14 EXTI_EMR_MR14
#define EXTI_EMR_EM15 EXTI_EMR_MR15
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
#define EXTI_EMR_EM19 EXTI_EMR_MR19
#define EXTI_EMR_EM20 EXTI_EMR_MR20
#define EXTI_EMR_EM21 EXTI_EMR_MR21
#define EXTI_EMR_EM22 EXTI_EMR_MR22
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#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event
configuration bit of line 2 */
#define EXTI_RTSR_TR3_Pos (3U)
#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event
configuration bit of line 3 */
#define EXTI_RTSR_TR4_Pos (4U)
#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event
configuration bit of line 4 */
#define EXTI_RTSR_TR5_Pos (5U)
#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event
configuration bit of line 5 */
#define EXTI_RTSR_TR6_Pos (6U)
#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event
configuration bit of line 6 */
#define EXTI_RTSR_TR7_Pos (7U)
#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event
configuration bit of line 7 */
#define EXTI_RTSR_TR8_Pos (8U)
#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event
configuration bit of line 8 */
#define EXTI_RTSR_TR9_Pos (9U)
#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event
configuration bit of line 9 */
#define EXTI_RTSR_TR10_Pos (10U)
#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event
configuration bit of line 10 */
#define EXTI_RTSR_TR11_Pos (11U)
#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event
configuration bit of line 11 */
#define EXTI_RTSR_TR12_Pos (12U)
#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event
configuration bit of line 12 */
#define EXTI_RTSR_TR13_Pos (13U)
#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event
configuration bit of line 13 */
#define EXTI_RTSR_TR14_Pos (14U)
#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event
configuration bit of line 14 */
#define EXTI_RTSR_TR15_Pos (15U)
#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event
configuration bit of line 15 */
#define EXTI_RTSR_TR16_Pos (16U)
#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event
configuration bit of line 16 */
#define EXTI_RTSR_TR17_Pos (17U)
#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event
configuration bit of line 17 */
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event
configuration bit of line 18 */
#define EXTI_RTSR_TR19_Pos (19U)
#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event
configuration bit of line 19 */
#define EXTI_RTSR_TR20_Pos (20U)
#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event
configuration bit of line 20 */
#define EXTI_RTSR_TR21_Pos (21U)
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#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event
configuration bit of line 21 */
#define EXTI_RTSR_TR22_Pos (22U)
#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event
configuration bit of line 22 */
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configuration bit of line 16 */
#define EXTI_FTSR_TR17_Pos (17U)
#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event
configuration bit of line 17 */
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event
configuration bit of line 18 */
#define EXTI_FTSR_TR19_Pos (19U)
#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event
configuration bit of line 19 */
#define EXTI_FTSR_TR20_Pos (20U)
#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event
configuration bit of line 20 */
#define EXTI_FTSR_TR21_Pos (21U)
#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event
configuration bit of line 21 */
#define EXTI_FTSR_TR22_Pos (22U)
#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event
configuration bit of line 22 */
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stm32f401xc.h - Printed on 09/12/2019 22:19:39
#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on
line 12 */
#define EXTI_SWIER_SWIER13_Pos (13U)
#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on
line 13 */
#define EXTI_SWIER_SWIER14_Pos (14U)
#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on
line 14 */
#define EXTI_SWIER_SWIER15_Pos (15U)
#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on
line 15 */
#define EXTI_SWIER_SWIER16_Pos (16U)
#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on
line 16 */
#define EXTI_SWIER_SWIER17_Pos (17U)
#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on
line 17 */
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on
line 18 */
#define EXTI_SWIER_SWIER19_Pos (19U)
#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on
line 19 */
#define EXTI_SWIER_SWIER20_Pos (20U)
#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on
line 20 */
#define EXTI_SWIER_SWIER21_Pos (21U)
#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on
line 21 */
#define EXTI_SWIER_SWIER22_Pos (22U)
#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on
line 22 */
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#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
#define EXTI_PR_PR11_Pos (11U)
#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
#define EXTI_PR_PR12_Pos (12U)
#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
#define EXTI_PR_PR13_Pos (13U)
#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
#define EXTI_PR_PR14_Pos (14U)
#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
#define EXTI_PR_PR15_Pos (15U)
#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
#define EXTI_PR_PR16_Pos (16U)
#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
#define EXTI_PR_PR17_Pos (17U)
#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
#define EXTI_PR_PR19_Pos (19U)
#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR_PR20_Pos (20U)
#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR_PR21_Pos (21U)
#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR_PR22_Pos (22U)
#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U
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#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
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stm32f401xc.h - Printed on 09/12/2019 22:19:40
#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
#define FLASH_OPTCR_nRST_STOP_Pos (6U)
#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
#define FLASH_OPTCR_RDP_Pos (8U)
#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
#define FLASH_OPTCR_nWRP_Pos (16U)
#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
#define FLASH_OPTCR_nWRP_0 0x00010000U
#define FLASH_OPTCR_nWRP_1 0x00020000U
#define FLASH_OPTCR_nWRP_2 0x00040000U
#define FLASH_OPTCR_nWRP_3 0x00080000U
#define FLASH_OPTCR_nWRP_4 0x00100000U
#define FLASH_OPTCR_nWRP_5 0x00200000U
#define FLASH_OPTCR_nWRP_6 0x00400000U
#define FLASH_OPTCR_nWRP_7 0x00800000U
#define FLASH_OPTCR_nWRP_8 0x01000000U
#define FLASH_OPTCR_nWRP_9 0x02000000U
#define FLASH_OPTCR_nWRP_10 0x04000000U
#define FLASH_OPTCR_nWRP_11 0x08000000U
/******************************************************************************/
/* */
/* General Purpose I/O */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODER0_Pos (0U)
#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODER1_Pos (2U)
#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODER2_Pos (4U)
#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODER3_Pos (6U)
#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
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#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODER4_Pos (8U)
#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODER5_Pos (10U)
#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODER6_Pos (12U)
#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODER7_Pos (14U)
#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODER8_Pos (16U)
#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODER9_Pos (18U)
#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODER10_Pos (20U)
#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODER11_Pos (22U)
#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODER12_Pos (24U)
#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODER13_Pos (26U)
#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODER14_Pos (28U)
#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODER15_Pos (30U)
#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
#define GPIO_MODER_MODE0 GPIO_MODER_MODER0
#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
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#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
#define GPIO_MODER_MODE3 GPIO_MODER_MODER3
#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
#define GPIO_MODER_MODE4 GPIO_MODER_MODER4
#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
#define GPIO_MODER_MODE5 GPIO_MODER_MODER5
#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
#define GPIO_MODER_MODE6 GPIO_MODER_MODER6
#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
#define GPIO_MODER_MODE7 GPIO_MODER_MODER7
#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
#define GPIO_MODER_MODE9 GPIO_MODER_MODER9
#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
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#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
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#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
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#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
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#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos (14U)
#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos (16U)
#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos (18U)
#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos (20U)
#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos (22U)
#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos (24U)
#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos (26U)
#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos (28U)
#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos (30U)
#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
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#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
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#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
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#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
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#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
#define GPIO_BRR_BR0 GPIO_BSRR_BR0
#define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
#define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
#define GPIO_BRR_BR1 GPIO_BSRR_BR1
#define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
#define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
#define GPIO_BRR_BR2 GPIO_BSRR_BR2
#define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
#define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
#define GPIO_BRR_BR3 GPIO_BSRR_BR3
#define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
#define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
#define GPIO_BRR_BR4 GPIO_BSRR_BR4
#define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
#define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
#define GPIO_BRR_BR5 GPIO_BSRR_BR5
#define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
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#define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
#define GPIO_BRR_BR6 GPIO_BSRR_BR6
#define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
#define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
#define GPIO_BRR_BR7 GPIO_BSRR_BR7
#define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
#define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
#define GPIO_BRR_BR8 GPIO_BSRR_BR8
#define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
#define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
#define GPIO_BRR_BR9 GPIO_BSRR_BR9
#define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
#define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
#define GPIO_BRR_BR10 GPIO_BSRR_BR10
#define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
#define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
#define GPIO_BRR_BR11 GPIO_BSRR_BR11
#define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
#define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
#define GPIO_BRR_BR12 GPIO_BSRR_BR12
#define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
#define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
#define GPIO_BRR_BR13 GPIO_BSRR_BR13
#define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
#define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
#define GPIO_BRR_BR14 GPIO_BSRR_BR14
#define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
#define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
#define GPIO_BRR_BR15 GPIO_BSRR_BR15
#define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
#define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos (1U)
#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos (2U)
#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos (3U)
#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos (4U)
#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos (5U)
#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos (6U)
#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos (7U)
#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos (8U)
#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos (9U)
#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
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#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos (16U)
#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
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#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
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#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register ********************/
#define I2C_CR1_PE_Pos (0U)
#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral
Enable */
#define I2C_CR1_SMBUS_Pos (1U)
#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus
Mode */
#define I2C_CR1_SMBTYPE_Pos (3U)
#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus
Type */
#define I2C_CR1_ENARP_Pos (4U)
#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
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#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP
Enable */
#define I2C_CR1_ENPEC_Pos (5U)
#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC
Enable */
#define I2C_CR1_ENGC_Pos (6U)
#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call
Enable */
#define I2C_CR1_NOSTRETCH_Pos (7U)
#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable
(Slave mode) */
#define I2C_CR1_START_Pos (8U)
#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */
#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start
Generation */
#define I2C_CR1_STOP_Pos (9U)
#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop
Generation */
#define I2C_CR1_ACK_Pos (10U)
#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge
Enable */
#define I2C_CR1_POS_Pos (11U)
#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */
#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position
(for data reception) */
#define I2C_CR1_PEC_Pos (12U)
#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error
Checking */
#define I2C_CR1_ALERT_Pos (13U)
#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus
Alert */
#define I2C_CR1_SWRST_Pos (15U)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software
Reset */
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#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
#define I2C_OAR1_ADD1_Pos (1U)
#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
#define I2C_OAR1_ADD2_Pos (2U)
#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
#define I2C_OAR1_ADD3_Pos (3U)
#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
#define I2C_OAR1_ADD4_Pos (4U)
#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
#define I2C_OAR1_ADD5_Pos (5U)
#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
#define I2C_OAR1_ADD6_Pos (6U)
#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
#define I2C_OAR1_ADD7_Pos (7U)
#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
#define I2C_OAR1_ADD8_Pos (8U)
#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
#define I2C_OAR1_ADD9_Pos (9U)
#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
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#define I2C_SR1_TXE_Pos (7U)
#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty
(transmitters) */
#define I2C_SR1_BERR_Pos (8U)
#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus
Error */
#define I2C_SR1_ARLO_Pos (9U)
#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master
mode) */
#define I2C_SR1_AF_Pos (10U)
#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */
#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge
Failure */
#define I2C_SR1_OVR_Pos (11U)
#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
#define I2C_SR1_OVR I2C_SR1_OVR_Msk
/*!<Overrun/Underrun */
#define I2C_SR1_PECERR_Pos (12U)
#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in
reception */
#define I2C_SR1_TIMEOUT_Pos (14U)
#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow
Error */
#define I2C_SR1_SMBALERT_Pos (15U)
#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus
Alert */
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#define I2C_CCR_FS_Pos (15U)
#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */
#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode
Selection */
/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY_Pos (0U)
#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only,
read 0000h) */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR register ********************/
#define PWR_CR_LPDS_Pos (0U)
#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power
Deepsleep */
#define PWR_CR_PDDS_Pos (1U)
#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down
Deepsleep */
#define PWR_CR_CWUF_Pos (2U)
#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup
Flag */
#define PWR_CR_CSBF_Pos (3U)
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#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby
Flag */
#define PWR_CR_PVDE_Pos (4U)
#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector
Enable */
/* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS
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#define PWR_CSR_BRE_Pos (9U)
#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator
enable */
#define PWR_CSR_VOSRDY_Pos (14U)
#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage
scaling output selection ready */
/* Legacy define */
#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (0U)
#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
#define RCC_CR_HSION RCC_CR_HSION_Msk
#define RCC_CR_HSIRDY_Pos (1U)
#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
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Page 58
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#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system
clock */
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#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
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stm32f401xc.h - Printed on 09/12/2019 22:19:50
#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
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stm32f401xc.h - Printed on 09/12/2019 22:19:50
#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
#define RCC_APB1RSTR_PWRRST_Pos (28U)
#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
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Page 63
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#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
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#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
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#define RCC_CSR_BORRSTF_Pos (25U)
#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
#define RCC_CSR_PINRSTF_Pos (26U)
#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
#define RCC_CSR_PORRSTF_Pos (27U)
#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
#define RCC_CSR_SFTRSTF_Pos (28U)
#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
#define RCC_CSR_IWDGRSTF_Pos (29U)
#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
#define RCC_CSR_WWDGRSTF_Pos (30U)
#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
#define RCC_CSR_LPWRRSTF_Pos (31U)
#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
/* Legacy defines */
#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
#define RTC_TR_PM RTC_TR_PM_Msk
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#define RTC_TR_HT_Pos (20U)
#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
#define RTC_TR_HT RTC_TR_HT_Msk
#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
#define RTC_TR_HU_Pos (16U)
#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TR_HU RTC_TR_HU_Msk
#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
#define RTC_TR_MNT_Pos (12U)
#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TR_MNT RTC_TR_MNT_Msk
#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TR_MNU_Pos (8U)
#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TR_MNU RTC_TR_MNU_Msk
#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TR_ST_Pos (4U)
#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
#define RTC_TR_ST RTC_TR_ST_Msk
#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
#define RTC_TR_SU_Pos (0U)
#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
#define RTC_TR_SU RTC_TR_SU_Msk
#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
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#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
#define RTC_DR_DU RTC_DR_DU_Msk
#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
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/* Legacy defines */
#define RTC_CR_BCK RTC_CR_BKP
Page 69
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#define RTC_ALRMAR_MSK4_Pos (31U)
#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
#define RTC_ALRMAR_WDSEL_Pos (30U)
#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_DT_Pos (28U)
#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMAR_DU_Pos (24U)
#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMAR_MSK3_Pos (23U)
#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_PM_Pos (22U)
#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_HT_Pos (20U)
#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMAR_HU_Pos (16U)
#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMAR_MSK2_Pos (15U)
#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_MNT_Pos (12U)
#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMAR_MNU_Pos (8U)
#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMAR_MSK1_Pos (7U)
#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_ST_Pos (4U)
#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMAR_SU_Pos (0U)
#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
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#define RTC_ALRMBR_DT_Pos (28U)
#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMBR_DU_Pos (24U)
#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMBR_MSK3_Pos (23U)
#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_PM_Pos (22U)
#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_HT_Pos (20U)
#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMBR_HU_Pos (16U)
#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMBR_MSK2_Pos (15U)
#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_MNT_Pos (12U)
#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMBR_MNU_Pos (8U)
#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMBR_MSK1_Pos (7U)
#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_ST_Pos (4U)
#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMBR_SU_Pos (0U)
#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
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#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
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#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
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#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
/* Legacy defines */
#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
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#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP9R RTC_BKP9R_Msk
/******************************************************************************/
/* */
/* SD host Interface */
/* */
/******************************************************************************/
/****************** Bit definition for SDIO_POWER register ******************/
#define SDIO_POWER_PWRCTRL_Pos (0U)
#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power
supply control bits) */
#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
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#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable
bit */
#define SDIO_CLKCR_PWRSAV_Pos (9U)
#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving
configuration bit */
#define SDIO_CLKCR_BYPASS_Pos (10U)
#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass
enable bit */
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#define SDIO_RESPCMD_RESPCMD_Pos (0U)
#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
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#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
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full */
#define SDIO_STA_RXFIFOF_Pos (17U)
#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO
full */
#define SDIO_STA_TXFIFOE_Pos (18U)
#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO
empty */
#define SDIO_STA_RXFIFOE_Pos (19U)
#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO
empty */
#define SDIO_STA_TXDAVL_Pos (20U)
#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in
transmit FIFO */
#define SDIO_STA_RXDAVL_Pos (21U)
#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive
FIFO */
#define SDIO_STA_SDIOIT_Pos (22U)
#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt
received */
#define SDIO_STA_CEATAEND_Pos (23U)
#define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion
signal received for CMD61 */
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#define SDIO_MASK_DCRCFAILIE_Pos (1U)
#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt
Enable */
#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt
Enable */
#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt
Enable */
#define SDIO_MASK_TXUNDERRIE_Pos (4U)
#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error
Interrupt Enable */
#define SDIO_MASK_RXOVERRIE_Pos (5U)
#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error
Interrupt Enable */
#define SDIO_MASK_CMDRENDIE_Pos (6U)
#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received
Interrupt Enable */
#define SDIO_MASK_CMDSENTIE_Pos (7U)
#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt
Enable */
#define SDIO_MASK_DATAENDIE_Pos (8U)
#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt
Enable */
#define SDIO_MASK_STBITERRIE_Pos (9U)
#define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt
Enable */
#define SDIO_MASK_DBCKENDIE_Pos (10U)
#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt
Enable */
#define SDIO_MASK_CMDACTIE_Pos (11U)
#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt
Enable */
#define SDIO_MASK_TXACTIE_Pos (12U)
#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting
Interrupt Enable */
#define SDIO_MASK_RXACTIE_Pos (13U)
#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting
interrupt enabled */
#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty
interrupt Enable */
#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full
interrupt Enable */
#define SDIO_MASK_TXFIFOFIE_Pos (16U)
#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt
Enable */
#define SDIO_MASK_RXFIFOFIE_Pos (17U)
#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt
Enable */
#define SDIO_MASK_TXFIFOEIE_Pos (18U)
#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt
Enable */
#define SDIO_MASK_RXFIFOEIE_Pos (19U)
#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt
Enable */
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#define SDIO_MASK_TXDAVLIE_Pos (20U)
#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO
interrupt Enable */
#define SDIO_MASK_RXDAVLIE_Pos (21U)
#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO
interrupt Enable */
#define SDIO_MASK_SDIOITIE_Pos (22U)
#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt
Received interrupt Enable */
#define SDIO_MASK_CEATAENDIE_Pos (23U)
#define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion
signal received Interrupt Enable */
/******************************************************************************/
/* */
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
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#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame
Format */
#define SPI_CR1_CRCNEXT_Pos (12U)
#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC
next */
#define SPI_CR1_CRCEN_Pos (13U)
#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation
enable */
#define SPI_CR1_BIDIOE_Pos (14U)
#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in
bidirectional mode */
#define SPI_CR1_BIDIMODE_Pos (15U)
#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode
enable */
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#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
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#define SPI_I2SPR_MCKOE_Pos (9U)
#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output
Enable */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap
Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_ADC1DC2_Pos (16U)
#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how
to use this bit */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
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/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
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#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
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/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
#define TIM_CR1_UDIS_Pos (1U)
#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
#define TIM_CR1_URS_Pos (2U)
#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
#define TIM_CR1_OPM_Pos (3U)
#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
#define TIM_CR1_DIR_Pos (4U)
#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
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#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master
Mode Selection) */
#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x0010 */
#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x0020 */
#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x0040 */
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#define TIM_SR_CC1IF_Pos (1U)
#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1
interrupt Flag */
#define TIM_SR_CC2IF_Pos (2U)
#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2
interrupt Flag */
#define TIM_SR_CC3IF_Pos (3U)
#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3
interrupt Flag */
#define TIM_SR_CC4IF_Pos (4U)
#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4
interrupt Flag */
#define TIM_SR_COMIF_Pos (5U)
#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt
Flag */
#define TIM_SR_TIF_Pos (6U)
#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt
Flag */
#define TIM_SR_BIF_Pos (7U)
#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt
Flag */
#define TIM_SR_CC1OF_Pos (9U)
#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1
Overcapture Flag */
#define TIM_SR_CC2OF_Pos (10U)
#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2
Overcapture Flag */
#define TIM_SR_CC3OF_Pos (11U)
#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3
Overcapture Flag */
#define TIM_SR_CC4OF_Pos (12U)
#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4
Overcapture Flag */
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#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break
Generation */
/*----------------------------------------------------------------------------*/
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#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
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#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear
Enable */
/*----------------------------------------------------------------------------*/
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#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output
Polarity */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3
Complementary output enable */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3
Complementary output Polarity */
#define TIM_CCER_CC4E_Pos (12U)
#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output
enable */
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output
Polarity */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4
Complementary output Polarity */
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#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
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#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2
Internal trigger 1 remap) */
#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter */
/* */
/******************************************************************************/
/******************* Bit definition for USART_SR register *******************/
#define USART_SR_PE_Pos (0U)
#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */
#define USART_SR_PE USART_SR_PE_Msk /*!<Parity
Error */
#define USART_SR_FE_Pos (1U)
#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */
#define USART_SR_FE USART_SR_FE_Msk /*!<Framing
Error */
#define USART_SR_NE_Pos (2U)
#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */
#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error
Flag */
#define USART_SR_ORE_Pos (3U)
#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */
#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun
Error */
#define USART_SR_IDLE_Pos (4U)
#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */
#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line
detected */
#define USART_SR_RXNE_Pos (5U)
#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */
#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not
Empty */
#define USART_SR_TC_Pos (6U)
#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */
#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission
Complete */
#define USART_SR_TXE_Pos (7U)
#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */
#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register
Empty */
#define USART_SR_LBD_Pos (8U)
#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */
#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection
Flag */
#define USART_SR_CTS_Pos (9U)
#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */
#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS
Flag */
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#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver
Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter
Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt
Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt
Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete
Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt
Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt
Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity
Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control
Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup
method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!<Word
length */
#define USART_CR1_UE_Pos (13U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART
Enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8
enable */
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#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock
Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock
Enable */
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#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x0008 */
#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x0010 */
#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x0020 */
#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x0040 */
#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x0080 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T_Pos (0U)
#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit
counter (MSB to LSB)) */
#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x01 */
#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x02 */
#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x04 */
#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x08 */
#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x10 */
#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x20 */
#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x40 */
/* Legacy defines */
#define WWDG_CR_T0 WWDG_CR_T_0
#define WWDG_CR_T1 WWDG_CR_T_1
#define WWDG_CR_T2 WWDG_CR_T_2
#define WWDG_CR_T3 WWDG_CR_T_3
#define WWDG_CR_T4 WWDG_CR_T_4
#define WWDG_CR_T5 WWDG_CR_T_5
#define WWDG_CR_T6 WWDG_CR_T_6
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#define WWDG_SR_EWIF_Pos (0U)
#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt
Flag */
/******************************************************************************/
/* */
/* DBG */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
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#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
/*!< 0x00800000 */
#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
/* Old IWDGSTOP bit definition, maintained for legacy purpose */
#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
/******************************************************************************/
/* */
/* USB_OTG */
/* */
/******************************************************************************/
/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time
*/
#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
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#define USB_OTG_DCFG_DSPD_Pos (0U)
#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status
OUT handshake */
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#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce
done */
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selection */
#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator
complement */
#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass
through */
#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect
disable */
#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host
mode */
#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral
mode */
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx
packet */
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(nonisochronous endpoints) */
#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when
TxFIFO empty mask */
#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with
EP mismatch mask */
#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK
effective mask */
#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun
mask */
#define USB_OTG_DIEPMSK_BIM_Pos (9U)
#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt
mask */
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#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when
endpoint disabled mask */
#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received
mask */
#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP
packets received mask */
#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error
mask */
#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt
mask */
#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt
mask */
#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt
mask */
#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt
mask */
/******************** Bit definition for USB_OTG_GINTSTS register ********************/
#define USB_OTG_GINTSTS_CMOD_Pos (0U)
#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of
operation */
#define USB_OTG_GINTSTS_MMIS_Pos (1U)
#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch
interrupt */
#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG
interrupt */
#define USB_OTG_GINTSTS_SOF_Pos (3U)
#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of
frame */
#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO
nonempty */
#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO
empty */
#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic
NAK effective */
#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK
effective */
#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early
suspend */
#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB
suspend */
#define USB_OTG_GINTSTS_USBRST_Pos (12U)
#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB
reset */
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#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration
done */
#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet
dropped interrupt */
#define USB_OTG_GINTSTS_EOPF_Pos (15U)
#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame
interrupt */
#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint
interrupt */
#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint
interrupt */
#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous
IN transfer */
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!<
0x00200000 */
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete
periodic transfer */
#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch
suspended */
#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port
interrupt */
#define USB_OTG_GINTSTS_HCINT_Pos (25U)
#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels
interrupt */
#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO
empty */
#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status
change */
#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected
interrupt */
#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new
session detected interrupt */
#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup
detected interrupt */
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#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty
mask */
#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty
mask */
#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN
NAK effective mask */
#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective
mask */
#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend
mask */
#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend
mask */
#define USB_OTG_GINTMSK_USBRST_Pos (12U)
#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset
mask */
#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done
mask */
#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet
dropped interrupt mask */
#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame
interrupt mask */
#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch
interrupt mask */
#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt
mask */
#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt
mask */
#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous
IN transfer mask */
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!<
0x00200000 */
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete
periodic transfer mask */
#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended
mask */
#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt
mask */
#define USB_OTG_GINTMSK_HCIM_Pos (25U)
#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt
mask */
#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty
mask */
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#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status
change mask */
#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected
interrupt mask */
#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new
session detected interrupt mask */
#define USB_OTG_GINTMSK_WUIM_Pos (31U)
#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup
detected interrupt mask */
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#define USB_OTG_NPTXFD_Pos (16U)
#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO
depth */
#define USB_OTG_TX0FSA_Pos (0U)
#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM
start address */
#define USB_OTG_TX0FD_Pos (16U)
#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO
depth */
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#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable
*/
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0xFFFFFFFF */
#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
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suspend */
#define USB_OTG_HPRT_PRST_Pos (8U)
#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port
reset */
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mask */
#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt
mask */
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enable */
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#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
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mismatch */
#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK
effective */
#define USB_OTG_DIEPINT_TXFE_Pos (7U)
#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
#define USB_OTG_DIEPINT_BNA_Pos (9U)
#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available
interrupt */
#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
#define USB_OTG_DIEPINT_BERR_Pos (12U)
#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
#define USB_OTG_DIEPINT_NAK_Pos (13U)
#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
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#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
#define USB_OTG_HCTSIZ_DPID_Pos (29U)
#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
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#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
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#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
/* Legacy define */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
/**
@}*
*/
/**
@addtogroup Exported_macros
@{*
*/
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((INSTANCE) == DMA2_Stream3) || \
((INSTANCE) == DMA2_Stream4) || \
((INSTANCE) == DMA2_Stream5) || \
((INSTANCE) == DMA2_Stream6) || \
((INSTANCE) == DMA2_Stream7))
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((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
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((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
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/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM9))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM9))
/* Legacy defines */
#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
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((INSTANCE) == USART6))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
/*
* @brief Specific devices reset values definitions
*/
#define RCC_PLLCFGR_RST_VALUE 0x24003010U
#define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power
scale 2 */
#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power
scale 2 */
#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power
scale 3 */
#define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power
scale 3 */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
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#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F401xC_H */
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