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1 1
Compal Confidential
2 2
3
2010-06-11 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 1 of 45
A B C D E
A B C D E
Danube
Compal Confidential AMD S1G4 Processor
PCB Memory BUS(DDR3)
Model Name : PEW96 ZZZ uPGA-638 Package 204pin DDRIII-SO-DIMM X2
LA-6552P MB Rev0: DA60000IM00 Dual Channel BANK 0, 1, 2, 3 page 10,11
File Name : LA-6552P Champlain page 6,7,8,9 1.5V DDRIII 1066~1333MHz
1
P/N : DA60000IM00 LA-6552P RE0 M/B 1
Hyper Transport Link
16 x 16
LVDS
page 15 Thermal Sensor
ATI RS880M
ADM1032
page 8
CRT uFCBGA-528
page 17
page 12,13,14 page 27 page 15 page 27 page 26 page 26
Power Circuit
page 34,35,36,37,38
Security Classification Compal Secret Data Compal Electronics, Inc.
39,40,41,42 Issued Date 2010/04/12 Deciphered Date 2010/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 2 of 45
A B C D E
5 4 3 2 1
D D
32.768K Hz 25MHz
C
A_SODIMM
1066MHz
AMD AMD AMD C
ATI
MEM_MB_CLK1_P/N CPU_CLKP/N
SB ATI
S1G4
MEM_MB_CLK7_P/N
CPU SOCKET 200MHz
SB820M CLK_NBHT
NB
B_SODIMM
1066MHz Internal CLK GEN.
100MHz
RS880M
CLK_48M_SD
48MHz
CLK_PCIE_WWAN
100MHz
CLK_PCIE_MINI1
100MHz
CLK_PCIE_LAN
B B
100MHz
GbE LAN
CardReader WWAN WLAN
BCM
RTS5137 Mini PCI Socket Mini PCI Socket
57780
A A
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU (1.375-1.5V) ON OFF OFF
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V) ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+CPU_VDDR 1.05V switched power rail ON OFF OFF
+0.75V 0.75V switched power rail for DDR terminator ON ON OFF Board ID / SKU ID Table for AD channel
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF Vcc 3.3V +/- 5%
+1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.5VS 1.5V power rail for MINI Card ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS 1.8V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VALW 3.3V always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS 3.3V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V_LAN 3.3V power rail for LAN ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB VSB always on power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+RTCVCC RTC power ON ON ON
2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 4 of 45
A B C D E
5 4 3 2 1
D D
VDDA18 0.64A
1.8V_S0 VDDG18 0.005A
VDDLT18 0.22A
PLLs 0.1A
VDDG33 0.06A
PU6 +1.1VALW +1.1VALW 3.3V_S0 AVDD 0.125A
RT8209BGQW U36 VDDLT33 0A
SI4800BDY
No Use VDD18_MEM 1.8V 0.005A
+1.1VS VDD_MEM 1.8V 0.23A
C +1.5V +1.5VS C
PU19 U35
TSP51117RGYR SI4800BDY
+1VSG PCIE_VDDC 2 A
PU10 1.0V DP[F:A]_VDD10 230 mA VRAM 1GB
+1.8VS DPLL_VDDC 125 mA
APL5913 SPV10 100 mA 64Mx16 (K4B1G1646E) * 8
PU14 PU11
+1.5VS
APL5913 MP2121DQ 1.5V VDDR1 TBD A 1.5V 2.4 A
PCIE_PVDD 40 mA
+1.8VSP2 +1.8VSP1 PCIE_VDDR 400 mA
TSVDD 5 mA
+3VALW VDDR4 TBD mA
VDD_CT 17 mA
DP[F:A]_PVDD 20 mA
+INVPWR_B+ PU4 1.8V DP[F:A]_VDD18 330 mA
SN0806081 RHBR AVDD 70 mA
VDD1DI 45 mA
+5VALW U37 +3VS A2VDDQ 1.5 mA
SI1800BDY VDD2DI 50 mA
DPLL_PVDD 75 mA
MPV18 150 mA
SPV18 50 mA
B LCD panel B
Delay +3VS_DELAY 3.3V VDDR3 60 mA
15.6" A2VDD 130 mA
U34
SI4800BDY +5VS
B+ 300mA
+3.3 350mA SouthBridge AMD SB820M
+5VS 500mA
VDDIO_33_PCIGP 0.020A
3.3V_S0 VDDPL_33_PCIE 0.030A
VDDPL_33_SATA 0.020A
VDDPL_33_SYS
VDDIO_33_S
+3VALW VDDPL_33_USB_S
U25/U40 VDDAN_33_USB_S 0.2A
TPS2061DRG4 +USB_VCCA 3.3V_S5 VDDAN_33_S
VDDXL_33_S
+USB_VCCB
VDDIO_AZ_S
VDDCR_11_GBE_S
A Audio AMP Audio Codec Realtek EC LAN VDDRF_GBE_S A
USB X3 SATA ICS9LPRS488B Mini Card No Use VDDIO_33_GBE_S
TPA6017A2 ALC272X RTS5137 ENE KB926 BCM57780 RTC VDDIO_GBE_S
VDDIO_18_FC
+5V Bettary
+5V 25mA +5V 3A +5V 45mA +3.3VALW 30mA +3.3VALW 750mA +3.3V 400mA +1.5VS 500mA
Dual+1 +3.3VS 300mA +3.3VS 3mA +3.3VS 1A 2.5~3.6V VDDBT_RTC_G
2.5A +3.3V +3.3VS 25mA +1.1V +3.3VALW 330mA BAT
1 1
+1.1VS
VLDT CAP.
250 mil
2 2 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
<12> H_CADIP[0..15] H_CADOP[0..15] <12>
10U_0805_10V4Z 10U_0805_10V4Z
H_CADIN[0..15] H_CADON[0..15] 1 1 2 2 2 2
<12> H_CADIN[0..15] H_CADON[0..15] <12>
FOX_PZ63823-284S-41F_Champlian
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G4 HT I/F
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 6 of 45
A B C D E
A B C D E
C8
FOX_PZ63823-284S-41F_Champlian FOX_PZ63823-284S-41F_Champlian
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G4 DDRIII I/F
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 7 of 45
A B C D E
A B C D E
Champlain: C1E
C1E: LDT_REQ# no connect
+2.5VDDA
CLMC: LDT_REQ# connect to NB +1.5V
L1 VDDA=0.25A
+2.5VS 1 2 3300P_0402_50V7K
1
+ no support in S1g4
C11 4.7U_0805_10V4Z C12 C13 C14 R6
2
0.22U_0603_16V4Z 10K_0402_5%
220U_6.3V_M 2 2 2 R7 <BOM Structure>
2 2
1K_0402_5%
JCPU1D
B
1 1
1
Q1
E
F8 M11 CPU_THERMTRIP#_R 3 1 1 2
VDDA1 VSS H_THERMTRIP# <19>
C
F9 W18 R8 0_0402_5%
VDDA2 RSVD11 MMBT3904_NL_SOT23-3
1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC 1 2
<18> CLK_CPU_BCLK CPU_CLKIN_SC_N CLKIN_H SVC CPU_SVD CPU_SVC <42> MAINPWON <35,36>
C16 A8 A4 R9 @ 0_0402_5%
CLKIN_L SVD CPU_SVD <42>
1
LDT_RST# B7 1 2
RESET_L +1.5V
R10 H_PWRGD A7 R11 300_0402_5%
169_0402_1% LDT_STOP# PWROK CPU_THERMTRIP#_R
F10 AF6
LDTSTOP_L THERMTRIP_L H_PROCHOT#
C6 AC7
2
T2 PAD LDTREQ_L PROCHOT_L
<18> CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 PAD T3
C15 3900P_0402_50V7K +1.5V 1 2 CPU_SIC AF4 H_PROCHOT# 1 2
CPU_SID SIC H_PROCHOT_R# <18>
+1.5V R12 1 2 1K_0402_5% AF5 R13 0_0402_5%
R14 1K_0402_5% SID THERMDC_CPU
AE6 ALERT_L THERMDC W7
+1.5VS THERMDA_CPU
THERMDA W8 PROCHOT:
R15 1 2 44.2_0402_1% CPU_HTREF0 R6 HT_REF0
+1.1VS R16 1 2 44.2_0402_1% CPU_HTREF1 P6 Input: For HTC Function
HT_REF1
2
R17 CPU_VDD0_FB_H
Output: Over Temperature Condition
<42> CPU_VDD0_FB_H F6 VDD0_FB_H VDDIO_FB_H W9 PAD T4
300_0402_5% CPU_VDD0_FB_L E6 Y9
<42> CPU_VDD0_FB_L VDD0_FB_L VDDIO_FB_L PAD T11
1 FOX_PZ63823-284S-41F_Champlian
@
C20 CPU_TEST27 1 2
@ R28 1K_0402_5%
2 U1
1 8 EC_SMB_CK2
VDD SCLK EC_SMB_CK2 <28>
3 THERMDA_CPU EC_SMB_DA2 3
2
D+ SDATA
7 EC_SMB_DA2 <28> For SCAN connect use
THERMDC_CPU 3 6 CPU_TEST12 1 2
D- ALERT# R29 1K_0402_5%
1 2
C21 100P_0402_50V8J 4 5 CPU_TEST18 1 2
@ THERM# GND R30 1K_0402_5%
CPU_TEST19 1 2
ADM1032ARMZ_MSOP8 R31 1K_0402_5%
+1.5V CPU_TEST20 1 2
Address 1001 100X b R32 1K_0402_5%
CPU_TEST21 1 2
R33 1K_0402_5%
220_0402_5% R36
220_0402_5% R37
220_0402_5% R38
300_0402_5% R39
300_0402_5% R40
CPU_TEST22 1 2
R34 1K_0402_5%
1
2
CPU internal thermal sensor CPU_TEST24 1 2
R35 1K_0402_5%
CPU_TEST23 1 2
1 2 FDV301N, the Vgs is: R265 1K_0402_5%
JP2
min = 0.65V
2
1
C22 0.1U_0402_16V4Z
Typ = 0.85V @ @ @ @ 1 2
R41 3 4
R42 Max = 1.5V
CPU_DBREQ# 5 6 R43
+3VS 2 1 2 1 1 2
CPU_DBRDY 7 8 @ 0_0402_5%
20K_0402_5% 34.8K_0402_1% CPU_TCK 9 10
CPU_TMS 11 12 +3VS
CPU_TDI 13 14
CPU_TRST# 15 16
2.09V for Gate 17 18
2
5
G
CPU_TDO U2
19 20 LDT_RST#
2
P
CPU_SID 3 EC_SMB_DA2 21 22 HDT_RST# B
1 23 24
4
Y
S
26 A 1 SB_PWRGD <13,19,28>
G
4 4
Q2 FDV301N_NL_SOT23-3 @ NC7SZ08P5X_NL_SC70-5
3
CONN@ SAMTEC_ASP-68200-07
2
G
CPU_SIC 3 EC_SMB_CK2
1 Security Classification Compal Secret Data Compal Electronics, Inc.
S
JCPU1F
+1.5V
+CPU_CORE_NB decoupling. F11
F13
VSS52
VSS53
VSS54
VSS117
VSS118
VSS119
U18
V2
F15 V7
VSS55 VSS120
F17 V9
+CPU_CORE_NB VSS56 VSS121
F19 V11
VSS57 VSS122
F21 V13
VSS58 VSS123
1 1 1 1 1 1 F23 V15
C44 C45 C46 C47 C48 C50 VSS59 VSS124
1 1 1 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M C42 C43 C49 VSS60 VSS125
H7 W6
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VSS61 VSS126
H9 Y21
2 2 2 2 2 2 VSS62 VSS127
H21 Y23
2 2 2 VSS63 VSS128
H23 N6
VSS64 VSS129
J4
VSS65
FOX_PZ63823-284S-41F_Champlian
Under CPU Socket Athlon 64 S1
Processor Socket
+1.5V
C97
C98
C99
C100 0.1U_0402_16V7K
C101 0.1U_0402_16V7K
C96
Between CPU Socket and DIMM
+1.5V +CPU_VDDR 2 2 2 2 2 2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
3 3
Near Power Supply @ @ @ @ @ @
1 1 1 1 1 1
VDDR decoupling. 1
1
C51 C52 C53 C54 C354 C355 C55 1 1 1 1 1 1
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z C56 + 220U_6.3V_M 22U_0805_6.3V6M
2 2 2 2 2 2 2
2
180PF Qt'y follow the distance between
+1.5V +1.5V CPU socket and DIMM0. <2.5inch> +CPU_VDDR Reserve for EMI
1 1 2 2 1 1
C64 C65 C66 C67 C68 C69 1 1 1 1 1 1 1 1
0.01U_0402_25V4Z 0.01U_0402_25V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 180P_0402_50V8J 180P_0402_50V8J C57 C58 C59 C60 C61 C62 C63 C70
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
2 2 1 1 2 2
2 2 2 2 2 2 2 2
+1.5V
Near CPU Socket Right side.
Change as SGA19331D10 (ESR9 ohm) for PVT +CPU_VDDR
1
1 1 1 1
+
C71 C72 C73 C74 C75 1 1 1 1 1 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 330U_D2_2V_Y C76 C77 C78 C79 C80 C81 C82 C83
2 2 2 2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2 2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G4 PWR & GND
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 9 of 45
A B C D E
A B C D E
JDIMM1
1 VREF_DQ VSS1 2
3 4 DDRA_SDQ4
DDRA_SDQ0 VSS2 DQ4 DDRA_SDQ5
5 DQ0 DQ5 6
DDRA_SDQ1 7 8
DQ1 VSS3 DDRA_SDQS0#
9 VSS4 DQS#0 10 DDRA_SDQS0# <7>
DDRA_SDM0 11 12 DDRA_SDQS0
DM0 DQS0 DDRA_SDQS0 <7> DDRA_SDQ[0..63]
13 VSS5 VSS6 14
DDRA_SDQ2 DDRA_SDQ6 DDRA_SDQ[0..63] <7>
15 16
DDRA_SDQ3 DQ2 DQ6 DDRA_SDQ7 DDRA_SDM[0..7]
17 18 DDRA_SDM[0..7] <7>
DQ3 DQ7
19 20
1 DDRA_SDQ8 VSS7 VSS8 DDRA_SDQ12 1
21 22
DDRA_SDQ9 DQ8 DQ12 DDRA_SDQ13
23 24
DQ9 DQ13 DDRA_SMA[0..15]
25 26 DDRA_SMA[0..15] <7>
DDRA_SDQS1# VSS9 VSS10 DDRA_SDM1
<7> DDRA_SDQS1# 27 28
DDRA_SDQS1 DQS#1 DM1 MEM_MA_RST#
<7> DDRA_SDQS1 29 30 MEM_MA_RST# <7>
DQS1 RESET#
31 32
DDRA_SDQ10 VSS11 VSS12 DDRA_SDQ14
33 34
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
35 36
DQ11 DQ15
37 38
DDRA_SDQ16 VSS13 VSS14 DDRA_SDQ20
39 40
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21
41 42
DQ17 DQ21
43 VSS15 VSS16 44
DDRA_SDQS2# 45 46 DDRA_SDM2
<7> DDRA_SDQS2# DDRA_SDQS2 DQS#2 DM2
<7> DDRA_SDQS2 47 DQS2 VSS17 48
49 50 DDRA_SDQ22
DDRA_SDQ18 VSS18 DQ22 DDRA_SDQ23
51 DQ18 DQ23 52
DDRA_SDQ19 53 54
DQ19 VSS19 DDRA_SDQ28
55 VSS20 DQ28 56
DDRA_SDQ24 57 58 DDRA_SDQ29 +VREF_CA +1.5V
DDRA_SDQ25 DQ24 DQ29 +VREF_DQ +1.5V
59 DQ25 VSS21 60
61 62 DDRA_SDQS3#
VSS22 DQS#3 DDRA_SDQS3# <7>
2
DDRA_SDM3 63 64 DDRA_SDQS3
DM3 DQS3 DDRA_SDQS3 <7>
2
65 66 R310
DDRA_SDQ26 VSS23 VSS24 DDRA_SDQ30 R48 1K_0402_1%
67 DQ26 DQ30 68
DDRA_SDQ27 69 70 DDRA_SDQ31 1K_0402_1%
DQ27 DQ31
71 72
1
VSS25 VSS26 +VREF_CA
1
+VREF_DQ
1000P_0402_50V7K
0.01U_0402_25V7K
4.7U_0805_10V4Z
DDRA_CKE0 73 74 DDRA_CKE1
<7> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <7>
1000P_0402_50V7K
0.01U_0402_25V7K
4.7U_0805_10V4Z
75 VDD1 VDD2 76 1 2 1
2
77 78 DDRA_SMA15 1 2 1 C235 C351 C680
NC1 A15
2
2 DDRA_SBS2# DDRA_SMA14 C84 C85 C10 @ R315 2
<7> DDRA_SBS2# 79 BA2 A14 80
81 82 @ R49 1K_0402_1%
DDRA_SMA12 VDD3 VDD4 DDRA_SMA11 1K_0402_1% 2 1 2
83 A12/BC# A11 84
DDRA_SMA9 DDRA_SMA7 2 1 2
85 86
1
A9 A7
87 88
1
DDRA_SMA8 VDD5 VDD6 DDRA_SMA6
89 A8 A6 90
DDRA_SMA5 91 92 DDRA_SMA4
A5 A4
93 94
DDRA_SMA3 VDD7 VDD8 DDRA_SMA2
95 96
DDRA_SMA1 A3 A2 DDRA_SMA0
97 98
A1 A0
99 100
DDRA_CLK0 VDD9 VDD10 DDRA_CLK1
101 102 DDRA_CLK1 <7>
<7> DDRA_CLK0 DDRA_CLK0# CK0 CK1 DDRA_CLK1#
103 104 DDRA_CLK1# <7>
<7> DDRA_CLK0# CK0# CK1#
105 106
DDRA_SMA10 VDD11 VDD12 DDRA_SBS1#
107 108 DDRA_SBS1# <7>
DDRA_SBS0# A10/AP BA1 DDRA_SRAS#
<7> DDRA_SBS0# 109 110 DDRA_SRAS# <7>
BA0 RAS#
111 112
DDRA_SWE# VDD13 VDD14 DDRA_SCS0#
113 114 DDRA_SCS0# <7>
<7> DDRA_SWE# DDRA_SCAS# WE# S0# DDRA_ODT0
<7> DDRA_SCAS# 115 116 DDRA_ODT0 <7>
CAS# ODT0
117 118
DDRA_SMA13 VDD15 VDD16 DDRA_ODT1
119 120 DDRA_ODT1 <7>
DDRA_SCS1# A13 ODT1
121 122
<7> DDRA_SCS1# S1# NC2
123 124
VDD17 VDD18 +1.5V
125 126 +VREF_CA
NCTEST VREF_CA
127 128
VSS27 VSS28
1000P_0402_50V7K
DDRA_SDQ32 129 130 DDRA_SDQ36 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37
131 132 1 2 2 2 2 2 2 2 2 2 2
DQ33 DQ37
C89
133 134
DDRA_SDQS4# VSS29 VSS30 DDRA_SDM4 C87 C643 C88 C644 C640 C645 C641 C646 C642 C647
<7> DDRA_SDQS4# 135 136
DDRA_SDQS4 DQS#4 DM4
<7> DDRA_SDQS4 137 138
DQS4 VSS31 DDRA_SDQ38 2 1 1 1 1 1 1 1 1 1 1
139 140
DDRA_SDQ34 VSS32 DQ38 DDRA_SDQ39 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
141 142
3 DDRA_SDQ35 DQ34 DQ39 3
143 144
DQ35 VSS33 DDRA_SDQ44
145 146
DDRA_SDQ40 VSS34 DQ44 DDRA_SDQ45
147 148
DDRA_SDQ41 DQ40 DQ45
149 150
DQ41 VSS35 DDRA_SDQS5#
151 152 DDRA_SDQS5# <7>
DDRA_SDM5 VSS36 DQS#5 DDRA_SDQS5 +0.75VS
153 154 DDRA_SDQS5 <7>
DM5 DQS5
155 156
DDRA_SDQ42 VSS37 VSS38 DDRA_SDQ46 0.1U_0402_16V4Z
157 158
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
159 160 2 2 1
DQ43 DQ47
161 162
DDRA_SDQ48 VSS39 VSS40 DDRA_SDQ52 C665 C664 C961
163 164
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53
165 166
DQ49 DQ53 1 1 2
167 168
DDRA_SDQS6# VSS41 VSS42 DDRA_SDM6 0.1U_0402_16V4Z 4.7U_0805_10V4Z
<7> DDRA_SDQS6# 169
DQS#6 DM6
170 Place near DIMM1
DDRA_SDQS6 171 172
<7> DDRA_SDQS6 DQS6 VSS43
173 174 DDRA_SDQ54
DDRA_SDQ50 VSS44 DQ54 DDRA_SDQ55
175 176
DDRA_SDQ51 DQ50 DQ55
177 178
DQ51 VSS45 DDRA_SDQ60
179 180
DDRA_SDQ56 VSS46 DQ60 DDRA_SDQ61
181 182
DDRA_SDQ57 DQ56 DQ61
183 184
DQ57 VSS47 DDRA_SDQS7#
185 186 DDRA_SDQS7# <7>
DDRA_SDM7 VSS48 DQS#7 DDRA_SDQS7
187 188 DDRA_SDQS7 <7>
DM7 DQS7 +1.5V
189 190
DDRA_SDQ58 VSS49 VSS50 DDRA_SDQ62
191 192
DDRA_SDQ59 DQ58 DQ62 DDRA_SDQ63
193 194
R50 10K_0402_5% DQ59 DQ63 +1.5V +0.75VS
195 196 C690 2 2 2
VSS51 VSS52
1 2 197 198 PAD T9
SA0 EVENT# C691 C692 C693
+3VS 199 200 SB_SMDAT0 <11,19,26> 2 1
VDDSPD SDA
201 202 SB_SMCLK0 <11,19,26>
SA1 SCL @ 1 1 1
203 204 +0.75VS
VTT1 VTT2 0.1U_0402_16V4Z
1
0.01U_0402_16V7K
4 R51 0.01U_0402_16V7K 4
205 G1 G2 206
+3VS
10K_0402_5% FOX_AS0A626-U8SN-7F 0.01U_0402_16V7K
CONN@
2
1 1
C90 C91
Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z Issued Date 2010/04/12 2010/10/12 Title
2
2.2U_0805_10V6K 2 Deciphered Date
DIMM_A STD H:8mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII SO-DIMM 1
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
<Address: 00> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 10 of 45
A B C D E
A B C D E
JDIMM2
1 VREF_DQ VSS1 2
3 4 DDRB_SDQ4
DDRB_SDQ0 VSS2 DQ4 DDRB_SDQ5
5 DQ0 DQ5 6
DDRB_SDQ1 7 8
DQ1 VSS3 DDRB_SDQS0#
9 VSS4 DQS#0 10 DDRB_SDQS0# <7>
DDRB_SDM0 11 12 DDRB_SDQS0
DM0 DQS0 DDRB_SDQS0 <7> DDRB_SDQ[0..63]
13 VSS5 VSS6 14
DDRB_SDQ2 DDRB_SDQ6 DDRB_SDQ[0..63] <7>
15 16
DDRB_SDQ3 DQ2 DQ6 DDRB_SDQ7 DDRB_SDM[0..7]
17 18 DDRB_SDM[0..7] <7>
DQ3 DQ7
19 20
1 DDRB_SDQ8 VSS7 VSS8 DDRB_SDQ12 1
21 22
DDRB_SDQ9 DQ8 DQ12 DDRB_SDQ13
23 24
DQ9 DQ13 DDRB_SMA[0..15]
25 26 DDRB_SMA[0..15] <7>
DDRB_SDQS1# VSS9 VSS10 DDRB_SDM1
<7> DDRB_SDQS1# 27 28
DDRB_SDQS1 DQS#1 DM1 MEM_MB_RST#
<7> DDRB_SDQS1 29 30 MEM_MB_RST# <7>
DQS1 RESET#
31 32
DDRB_SDQ10 VSS11 VSS12 DDRB_SDQ14
33 34
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
35 36
DQ11 DQ15
37 38
DDRB_SDQ16 VSS13 VSS14 DDRB_SDQ20
39 40
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
41 42
DQ17 DQ21
43 VSS15 VSS16 44
DDRB_SDQS2# 45 46 DDRB_SDM2
<7> DDRB_SDQS2# DDRB_SDQS2 DQS#2 DM2
<7> DDRB_SDQS2 47 DQS2 VSS17 48
49 50 DDRB_SDQ22
DDRB_SDQ18 VSS18 DQ22 DDRB_SDQ23
51 DQ18 DQ23 52
DDRB_SDQ19 53 54
DQ19 VSS19 DDRB_SDQ28
55 VSS20 DQ28 56
DDRB_SDQ24 57 58 DDRB_SDQ29
DDRB_SDQ25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDRB_SDQS3#
DDRB_SDM3 VSS22 DQS#3 DDRB_SDQS3 DDRB_SDQS3# <7>
63 DM3 DQS3 64 DDRB_SDQS3 <7>
65 VSS23 VSS24 66
DDRB_SDQ26 67 68 DDRB_SDQ30
DDRB_SDQ27 DQ26 DQ30 DDRB_SDQ31
69 DQ27 DQ31 70
71 VSS25 VSS26 72
DDRB_CKE0 73 74 DDRB_CKE1
<7> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <7>
75 VDD1 VDD2 76
77 78 DDRB_SMA15
2 DDRB_SBS2# NC1 A15 DDRB_SMA14 2
<7> DDRB_SBS2# 79 BA2 A14 80
81 VDD3 VDD4 82
DDRB_SMA12 83 84 DDRB_SMA11
DDRB_SMA9 A12/BC# A11 DDRB_SMA7
85 A9 A7 86
87 VDD5 VDD6 88
DDRB_SMA8 89 90 DDRB_SMA6 +VREF_DQ +VREF_CA
DDRB_SMA5 A8 A6 DDRB_SMA4
91 A5 A4 92
93 94
DDRB_SMA3 VDD7 VDD8 DDRB_SMA2 +VREF_DQ +VREF_CA
95 96
DDRB_SMA1 A3 A2 DDRB_SMA0
97 98
A1 A0
1000P_0402_50V7K
1000P_0402_50V7K
99 100
VDD9 VDD10
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
DDRB_CLK0 101 102 DDRB_CLK1
<7> DDRB_CLK0 CK0 CK1 DDRB_CLK1 <7>
DDRB_CLK0# 103 104 DDRB_CLK1# 1 1 1 1 1 1
<7> DDRB_CLK0# CK0# CK1# DDRB_CLK1# <7>
105 106 C92 C93 C682 C352 C353 C683
DDRB_SMA10 VDD11 VDD12 DDRB_SBS1#
107 108 DDRB_SBS1# <7>
DDRB_SBS0# A10/AP BA1 DDRB_SRAS#
<7> DDRB_SBS0# 109 110 DDRB_SRAS# <7>
BA0 RAS# 2 2 2 2 2 2
111 112
DDRB_SWE# VDD13 VDD14 DDRB_SCS0#
113 114 DDRB_SCS0# <7>
<7> DDRB_SWE# DDRB_SCAS# WE# S0# DDRB_ODT0
<7> DDRB_SCAS# 115 116 DDRB_ODT0 <7>
CAS# ODT0
117 118
DDRB_SMA13 VDD15 VDD16 DDRB_ODT1
119 120 DDRB_ODT1 <7>
DDRB_SCS1# A13 ODT1
121 122
<7> DDRB_SCS1# S1# NC2
123 124
VDD17 VDD18
125 126 +VREF_CA
NCTEST VREF_CA
127 128
VSS27 VSS28
1000P_0402_50V7K
DDRB_SDQ32 129 130 DDRB_SDQ36
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37
131 132 1
DQ33 DQ37 C94
133 134
DDRB_SDQS4# VSS29 VSS30 DDRB_SDM4
<7> DDRB_SDQS4# 135 136
DDRB_SDQS4 DQS#4 DM4
<7> DDRB_SDQS4 137 138
DQS4 VSS31 DDRB_SDQ38 2
139 140
DDRB_SDQ34 VSS32 DQ38 DDRB_SDQ39
141 142
3 DDRB_SDQ35 DQ34 DQ39 3
143 144
DQ35 VSS33 DDRB_SDQ44
145 146
DDRB_SDQ40 VSS34 DQ44 DDRB_SDQ45
147 148
DDRB_SDQ41 DQ40 DQ45
149 150
DQ41 VSS35 DDRB_SDQS5#
151 152 DDRB_SDQS5# <7>
DDRB_SDM5 VSS36 DQS#5 DDRB_SDQS5 +1.5V
153 154 DDRB_SDQS5 <7>
DM5 DQS5
155 156
DDRB_SDQ42 VSS37 VSS38 DDRB_SDQ46 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
157 158
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
159 160 2 2 2 2 2 2 2 2 2 2
DQ43 DQ47
161 162
DDRB_SDQ48 VSS39 VSS40 DDRB_SDQ52 C677 C670 C666 C671 C667 C672 C668 C673 C669 C674
163 164
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
165 166
DQ49 DQ53 1 1 1 1 1 1 1 1 1 1
167 168
DDRB_SDQS6# VSS41 VSS42 DDRB_SDM6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<7> DDRB_SDQS6# 169 170
DDRB_SDQS6 DQS#6 DM6
<7> DDRB_SDQS6 171 172
DQS6 VSS43 DDRB_SDQ54
173 174
DDRB_SDQ50 VSS44 DQ54 DDRB_SDQ55
175 176
DDRB_SDQ51 DQ50 DQ55
177 178
DQ51 VSS45 DDRB_SDQ60 +1.5V
179 180
DDRB_SDQ56 VSS46 DQ60 DDRB_SDQ61 +0.75VS
181 182
DDRB_SDQ57 DQ56 DQ61
183 184
DQ57 VSS47 DDRB_SDQS7# 0.1U_0402_16V4Z
185 186 DDRB_SDQS7# <7>
DDRB_SDM7 VSS48 DQS#7 DDRB_SDQS7
187 188 DDRB_SDQS7 <7> 2 2 1 1
DM7 DQS7
189 190
DDRB_SDQ58 VSS49 VSS50 DDRB_SDQ62 C676 C675 C925 + C86
191 192
DDRB_SDQ59 DQ58 DQ62 DDRB_SDQ63 @ 330U_X_2VM_R6M
193 194
R52 10K_0402_5% DQ59 DQ63 1 1 2
195 196
VSS51 VSS52 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 2
1 2 197 198 PAD T10
SA0 EVENT#
+3VS 199 200 SB_SMDAT0 <10,19,26>
VDDSPD SDA
201
SA1 SCL
202 SB_SMCLK0 <10,19,26> Place near DIMM2
203 204 +0.75VS
VTT1 VTT2
1
4 R53 4
205 G1 G2 206
10K_0402_5% FOX_AS0A626-U4SN-7F
CONN@
2
DIMM_B STD H:4mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII SO-DIMM 2
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
<Address: 01> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 11 of 45
A B C D E
A B C D E
U3B
D4 GFX_RX0P GFX_TX0P A5 GMCH_HDMI_TXD2+ <16>
C4
GFX_RX0N PART 2 OF 6 GFX_TX0N
B5 GMCH_HDMI_TXD2- <16>
A3 A4 GMCH_HDMI_TXD1+ <16>
GFX_RX1P GFX_TX1P
B3 B4 GMCH_HDMI_TXD1- <16>
1 GFX_RX1N GFX_TX1N 1
C2 C3 GMCH_HDMI_TXD0+ <16>
GFX_RX2P GFX_TX2P
C1 B2 GMCH_HDMI_TXD0- <16>
GFX_RX2N GFX_TX2N
E5 D1 GMCH_HDMI_TXC+ <16>
GFX_RX3P GFX_TX3P
F5 D2 GMCH_HDMI_TXC- <16>
GFX_RX3N GFX_TX3N
G5 E2
GFX_RX4P GFX_TX4P
G6 E1
GFX_RX4N GFX_TX4N
H5 F4
GFX_RX5P GFX_TX5P
H6 F3
GFX_RX5N GFX_TX5N
J6 F1
GFX_RX6P GFX_TX6P
J5 F2
GFX_RX6N GFX_TX6N
J7 H4
GFX_RX7P GFX_TX7P
J8 GFX_RX7N GFX_TX7N H3
L5 GFX_RX8P GFX_TX8P H1
L6 GFX_RX8N GFX_TX8N H2
M8 GFX_RX9P GFX_TX9P J2
L8 GFX_RX9N GFX_TX9N J1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880-HT/PCIE
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 12 of 45
A B C D E
A B C D E
0.1U_0402_16V4Z +1.8VS
2
1 2
R417 R63 U4
5
+1.1VS +NB_PLLVDD @ C684 2.2K_0402_5% NC7SZ08P5X_NL_SC70-5
5
L2 C696 C679 300_0402_5% NB_PWRGD 2
P
B
1 2 2 4 NB_PWRGD_R
P
1
1
+3VS 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K B NB_LDTSTOP# Y
1 1 Y 4 <8,19,28> SB_PWRGD 1 A
G
FBMA-L11-160808-221LMT 0603 L3 1 @
<8,18> LDT_STOP# A
G
C141 C142 1 2 C144 C143 U8
3
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z
+AVDD1
1 1 1 1
3
1 2 2 FBMA-L11-160808-221LMT 0603 NC7SZ08P5X_NL_SC70-5 1
@
2.2U_0603_6.3V4Z
2 2 2 2 1 2
1U_0402_6.3V4Z R64 @ 0_0402_5%
+1.8VS
L4 AMD suggest
+1.8VS +NB_HTPVDD 1 2 +AVDDDI
L5 1
125mA
1 2 FBMA-L11-160808-221LMT 0603
1 1 C145
FBMA-L11-160808-221LMT 0603 0.1U_0402_16V4Z
C146 C147 2 U3C
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z F12 A22 TXOUT0+ <15>
2 2 +1.8VS AVDD1(NC) TXOUT_L0P(NC)
20mA E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 TXOUT0- <15>
F14 AVDDDI(NC) TXOUT_L1P(NC) A21 TXOUT1+ <15>
L6 4mA G15 B21 TXOUT1- <15>
+AVDDQ AVSSDI(NC) TXOUT_L1N(NC)
1 2 H15 AVDDQ(NC) TXOUT_L2P(NC) B20 TXOUT2+ <15>
1 1 H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20 TXOUT2- <15>
FBMA-L11-160808-221LMT 0603 A19
C148 C149 TXOUT_L3P(NC)
E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19
+1.8VS +VDDA18HTPLL 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z F17
CRT/TVOUT
L7 2 2 Y(DFT_GPIO2)
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18
1 2 TXOUT_U0N(NC) A18
1 1 GMCH_CRT_R G18 A17
<17> GMCH_CRT_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
FBMA-L11-160808-221LMT 0603 G17 B17 L8
C150 C151 GMCH_CRT_G REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) +VDDLTP18
<17> GMCH_CRT_G E18 GREEN(DFT_GPIO1) TXOUT_U2P(NC) D20 1 2 +1.8VS
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z F18 D21 1 1
2 2 GMCH_CRT_B GREENb(NC) TXOUT_U2N(NC) FBMA-L11-160808-221LMT 0603
<17> GMCH_CRT_B E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
F19 D19 C152 C153
BLUEb(NC) TXOUT_U3N(NC) 1U_0402_6.3V4Z 2.2U_0603_6.3V4Z
GMCH_CRT_HSYNC A11 B16 2 2
2 <14,17> GMCH_CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) TXCLK+ <15> 2
GMCH_CRT_VSYNC B11 A16
<14,17> GMCH_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) TXCLK- <15>
GMCH_CRT_CLK F8 D16
+1.8VS +VDDA18PCIEPLL <17> GMCH_CRT_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
GMCH_CRT_DATA E8 D17
<17> GMCH_CRT_DATA DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1)
L9
1 2 1 2 DAC_RSET G14 15mA L10
R65 715_0402_1% DAC_RSET(PWM_GPIO1) +VDDLTP18 +VDDLT18
1 1
+NB_PLLVDD
65mA VDDLTP18(NC) A13 1 2 +1.8VS
FBMA-L11-160808-221LMT 0603 +NB_PLLVDD A12 B13 1 1 BLM18AG601SN1D_2P
C154 C155 +NB_HTPVDD 20mA PLLVDD(NC) VSSLTP18(NC) C156
+NB_HTPVDD D14
PLLVDD18(NC) 300mA +VDDLT18
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z B12 A15 0.1U_0402_16V4Z C157
LVTM
2 2 PLLVSS(NC) VDDLT18_1(NC) 4.7U_0805_10V4Z
20mA B15
PLL PWR
VDDLT18_2(NC) 2 2
+VDDA18HTPLL H17 A14
VDDA18HTPLL VDDLT33_1(NC)
120mA VDDLT33_2(NC)
B14
+VDDA18PCIEPLL D7
VDDA18PCIEPLL1
E7 C14
VDDA18PCIEPLL2 VSSLT1(VSS)
D15
VSSLT2(VSS)
<14,18,28> A_RST# D8 C16
NB_PWRGD_R A10 SYSRESETb VSSLT3(VSS)
<19> NB_PWRGD 1 2 C18
R67 0_0402_5% NB_LDTSTOP# POWERGOOD VSSLT4(VSS)
C10 C20
NB_ALLOW_LDTSTOP C12 LDTSTOPb VSSLT5(VSS)
2 1 E20
PM
+1.8VS ALLOW_LDTSTOP VSSLT6(VSS)
R68 300_0402_5% C22
VSSLT7(VSS)
<18> CLK_NBHT C25
HT_REFCLKP
<18> CLK_NBHT# C24
HT_REFCLKN
CLOCKs
<18> NB_DISP_CLKN F11 E9 GMCH_ENVDD <15>
4.7K_0402_5% REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP)
F7
LVDS_BLON(PCE_RCALRP)
R106 1 2 CLK_NBGFX T2 G12 VARY_ENBKL R71 1 UNVB@ 2 0_0402_5% ENBKL <28>
GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2)
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
R83 1 2 CLK_NBGFX# T1
GFX_REFCLKN
1
4.7K_0402_5% R72 1 VB@ 2 0_0402_5% GMCH_INVT_PWM <15>
+3VS
close NB U1
GPP_REFCLKP R76 1 VB@
U2
GPP_REFCLKN 2 0_0402_5%
3 If support VB, pop VB@ and reserve R71 3
<18> CLK_SBLINK_BCLK V4
2
R77 GMCH_LCD_CLK GPPSB_REFCLKP(SB_REFCLKP)
1 2 4.7K_0402_5% <18> CLK_SBLINK_BCLK# V3
GPPSB_REFCLKN(SB_REFCLKN) R73 R74 R75
R78 1 2 4.7K_0402_5% GMCH_LCD_DATA <15> GMCH_LCD_CLK
GMCH_LCD_CLK B9
GMCH_LCD_DATA I2C_CLK
R79 1 2 4.7K_0402_5% GMCH_CRT_CLK <15> GMCH_LCD_DATA GMCH_HDMI_DATA
A9
B8
I2C_DATA MIS. TMDS_HPD(NC)
D9
D10
GMCH_HDMI_DET <16>
<16> GMCH_HDMI_DATA DDC_DATA0/AUX0N(NC) HPD(NC)
@ GMCH_HDMI_CLK A8 @
<16> GMCH_HDMI_CLK DDC_CLK0/AUX0P(NC)
R80 1 2 4.7K_0402_5% GMCH_CRT_DATA B7
DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5)
D12 1 2 SUS_STAT# <19> To SB
@ 1 2 A7 R81 0_0402_5%
DDC_DATA1/AUX1N(NC)
R82 2K_0402_5%
THERMALDIODE_P
AE8 SUS_STAT_R# <14>Strap pin
POWER_SEL B10 AD8
<39> POWER_SEL STRP_DATA THERMALDIODE_N
G11 D13 1 2
RSVD TESTMODE R84
1 2 C8 1.8K_0402_5%
R85 150_0402_1% AUX_CAL(NC)
RS780M_FCBGA528
RS880 POWER_SEL RS880 A11(SA000032710)
HIGH 0.95V
LOW 1.1V
1 2 GMCH_CRT_R
R87 140_0402_1%
1 2 GMCH_CRT_G
R88 150_0402_1%
1 2 GMCH_CRT_B
R89 150_0402_1%
4 4
+1.8VS
1
R90
1K_0402_5%
R91 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 NB_ALLOW_LDTSTOP 2010/04/12 2010/10/12 Title
<18> ALLOW_LDTSTOP Issued Date Deciphered Date
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880 VEDIO/CLK GEN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 13 of 45
A B C D E
A B C D E
600mA
L12 D23 PART 6/6 B1
C165 C166 C159 C167 C200 VSSAHT2 VSSAPCIE2
1 2 +1.1VS E22 D3
FBMA-L11-201209-221LMA30T_0805 VSSAHT3 VSSAPCIE3
G22 D5
2 2 2 2 2 U3E VSSAHT4 VSSAPCIE4
2.5A +VDDA11PCIE
G24
VSSAHT5 VSSAPCIE5
E4
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z J17 A6 C160 1 2 10U_0805_10V4Z G25 G1
1 VDDHT_1 VDDPCIE_1 C162 VSSAHT6 VSSAPCIE6 1
K16
VDDHT_2 PART 5/6 VDDPCIE_2
B6 1 2 10U_0805_10V4Z H19
VSSAHT7 VSSAPCIE7
G2
L16 C6 J22 G4
L13 1U_0402_6.3V4Z VDDHT_3 VDDPCIE_3 VSSAHT8 VSSAPCIE8
M16 D6 L17 H7
0.1U_0402_16V4Z +VDDHTRX VDDHT_4 VDDPCIE_4 C163 VSSAHT9 VSSAPCIE9
2 1 P16 E6 1 2 4.7U_0805_10V4Z L22 J4
VDDHT_5 VDDPCIE_5 VSSAHT10 VSSAPCIE10
R16 F6 L24 R7
FBMA-L11-201209-221LMA30T_0805 VDDHT_6 VDDPCIE_6 C168 VSSAHT11 VSSAPCIE11
1 1 1 1 1 T16
VDDHT_7 VDDPCIE_7
G7 1 2 1U_0402_6.3V4Z L25
VSSAHT12 VSSAPCIE12
L1
700mA H8 C171 1 2 1U_0402_6.3V4Z M20 L2
C164 C169 C170 C161 C201 VDDPCIE_8 VSSAHT13 VSSAPCIE13
H18 J9 N22 L4
VDDHTRX_1 VDDPCIE_9 VSSAHT14 VSSAPCIE14
G19 K9 1 2 P20 L7
2 2 2 2 2 VDDHTRX_2 VDDPCIE_10 C172 VSSAHT15 VSSAPCIE15
F20 M9 1 2 0.1U_0402_16V4Z R19 M6
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDHTRX_3 VDDPCIE_11 C173 0.1U_0402_16V4Z VSSAHT16 VSSAPCIE16
E21 L9 R22 N4
VDDHTRX_4 VDDPCIE_12 VSSAHT17 VSSAPCIE17
D22 VDDHTRX_5 VDDPCIE_13 P9 R24 VSSAHT18 VSSAPCIE18 P6
B23 VDDHTRX_6 VDDPCIE_14 R9 R25 VSSAHT19 VSSAPCIE19 R1
A23 VDDHTRX_7 VDDPCIE_15 T9 H20 VSSAHT20 VSSAPCIE20 R2
L14 680mA V9 U22 R4
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX VDDPCIE_16 VSSAHT21 VSSAPCIE21
+1.1VS 2 1 AE25 VDDHTTX_1 VDDPCIE_17 U9 V19 VSSAHT22 VSSAPCIE22 V7
AD24 W22 U4
GROUND
FBMA-L11-201209-221LMA30T_0805 VDDHTTX_2 VSSAHT23 VSSAPCIE23
2 1 1 1 1 1 1 AC23 VDDHTTX_3 VDDC_1 K12 W24 VSSAHT24 VSSAPCIE24 V8
C261 C174 AB22 J14 W25 V6
@ C175 C176 C177 C178 C202 VDDHTTX_4 VDDC_2 VSSAHT25 VSSAPCIE25
AA21 VDDHTTX_5 VDDC_3 U16 Y21 VSSAHT26 VSSAPCIE26 W1
10U_0805_10V4Z Y20 J11 AD25 W2
1 2 2 2 2 2 2 VDDHTTX_6 VDDC_4 +NB_CORE VSSAHT27 VSSAPCIE27
W19 VDDHTTX_7 VDDC_5 K15 VSSAPCIE28 W4
POWER
0.1U_0402_16V4Z 1U_0402_6.3V4Z V18 M12 L12 W7
4.7U_0603_6.3V6K 0.1U_0402_16V4Z VDDHTTX_8 VDDC_6 VSS11 VSSAPCIE29
U17 VDDHTTX_9 VDDC_7 L14 10A M14 VSS12 VSSAPCIE30 W8
T17 VDDHTTX_10 VDDC_8 L11 N13 VSS13 VSSAPCIE31 Y6
C189
R17 VDDHTTX_11 VDDC_9 M13 P12 VSS14 VSSAPCIE32 AA4
P17 VDDHTTX_12 VDDC_10 M15 P15 VSS15 VSSAPCIE33 AB5
M17 VDDHTTX_13 VDDC_11 N12 R11 VSS16 VSSAPCIE34 AB1
C191
C182
C187
C193
C194
C180
C188
C183
C195
C184
C196
L15 700mA N14 1 R14 AB7
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE VDDC_12 VSS17 VSSAPCIE35
+1.8VS 2 1 J10 P11 1 1 1 1 1 1 1 1 1 1 1 T12 AC3
FBMA-L11-201209-221LMA30T_0805 VDDA18PCIE_1 VDDC_13 + VSS18 VSSAPCIE36
P10 VDDA18PCIE_2 VDDC_14 P13 U14 VSS19 VSSAPCIE37 AC4
220U_C6_6.3V_M_R15
1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14 U11 VSS20 VSSAPCIE38 AE1
2 2
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M10 VDDA18PCIE_4 VDDC_16 R12 U15 VSS21 VSSAPCIE39 AE4
C181 C179 C192 C185 C190 C186 L10 R15 2 2 2 2 2 2 2 2 2 2 2 2 V12 AB2
VDDA18PCIE_5 VDDC_17 VSS22 VSSAPCIE40
W9 VDDA18PCIE_6 VDDC_18 T11 W11 VSS23
4.7U_0603_6.3V6K 2 2 2 2 2 2
H9 VDDA18PCIE_7 VDDC_19 T15 W15 VSS24
0.1U_0402_16V4Z 0.1U_0402_16V4Z T10 U12 AC12 AE14
4.7U_0603_6.3V6K VDDA18PCIE_8 VDDC_20 VSS25 VSS1
R10 VDDA18PCIE_9 VDDC_21 T14 AA14 VSS26 VSS2 D11
Y9 VDDA18PCIE_10 VDDC_22 J16 Y18 VSS27 VSS3 G8
AA9
VDDA18PCIE_11 23mA AB11
VSS28 VSS4
E14
AB9 AE10 AB15 E15
VDDA18PCIE_12 VDD_MEM1(NC) VSS29 VSS5
AD9 AA11 AB17 J15
VDDA18PCIE_13 VDD_MEM2(NC) VSS30 VSS6
AE9 Y11 AB19 J12
VDDA18PCIE_14 VDD_MEM3(NC) VSS31 VSS7
U10 AD10 AE20 K14
VDDA18PCIE_15 VDD_MEM4(NC) VSS32 VSS8
10mA VDD_MEM5(NC)
AB10 AB21
VSS33 VSS9
M11
+1.8VS F9 AC10 K11 L15
VDD18_1 VDD_MEM6(NC) VSS34 VSS10
G9
VDD18_2 60mA RS780M_FCBGA528
AE11 H11 +3VS
VDD18_MEM1(NC) VDD33_1(NC)
AD11 H12
VDD18_MEM2(NC) VDD33_2(NC)
5mA 1 1 RS880 A11(SA000032710)
1 RS780M_FCBGA528
C197 C198 C199
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
RS880 A11(SA000032710) 2 2
2
3 U3D 3
PAR 4 OF 6
Side port and Strap setting AB12
AE16
V11
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
AA18
AA20
AA19
AE15 Y19
MEM_A3(NC) MEM_DQ3/DVO_D0(NC)
AA12 V17
MEM_A4(NC) MEM_DQ4(NC)
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb AB16
MEM_A5(NC) MEM_DQ5/DVO_D1(NC)
AA17
Debug Mode AB14
MEM_A6(NC) MEM_DQ6/DVO_D2(NC)
AA15
AD14 Y15
MEM_A7(NC) MEM_DQ7/DVO_D4(NC)
<13,17> GMCH_CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO. (VSYNC) AD13
MEM_A8(NC) MEM_DQ8/DVO_D3(NC)
AC20
R92 3K_0402_5% 1 : Disable AD15 AD19
MEM_A9(NC) MEM_DQ9/DVO_D5(NC)
2 1 AC16 AE22
SBD_MEM/DVO_I/F
R93 @ 3K_0402_5% 0 : Enable AE13
MEM_A10(NC) MEM_DQ10/DVO_D6(NC)
AC18
MEM_A11(NC) MEM_DQ11/DVO_D7(NC)
AC14 AB20
MEM_A12(NC) MEM_DQ12(NC)
Y14 AD22
MEM_A13(NC) MEM_DQ13/DVO_D9(NC)
AC22
MEM_DQ14/DVO_D10(NC)
DFT_GPIO1: LOAD_EEPROM_STRAPS AD16
MEM_BA0(NC) MEM_DQ15/DVO_D11(NC)
AD21
Load EEPROM Strap AE17
MEM_BA1(NC)
Selects Loading of STRAPS from EPROM AD17
MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC)
Y17
D1 @ 1 : Bypass the loading of EEPROM straps and use Hardware Default Values W18
CH751H-40_SC76 MEM_DQS0N/DVO_IDCKN(NC)
0 : I2C Master can load strap values from EEPROM if connected, or use W12 AD20
MEM_RASb(NC) MEM_DQS1P(NC)
<13> SUS_STAT_R# 2 1 A_RST# <13,18,28> Y12 AE21
default values if not connected MEM_CASb(NC) MEM_DQS1N(NC)
AD18
MEM_WEb(NC)
2 1 AB13 W17
R264 @ 3K_0402_5% MEM_CSb(NC) MEM_DM0(NC)
AB18 AE19
MEM_CKE(NC) MEM_DM1/DVO_D8(NC)
V14
MEM_ODT(NC) 15mA
AE23 +1.8VS
IOPLLVDD18(NC)
V15 AE24 +1.1VS
MEM_CKP(NC) IOPLLVDD(NC)
Enable Side Port Memory W14
MEM_CKN(NC) 26mA
Enable Side Port Memory IOPLLVSS(NC)
AD23
AE12 MEM_COMPP(NC)
4 4
RS880: HSYNC# AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18
<13,17> GMCH_CRT_HSYNC 2 1 +3VS 0: Enable Register Readback of strap:
R94 3K_0402_5% NB_CLKCFG:CLK_TOP_SPARE_D[1] RS780M_FCBGA528
@ 1 : Disable
2
R95
1
3K_0402_5% RS880 A11(SA000032710)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880 PWR/GND
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 14 of 45
A B C D E
5 4 3 2 1
1
W=60mils 43 4 +LCDVDD_L 2 @ 1
G3 4 +LCDVDD
R250 44 5 +LCDVDD R841 0_0603_5%
300_0603_5% G4 5
45 G5 6 6
1
1 46 G6 7 7
INVT_PWM
+3VS W=60mils
R251 C538 8
2
8 DISPOFF#
100K_0402_5% 9 9
4.7U_0805_10V4Z 10 GMCH_LCD_CLK
2 10 GMCH_LCD_DATA GMCH_LCD_CLK <13>
11 GMCH_LCD_DATA <13>
2
11
12 DAC_BRIG <28>
12
3
D D S
TXOUT0- D
13 TXOUT0- <13>
Q11
G
AO3413_SOT23-3 13 TXOUT0+
2 2 1 2 14
14 TXOUT0+ <13>
G R252 1K_0402_5% Q13 15
15 TXOUT1-
S 1
D 16 TXOUT1- <13>
1
2N7002_SOT23 C539 +LCDVDD 16 TXOUT1+
17 TXOUT1+ <13>
17
W=60mils 18
18
1
D Q23 0.047U_0402_16V7K TXOUT2-
19 TXOUT2- <13>
GMCH_ENVDD 2 19 TXOUT2+
<13> GMCH_ENVDD 2 <NCQD0 use> 20
20 TXOUT2+ <13>
G 1 1 21
21 TXCLK-
1 R507 2 S 2N7002_SOT23 C540 C541 22 TXCLK- <13>
3
100K_0402_5% 22 TXCLK+
23 TXCLK+ <13>
4.7U_0805_10V4Z 0.1U_0402_16V4Z 23
24 24
2 2 25
25
26 26
27 R842 2 @ 1 0_0402_5%
27 DMIC_DATA_R DMIC_DATA LOCAL_DIM <28>
28 R885 2 @ 1 0_0603_5%
28 DMIC_CLK_R DMIC_CLK DMIC_DATA <30>
29 R886 2 @ 1 0_0603_5%
29 DMIC_CLK <30>
30 R843 2 @ 1 0_0402_5%
30 COLOY_ENG_EN <28>
31 +3VS_DMIC R887 2 @ 1 0_0402_5% +3VS
31
32 32
33 33
+3VS 34
+LCDVDD 34
35 35
+INVPWR_B+ B+ 36
36
1
37 37 +3VS
L58 2 1 R121 38
38 USB20_N5 <19>
W=40mils FBMA-L11-201209-221LMA30T_0805 D9 @ 39
39 USB20_P5 <19>
CH751H-40PT_SOD323-2 4.7K_0402_5% 1 1 40
L59 2 @ C546 C547 40
1
2
FBMA-L11-201209-221LMA30T_0805 BKOFF# 1 2 DISPOFF# IPEX_20143-040E-20F
<28> BKOFF#
1 1 10U_0805_10V4Z 0.1U_0402_16V4Z CONN@
C544 C545 R172 1 2 0_0402_5% 2 2
C C
680P_0402_50V7K 68P_0402_50V8J R171 1 2 10K_0402_5% D14 @
2 2 USB20_N5
6 CH3 CH2 3
@
DMIC_DATA_R 1 2 +3VS 5 2
C1024 @ 220P_0402_50V7K Vp Vn
DMIC_CLK_R 1 2
C1025 @ 220P_0402_50V7K
DAC_BRIG 1 2 USB20_P5 4 1
C542 220P_0402_50V7K CH4 CH1
INVT_PWM 1 2 CM1293-04SO_SOT23-6
C543 220P_0402_50V7K
DISPOFF# 1 2
EC_INVT_PWM 1 UNVB@ 2 INVT_PWM C548 220P_0402_50V7K
<28> EC_INVT_PWM
R260 0_0402_5%
1
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 15 of 45
5 4 3 2 1
5 4 3 2 1
D3 F1
W=40mils
2
10K_0402_5%
10K_0402_5%
+5VS 2 1 +HDMI_5V_OUT_1 1 2
1
1
4.7K_0402_5%
R274
R275
RB491D_SC59-3 1.1A_6VDC_FUSE C549
R276 R277 HDMI@ HDMI@ 0.1U_0402_16V4Z
HDMI@ 4.7K_0402_5% HDMI@
2
2
G
@ @ HDMI@
@ JHDMI1
2
D HDMI_SCLK HDMI_HPD D
3 1 19
HP_DET
<13> GMCH_HDMI_CLK
D
+HDMI_5V_OUT 18
Q16 +5V
17
DDC/CEC_GND
2
G
<5V tolerant> BSH111 1N_SOT23-3 HDMI_SDATA 16
HDMI_SCLK SDA
15
HDMI_SDATA SCL
3 1 14
Reserved
<13> GMCH_HDMI_DATA
D
13
@ Q17 HDMI_R_CK- CEC
12 20
BSH111 1N_SOT23-3 CK- GND
11 21
HDMI_R_CK+ CK_shield GND
10 22
HDMI_R_D0- CK+ GND
2 HDMI@ 1 9
D0- GND
23
R278 0_0402_5% 8
HDMI_R_D0+ D0_shield
7 D0+
2 HDMI@ 1 HDMI_R_D1- 6
R279 0_0402_5% D1-
5 D1_shield
HDMI_R_D1+ 4
HDMI_R_D2- D1+
Check 5V tolerant 3 D2-
2 D2_shield
HDMI_R_D2+ 1 D2+
Place closed to JHDMI1 SUYIN_100042MR019S153ZL
CONN@
<NAV70 use>
+3VS
2
HDMI@
+HDMI_5V_OUT R280
C 0_0402_5% C
HDMI_HPD
1
1 1
2
C681 @ 1 C687
@ 1 R304 2 R411 0.1U_0402_16V7K C HDMI@
+3VS
100K_0402_5% @ 2 1 2 HDMI_HPD
5
1
1
2 4 GMCH_HDMI_DET <13> GMCH_HDMI_DET GMCH_HDMI_DET Q18
A Y MMBT3904_NL_SOT23-3 R283
G
1
U40 365K_0402_1%
@ HDMI@
3
R284
2
10K_0402_5%
HDMI@
2
SN74AHCT1G125GW_SOT353-5
Reserve
HDMI@
HDMI_C_CLK- R285 1 2 0_0402_5% HDMI_R_CK-
WCM-2012-900T_0805
@ 4 3
C550 HDMI@2 HDMI_C_TX2- 4 3
<12> GMCH_HDMI_TXD2- 1 0.1U_0402_16V7K R286 1 HDMI@ 2 715_0402_1%
C551 HDMI@2 1 0.1U_0402_16V7K HDMI_C_TX2+ R287 1 HDMI@ 2 715_0402_1% HDMI_C_CLK+ R288 1 2 0_0402_5% HDMI_R_CK+
B <12> GMCH_HDMI_TXD2+ B
HDMI@
C552 HDMI@2 1 0.1U_0402_16V7K HDMI_C_TX1- R289 1 HDMI@ 2 715_0402_1%
<12> GMCH_HDMI_TXD1- HDMI_C_TX1+ HDMI_C_TX0- HDMI_R_D0-
C553 HDMI@2 1 0.1U_0402_16V7K R290 1 HDMI@ 2 715_0402_1% R291 1 HDMI@ 2 0_0402_5%
<12> GMCH_HDMI_TXD1+
C554 HDMI@2 1 0.1U_0402_16V7K HDMI_C_TX0- R292 1 HDMI@ 2 715_0402_1% 1 2
<12> GMCH_HDMI_TXD0- HDMI_C_TX0+ 1 2
C555 HDMI@2 1 0.1U_0402_16V7K R293 1 HDMI@ 2 715_0402_1% 10mil L61
<12> GMCH_HDMI_TXD0+
WCM-2012-900T_0805
C556 HDMI@2 1 0.1U_0402_16V7K HDMI_C_CLK- R294 1 HDMI@ 2 715_0402_1% @ 4 3
<12> GMCH_HDMI_TXC- HDMI_C_CLK+ 4 3
C557 HDMI@2 1 0.1U_0402_16V7K R295 1 HDMI@ 2 715_0402_1%
<12> GMCH_HDMI_TXC+
HDMI_C_TX0+ R296 1 2 0_0402_5% HDMI_R_D0+
HDMI@
1
R298 WCM-2012-900T_0805
HDMI@ @ 4 3
100K_0402_5% 4 3
10mil HDMI_C_TX1+ HDMI_R_D1+
R299 1 2 0_0402_5%
2
HDMI@
1 2
L63 1 2
WCM-2012-900T_0805
@
Place closed to JHDMI1 4
4 3
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 16 of 45
5 4 3 2 1
A B C D E
2
D7 F2 W=40mils
2 1 1 2
RB491D_SC59-3 1.1A_6VDC_FUSE
1
D4 D5
PJDLC05C_SOT23-3 PJDLC05C_SOT23-3 C558
@ @ 0.1U_0402_16V4Z
2
1
1 1
1
1 1 1 1 1 1 3
R305 R307 R308 C559 C560 C561 C562 C563 C564 9
14 G 16
150_0402_1% 4 17
2 2 2 2 2 2 G
10
2
140_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 15
10P_0402_50V8J 1 5
150_0402_1% 10P_0402_50V8J C565
C-H_13-12201513CP
100P_0402_50V8J CONN@
2
+CRT_VCC
CRT_HSYNC_2 CRT_DET# <19>
L67 1 2
C569 1 2 0.1U_0402_16V4Z R312 2 1 10K_0402_5% FCM2012CF-800T06_2P DSUB_12
2
L68 1 2 CRT_VSYNC_2 1 R311
1
U18 FCM2012CF-800T06_2P 1 1 100K_0402_5%
@
OE#
P
GMCH_CRT_HSYNC 2 4 CRT_HSYNC_1 C566 C567 DSUB_15
<13,14> GMCH_CRT_HSYNC
1
A Y 10P_0402_50V8J 10P_0402_50V8J C568 2
2 G 2 2 68P_0402_50V8J 1 2
74AHCT1G125GW_SOT353-5
3
C570 +CRT_VCC
+CRT_VCC 68P_0402_50V8J
2
C571 1 2 0.1U_0402_16V4Z
1
U19
OE#
P
GMCH_CRT_VSYNC 2 4 CRT_VSYNC_1
<13,14> GMCH_CRT_VSYNC A Y
G
74AHCT1G125GW_SOT353-5
Change as SA411250110
+3VS
3 3
1
R317 1 R318
4.7K_0402_5% 4.7K_0402_5%
2
2
G
@
DSUB_12 1 3 GMCH_CRT_DATA
GMCH_CRT_DATA <13>
S
Q53
2
BSH111 1N_SOT23-3
G
@
DSUB_15 1 3 GMCH_CRT_CLK
GMCH_CRT_CLK <13>
S
Q65
BSH111 1N_SOT23-3
2 1
R321 0_0402_5%
2 1
R323 0_0402_5%
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 17 of 45
A B C D E
A B C D E
R370
C572 1 2 150P_0402_50V8J U20A
@ 33_0402_5%
2 1 P1
SB800 Part 1 of 5
W2
A_RST# PCIE_RST# PCICLK0
<13,14,28> A_RST# 2 1 33_0402_5%L1 A_RST# PCICLK1/GPO36 W1 PCI_CLK1 <22>
R325 W3
PCI CLKS
PCICLK2/GPO37 PCI_CLK2 <22>
C579 1 2 0.1U_0402_16V7K SB_RX0P_C AD26 W4
<12> SB_RX0P A_TX0P PCICLK3/GPO38 PCI_CLK3 <22>
C573 1 2 0.1U_0402_16V7K SB_RX0N_C AD27 Y1
<12> SB_RX0N A_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 <22>
C574 1 2 0.1U_0402_16V7K SB_RX1P_C AC28
<12> SB_RX1P SB_RX1N_C A_TX1P
C575 1 2 0.1U_0402_16V7K AC29 V2 PAD T26
<12> SB_RX1N SB_RX2P_C A_TX1N PCIRST#
C576 1 2 0.1U_0402_16V7K AB29
<12> SB_RX2P SB_RX2N_C A_TX2P
C580 1 2 0.1U_0402_16V7K AB28
<12> SB_RX2N SB_RX3P_C A_TX2N
C577 1 2 0.1U_0402_16V7K AB26 AA1
<12> SB_RX3P A_TX3P AD0/GPIO0
C578 1 2 0.1U_0402_16V7K SB_RX3N_C AB27 AA4
1 <12> SB_RX3N A_TX3N AD1/GPIO1 +3VALW 1
AA3
AD2/GPIO2 C581
<12> SB_TX0P AE24 AB1
A_RX0P AD3/GPIO3
<12> SB_TX0N AE23 AA5 1 2
A_RX0N AD4/GPIO4
<12> SB_TX1P AD25
A_RX1P AD5/GPIO5
AB2 AMD suggest add GPIO control gate
0.1U_0402_16V4Z
5
<12> SB_TX2N AC25 AA6 R427 @ 0_0402_5% U21
A_RX2N AD8/GPIO8
<12> SB_TX3P AB25 AC2 1 2 2
P
A_RX3P AD9/GPIO9 R425 0_0402_5% B PLT_RST#
<12> SB_TX3N AB24 AC3 4 PLT_RST# <24,26>
A_RX3N AD10/GPIO10 A_RST# Y
AC4 1
AD11/GPIO11 A
G
R326 2 1 590_0402_1% AD29 AC1 NC7SZ08P5X_NL_SC70-5
PCIE_CALRP AD12/GPIO12
1
+1.1VS_PCIE R327 2 1 2K_0402_1% AD28 AD1
3
PCIE_CALRN AD13/GPIO13 R328
AD14/GPIO14 AD2
AA28 AC6 8.2K_0402_5%
GPP_TX0P AD15/GPIO15 @
AA29 GPP_TX0N AD16/GPIO16 AE2
Y29 AE1
2
GPP_TX1P AD17/GPIO17
Y28 GPP_TX1N AD18/GPIO18 AF8
Y26 GPP_TX2P AD19/GPIO19 AE3
Y27 GPP_TX2N AD20/GPIO20 AF1
+3VS W28 AG1
+1.5VS GPP_TX3P AD21/GPIO21
W29 GPP_TX3N AD22/GPIO22 AF2
AE9 PCI_AD23
AD23/GPIO23 PCI_AD23 <22>
2
PCI INTERFACE
2 CBE1# 2
CBE2# AD8
level shift to ISL6265 CBE3# AA10
FRAME# AE8
DEVSEL# AB9
<13> CLK_SBLINK_BCLK M23 PCIE_RCLKP/NB_LNK_CLKP IRDY# AJ3
NB A LINK <13> CLK_SBLINK_BCLK# P23 PCIE_RCLKN/NB_LNK_CLKN TRDY# AE7
PAR AC5
<13> NB_DISP_CLKP U29 AF5
NB_DISP_CLKP STOP#
<13> NB_DISP_CLKN U28 AE6
NB_DISP_CLKN PERR#
ISL6265 PWROK input, TTL level: 0.8V~2.0V SERR#
AE4
<13> CLK_NBHT T26 AE11
NB_HT_CLKP REQ0#
When this pin is high, the SVI interface is NB HT <13> CLK_NBHT# T27
NB_HT_CLKN REQ1#/GPIO40
AH5
AH4
active and I2C protocol is running. While this <8> CLK_CPU_BCLK V21
REQ2#/CLK_REQ8#/GPIO41
AC12
CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42
pin is low, the SVC, SVD, and VFIXEN input CPU <8> CLK_CPU_BCLK# T21
CPU_HT_CLKN GNT0#
AD12
AJ5
states determine the pre-PWROK metal VID or GNT1#/GPO44
V23 AH6
SLT_GFX_CLKP GNT2#/GPO45
VFIX mode voltage. This pin must be low prior T23 AB12
SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46
AB11 CLKRUN# <28>
to the ISL6265 PGOOD output going high CLKRUN# +RTCBATT
L29 AD7
GPP_CLK0P LOCK#
L28
GPP_CLK0N
AJ6
INTE#/GPIO32
<24> CLK_PCIE_LAN N29 AG6
GPP_CLK1P INTF#/GPIO33
1
LAN <24> CLK_PCIE_LAN# N28 AG4 CONN@
GPP_CLK1N INTG#/GPIO34 PBJ1
AJ4
+
INTH#/GPIO35
M29
GPP_CLK2P
M28
GPP_CLK2N
-
1 2 M25 G28 LPC_FRAME# <28>
C689 GPP_CLK5N LFRAME# SUYIN_060003HA002G202ZL
J25
2
LDRQ0#
1
GPP_CLK7P
N27
25M_CLK_X2 GPP_CLK7N
1 2 G21 ALLOW_LDTSTOP <13>
C688 ALLOW_LDTSTP/DMA_ACTIVE#
T29 H21 H_PROCHOT_R# <8>
27P_0402_50V8J GPP_CLK8P PROCHOT#
T28 K19 H_PWRGD <8>
GPP_CLK8N LDT_PG
CPU
1
D2 R331
RTC
2
@ R332 20M_0402_5%
1 2 SB820M_FCBGA605 2
1 2 1
R333 510_0402_5% 3
C582 +CHGRTC
0.1U_0402_16V4Z
C584 1 1 C585 W=20mils
2
0.1U_0402_16V4Z
1 2 SB_32KHI 1U_0402_6.3V4Z 1
R334 C583 DAN202UT106_SC70-3
4 Y3 4
18P_0402_50V8J @
1
1
20M_0603_5% 4 3
OSC NC
C586
2
32.768KHZ_12.5PF_Q13MC14610002
SB_32KHO
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
18P_0402_50V8J Issued Date 2010/04/12 2010/10/12 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB820-PCIE/PCI/ACPI/LPC/RTC
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 18 of 45
A B C D E
A B C D E
+3VALW
2
@
R336
100K_0402_5%
U20D
<28> EC_SWI# J2 A10
1
CRT_DET PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
K1 RI#/GEVENT22#
CRT_DET D3 G19 USB_RCOMP 1 2
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
1
D 11.8K_0402_1% R338
<28> PM_SLP_S3# F1 SLP_S3#
2 @ H1
<17> CRT_DET# <28> PM_SLP_S5# SLP_S5#
G Q22 F2
USB 2.0
<10,11,26> SB_SMDAT0 AE22 SDA0/GPIO47 USB_HSD7N G14 USB20_N7 <27>
R588 1 UNVB@ 2 100K_0402_5% SB_SMCLK1 F5
Cinfigure to output or Internal PU/PD SB_SMDAT1 SCL1/GPIO227 USB20_P6
F4 SDA1/GPIO228 USB_HSD6P G16 USB20_P6 <26>
Check SW: VB_EN AH21 G18 USB20_N6 CardReader
ACF_EN LAY_SEL: 1-> 6L* CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N USB20_N6 <26>
R402 1 2 2.2K_0402_5% LAN <24> LAN_CLKREQ# AB18
0-> 8L CLK_REQ1#/FANOUT4/GPIO61 USB20_P5
E1 D16 USB20_P5 <15>
GPIO
@ IR_LED#/LLB#/GPIO184 USB_HSD5P USB20_N5
2 1 100K_0402_5% AJ21 C16 USB20_N5 <15> Camera
2 R406 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD5N 2
H4 DDR3_RST#/GEVENT7#
D5 GBE_LED0/GPIO183 USB_HSD4P B14
R846 1 @ 2 2.2K_0402_5% MUXLESS_SEL MUXLESS SEL: 1->PX with Muxless D7 A14
0->PX with Mux GBE_LED1/GEVENT9# USB_HSD4N
G5 GBE_LED2/GEVENT10#
2 1 K3 E18
R847 100K_0402_5% GBE_STAT0/GEVENT11# USB_HSD3P
AA20 CLK_REQG#/GPIO65/OSCIN USB_HSD3N E16
EHCI1 / OHCI1
J16 USB20_P2
USB_HSD2P USB20_N2 USB20_P2 <27>
H3
BLINK/USB_OC7#/GEVENT18# USB_HSD2N
J18 USB20_N2 <27> Ext USB3 <Wake Up support>
EC_LID_OUT# D1
<28> EC_LID_OUT# USB_OC6#/IR_TX1/GEVENT6# USB20_P1
E4 B17 USB20_P1 <27>
USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P
USB OC
T27 PAD D4 A17 USB20_N1 Ext USB2
USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N USB20_N1 <27>
E8
USB_OC#2 USB_OC3#/AC_PRES/TDO/GEVENT15# USB20_P0
<27> USB_OC#2 F7 A16 USB20_P0 <27>
USB_OC#1 USB_OC2#/TCK/GEVENT14# USB_HSD0P USB20_N0
<27> USB_OC#1 E7
USB_OC1#/TDI/GEVENT13# USB_HSD0N
B16 USB20_N0 <27> Ext USB1
USB_OC#0 F8
<27> USB_OC#0 USB_OC0#/TRST#/GEVENT12#
R345 1 2 33_0402_5%
<30> HDA_BITCLK_AUDIO HDA_BITCLK M3 D25 Check SW:
<22> HDA_SDOUT HDA_SDOUT AZ_BITCLK SCL2/GPIO193
R346 1 2 33_0402_5% N1 F23 Cinfigure to output or Internal PU/PD
<30> HDA_SDOUT_AUDIO AZ_SDOUT SDA2/GPIO194
HDA_SDIN0 L2 B26 SB_SIC
<30> HDA_SDIN0 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195
HDA_SDIN1 M2 E26 SB_SID
HD AUDIO
AZ_SDIN1/GPIO168 SDA3_LV/GPIO196
M1 F25
AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197
M4 E22
R347 1 HDA_SYNC AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198
<30> HDA_SYNC_AUDIO 2 33_0402_5% N2 F22 GPIO199 <22>
R348 1 HDA_RST# AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199
<30> HDA_RST_AUDIO# 2 33_0402_5% P2 E21 GPIO200 <22> STRAP PIN
AZ_RST# EC_PWM3/EC_TIMER3/GPIO200
G24
GBE_COL KSI_0/GPIO201
T1 G25
GBE_CRS GBE_COL KSI_1/GPIO202
T4 E28
GBE_CRS KSI_2/GPIO203
L6 E29
3 GBE_MDIO GBE_MDCK KSI_3/GPIO204 3
L5 D29
GBE_MDIO KSI_4/GPIO205
T9 D28
GBE_RXCLK KSI_5/GPIO206
U1 C29
GBE_RXD3 KSI_6/GPIO207
U3 C28
GBE_RXD2 KSI_7/GPIO208
T2
GBE_RXD1
GBE LAN
U2 B28
+3VS GBE_RXD0 KSO_0/GPIO209
T5 A27
GBE_RXERR GBE_RXCTL/RXDV KSO_1/GPIO210
V5 B27
EMBEDDED CTRL
@ HDA_BITCLK GBE_RXERR KSO_2/GPIO211
1 2 P5 D26
GBE_TXCLK KSO_3/GPIO212
R349 10K_0402_5% R342 1 2 2.2K_0402_5% SB_SMCLK0 M5
GBE_TXD3 KSO_4/GPIO213
A26
1 @ 2 HDA_SDIN0 P9 C26
GBE_TXD2 KSO_5/GPIO214
R350 10K_0402_5% R343 1 2 2.2K_0402_5% SB_SMDAT0 T7 A24
@ HDA_SDIN1 GBE_TXD1 KSO_6/GPIO215
1 2 P7 B25
R351 10K_0402_5% R344 1 SUS_STAT# GBE_TXD0 KSO_7/GPIO216
2 4.7K_0402_5% M7 A25
GBE_TXCTL/TXEN KSO_8/GPIO217
P4 D24
GBE_PHY_PD KSO_9/GPIO218
M9 B24
GBE_PHY_INTR GBE_PHY_RST# KSO_10/GPIO219
V7 C24
GBE_PHY_INTR KSO_11/GPIO220
B23
KSO_12/GPIO221
T28 PAD E23 A23
PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222
T29 PAD E24 D22
PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223
F21 C22
EMBEDDED CTRL
SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224
G29 A22
+3VALW FC_RST#/GPO160 KSO_16/GPIO225
B22
KSO_17/GPIO226
D27
+3VALW PS2KB_DAT/GPIO189
F28
R352 1 GBE_MDIO PS2KB_CLK/GPIO190
2 10K_0402_5% F29
PS2M_DAT/GPIO191
E27
R420 1 @ PS2M_CLK/GPIO192
2 10K_0402_5%
1 2 SB_PCIE_WAKE#
R355 10K_0402_5% R3531 @ 2 10K_0402_5% GBE_COL SB820M_FCBGA605
1 @ 2 EC_LID_OUT#
R357 100K_0402_5% R428 1 2 10K_0402_5%
4 SB_SIC 4
1 2
R359 2.2K_0402_5% R354 1 @ 2 10K_0402_5% GBE_CRS
1 2 SB_SID
R360 2.2K_0402_5% R429 1 2 10K_0402_5%
1 2 H_THERMTRIP#
R361 10K_0402_5% R356 1 @ 2 10K_0402_5% GBE_RXERR
1 2 SB_SMCLK1
R362 2.2K_0402_5% R430 1 2 10K_0402_5%
1 2 SB_SMDAT1 Security Classification Compal Secret Data Compal Electronics, Inc.
R363 2.2K_0402_5% R358 1 2 10K_0402_5% GBE_PHY_INTR 2010/04/12 2010/10/12 Title
Issued Date Deciphered Date
R431 1 @ 2 10K_0402_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB820 USB/HD audio
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 19 of 45
A B C D E
A B C D E
U20B
AH9
SB800 AH28
1 <23> SATA_STX_DRX_P0 SATA_TX0P FC_CLK 1
<23> SATA_STX_DRX_N0
AJ9
SATA_TX0N Part 2 of 5 FC_FBCLKOUT
AG28
HDD AJ8
FC_FBCLKIN
AF26
<23> SATA_DTX_C_SRX_N0 SATA_RX0N
<23> SATA_DTX_C_SRX_P0 AH8 AF28
SATA_RX0P FC_OE#/GPIOD145
AG29
FC_AVD#/GPIOD146
<23> SATA_STX_DRX_P1 AH10 AG26
SATA_TX1P FC_WE#/GPIOD148
<23> SATA_STX_DRX_N1 AJ10 AF27
SATA_TX1N FC_CE1#/GPIOD149
ODD AG10
FC_CE2#/GPIOD150
AE29
AF29
<23> SATA_DTX_C_SRX_N1 SATA_RX1N FC_INT1/GPIOD144
<23> SATA_DTX_C_SRX_P1 AF10 AH27
SATA_RX1P FC_INT2/GPIOD147
AG12 SATA_TX2P FC_ADQ0/GPIOD128 AJ27
AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26
FC_ADQ2/GPIOD130 AH25
AJ12 SATA_RX2N FC_ADQ3/GPIOD131 AH24
AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23
FC_ADQ5/GPIOD133 AH23
AH14 SATA_TX3P FC_ADQ6/GPIOD134 AJ22
AJ14 SATA_TX3N FC_ADQ7/GPIOD135 AG21
FC_ADQ8/GPIOD136 AF21
AG14 SATA_RX3N FC_ADQ9/GPIOD137 AH22
AF14 AJ23
FLASH
SATA_RX3P FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139 AF23
AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24
AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25
FC_ADQ14/GPIOD142 AG25
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26
AH17 SATA_RX4P
SERIAL ATA
AJ18 SATA_TX5P
AH18 SATA_TX5N FANOUT0/GPIO52 W5
FANOUT1/GPIO53 W6
2 2
AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19 SATA_RX5P
FANIN0/GPIO56 W7
R364 1K_0402_1% V9
SATA_CALRP FANIN1/GPIO57
2 1 AB14 W8
SATA_CALRN SATA_CALRP FANIN2/GPIO58
+1.1VS_SATA 2 1 AA14 SATA_CALRN
R365 931_0402_1% B6
TEMPIN0/GPIO171
A6
TEMPIN1/GPIO172 @ R366
<29> SATA_LED# AD11 A5
SATA_ACT#/GPIO67 TEMPIN2/GPIO173
B5 1 2 EC_THERM# <28>
TEMPIN3/TALERT#/GPIO174 0_0402_5%
C7
R367 1 TEMP_COMM Check SW:
+3VS 2 10K_0402_5%
A3 Cinfigure to output or Internal PU/PD
SATA_X1 AD16 VIN0/GPIO175
B4
HW MONITOR
SATA_X1 VIN1/GPIO176
A4
VIN2/GPIO177
C5
VIN3/GPIO178 MEM_1V5
A7
VIN4/GPIO179
B7
VIN5/GPIO180
B8
SATA_X2 AC16 VIN6/GBE_STAT3/GPIO181
A8
SATA_X2 VIN7/GBE_LED3/GPIO182
J5 G27
SPI_DI/GPIO164 NC1
E2 Y2
SPI_DO/GPIO163 NC2
SPI ROM
K4
SPI_CLK/GPIO162
K9
SPI_CS1#/GPIO165
@ G2
ROM_RST#/GPIO161
1 2 SATA_X1
C588
1
27P_0402_50V8J @ SB820M_FCBGA605
3 @ 3
Y4 R368
25MHZ_20PF_7A25000012 10M_0402_5%
SB820 A12(SA00003IW10)
2
@
2
1 2 SATA_X2
C589
27P_0402_50V8J
0.1U_0402_16V4Z
5
U22
MEM_1V5 2
P
B
4 1 2 VDDR_SW <39>
Y R424 33_0402_5%
<18,22> PCI_AD24 1 2 1
A
G
R422 0_0402_5% 2
NC7SZ08P5X_NL_SC70-5
3
C686
150P_0402_50V8J
1
1 @ 2
PCI_AD24 R423 0_0402_5%
1 : VDDR=1.05V
0 : VDDR=0.9V
For VDDR Voltage Switch, AMD suggest
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB820 SATA/IDE/SPI
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 20 of 45
A B C D E
A B C D E
+1.1VS_VDDC U20E
510mA
1 2 +1.1VS
U20C R369 0_0805_5%
Part 3 of 5
SB800
131mA SB800 Y14 VSSIO_SATA_1 VSS_1 AJ2
+3VS AH1 N13 10U_0805_10V4Z 1 2 C590 Y16 A28
VDDIO_33_PCIGP_1 VDDCR_11_1 VSSIO_SATA_2 VSS_2
V6 R15 AB16 A2
VDDIO_33_PCIGP_2 VDDCR_11_2 1U_0402_6.3V4Z C596 VSSIO_SATA_3 VSS_3
1 2 Y19 N17 2 1 AC14 E5
C591 22U_0805_6.3V6M VDDIO_33_PCIGP_3 VDDCR_11_3 1U_0402_6.3V4Z C594 VSSIO_SATA_4 VSS_4
CORE S0
AE5 U13 2 1 AE12 D23
1 C592 0.1U_0402_16V4Z VDDIO_33_PCIGP_4 VDDCR_11_4 0.1U_0402_16V4Z C597 VSSIO_SATA_5 VSS_5 1
1 2 AC21
VDDIO_33_PCIGP_5 VDDCR_11_5
U17 2 1 AE14
VSSIO_SATA_6 VSS_6
E25
C593 1 2 0.1U_0402_16V4Z AA2 V12 0.1U_0402_16V4Z 2 1 C598 AF9 E6
C599 0.1U_0402_16V4Z VDDIO_33_PCIGP_6 VDDCR_11_6 VSSIO_SATA_7 VSS_7
PCI/GPIO I/O
1 2 AB4
VDDIO_33_PCIGP_7 VDDCR_11_7
V18 AF11
VSSIO_SATA_8 VSS_8
F24
AC8 W12 AF13 N15
VDDIO_33_PCIGP_8 VDDCR_11_8 VSSIO_SATA_9 VSS_9
AA7 W18 AF16 R13
VDDIO_33_PCIGP_9 VDDCR_11_9 VSSIO_SATA_10 VSS_10
AA9 AG8 R17
VDDIO_33_PCIGP_10 +1.1VS_CKVDD L69 VSSIO_SATA_11 VSS_11
AF7
VDDIO_33_PCIGP_11 400mA AH7
VSSIO_SATA_12 VSS_12
T10
AA19 K28 2 1 +1.1VS AH11 P10
VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 FBMA-L11-201209-221LMA30T_0805 VSSIO_SATA_13 VSS_13
K29 AH13 V11
VDDAN_11_CLK_2 VSSIO_SATA_14 VSS_14
VDDAN_11_CLK_3
J28 External Clock, connect to +1.1VS AH16
VSSIO_SATA_15 VSS_15
U15
K26 22U_0805_6.3V6M 1 2 C595 AJ7 M18
71mA
VDDAN_11_CLK_4
J21 directly, no need thick trace AJ11
VSSIO_SATA_16 VSS_16
V19
CLKGEN I/O
VDDAN_11_CLK_5 1U_0402_6.3V4Z C600 VSSIO_SATA_17 VSS_17
AF22 VDDIO_18_FC_1 VDDAN_11_CLK_6 J20 2 1 AJ13 VSSIO_SATA_18 VSS_18 M11
1U_0402_6.3V4Z C601
FLASH I/O
AE25 VDDIO_18_FC_2 VDDAN_11_CLK_7 K21 2 1 check can be removed? AJ16 VSSIO_SATA_19 VSS_19 L12
AF24 J22 0.1U_0402_16V4Z 2 1 C602 L18
VDDIO_18_FC_3 VDDAN_11_CLK_8 0.1U_0402_16V4Z C603 VSS_20
1 2 AC22 VDDIO_18_FC_4 2 1 A9 VSSIO_USB_1 VSS_21 J7
R371 0_0402_5% B10 P3
VSSIO_USB_2 VSS_22
VDDRF_GBE_S V1 1 2 K11 VSSIO_USB_3 VSS_23 V4
R372 0_0402_5% B9 AD6
POWER VDDIO_33_GBE_S M10 1 2
+3VALW
D10
VSSIO_USB_4
VSSIO_USB_5
VSS_24
VSS_25 AD4
43mA R373 0_0402_5% D12 AB7
@ VSSIO_USB_6 VSS_26
+VDDPL_3V_PCIE AE28 VDDPL_33_PCIE D14 VSSIO_USB_7 VSS_27 AC9
GBE LAN
U85 D17 V8
L70 +1.1VS_PCIE +VDDCR_USB @ VSSIO_USB_8 VSS_28
600mA VIN 1 E9 VSSIO_USB_9 VSS_29 W9
L107
PCI EXPRESS
+1.1VS 2 1 U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 1 2 F9 VSSIO_USB_10 VSS_30 W10
FBMA-L11-201209-221LMA30T_0805 V22 L9 R374 0_0402_5% 2 1 5 1U_0402_6.3V6K F12 AJ28
VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 FBMA-L11-160808-221LMT 0603 VOUT VSSIO_USB_11 VSS_31
V26 VDDAN_11_PCIE_3 GND 2 1 2 F14 VSSIO_USB_12 VSS_32 B29
C604 1 2 22U_0805_6.3V6M V27 F16 U4
C605 1U_0402_6.3V4Z VDDAN_11_PCIE_4 C989 VSSIO_USB_13 VSS_33
1 2 V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6 1 2 4 FB C9 VSSIO_USB_14 VSS_34 Y18
C606 1 2 0.1U_0402_16V4Z V29 P8 R375 0_0402_5% 3 @ G11 Y10
C607 0.1U_0402_16V4Z VDDAN_11_PCIE_6 VDDIO_GBE_S_2 EN VSSIO_USB_15 VSS_35
GROUND
1 2 W22 VDDAN_11_PCIE_7 F18 VSSIO_USB_16 VSS_36 Y12
W26 VDDAN_11_PCIE_8 D9 VSSIO_USB_17 VSS_37 Y11
2 APL5317 2
H12 VSSIO_USB_18 VSS_38 AA11
+VDDPL_3V_SATA H14 VSSIO_USB_19 VSS_39 AA12
+3VALW
93mA H16 VSSIO_USB_20 VSS_40 G4
+1.1VS_SATA
AD14 VDDPL_33_SATA 32mA H18 VSSIO_USB_21 VSS_41 J4
L71 A21 J11 G8
VDDIO_33_S_1 VSSIO_USB_22 VSS_42
+1.1VS 2 1 AJ20 VDDAN_11_SATA_1 VDDIO_33_S_2 D21 J19 VSSIO_USB_23 VSS_43 G9
FBMA-L11-201209-221LMA30T_0805 567mA AF18 B21 2.2U_0603_6.3V4Z 1 2 C608 K12 M12
VDDAN_11_SATA_4 VDDIO_33_S_3 VSSIO_USB_24 VSS_44
SERIAL ATA
AH20 K10 2.2U_0603_6.3V4Z 1 2 C609 K14 AF25
C610 22U_0805_6.3V6M VDDAN_11_SATA_2 VDDIO_33_S_4 VSSIO_USB_25 VSS_45
1 2 AG19 L10 K16 H7
3.3V_S5 I/O
C611 1U_0402_6.3V4Z VDDAN_11_SATA_3 VDDIO_33_S_5 VSSIO_USB_26 VSS_46
1 2 AE18 J9 K18 AH29
C612 1U_0402_6.3V4Z VDDAN_11_SATA_5 VDDIO_33_S_6 +1.1VALW VSSIO_USB_27 VSS_47
1 2 AD18 T6 H19 V10
C613 0.1U_0402_16V4Z VDDAN_11_SATA_6 VDDIO_33_S_7 VSSIO_USB_28 VSS_48
1 2 AE16 T8 P6
C614 0.1U_0402_16V4Z VDDAN_11_SATA_7 VDDIO_33_S_8 VSS_49
1 2 VSS_50
N4
Y4 L4
C615 2 EFUSE VSS_51
check 220ohm bead 113mA 1 1U_0402_6.3V4Z VSS_52
L8
L72 +AVDD_USB C616 2 1 1U_0402_6.3V4Z
658mA
CORE S5
F26 D8
VDDCR_11_S_1 VSSAN_HWM
+3VALW 2 1 A18 G26
FBMA-L11-201209-221LMA30T_0805 VDDAN_33_USB_S_1 VDDCR_11_S_2
A19
VDDAN_33_USB_S_2 TBD M19
VSSXL VSSPL_SYS
M20
A20 M8 +VDDIO_AZ
C617 10U_0805_10V4Z VDDAN_33_USB_S_3 VDDIO_AZ_S +1.1VALW
1 2 B18
C618 10U_0805_10V4Z VDDAN_33_USB_S_4 +VDDCR_USB
1 2 B19
VDDAN_33_USB_S_5 VDDCR_11_USB_S_1
A11 197mA P21
VSSIO_PCIECLK_1 VSSIO_PCIECLK_14
H23
C619 1 2 1U_0402_6.3V4Z B20 B11 2 1 P20 H26
VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 VSSIO_PCIECLK_2 VSSIO_PCIECLK_15
USB I/O
L81
4 4
2 1 1 2
FBMA-L11-160808-221LMT 0603 R376 0_0402_5%
1 1 1
C636
C637 C638
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2 2
For 3V AZ device
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/04/12 Deciphered Date 2010/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB820 power/GND
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 21 of 45
A B C D E
A B C D E
PULL LOW POWER ALLOW PCIE WATCHDOG USE Inter CLK EC CLOCKGEN
MODE GEN2 TIMER DEBUG Gen Mode ENABLE ENABLE H,H = Reserved
HIGH
ENABLE STRAP Enable
1 H,L = SPI ROM 1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
R385
R377
R378
R379
R380
R381
R382
R383
R384
2
2
@ @ @ @ @ @
<19> HDA_SDOUT
<18> PCI_CLK1
<18> PCI_CLK2
<18> PCI_CLK3
<18> PCI_CLK4
<18,28> LPC_CLK0_EC
<18> LPC_CLK1
<19> GPIO200
2 <19> GPIO199 2
2.2K_0402_5%
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
R393
R394
R386
R387
R388
R389
R390
R391
R392
@ @ @
2
2
+3VS +3VS
DEBUG STRAPS
10K_0402_5%
10K_0402_5%
1
1
R395
R396
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
3 3
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
2
USE PCI DISABLE ILA USE FC PLL USE DEFAULT DISABLE PCI <18> PCI_AD29
PULL PLL AUTORUN PCIE STRAPS MEM BOOT <18> PCI_AD28
HIGH <18> PCI_AD27
<18> PCI_AD26
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
<18> PCI_AD25
<18,20> PCI_AD24
<18> PCI_AD23
PULL BYPASS ENABLE ILA BYPASS USE EEPROM ENABLE PCI
LOW PCI PLL AUTORUN FC PLL PCIE STRAPS MEM BOOT
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R397
R398
R399
R400
R401
2
2
Check AD29,AD28 strap function @ @ @ @ @
check default
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB820 STRAPS
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 22 of 45
A B C D E
A B C D E F G H
1
SATA HDD Conn. 1
JHDD1
1
C656 1 SATA_STX_C_DRX_P0 GND
<20> SATA_STX_DRX_P0 2 0.01U_0402_16V7K 2
C658 1 SATA_STX_C_DRX_N0 A+
<20> SATA_STX_DRX_N0 2 0.01U_0402_16V7K 3
A-
4
C657 1 SATA_DTX_SRX_N0 GND
<20> SATA_DTX_C_SRX_N0 2 0.01U_0402_16V7K 5
C659 1 SATA_DTX_SRX_P0 B-
<20> SATA_DTX_C_SRX_P0 2 0.01U_0402_16V7K 6
B+
7 GND
+3VS
+3VS 8 V33
1 9 V33
C639 10 V33
11 GND
0.1U_0402_16V4Z 12
2 GND
13 GND
14 V5
15 V5
R405 1 2 0_0805_5% +5VS_HDD 16
+5VS V5
17 GND
18 Reserved
10U_0805_10V4Z 0.1U_0402_16V4Z 19 GND
20 V12
1 1 1 1 21 V12 GND 24
C660 C661 C662 C663 22 23
V12 GND
2 2 2 2 SANTA_192301-1
2 CONN@ 2
1U_0402_6.3V4Z 1000P_0402_50V7K
<NAV70 use>
JODD1
1
C648 1 SATA_STX_C_DRX_P1 1
<20> SATA_STX_DRX_P1 2 0.01U_0402_16V7K 2
C649 1 SATA_STX_C_DRX_N1 2
<20> SATA_STX_DRX_N1 2 0.01U_0402_16V7K 3
3
4
C650 1 SATA_DTX_SRX_N1 4
<20> SATA_DTX_C_SRX_N1 2 0.01U_0402_16V7K 5
5
C651 1 2 0.01U_0402_16V7K SATA_DTX_SRX_P1 6
<20> SATA_DTX_C_SRX_P1 6
7
R403 1 @ 7
2 1K_0402_1% 8
8
9
3 9 3
10
10
11 13
11 GND
+5VS 12 14
12 GND
80mils
ACES_85201-1205N
CONN@
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 23 of 45
A B C D E F G H
A B C D
+3V_LAN
R800
60mil
+3VALW 1 2
0_1206_5%
2 1
C902
C901
4.7U_0805_10V4Z
U70 1 2
0.1U_0402_16V4Z
+3V_LAN 42 25 +LAN_BIASVDDH
VDDC BIASVDDH
1 1
35 LAN_MIDI2-
TRD2_N LAN_MIDI2- <25> +3V_LAN
34 LAN_MIDI2+
TRD2_P LAN_MIDI2+ <25>
+LAN_GPHYPLLVDDL 24 C906 1 2 0.1U_0402_16V4Z
GPHY_PLLVDDL
31 LAN_MIDI1- @
TRD1_N LAN_MIDI1- <25>
2
32 LAN_MIDI1+ R802 R803
TRD1_P LAN_MIDI1+ <25>
1K_0402_1% 1K_0402_1%
+LAN_PCIEPLLVDD 18 @
PCIE_PLLVDDL LAN_MIDI0- U71 @
29 LAN_MIDI0- <25>
1
TRD0_N
21 PCIE_PLLVDDL 8 VCC A0 1
28 LAN_MIDI0+ 7 2
TRD0_P LAN_MIDI0+ <25> WP A1
SPROM_CLK 6 3
SPROM_DOUT SCL NC
5 SDA GND 4
AT24C02_SO8
2
2 2
1
PCIE_TXD_N SPD1000LED#
<12> PCIE_ITX_C_PRX_P0 22 PCIE_RXD_P
<12> PCIE_ITX_C_PRX_N0 23 PCIE_RXD_N TRAFFICLED# 45 2 1 LAN_ACTIVITY# <25>
LAN_PME# 4 R805
WAKE# 0_0402_5%
LAN_RESET# 2 REST#
20 PCIE_REFCLK_P
R806 1 @ 2 0_0402_5% 19
<19,26> SB_PCIE_W AKE# PCIE_REFCLK_N
<28> EC_PME# R807 1 2 0_0402_5%
+3V_LAN R808 1 2 4.7K_0402_5%
R809 1
20mil
<18,26> PLT_RST# 2 0_0402_5% L100
5 +LAN_XTALVDDH 1 1 2 +3V_LAN
MODE C909 BLM18AG601SN1D_2P
<18> CLK_PCIE_LAN
0.1U_0402_16V4Z
<18> CLK_PCIE_LAN#
2
20mil L101
43 SPROM_DOUT +LAN_BIASVDDH 1 1 2
EEDATA C910 BLM18AG601SN1D_2P
44 SPROM_CLK
R810 1 EECLK
+3VS 2 1K_0402_5% 40 VMAIN_PRSINT
0.1U_0402_16V4Z
2
R813 1
20mil
2 10K_0402_5% 1 LOW_PWR
L102
+LAN_AVDDH
1 1 1 2
L103
C911 C912 BLM18AG601SN1D_2P
11 +1.2V_LAN_OUT 1 2 +1.2V_LAN
SR_LX 4.7UH_PG031B-4R7MS_1.1A_20% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
LAN_XTALO_R 2 2
3
T12 PAD 13 XTALO SR_VFB 8 1 1 3
C913
LAN_XTALI 12 C914 20mil
T13 PAD XTALI 0.1U_0402_16V4Z 10U_0805_10V4Z L104
2 2 +LAN_PCIEPLLVDD 1 2 +1.2V_LAN
1 2 BLM18AG601SN1D_2P
R814
C915
1 2 LAN_RDAC 26 C916
RDAC 0.1U_0402_16V4Z 4.7U_0805_10V4Z
SR_VDDP 10 +3V_LAN 2 1
1.24K_0402_1% 1 1
9 C917 C918
SR_VDD
2 2 20mil L105
<19> LAN_CLKREQ# 3 CLKREQ# 4.7U_0603_6.3V6K 0.1U_0402_16V4Z +LAN_GPHYPLLVDDL 1 2 +1.2V_LAN
7 1 2 BLM18AG601SN1D_2P
NC C919
C920
PAD
0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 1
49
4
R815 4
200_0402_1%
Y5
2
1 2 LAN_XTALO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 24 of 45
A B C D
5 4 3 2 1
D D
BH GS5009-D <SP050006B00>
LAN Connector
JRJ45
T25 12
<24> LAN_ACTIVITY# Yellow LED-
1 TCT1 MCT1 24 +3V_LAN 2 1 11 Yellow LED+
<24> LAN_MIDI0+ LAN_MIDI0+ 2 23 RJ45_MIDI0+ R823 1K_0402_5%
LAN_MIDI0- TD1+ MX1+ RJ45_MIDI0- RJ45_MIDI3-
<24> LAN_MIDI0- 3 TD1- MX1- 22 1 2 8 PR4-
C938 220P_0402_50V7K
4 21 RJ45_MIDI3+ 7
LAN_MIDI1+ TCT2 MCT2 RJ45_MIDI1+ PR4+
<24> LAN_MIDI1+ 5 TD2+ MX2+ 20
<24> LAN_MIDI1- LAN_MIDI1- 6 19 RJ45_MIDI1- RJ45_MIDI1- 6
TD2- MX2- PR2-
7 18 RJ45_MIDI2- 5
LAN_MIDI2+ TCT3 MCT3 RJ45_MIDI2+ PR3-
<24> LAN_MIDI2+ 8 TD3+ MX3+ 17
<24> LAN_MIDI2- LAN_MIDI2- 9 16 RJ45_MIDI2- RJ45_MIDI2+ 4
TD3- MX3- PR3+
10 15 RJ45_MIDI1+ 3
LAN_MIDI3+ TCT4 MCT4 RJ45_MIDI3+ PR2+ @
<24> LAN_MIDI3+ 11 TD4+ MX4+ 14
<24> LAN_MIDI3- LAN_MIDI3- 12 13 RJ45_MIDI3- RJ45_MIDI0- 2 R413 0_0805_5%
TD4- MX4- PR1-
SHLD2 13 2 1
RJ45_MIDI0+ 1 14
C PR1+ SHLD1 C
2
350UH_IH-037-2 10
<24> LAN_LINK# Green LED- R412
1 1 1 1 R819 R820 +3V_LAN 2 1 9 0_0805_5%
C928 C929 C930 C931 75_0402_1% 75_0402_1% R824 1K_0402_5% Green LED+
@
1 2 SANTA_130451-K
1
1
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z C942 220P_0402_50V7K CONN@
2 2 2 2
R821 R822
0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1%
RJ45_GND 1 2 LANGND 40mil
2
1 2
RJ45_GND C940
Place close to TCT pin 1000P_1206_2KV7K C941 C939
40mil 4.7U_0805_10V4Z
2 1
LAN_ACTIVITY# 0.1U_0402_16V4Z
LAN_LINK#
2
D40
LAN_ACTIVITY# 1 2
PJDLC05_SOT23-3 C943 220P_0402_50V7K
@
LAN_LINK# 1 2
C944 220P_0402_50V7K
B B
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 25 of 45
5 4 3 2 1
A B C D E
1 1 1 1 1 1
C705 C706 C707 C708 C709 C710
1 1
JMINI1
SB_PCIE_WAKE# R440 1 @ 2 0_0402_5% 1 2 +3VS
<19,24> SB_PCIE_WAKE# 1 2
3 4
3 4
5 6 +1.5VS
5 6
<19> MINI1_CLKREQ# 7
7 8
8 Mini Card Power Rating
9 10
9 10
<18> CLK_PCIE_MINI1# 11
11 12
12 Power Primary Power (mA) Auxiliary Power (mA)
<18> CLK_PCIE_MINI1 13 14
13 14
15
15 16
16 Peak Normal Normal
+3VS 1000 750
17 17 18 18
19 20 WL_OFF# +3V 330 250 250 (wake enable)
19 20 PLT_RST# WL_OFF# <28>
21 21 22 22 PLT_RST# <18,24>
23 24 +3V_WLAN 1 2 +1.5VS 500 375 5 (Not wake enable)
<12> PCIE_PTX_C_IRX_N1 23 24 +3VS
25 26 R441 1 2 0_0603_5% +3VALW
<12> PCIE_PTX_C_IRX_P1 25 26
27 28 R442 @ 0_0603_5%
27 28 MINI1_SMBCLK @
29 29 30 30 1 2 SB_SMDAT0 <10,11,19>
<12> PCIE_ITX_C_PRX_N1 31 32 MINI1_SMBDAT R443
1 @ 0_0603_5%
2
31 32 SB_SMCLK0 <10,11,19>
<12> PCIE_ITX_C_PRX_P1 33 34 R444 0_0603_5%
33 34
35 35 36 36 USB20_N8 <19>
37 37 38 38 USB20_P8 <19>
+3VS 39 39 40 40
41 42 (MINI1_LED#) WIMAX_LED#
41 42 WLAN_LED#_L +3VS
43 43 44 44
45 45 46 46
0_0402_5% 47 48
47 48
1
R445 1 2 E51TXD_P80DATA_R 49 50
<28> E51TXD_P80DATA 49 50
E51RXD_P80CLK 51 52 0_0402_5%
<28> E51RXD_P80CLK 51 52 R835 1 2 R848
2 +3VS 100K_0402_5% 2
G1
G2
G3
G3
2
2
ACES_88910-5204
53
54
55
56
R492 CONN@ WIMAX_LED# 2
100K_0402_5% 1 MINI1_LED# <28>
1 @ 2 WLAN_LED#_L 3
<NAV70 use> R836 10K_0402_5% (9~16mA)
1
CHP202UPT_SOT323-3
D44 @
Height : 4mm 1 2
R837 0_0402_5%
3 3
+3VS +3VS_CR
30mil
R854 1 2 0_0805_5%
2 1 10mil +SDPWR_MMCPWR
C981 100P_0402_50V8J U84 5IN1_LED#
5IN1_LED# <29>
R855 1 2 RREF 1
6.2K_0603_1% REFE @ C982 1
17 1 2 2 10P_0402_50V8J JCR1
USB20_N6 GPIO0 R856 10_0402_5% @ XDD4_SDD3_MSD1
<19> USB20_N6 2 1
USB20_P6 DM CLK_SD_48M_R XDD2_SDCMD D3
<19> USB20_P6 3 24 2 1 CLK_SD_48M <18> 2
DP CLK_IN R857 0_0402_5% CMD
3
+3VS_CR VSS1
4 23 4
+CARDPWR 3V3_IN XD_D7 XDD0_SDCLK_MSD2 VDD
30mil VREG
5
CARD_3V3
5
CLK
1 2 6 22 6
C984 V18 SP14 XDD5_SDD2_MS_D5 VSS2
C983
1
C985
10mil SP13
21
XDD4_SDD3_MSD1 +CARDPWR +SDPWR_MMCPWR XDCLE_SDD0
7 20 7
4.7U_0805_10V4Z 1U_0402_6.3V6K XD_CD# SP12 XDCE#_SDD1 D0
19 8
2 1 XDDRY_SDWP_MSCLK SP11 XDD2_SDCMD XDD5_SDD2_MS_D5 D1
2
8
SP1 SP10
18 30mil 30mil XDDRY_SDWP_MSCLK
9
D2
0.1U_0402_16V4Z 9 16 1 2 10
XDCE#_SDD1 SP2 SP9 XDD0_SDCLK_MSD2 R858 0_0805_5% XDWE#_SDCD# WP
10 15 11
SP3 SP8 CD
EPAD
XDCLE_SDD0 11 14
SP4 SP7
2
12 13 XDWE#_SDCD# @ 1 1 1
SP5 SP6
RTS5138-GR_QFN24_4X4 R859 C986 C987 C988
25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD / CardReader RTS5137
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 26 of 45
A B C D E
A B C D E
+3VALW
1
+USB_VCCA +USB_VCCA
U24 80mil R446
1
1 8 100K_0402_5% 1
GND VOUT + C711
2 7
VIN VOUT C712
3 6
2
VIN VOUT R447 1
1 4 5 2 10K_0402_5% USB_OC#0 <19>
220U_6.3V_M
2
1 C713 EN FLG 2 1
RT9715BGS_SO8 470P_0402_50V7K
W=80mils
4.7U_0805_10V4Z 1
2 C714
0.1U_0402_16V4Z
1 2
2 R448 @ 0_0402_5%
<33> SYSON#
1
+USB_VCCB R449 @ USB20_P0_R 3
U25 0_0402_5% USB20_P0 3
80mil <19> USB20_P0 4 4 3 3 4 4 <NAL00 use>
1 8 R450 1 2 5
GND VOUT USB_OC#2 <19> GND
2 7 100K_0402_5% WCM2012F2S-900T04_0805 6
VIN VOUT GND
3 6 7
2
VIN VOUT GND
1 4 EN FLG 5 1 2 USB_OC#1 <19> 8 GND
C715 R452 1 2
RT9715BGS_SO8 10K_0402_5% 1 R451 @ 0_0402_5% SUYIN_020133MB004S580ZL-C
4.7U_0805_10V4Z C716 CONN@
2
0.1U_0402_16V4Z
2
SYSON#
D10
USB20_N0_R 4 3 USB20_P0_R
2 2
+USB_VCCA 5 2
To USB/B Connector 6 1
PJUSB208_SOT23-6
ESD Change P/N SC300000B00 For DVT
+USB_VCCB
(Port 1,2)
JUSB2
1
1
2
2
3
3
4
4
5
5 USB20_N1
6 USB20_N1 <19>
6 USB20_P1
7 USB20_P1 <19>
7
8
8 USB20_N2
9
9 USB20_P2 USB20_N2 <19>
10
10 USB20_P2 <19>
13 11
GND 11
14 12
GND 12
ACES_85201-1205N
CONN@
+3VALW +3VS
3
<NAL00 use> Bluetooth Conn. 3
1 BT@
C718 C719
BT@
0.1U_0402_16V4Z BT@ 1U_0402_6.3V4Z
3
2
S
G Q24
1 BT@ 2 2
<28> BT_ON#
R453 10K_0402_5%
D AO3413_SOT23-3
1
C720 W=40mils
BT@ +BT_VCC
0.1U_0402_16V4Z
1
1
C721 BT@ C722 BT@ BT@
R454
+BT_VCC 4.7U_0805_10V4Z 300_0603_5%
2 0.1U_0402_16V4Z
JBT1
2
10 8
GND 8 BT@
7
7
1
D
6 USB20_P7 <19>
6 Q25
5 USB20_N7 <19> 2
5 G 2N7002_SOT23
4
4
3 S
3
3
2
2
9 1
GND 1
ACES_87213-0800G
CONN@
4 4
<NAL00 use>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BlueTooth / Int USB x2 /eSATA
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 27 of 45
A B C D E
5 4 3 2 1
2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2+EC_VCCA +3VALW
1 1 C725 1 1 2 2
1
BLM18AG601SN1D_2P R109 JP7 Place on MiniCard door
C724 1 0_0402_5% 1
C726 C727 C728 C729 1 E51RXD_P80CLK
@ 2 2 E51RXD_P80CLK <26>
1000P_0402_50V7K 1000P_0402_50V7K C730 3 E51TXD_P80DATA
E51TXD_P80DATA <26>
1
KSO[0..17] 2 2 2 2 1 1 MB_SL 3
KSO[0..17] <29> 4 4
2
ECAGND
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2
KSI[0..7] ACES_85205-0400
KSI[0..7] <29>
@
D R491 D
+3VALW
111
125
4.7K_0402_5%
22
33
96
67
1
9
U26 65W /90W # 2 1
R458 100K_0402_5%
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
VR_ON 2 1
R459 100K_0402_5%
3S/4S# 1 2
EC_GA20 1 21 R460 4.7K_0402_5%
<19> EC_GA20 EC_KBRST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP#
<19> EC_KBRST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# <30>
SERIRQ 3 26
<18> SERIRQ LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF
<18> LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF <37,40>
C732 LPC_AD3 5 2 1 ECAGND
<18> LPC_AD3 LAD3
@ 22P_0402_50V8J @ LPC_AD2 7 PWM Output C731 0.01U_0402_16V7K
<18> LPC_AD2 LAD2
2 1 2 1 LPC_AD1 8 63 BATT_TEMP
<18> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <35>
R461 33_0402_5% LPC_AD0
<18> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
Analog Project ID definition
ADP_I/AD2/GPIO3A 65 ADP_I <37>
LPC_CLK0_EC 12 AD Input 66 AD_BID0 +3VALW
<18,22> LPC_CLK0_EC PCICLK AD3/GPIO3B
13 75 AD_PID0
<13,14,18> A_RST# PCIRST#/GPIO05 AD4/GPIO42 Project_ID : 0-> NEW75/85/95
37 76 MB_SL
ECRST# SELIO2#/AD5/GPIO43
2
EC_SCI# 20 1-> PEW76/86/96
<19> EC_SCI# SCI#/GPIO0E 2-> PEW56(BA51)
+3VALW 2 1 1 2 38 R463
<18> CLKRUN# CLKRUN#/GPIO1D
R462 47K_0402_5% @
DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG
DAC_BRIG <15> Ra
2 1 R99 0_0402_5% 70 EN_DFAN1 100K_0402_5%
EN_DFAN1/DA1/GPIO3D EN_DFAN1 <32>
C733 0.1U_0402_16V4Z DA Output 71 IREF
IREF <37>
1
IREF/DA2/GPIO3E
2
+5VS KSI0 55 72 CALIBRATE# AD_PID0
KSI0/GPIO30 DA3/GPIO3F CALIBRATE# <37>
KSI1 56 KSI1/GPIO31
2
@ KSI2 57 1
KSI2/GPIO32
1 2 TP_CLK R489 KSI3 58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE#
EC_MUTE# <31> Rb R464 C734
C R465 4.7K_0402_5% 4.7K_0402_5% KSI4 59 84 C
1
1
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK <29>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <29>
KSO1 40
+3VALW +3VS KSO2 KSO1/GPIO21
41 KSO2/GPIO22
For PVT 0602 KSO3 42 97 3S/4S#
KSO3/GPIO23 SDICS#/GPXOA00 3S/4S# <37>
KSO4 43 98 65W /90W # Analog Board ID definition
KSO4/GPIO24 SDICLK/GPXOA01 65W /90W # <37>
KSO5 VLDT_EN
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 VLDT_EN <33,39>
2
2
KSO9 48 119 0_0402_5% @ 1-> wo/ pach code
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO <29>
KSO10 49 120 R469
EC_SO_SPI_SI <29>
1
KSO10/GPIO2A SPIDO/WR#
1 2 EC_SMB_CK2 KSO11 50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 1 2 EC_SPICLK <29> Ra
R467 2.2K_0402_5% KSO12 51 128 100K_0402_5%
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# <29>
1 2 EC_SMB_DA2 KSO13 52
1
R468 2.2K_0402_5% KSO14 KSO13/GPIO2D C783 AD_BID0
53 KSO14/GPIO2E
KSO15 54 73 33P_0402_50V8K
KSO15/GPIO2F CIR_RX/GPIO40
2
+3VALW KSO16 81 74
KSO16/GPIO48 CIR_RLC_TX/GPIO41 @ 1
KSO17 82 89 R470 C735
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <37> Rb
1 2 EC_SMB_CK1 90 BATT_BLUE_LED#
BATT_CHGI_LED#/GPIO52 BATT_BLUE_LED# <29>
R471 2.2K_0402_5% 91 8.2K_0402_5% 0.1U_0402_16V4Z
EC_SMB_DA1 EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_AMB_LED# 2
1 2 <35> EC_SMB_CK1 77 GPIO 92
1
R472 2.2K_0402_5% EC_SMB_DA1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 PW R_LED BATT_AMB_LED# <29>
<35> EC_SMB_DA1 78 SDA1/GPIO45 SUSP_LED#/GPIO55 93 PW R_LED <29>
1 2 KSO1 EC_SMB_CK2 79 SM Bus 95 SYSON Reserve for EMI, close to EC
<8> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <33,38>
R473 47K_0402_5% EC_SMB_DA2 80 121 VR_ON
<8> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <39,42>
1 2 KSO2 127 ACIN
B R474 47K_0402_5% AC_IN/GPIO59 ACIN <33,37> B
2 1 LID_SW #
R475 100K_0402_5% PM_SLP_S3# 6 100 EC_RSMRST# +3VS
<19> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <19>
1 @ 2 EC_PME# PM_SLP_S5# 14 101 EC_LID_OUT#
<19> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <19>
R476 10K_0402_5% EC_SMI# 15 102 EC_ON
<19> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <32,36> EC_REV : 1-> D3
2 1 PBTN_OUT# LOCAL_DIM 16 103 EC_SW I# EC_REV 2 @ 1
<15> LOCAL_DIM LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SW I# <19> 0-> E0
R497 100K_0402_5% MINI1_LED# 17 104 EC_PW ROK R838 100K_0402_5%
<26> MINI1_LED# SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF#
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# <15> 2 1
COLOY_ENG_EN 19 GPIO 106 W L_OFF# R839 100K_0402_5%
<15> COLOY_ENG_EN EC_PME#/GPIO0D WL_OFF#/GPXO09 W L_OFF# <26>
For LED INV_PWM freq to 1K EC_INVT_PW M 25 107 EC_REV
<15> EC_INVT_PW M EC_THERM#/GPIO11 GPXO10
FAN_SPEED1 28 108 VGA_ON <33,41> Delay SUSP# 10ms
ENBKL <32> FAN_SPEED1 BT_ON# FAN_SPEED1/FANFB1/GPIO14 GPXO11
2 1 <27> BT_ON# 29 FANFB2/GPIO15
R488 100K_0402_5% E51TXD_P80DATA 30
LOCAL_DIM E51RXD_P80CLK EC_TX/GPIO16 VGATE
2 1 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 VGATE <42>
R844 100K_0402_5% ON/OFF 32 112 ENBKL
<32> ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <13>
2 1 COLOY_ENG_EN <29> PW R_SUSP_LED PW R_SUSP_LED 34 114 EAPD
PWR_LED#/GPIO19 GPXID3 EAPD <30>
R845 100K_0402_5% W LAN_LED# 36 GPI 115 EC_THERM# EC_PW ROK 1 2
<29> W LAN_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# <20> SB_PW RGD <8,13,19>
116 SUSP# R254 0_0402_5%
GPXID5 SUSP# <33>
For Low PWR panel use 117 PBTN_OUT#
GPXID6 EC_PME# PBTN_OUT# <19>
GPXID7 118 EC_PME# <24>
EC_CRY1 122
EC_CLK 1 EC_CRY2 XCLK1
<18> EC_CLK 2 123 XCLK0 V18R 124
R888 0_0402_5% 1
AGND
@ C736
GND
GND
GND
GND
GND
KB926QFB1_LQFP128_14X14 2
11
24
35
94
113
69
OSC
15P_0402_50V8J 1 1 BLM18AG601SN1D_2P
<BOM Structure>
NC
NC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB926
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Monday, June 14, 2010 Sheet 28 of 45
5 4 3 2 1
To TP/B Conn. +5VS
JTP1
1 1
2 +5VS
2 TP_CLK <28>
+3VALW 1 2 C742 1 2 0.1U_0402_16V4Z 3
3 LEFT_BTN# TP_DATA <28>
R479 0_0603_5% 4
4 RIGHT_BTN# C745
5
+SPI_VCC 5
6
6 0.1U_0402_16V4Z
7
U27 GND
<28> EC_SPICS#/FSEL# 8
EC_SPICS#/FSEL# GND
1 8
CS# VCC
R480 1 2 4.7K_0402_5% SPI_WP# 3
WP# SCLK
6 EC_SPICLK_R R481 1 2 0_0402_5% EC_SPICLK <28>
ACES_85201-0605N
+3VALW R482 1 2 4.7K_0402_5% SPI_HOLD# 7 5 EC_SO_SPI_SI <28>
CONN@
HOLD# SI
4 2 EC_SI_SPI_SO <28>
GND SO
MX25L1605DM2I-12G SOP 8P RIGHT_BTN# TP_CLK
SA00002TO00 SW1 SW2
SMT1-05-A_4P SMT1-05-A_4P LEFT_BTN# TP_DATA
LEFT_BTN# 3 1 RIGHT_BTN# 3 1
2
4 2 4 2 D11 D13
5
6
5
6
PJDLC05C_SOT23-3
PJDLC05C_SOT23-3
1
JLED1
1 1 +3VALW
2 LID_SW#
2 LID_SW# <28>
3 WLAN_LED# WLAN_LED# <28>
3 MEDIA_LED#
4 4
5 5 +3VS
6 PWR_LED#
JKB1
INT_KBD Conn. 6
7 7
8
ON/OFFBTN#
ON/OFFBTN# <32>
8
GND 9
KSO0 26 28 10
KSO1 KSO0 G2 GND
25 27
KSO2 KSO1 G1 ACES_85201-08051
24
KSO3 KSO2 KSI[0..7] CONN@
23 KSI[0..7] <28>
KSO4 KSO3
22
KSO5 KSO4 KSO[0..17]
21 KSO[0..17] <28>
KSO6 KSO5
20
KSO7 KSO6
19
KSO8 KSO7
18
KSO9 KSO8
17
KSO10 KSO9
16
KSO11 KSO10
15
KSO12 KSO11
14
KSO13 KSO12 +3VS
13
KSO13 Pop R486 for RTS5137
KSO14 12
KSO15 KSO14
11
KSO15
2
KSO16 10 +3VS
KSO17 KSO16 R486
9
KSI0 KSO17
8
KSI1 KSI0 100K_0402_5%
7
KSI1
5
KSI2 6 U29
1
KSI3 KSI2
5 2
P
KSI4 KSI3 MEDIA_LED# B 5IN1_LED# <26>
4 4
KSI5 KSI4 Y
3 1 SATA_LED# <20>
KSI5 A
G
KSI6 2
KSI7 KSI6 NC7SZ08P5X_NL_SC70-5
1
3
KSI7
KSO16 C747 1 2 100P_0402_50V8J
ACES_88747-2601 @ PWR_LED#
CONN@ KSO17 C748 1 2 100P_0402_50V8J
6
@ LED1
KSO15 C749 1 2 100P_0402_50V8J KSO7 C750 1 2 100P_0402_50V8J HT-191NB5_BLUE
@ @
KSO14 C751 1 2 100P_0402_50V8J KSO6 C752 1 2 100P_0402_50V8J 2 DMN66D0LDW-7_SOT363-6 1 2 2 1 PWR_LED#
<28> PWR_LED +3VS
@ @ Q26A R477 2.2K_0402_5% B
2
KSO13 C753 1 2 100P_0402_50V8J KSO5 C754 1 2 100P_0402_50V8J
1
@ @ R487
KSO12 C755 1 2 100P_0402_50V8J KSO4 C756 1 2 100P_0402_50V8J 100K_0402_5% LED2
@ @ 1 HT-191UD5_AMBER
R499 2.2K_0402_5% B
KSI2 C765 1 2 100P_0402_50V8J KSO0 C766 1 2 100P_0402_50V8J
@ @
KSO9 C767 1 2 100P_0402_50V8J KSI5 C768 1 2 100P_0402_50V8J 5 DMN66D0LDW-7_SOT363-6 LED4
<28> PWR_SUSP_LED
@ @ Q26B HT-191UD5_AMBER
2
For PVT 0608 Unpop Cap. Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/04/12 Deciphered Date 2010/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 29 of 45
A B C D E F G H
1 2
R784 0_0805_5%
+3VS +VDDA
+5VAMP
U81
60mil 40mil
1
+5VS L87 1 2 1 IN
1
R783
OUT 5 +VDDA 4.75V
C678
C899
C947
D38 20K_0402_1% FBMA-L11-201209-221LMA30T_0805 2
R789 L88 1 GND
2 1 1 1
CH751H-40PT_SOD323-2 10K_0402_5% 3 4 1 2
2
1 C936 FBMA-L11-201209-221LMA30T_0805 SHDN BYP C949 1
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2 MONO_IN @ @ G9191-475T1U_SOT23-5 0.01U_0402_25V7K
1U_0402_6.3V4Z 2 2 2
1
R786
2 HD Audio Codec (output = 300 mA)
1
C 2.4K_0402_1%
C952 1 R787 Q72
<28> BEEP# 2 1 2 2
1U_0402_6.3V4Z B
560_0402_5% E
3
2SC2411KT146_SOT23-3
C946 1 R788
2 1 2
<19> SB_SPKR 1U_0402_6.3V4Z
1
560_0402_5%
D37
CH751H-40PT_SOD323-2
L82
2 10mil BLM18AG601SN1D_2P
0.1U_0402_16V4Z +3VS_DVDD 1 2 +3VS MIC2_VREFO
1 1 1
C933 C953 C926
+AVDD_HDA
1
10U_0805_10V4Z
L86 2 2 2 R585
1 2 0.1U_0402_16V4Z
40mil 2.2K_0402_5%
+VDDA
BLM18AG601SN1D_2P 1 1 1 0.1U_0402_16V4Z
C935 C945
2
C950 Close to Conn
2 10U_0805_10V4Z INT_MIC 2
25
38
9
2 2 2 U82
0.1U_0402_16V4Z 1
DVDD_IO
AVDD1
AVDD2
DVDD
C808
220P_0402_50V7K
AMP_LEFT 2
14 LINE2_L LOUT1_L 35 AMP_LEFT <31>
15 36 AMP_RIGHT
LINE2_R LOUT_R AMP_RIGHT <31>
C794 4.7U_0805_10V4Z
1 2 MIC2_C_L 16 39
INT_MIC MIC2_L LOUT2_L
2 1INT_MIC_2 0_0603_5% R849 JMIC2
R523 1K_0402_1% 1 2 MIC2_C_R 17 41 INT_MIC 1 2 1
C797 4.7U_0805_10V4Z MIC2_R LOUT2_R 1
15mil 1 2 2
2
23 45 0_0603_5% R850
LINE1_L SPDIFO2
1 1
24 46 DMIC_CLK 220P_0402_50V7K 220P_0402_50V7K 3
LINE1_R DMIC_CLK1/2 DMIC_CLK <15> G1
4
G2
2
18 43 C979 C980
LINE1_VREFO NC 2 2 ACES_88266-02001
20
LINE2_VREFO DMIC_CLK3/4
44 1 2 1 2 C948 CONN@
R792 0_0402_5% 22P_0402_50V8J For EMI
MIC2_VREFO 19
4.7U_0805_10V4Z MIC2_VREFO
6 HDA_BITCLK_AUDIO <19>
MIC1_L C934 1 MIC1_C_L BITCLK
<31> MIC1_L 2 21
MIC1_L
MIC1_R 1 2 MIC1_C_R 22 8 1 2 D27 @
<31> MIC1_R HDA_SDIN0 <19>
1
C932 4.7U_0805_10V4Z MIC1_R SDATA_IN R793 33_0402_5% PJDLC05C_SOT23-3
MONO_IN 12 37
PCBEEP_IN MONO_OUT
29
CBP C951 2.2U_0805_10V6K
<19> HDA_RST_AUDIO# 11
3 RESET# 3
31 1 2
CPVEE
<19> HDA_SYNC_AUDIO 10
SYNC 10mil 2
28 MIC1_VREFO
MIC1_VREFO C954 HP_RIGHT
<19> HDA_SDOUT_AUDIO 5 HP_RIGHT <31>
SDATA_OUT HP_RIGHT
32 2.2U_0805_10V6K
DMIC_DATA HPOUT_R 1 HP_LEFT
<15> DMIC_DATA 2 HP_LEFT <31>
GPIO0/DMIC_DATA1/2
3 30
R794 2 SENSE_A GPIO1/DMIC_DATA3/4 CBN
<31> MIC_PLUG# 1 20K_0402_1% 13
SENSE A 10mil
R795 2 1 5.11K_0402_1% SENSE_B 34 27 CODEC_VREF
<31> HP_PLUG# SENSE B VREF
1 1
10U_0805_10V4Z
0.1U_0402_16V4Z
1 2 47 40
<28> EAPD EAPD JDREF
20K_0402_1%
C927
C937
R796 0_0402_5%
1
48 33 HP_LEFT
SPDIFO1 HPOUT_L 2 2
R797
4 26
DVSS1 AVSS1
7 42 J4
DVSS2 AVSS2 J1
2
ALC272-VA2-GR_LQFP48_7X7 1 2 1 2
1 2 1 2
Change to ALC272X
JUMP_43X39 @ JUMP_43X39 @
DGND AGND J2 J5
1 1
2 2
1 1
2 2
ALC272X JUMP_43X39 @ JUMP_43X39 @
J3 J6
Sense Pin Impedance Codec Signals Function 1
1 2 2
1 1
2 2
39.2K PORT-A (PIN 39, 41) LOUT2 JUMP_43X39 @ JUMP_43X39 @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC272X
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 30 of 45
A B C D E F G H
A B C D E
2
1
1
D39
16
15
3
G1
6
U83 R827 @ R829 4
100K_0402_5% 100K_0402_5% G2
PVDD1
PVDD2
VDD
PJDLC05C_SOT23-3 ACES_88266-02001
CONN@
2
C958 1 2 0.47U_0603_10V7K 7 2 GAIN0
RIN+ GAIN0
1
3 GAIN1
GAIN1
1
1 2 1 2 AMP_C_RIGHT 17
<30> AMP_RIGHT C957 0.47U_0603_10V7K R830 0_0603_5% RIN- SPKR+ @ R825 R826
ROUT+ 18
100K_0402_5% 100K_0402_5% JSPK1
SPKR+ R831 1 2 0_0603_5% SPK_R+ 1
SPKR- SPKR- R832 1 SPK_R- 1
14 2 0_0603_5% 2
2
C955 1 ROUT- 2
2 0.47U_0603_10V7K 9 20mil
LIN+ Right
2
4 SPKL+ D41 3
LOUT+ G1
4 G2
1 2 1 2 AMP_C_LEFT 5
<30> AMP_LEFT C971 0.47U_0603_10V7K R828 0_0603_5% LIN- SPKL- PJDLC05C_SOT23-3 ACES_88266-02001
LOUT- 8
CONN@
1
NC 12
2 2
EC_MUTE# BYPASS 10 Keep 10 mil width
19 SHUTDOWN
<28> EC_MUTE#
2
GND5
GND1
GND2
GND3
GND4
C956
0.47U_0603_10V7K
1
21
20
13
11
1 TPA6017A2_TSSOP20
2 2
C779 C774
Headphone Out
330P_0402_50V7K 330P_0402_50V7K
1 1 JHP1
1
<30> HP_LEFT R686 1 2 56.2_0603_1% HPOUT_L_1 1 2 HPOUT_L_2 2
L94 FBMA-L11-160808-700LMT_2P
<30> HP_RIGHT R685 1 2 56.2_0603_1% HPOUT_R_1 1 2 HPOUT_R_2 3
L93 FBMA-L11-160808-700LMT_2P
4
HP_PLUG# 5
<30> HP_PLUG#
SINGA_2SJ-0960-C01
3 CONN@ 3
MIC_PLUG# <NAL00 use>
HP_PLUG#
2
MIC1_VREFO MIC1_VREFO @
D24
PJDLC05C_SOT23-3
2
D43 D42
CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2
1 1
1 1
1
MIC JACK
R692 R693
4.7K_0402_5%
4.7K_0402_5% JMIC1
2
1
R694 1 2 MIC1_L_1 L89 1 2 MIC1_L_R 2
<30> MIC1_L
1K_0603_1% FBMA-L11-160808-700LMT_2P
R695 1 2 MIC1_R_1 L90 1 2 MIC1_R_R 3
<30> MIC1_R
1K_0603_1% FBMA-L11-160808-700LMT_2P
2
1 1 @ 4
D29
C780 C781 MIC_PLUG# 5
<30> MIC_PLUG#
220P_0402_50V7K 220P_0402_50V7K
2 2
PJDLC05C_SOT23-3
6
4 4
SINGA_2SJ-A960-C01
1
CONN@
<NAL00 use>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 31 of 45
A B C D E
ON/OFF switch Power Button
FAN1 Conn +3VALW
TOP Side
+5VS 1 2
+5VS R493 @ 10K_0603_5%
2
C821 10U_0805_10V4Z
1
1 2 1 2 R495
2 D25 R494 @ 10K_0603_5%
@ 1SS355_SOD323-2 100K_0402_5%
R566
Bottom Side
1
0_0603_5% SW3 D12
2
@ U35 @ D26 BAS16_SOT23-3
@D26 SMT1-05-A_4P 2
ON/OFFBTN# ON/OFF <28>
1 8 1 2 1 3 1
1
EN GND
2 VIN GND 7 3 51ON# <34>
+VCC_FAN1 3 6 2 4
VOUT GND C823 DAN202UT106_SC70-3
<28> EN_DFAN1 1 2 4 5
R567 0_0402_5% 1 VSET GND 10U_0805_10V4Z
6
5
C822 APL5607KI-TRG_SO8 1 2 2
@
ON/OFFBTN# <29>
C773 Change to SC600000B00
0.01U_0402_25V4Z +3VS C824
2 1000P_0402_50V7K 1000P_0402_50V7K
1 2 1
1
R568
1
10K_0402_5% D
40mil EC_ON 2 Q27
<28,36> EC_ON
JFAN1 G
2
+VCC_FAN1 1 S 2N7002_SOT23
3
1 R496
<28> FAN_SPEED1 2 2 G1 4
3 3 G2 5
1 10K_0402_5%
C825 CONN@
1
1000P_0402_50V7K ACES_85204-03001
2
H4 H5 H7 H8 H10
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
1
H11 H19 H24 H20 H21 H22 H23
H_3P0 H_3P0 H_3P0 H_4P2 H_4P2 H_4P2 H_4P2
1
H18 H17 H13
H_3P4 H_3P0X3P5N H_3P0N
1
FD1 FD2 FD3 FD4
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole & PBTN
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 32 of 45
A B C D E
+5VALW
+1.1VALW TO +1.1VS
+5VS
2
+1.1VALW +1.1VS
U36 R570
8 1 U38 100K_0402_5%
D S
7 D S 2 8 D S 1
2
6 3 1 1 7 2
1
D S D S
2
1 1 5 4 C827 R571 6 3 1 1
D G D S
1
C826 C828 470_0603_5% 1 5 4 C838 R578 SYSON#
D G <27> SYSON#
SI4800BDY_SO8 10U_0805_10V4Z C829 R577 C837
1
10U_0805_10V4Z 2 2 1K_0402_5% SI4800BDY_SO8 10U_0805_10V4Z C839 470_0603_5% D
1
2 2
10U_0805_10V4Z 1U_0402_6.3V4Z 2 2 2 Q30
<28,38> SYSON
1
2 1U_0402_6.3V4Z G 2N7002_SOT23
2
1
1
D 10U_0805_10V4Z S
3
1
1 D 1
2 SUSP R573
G 2 VLDT_EN# 100K_0402_5%
1 2 5VS_GATE S Q31 G
+VSB
3
R574 100K_0402_5% 2N7002_SOT23 +VSB 1 2 1.1VS_GATE S Q37
2
1 R581 47K_0402_5% 2N7002_SOT23
1
D C834
510K_0402_5%
SUSP 2 +5VALW
1
1
Q33G 0.1U_0603_25V7K D C844
2
R595
2N7002_SOT23 S VLDT_EN# 2
3
2
Q39G 0.1U_0603_25V7K
2N7002_SOT23 S @ 2 R576
3
100K_0402_5%
1 2
D
1
ACIN 2 Q48 SUSP
+3VALW TO +3VS <28,37> ACIN
G @
<40> SUSP
+3VS S 2N7002_SOT23
1
+3VALW D
<28> SUSP# 2 Q35
U39 G 2N7002_SOT23
1
8 1 S
3
D S
7 D S 2
2
6 3 R580
1 1 5
D
D
S
G 4 C842
1 1
R579 +1.5V to +1.5VS 10K_0402_5%
C840 C841 470_0603_5%
2
SI4800BDY_SO8 10U_0805_10V4Z C836 +1.5V +1.5VS
10U_0805_10V4Z 2 2
1 1
2 2
10U_0805_10V4Z 1U_0402_6.3V4Z
D
U37
2 SUSP 8 1
G D S
7 D S 2
2
2 1 3VS_GATE S Q36 6 3 +5VALW
+VSB 1 1
3
2 R582 200K_0402_5% 2N7002_SOT23 D S C832 C833 R572 2
1 1 5 D G 4
C830 C831
1
2
D SI4800BDY_SO8 10U_0805_10V4Z 470_0603_5%
1 2 2
SUSP 2 C843 1U_0402_6.3V4Z R583
1
Q38G 2 2 100K_0402_5%
2N7002_SOT23 S 0.1U_0603_25V7K 10U_0805_10V4Z 10U_0805_10V4Z
3
1
2 D
1
2 VGA_ON# VLDT_EN#
G
1 2 1.5VSG_GATE S Q32
+VSB
1
R575 100K_0402_5% 2N7002_SOT23 D
<28,39> VLDT_EN 2 Q40
510K_0402_5%
1 G 2N7002_SOT23
1
D C835 S
3
R596
VGA_ON# 2 1 2
R503 47K_0402_5% G 0.1U_0603_25V7K R584
Q34 S @ 2 10K_0402_5%
3
1 2N7002_SOT23
2
C848
1
D
0.22U_0603_16V4Z2 ACIN 2 Q49
G @
S 2N7002_SOT23
3
+5VALW
2
R587
100K_0402_5%
3 3
1
VGA_ON#
1
D
1
S
3
R586
+2.5VS +0.75VS +CPU_VDDR +NB_CORE +1.8VS +1.5V 10K_0402_5%
2
2
+5VS
1
D D D D D D
2 SUSP 2 SUSP 2 VLDT_EN# 2 VLDT_EN# 2 VGA_ON# 2 SYSON#
G G G G G G
S Q44 S 2N7002_SOT23 S Q56 S Q69 S Q46 S Q57
3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 33 of 45
A B C D E
A B C D
1 1
1
GND 6
PC3 PC4 PC5 PC6
PJP1 1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K
2
2 2
PJ1 PJ22
+3VALWP 1 1 2 2 +3VALW +1.8VSP 1 1 2 2 +1.8VS
JUMP_43X118 JUMP_43X118
(3.9A,160mils ,Via NO.= 8) (3A,120mils ,Via NO.=6)
VIN 1
PJ3
2 1
PJ26
2
+5VALWP 1 2 +5VALW +1.1VALWP 1 2 +1.1VALW
JUMP_43X118 JUMP_43X118
2
PJ11
PJ5
1
+0.75VSP 1 1 2 2 +0.75VS
+VSBP 1 1 2 2 +VSB
1
3 3
JUMP_43X118
PR10 PR11 JUMP_43X39 (3A,120mils ,Via NO.=6)
68_1206_5% 68_1206_5% (120mA,40mils ,Via NO.= 2)
PD3 PQ1
RLS4148_LL34-2 TP0610K-T1-E3_SOT23-3
2
PJ6
BATT+ 2 1 N1 3 1 PJ8 +1.5VP 1 2 +1.5V
VS +NB_COREP 1 1 2 2 +NB_CORE
1 2
JUMP_43X118
1
JUMP_43X118
1
PR14 JUMP_43X118
2
+3VLP
PJ21
+CPU_VDDRP 1 1 2 2 +CPU_VDDR
PR16
0_0603_5% JUMP_43X39
2 1 (1.5A,40mils ,Via NO.= 3)
4
+CHGRTC 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 34 of 45
A B C D
A B C D
VL
GND 10
1
GND 9 1
8 VL
8
7 7
6 EC_SMDA
6
1
5 EC_SMCA
5
2
4 TH PR29 PC21 PR28
4 PI 100_0402_1% 0.1U_0402_10V7K PR27 21K_0402_1% @ PR21
3
2
3 10K_0402_1% 100K_0402_1%
2 2
PR30
1 <40,41>
2
1 PU3 9.53K_0402_1%
1
2
PJP2
SUYIN_200275GR008G13GZR
VMB PR32
1 VCC TMSNS1 8 1 2
100_0402_1% 2 7
CONN@ EC_SMB_DA1 <28> GND RHYST1
PL2 @ PR169
SMB3025500YA_2P
<40,41> 3 6 47K_0402_1%
1 2
1
OT1 TMSNS2
BATT_S1 1 2 BATT+
1
4 OT2 RHYST2 5
EC_SMB_CK1 <28>
1
1
G718TM1U_SOT23-8
PC20 PC19 PR261
1000P_0402_50V7K 0.01U_0402_25V7K 1K_0402_5%
MAINPW ON <8,36>
2
2
PR24
6.49K_0402_1%
1
2 1 +3VALW P
PH1
100K_0402_1%_NCP15W F104F03RC
2
1
PR33 PH2 @
1K_0402_1% PC22
1U_0402_6.3V6K 100K_0402_1%_NCP15W F104F03RC
2
2
2
2 2
BATT_TEMP <28>
PQ3
TP0610K-T1-E3_SOT23-3
B+ 3 1 +VSBP
0.22U_0603_25V7K
1
1
PC24
PC25
PR34 0.1U_0603_25V7K
100K_0402_1% <BOM Structure>
2
3 3
2
VL
1 2
PR36
22K_0402_1%
2
PR38
100K_0402_1%
PR39
1
1K_0402_5% D
1 2 2 PQ4
<36,38> SPOK G 2N7002W -T/R7_SOT323-3
S
3
1
<BOM
PC27Structure>
1U_0402_6.3V6K
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 35 of 45
A B C D
5 4 3 2 1
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
2VREF_8205
1U_0603_10V6K
D D
1
PC344
2
PR264 PR265
13K_0402_1% 30.9K_0402_1%
1 2 1 2
PR266 PR267
RT8205_B+ 20K_0402_1% 20K_0402_1%
PL36 1 2 1 2
FBMA-L11-322513-151LMA50T_1210 Typ: 175mA
B+ 1 2 +3VLP RT8205_B+
ENTRIP2
ENTRIP1
PR268 PR269
10U_1206_25V6M
10U_1206_25V6M
1000P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
133K_0402_1% 154K_0402_1%
4.7U_0805_10V6K
1 2 1 2
1
1
PC362
PC351
PC347
PC348
PC349
PC350
8
7
6
5
5
6
7
8
PU19
2
2
PC352
ENTRIP2
FB2
TONSEL
REF
FB1
ENTRIP1
1
PQ59 25 PQ60
C AO4466_SO8 P PAD AO4466_SO8 C
2
4 4
7 VO2 VO1 24
SPOK <35,38>
8 23 PR271 PC354
PR270 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3
3
2
1
1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2
PL34 2.2_0603_5%
4.7UH_SIL104R-4R7PF_5.7A_30% PC353 UG_3V 10
VFB=2.0V 21 UG_5V PL35
0.1U_0603_25V7K UGATE2 UGATE1 10UH_MSCDRI-104A-100M-E_4.6A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
8
7
6
5
1
LG_3V LG_5V
4.7_1206_5%
4.7_1206_5%
12 LGATE2 LGATE1 19
5
6
7
8
PR272
PR273
PQ61
SKIPSEL
AO4712_SO8
VREG5
GND
VIN
NC
RT8205EGQW _W QFN24_4X4
EN
1 1
2
2
4
PC355 + 4 PC356 +
13
14
15
16
17
18
1
1
220U_6.3V_M PR274 PQ62 220U_6.3V_M
680P_0402_50V7K
680P_0402_50V7K
PC357
PC358
499K_0402_1% AO4712_SO8
2 2
1 2
2
1
2
3
2
B+
3
2
1
1
100K_0402_1%
1U_0603_10V6K
VL
1
PC359
1
PR275
PC360
Typ: 175mA
4.7U_0805_10V6K
2
ENTRIP1 ENTRIP2 RT8205
2
2
RT8205_B+
TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
B (2)SMPS2=375KHZ(+3VALWP) B
1
TPS51125A
0.1U_0603_25V7K
6
D D
2VREF_8205 TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
2
PC361
PQ63A 2 5 PQ63B
DMN66D0LDW -7_SOT363-6 G G DMN66D0LDW -7_SOT363-6 (2)SMPS2=305KHZ(+3VALWP)
3.3VALWP Delta I = 1.902A (Freq=305KHz)
S S Iocp = 7.108A ~ 8.34A
1
VL 2 1
PR279 PR276
1
2.2U_0603_10V7K
1U_0402_6.3V6K
1
1
PR278
PC363
PC23
2
1
200K_0402_1% D
2
<37> ACPRN 1 2 2
G
S
3
1
A PQ65 A
2N7002W -T/R7_SOT323-3
<28,32> EC_ON 2
PQ66
PDTC115EU_SOT323
Security Classification Compal Secret Data Compal Electronics, Inc.
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 36 of 45
5 4 3 2 1
A B C D
Iada=0~3.42A(65W/19V=3.421A)
CP = 85%*Iada ; CP = 2.91A
Iada=0~4.74A(90W/19V=4.736A) ADP_I = 19.9*Iadapter*Rsense B+
CP = 85%*Iada ; CP = 4.07A
P2 P3
PR61 B+ PL37 CHG_B+
PQ14 PQ15 0.02_2512_1% FBMA-L11-322513-151LMA50T_1210 PQ16
AO4407A_SO8 AO4407A_SO8 AO4407A_SO8
VIN 8 1 1 8 1 4 1 2 1 8
7 2 2 7 2 7
1 6 3 3 6 2 3 CSIN 3 6 1
5 5 5
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_50V7K
0.1U_0603_25V7K
CSIP PR63
5600P_0402_25V7K
4
4
1
1
PC50
PC51
47K_0402_1%
VIN PreCHG VIN
PC48
PC61
1 2
PC56
2
1
1
1
2
PR62
1
200K_0402_1% PR65
0.1U_0603_25V7K
1
2
PR94 PR280 10K_0402_1%
2.2U_0603_6.3V6K
PC62
PC49
200K_0402_1% PD16 191K_0402_1%
2
1
RB751V-40_SOD323-2
2
1 1
2
2
1 1
3
ACSETIN @ PD17
47K PQ19 BAS40CW _SOT323-3
1
PDTA144EU_SOT323-3 PR281 PQ20 3 ACOFF @ PR67
6251VDD
1
2 47K 10_1206_5% PC364 PDTC115EU_SOT323 2 1 200K_0402_1%
PR68 ACSETIN 1000P_0402_50V7K PR282 2 1 2 VIN
0_0402_5% 14.3K_0402_1%
2
2 1 PU5 PC127
<28> FSTCHG
2
1
VIN1
0.1U_0603_25V7K
2200P_0402_50V7K
0.1U_0603_25V7K
3
1
1
PQ21 PR70 47K_0402_5% DCIN D
100K_0402_1%
VIN1 100K_0402_1%
1 24 2 1
1
VDD DCIN
1
1
PR71
PC57
PC52
PDTC115EU_SOT323 6251VDD 1 2 2 PACIN
PR283
G
1
2 PR69 2 23 ACPRN S @ PQ23
3
150K_0402_1% ACSET ACPRN PR72 @ 2N7002W -T/R7_SOT323-3
1
PQ35 20_0402_5%
2
2
2 PC53
3
<28> 3S/4S#
5
6
7
8
0.047U_0603_16V7K
1
2
CSOP PQ55 D 2
4 21 1 2
1
PC54 CELLS CSOP PR73 ACPRN 2 PQ24
AO4466_SO8
PQ68A 6800P_0402_25V7K 20_0402_5% G 2N7002W -T/R7_SOT323-3
3
6
D DMN66D0LDW -7_SOT363-6 D
1 2 5 20 2 1 S
3
ICOMP CSIN
2
2 5 PQ68B PR75 PR74 4
G G DMN66D0LDW -7_SOT363-6 10K_0402_1% PC129 20_0402_5%
1 2 1 2 6 19 0.1U_0603_25V7K
1 2
<40,41>
1
PR77 VCOMP CSIP PR76 PL5 PR78
S S
1
3
2
1
0.01U_0402_25V7K 1 2 7 18 LX_CHG 1 2 CHG1 4
ICM PHASE
3.3_1206_5%
5
6
7
8
1
<28> ADP_I 2 3
PR80
PR79 PC58 6251VREF 8 17 DH_CHG
47K_0402_5% PR81 VREF UGATE PR82 PC59
1 2
PACIN 80.6K_0402_1% 0_0603_5% 0.1U_0603_25V7K
10U_1206_25V6M
10U_1206_25V6M
1 2
2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1 PQ57 @
2
<28> IREF CHLIM BOOT
1
4
0.01U_0402_25V7K
AO4466_SO8
1
1
PC68
PC63
PQ53 PR84 PD12
1
PC60
220P_0402_50V7K
2 10 ACLIM VDDP 15
PC128
100K_0402_1% PR87
2
2
1
2.55K_0402_1%
PR85
3
2
1
2
ACOFF 2 11 14 DL_CHG
<28,40> ACOFF
2
VADJ LGATE
1
2
PR86 @
4.7_0603_5%
12 13 PC64
2
1
GND PGND 4.7U_0805_6.3V6K
3
PQ54
2
1
3 3
PR88
15.4K_0402_1%
Iada=0~4.74A(90W) CP= 85%*Iada; CP=4.03A <28> CALIBRATE#
1 2
6251VDD
2
1
1 2 ACIN <28,33>
1
CP mode PR286
PR285 10K_0402_1%
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) 47K_0402_1%
2 PACIN
where Vaclm=1.464V (90W), Iinput=4.03A
2
PR84=12.1K;PR87=20K
1
1
PR84=12.1K;PR85=2.55K PR287
CC=0.6~4.48A 14.3K_0402_1%
2
<36> ACPRN 2
IREF=1.016*Icharge PQ67
PDTC115EU_SOT323
3
IREF=0.43V~3.24V
4 4
Charging Voltage
BATT Type (0x15) CV mode
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
Size Document Number Rev
- AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, June 11, 2010 Sheet 37 of 45
A B C D
A B C D
PL31
FBMA-L11-322513-151LMA50T_1210
1.1VALW _B+ 2 1 B+
10U_1206_25V6M
2200P_0402_50V7K
1
1
PC139
PC72
5
6
7
8
2
1 1
PR96
255K_0402_1% 4 PQ25
1 2 AO4466_SO8
PR97 PR98
0_0402_5% 2.2_0603_5%
1 2 BST_1.1VALW
1 2
3
2
1
<35,36> SPOK DCR= 7.5 mohm
1
@ PR99 PL6
15
14
1
30K_0402_5% @ PC74 PU6 PC75 1.0UH_PCMC104T-1R0MN_20A_20%
0.1U_0402_16V7K BST_1.1VALW -11 2 1 2
EN/DEM
NC
BOOT
+1.1VALWP
2
2
2 13 DH_1.1VALW 0.1U_0603_25V7K
TON UGATE
1
PR101 3 12 LX_1.1VALW
VOUT PHASE
5
6
7
8
100_0603_1% PR100 1
+5VALW 1 2 4 11 1 2 +5VALW 4.7_1206_5%
VDD CS PR102 + PC76
2
5 10 7.32K_0402_1% PQ26 330U_6.3V_M
FB VDDP AO4456_SO8
1
DL_1.1VALW 2
6 PGOOD LGATE 9 4
PGND
PC77 PC78
GND
4.7U_0603_6.3V6K 680P_0603_50V7K
2
1
<Vo=1.1V> VFB=0.75V S IC G5603RU1U TQFN 14P PW M PC80
3
2
1
4.7U_0805_10V6K
V=0.75*(1+4.7K/10K)=1.1V
2
Fsw=280KHz
2
PR103 2
1
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
=>1/2Delta I=1.03A PR104
Vtripmax=Iocp*Rdson=8.9*5.6*1.3=0.065V 8.45K_0402_1%
Rcs=Vtrip/9uA=0.065V/9uA=7.2K
2
choose Rcs=7.32K PL32
Iocpmax=((7.32K*11uA)/0.0045)+1.03A=19A FBMA-L11-322513-151LMA50T_1210
Iocpmin=((7.32K*9uA)/(0.0056*1.3))+1.03A=10A 1.5V_B+ 2 1 B+
Iocp=10A~19A
10U_1206_25V6M
2200P_0402_50V7K
1
1
PC82
PC83
5
6
7
8
2
PR106 PQ27
226K_0402_1% 4 AO4466_SO8
1 2
PR108
PR105 0_0402_5% 2.2_0603_5%
1 2 BST_1.5V 1 2
<28,33> SYSON
3
2
1
1
3 3
14
1
30K_0402_5% @PC85
@ PC85 PU7 0.1U_0603_25V7K 1.0UH_PCMC104T-1R0MN_20A_20%
0.1U_0402_16V7K BST_1.5V-1 1 2 1 2
EN/DEM
NC
BOOT
+1.5VP
2
2
2 13 DH_1.5V
TON UGATE
1
PR111 3 12 LX_1.5V PR110
VOUT PHASE
5
6
7
8
100_0603_1% 4.7_1206_5% 1
+5VALW 1 2 4 11 1 2 +5VALW
VDD CS PR112 + PC86
2
5 10 13K_0402_1% 330U_6.3V_M
FB VDDP PQ28
1
1
DL_1.5V AO4456_SO8 PC88 2
6 PGOOD LGATE 9 4
PGND
PC87 680P_0603_50V7K
GND
4.7U_0603_6.3V6K
2
2
1
S IC G5603RU1U TQFN 14P PW M PC90
7
3
2
1
4.7U_0805_10V6K
2
<Vo=1.5V> VFB=0.75V PR113
10K_0402_1%
Vo=0.75*(1+10K/10K)=1.5V 2 1
Fsw=335KHz
1
=>1/2Delta I=1.95A
4
Vtripmax=Iocp*Rdson=16.2*5.6*1.3=0.118V 4
Rcs=Vtrip/9uA=0.118V/9uA=13.1K
choose Rcs=13K
Iocpmax=((13K*11uA)/0.0045)+1.95A=32A
Iocpmin=((13K*9uA)/(0.0056*1.3))+1.95A=18A Security Classification Compal Secret Data Compal Electronics, Inc.
Iocp=18A~32A Issued Date 2010/04/12 Deciphered Date 2010/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.1VALWP/1.5VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 38 of 45
A B C D
A B C D
PL33
FBMA-L11-322513-151LMA50T_1210
NB_CORE_B+ 2 1 B+
10U_1206_25V6M
2200P_0402_50V7K
1 1
100U_25V_M
1
1
PC140
PC91
+
PC218
5
6
7
8
2
2
PR115
255K_0402_1% 4
1 2 PQ29
PR116 PR117 AO4466_SO8
100K_0402_5% 2.2_0603_5%
1 2 BST_NB_CORE
1 2
3
2
1
<28,33> VLDT_EN DCR= 7.5 mohm
1
@ PR118 PL8
15
14
1
30K_0402_5% PC94 PU8 PC93 1.0UH_PCMC104T-1R0MN_20A_20%
0.1U_0402_16V7K BST_NB_CORE-1
1 2 1 2
EN/DEM
NC
BOOT
+NB_COREP
2
2
2 13 DH_NB_CORE 0.1U_0603_25V7K
TON UGATE
1
PR120 3 12 LX_NB_CORE
VOUT PHASE
5
6
7
8
100_0603_1% PR119 1
1 2 4 11 1 2 +5VALW 4.7_1206_5%
+5VALW VDD CS PR121 + PC95
2
FB1_NB_COREP 5 10 7.5K_0402_1% PQ30 330U_6.3V_M
FB VDDP AO4456_SO8
1
DL_NB_CORE 2
6 PGOOD LGATE 9 4
PGND
<Vo=1.1V> VFB=0.75V PC96 PC97
GND
4.7U_0603_6.3V6K 680P_0603_50V7K
V=0.75*(1+4.7K/10K)=1.1V
2
1
2 2
3
2
1
4.7U_0805_10V6K
2
Cout ESR=15m ohm Rdson(max)=18m Rdson(typ)=15m
Ipeak=7.6A, Imax=5.4A, Iocp=9.2A PR122
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A 2.37K_0402_1%
=>1/2Delta I=1.03A 1 2
Vtripmax=Iocp*Rdson=9.2*5.6*1.3=0.067V
Rcs=Vtrip/9uA=0.067V/9uA=7.44K +5VALW
choose Rcs=7.5K
Iocpmax=((7.5K*11uA)/0.0045)+1.03A=19.36A
1
Iocpmin=((7.5K*9uA)/(0.018*1.3))+1.03A=10.3A POWER_SEL
Iocp=10.3A~19.36A PR158 PR131
11.8K_0402_1% 10K_0402_1% HIGH 0.95V
2
LOW 1.1V
PR159
1
D 10K_0402_5%
PQ44 2 2 1
2N7002W -T/R7_SOT323-3 G PQ43 PR157
1
D 2N7002W -T/R7_SOT323-3 0_0402_5%
S
3
1
1
+1.5V G
PR123 PC125 S
1
8.87K_0402_1% 0.1U_0402_25V6
2
+5VALW PC126
2
0.01U_0402_25V7K
2
1
3 3
PJ24
1
@ JUMP_43X79
1
PC115
1U_0402_6.3V6K
2
PR162
2
1 2 PU12
1
5 PC116
VCNTL
VIN 4.7U_0805_6.3V6K
7 POK
4
2
@ PR155 VOUT
3
10K_0402_1% VOUT +CPU_VDDRP
1
VLDT_EN
22U_0805_6.3V6M
1 2 8 EN FB 2
1
PC119
GND
1
9 PR154 PC118
2
VIN
1
0.1U_0402_16V7K APL5508-25DC-TRL_SOT89-3
2
+3VS 2 3
+5VALW
IN OUT
+2.5VSP
PR161 PR156 VDDR_SW
1
165K_0402_1% 249K_0402_1% GND
1
PC114
2
4.7U_0805_6.3V6K
PC113
HIGH 1.05V 1U_0402_6.3V6K @ PR153
1
150_1206_5%
2
PR152
2
4
10K_0402_1% LOW 0.9V 4
1
D
2 PQ58
2
@ PR160
10K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/04/12 Deciphered Date 2010/10/12 Title
NB_CORE/2.5VS/CPU_VDDRP
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 39 of 45
A B C D
5 4 3 2 1
PreCHG
+1.5V PR124
1K_1206_5%
1 2
PQ31
PR125 TP0610K-T1-E3_SOT23-3
B+
1
VIN 1K_1206_5% PD13
1 2 2 1 3 1
1
PJ17
JUMP_43X79 PR126 LL4148_LL34-2
2
1K_1206_5%
PU9 1 2
2
D D
1 8
VIN NC
+3VALW
1
PR127
2 7 1K_1206_5%
2
GND NC
1
PC101 1 2 PR128
1
PC100 3 6 1U_0603_6.3V6M 100K_0402_5% PR129
4.7U_0805_6.3V6K PR130 VREF VCNTL 100K_0402_5%
2
1K_0402_1% 4 5
VOUT NC
9
2
TP
UP7711U8 PSOP 8P
1
PR133 PR132
0.1U_0402_16V7K
+0.75VSP
1
300K_0402_5% PQ32 D 100K_0402_5%
PC102
1 2 2 PR134 PQ33
<33> SUSP
1
G 1K_0402_1% PD18 DTC115EUA_SC70-3
1 2
1
S PC103 2
3
PC104 2N7002W -T/R7_SOT323-3 22U_0805_6.3V6M <28,37> ACOFF 1 2
2
0.22U_0402_10V4Z 3 PQ34
2
+5VALWP DTC115EUA_SC70-3
BAS40CW _SOT323-3
2
3
Change 300K / 0.22u delay
3
Ipeak=1A, Imax=0.7A
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Precharge/+0.75VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 40 of 45
5 4 3 2 1
5 4 3 2 1
FB=0.6V
Note:Iload(max)=3.5A
D D
PU11 PL9
4
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
+3VALW 10 2 LX_1.8V 1 2
PG
PVIN LX +1.8VSP
68P_0402_50V8J
9 PVIN LX 3
PC1022
4.7_1206_5%
1
PC157
22U_0805_6.3VAM
22U_0805_6.3VAM
8 SVIN
1
PR143
22U_0805_6.3VAM PR147
PC117
PC124
6 10K_0402_1%
2
FB
5
2
EN
NC
NC
PR144
TP
200K_0402_1% FB_1.8V
<28,33> VGA_ON VGA_ON 1 2 1.8V_EN
11
1
1
680P_0603_50V7K
0.1U_0402_10V7K
PC155
PC1026
SY8033BDBC_DFN10_3X3 PR145
1
4.99K_0402_1%
2
PC156
2
0.22U_0603_25V7K @
2
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 41 of 45
5 4 3 2 1
A B C D E F G H
CPU_B+ PL15
FBMA-L18-453215-900LMA90T_1812
PC183 2 1 B+
33P_0402_50V8K
10U_1206_25V6M
2200P_0402_50V7K
0.01U_0402_25V7K
5
6
7
8
2 1
220U_25V_M
1
2200P_0402_50V7K
2200P_0402_50V7K
0.01U_0402_25V7K
0.01U_0402_25V7K
PQ69
1
AO4466_SO8 +
PC185
PC186
PC187
PC188
1
1 1
PC219
PC220
PC221
PC222
2 1 2 1
2
PR214 PC184 UGATE_NB 4 2
2
44.2K_0402_1% 1200P_0402_50V7K PR230
PR215 2.2_0603_5%
2_0603_5% BOOT_NB 1 2 1 2
+5VALW 1 2 PC189 PL16
3
2
1
1000P_0402_50V7K PC191 3.3UH_SIQB74B-3R3PF_5.9A_20% +CPU_CORE_NB
2 1 PHASE_NB 0.1U_0603_25V7K 1 2
1
PC190 PR216
5
6
7
8
0.1U_0603_16V7K 22K_0402_1% PR217
2 1 PQ70 4.7_1206_5% 1
2
PR218 AO4712_SO8
10_0402_5% + PC192
1 2
1 2 +CPU_CORE_NB 220U_D2_4VM
CPU_B+ 1 2 LGATE_NB 4 PC193
680P_0603_50V7K 2
PR219
+VDDNB
CPU_VDDNB_FB_H <8>
2
+3VS +5VS +3VS
2_0603_5% PR221
13.7K_0402_1%
Design Current: 2.8A
3
2
1
1
PR220
2 1 PHASE_NB Max current: 4A
0_0402_5% LGATE_NB OCP_min:5A
1
PC194 CPU_B+
0.1U_0603_16V7K PHASE_NB
2
1
2
PR222 PR223 UGATE_NB
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.01U_0402_25V7K
0_0402_5% @ 105K_0402_1%
5
2 1 CPU_VDDNB_FB_L <8>
PR224 PQ46
2
2
1
1
0_0402_5% AON6428L 1N DFN-8
PC195
PC196
PC223
PC197
PC198
PR225
1
2
105K_0402_1% PR228 10_0402_5% UGATE0 4
@ 105K_0402_1% 48
47
46
45
44
43
42
41
40
39
38
37
2
1
PU15
2 PHASE0 2
VIN
VCC
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
2
PR229 PL17
3
2
1
2.2_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
<28> VGATE 1 36 BOOT_NB BOOT0 1 2 1 2 1 2 +CPU_CORE
PR237 0_0402_5% OFS/VFIXEN BOOT_NB
1
1 2 2 35 BOOT0 PC199
PGOOD BOOT0
5
<18> H_PWRGD_L 1 2 0.1U_0603_25V7K PR232
1
PR231 0_0402_5% @ 3 34 UGATE0 16.2K_0402_1%
PWROK UGATE0 PQ48 PR233
2 1 4 33 PHASE0 AON6704L_DFN8-5 4.7_1206_5%
2
<8> CPU_SVD PR234 0_0402_5% SVD PHASE0
1 PR235 2
5 32 4 4 4.02K_0402_1%
1 2
SVC PGND0 +5VALW
2 1
<8> CPU_SVC PR236 0_0402_5% 6 31 LGATE0 PC200 PC201
ENABLE LGATE0 @ PQ47 680P_0603_50V7K 1 2
7 30 AON6704L_DFN8-5
3
2
1
3
2
1
2
RBIAS PVCC 0.1U_0402_16V7K
<28,39> VR_ON 8 29 LGATE1
OCSET LGATE1
1
PR238 PR239 ISL6265IRZ-T_QFN48_6X6~D PC202
2 1 2 1 9 28 1U_0603_16V6K LGATE0
21.5K_0402_1% 95.3K_0402_1% VDIFF0 PGND1
ISN0
ISP0
10 27 PHASE1
FB0 PHASE1
11 26 UGATE1
COMP0 UGATE1 CPU_B+
12 25 BOOT1 +CPU_CORE_0
VW0 BOOT1
Design Current: 25A
COMP1
VDIFF1
VSEN0
VSEN1
RTN0
RTN1
ISN0
ISN1
ISP0
VW1
ISP1
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.01U_0402_25V7K
FB1
5
PQ51 OCP_min:42A
13
14
15
16
17
18
19
20
21
22
23
24
49
1
AON6428L 1N DFN-8
PC203
PC204
PC205
PC206
ISP0
PR242 0_0402_5%
ISN0
2
1
ISN1
ISP1
UGATE1 4
<8> CPU_VDD0_FB_H VSEN0 0_0402_5%
0_0402_5%
2 PR244 1
2 PR250 1
PR241 PR240
0_0402_5%
+CPU_CORE 2 1 1 2 PHASE1
3 3
10_0402_5% PR243 PL18
2
3
2
1
2.2_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
<8> CPU_VDD0_FB_L RTN0 BOOT1 1 2 1 2 1 2 +CPU_CORE
PR245 10_0402_5%
1
2 1 PC207
5
0.1U_0603_25V7K PR247
1
RTN1 16.2K_0402_1%
<8> CPU_VDD1_FB_L PR246 10K_0402_1% PR248
2 1 PQ49 4.7_1206_5%
2
AON6704L_DFN8-5 1 PR249 2
@ PR252 1K_0402_1% 4 4 4.02K_0402_1%
1 2
+1.5VS 2 1
@ PQ52 PC208 PC209
<8> CPU_VDD1_FB_H VSEN1 680P_0603_50V7K 1 2
PR251 AON6704L_DFN8-5
3
2
1
3
2
1
2
+CPU_CORE 2 10_0402_5%
1 0.1U_0402_16V7K
ISN1
ISP1
255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K
2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1
PR262 @ PR263 @
1K_0402_5% 1K_0402_5%
2
4 4
2010
3 HDMI test fail 5V voltage too low at test termial 36 Change PR265 from 30K to 30.9K PVT
0604
2010
4 ESD test fail ESD solution Add PC22, PC23 PVT
0608
2010
5 EMI test fail EMI solution Enable 3V,5V,1.1V,1.5V,NB_CORE,CPU snubber PVT
0608
C C
10
B B
11
12
13
14
15
A A
16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 43 of 45
5 4 3 2 1
5 4 3 2 1
D D
5
C C
10
B B
11
12
13
14
15
A A
16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 44 of 45
5 4 3 2 1
5 4 3 2 1
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW96 LA-6552P
Date: Friday, June 11, 2010 Sheet 45 of 45
5 4 3 2 1
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