International Journal of Electrical and Electronics communication

Volume 1 Issue 1

Design of an LDPC Decoder and Its Performance

Palleti Raju Potnuru Surya Prasad
1 2
Department of E.C.E, PG Student, M.V.G.R Department of E.C.E, Associate Professor,
College of Engineering(Autonomous), M.V.G.R College of Engineering (Autonomous),
Vizianagaram, A.P-535005, India. Vizianagaram, A.P-535005, India.

Address for Correspondence

Palleti Raju,3-1-193/39, Vasavani Palem, Lawson’s Bay Colony (Post), Visakhapatnam, A.P-
530017, India.
E-Mail:rajupalleti17@gmail.com

Abstract
Low-Density Parity-Check codes (LDPC) are widely using ECC (Error Correcting Codes)
for having eminent capabilities. By using Message Passing Algorithm, these codes can be
decoded. These codes perform better than Turbo Codes and easily attains Shannon’s limit.
For low SNR, these codes provide low bit error rates. For high SNR, these codes provide no
error floor. These codes are used in various applications like Wi-Fi, Mobile WiMAX, DVD-
S2, and IEEE 802.3 (10 GBASE –T). The main feature of these codes is that they can provide
efficient encoding and decoding. In this paper, an LDPC encoder and decoder are
implemented by Verilog techniques. For simulation, Xilinx Vivado 14.2 and Questa Sim 10.4c
are used. And for synthesis, Leonardo Spectrum 2014b.4is used. These designs are also
implemented on Nexys 4-DDR XC7A100TCSG324-2L FPGA.

Keywords:Low Density Parity Check (LDPC); Bit Flipping; Mentor Graphics Custom IC
Design Tool; Leonardo Spectrum; FPGA.

INTRODUCTION Wireless Communications is one of the

In 1960, Gallager proposed LDPC (Low
density parity check) codes, which are
similar to linear block codes [1]. At that
time, these codes are neglected due to its
high computational complexity. In 1981,
LDPC codes are generalized into graphical
representation (Bipartite graph or Tanner
graph) by Tanner [5]. In 1990’s, these
codes are again came back by D. Mackay
and R. Neal, who constructed a parity
check matrix with dynamic sparseness [2]
[3]. Richardson and Urbanke improved the
parity check matrix to reduce the
complexity for faster encoding and
decoding. This code’s performance is very
close to channel capacity specified by
Shannon. In practical implementation,
these codes provide a high degree of
parallelism.
prime applications for error correcting
codes. Because of the eminent capability,
LDPC codes are being used in various
applications like Wi-Fi, Mobile WiMAX,
DVD-S2, and IEEE 802.3 (10 GBASE –T)
[4]. The standards like DVB-S, 3GPP-LTE
uses Turbo Codes.
The complexity and throughput of an
LDPC decoder depends on many
parameters such as block length, code rate,
processing node complexity,
interconnection complexity, no. of
iterations and parallelism level. There is a
balance between the performance of
decoder and complexity of decoding. The
parallelism in decoding provide eminent
throughput if properly used. The flexibility
in FPGA is suitable for designing LDPC

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 International Journal of Electrical and Electronics communication
Volume 1 Issue 1

decoder rather than in general purpose (variable node) is one and check node is
processor. the other [5]. The no. of bit nodes equals to
no. of columns and the no. of check nodes
REPRESENTATION OF LDPC equals to no. of rows in the matrix H. The
CODES connection (edges) between the check
The representation of LDPC codes can be nodes and the bit nodes represents non-
done either by using parity-check matrix zero entities in the matrix H. A parity
or by using a Tanner representation check matrix and its graphical
(bipartite graph). In Tanner representation, representation are given below.
there are nodes of two types, Bit node

Parity-Check Matrix ‘H’

Tanner representation of matrix ‘H’

Fig. 1: The Parity-check matrix ‘H’ and its equivalent graphical representation

In the matrix ‘H’, a cycle can be formed CLASSIFICATION

by one complete path through non-zero
entries with moves between rows and
columns alternatively. In a tanner graph, a
cycle can be formed by a path starting
from a node and ending at the same node.
The number of edges in that path gives the
length of the cycle. The smallest cycle is
called as girth. The smallest possible girth
is four. A tanner graph has a minimum
cycle of length four and has even cycle
lengths.
LDPC codes are having two classes,
Regular LDPC is one and Irregular LDPC
is the other. If the weight of each column
and each row are constant then the codes
are called regular LDPC codes. If the
weight of each column and each row are
different then the codes are called irregular
LDPC codes [6] [7].

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 International Journal of Electrical and Electronics communication
Volume 1 Issue 1

ENCODING PROCESS DECODING PROCESS

To encode the LDPC codes, first the In this paper, Bit Flip algorithm is used to
matrix ‘H’ should be transformed as given decode LDPC codes. Bit Flip algorithm is
below. known as hard decision algorithm.
The steps involved in the Bit Flip
H = P IN−K algorithm are as follows

The above form of parity check matrix is Step 1: Initialization

obtained by performing Gaussian
elimination method [7]. In this method,
only row operations should be used. The
addition of two rows should be modulo-2
addition. This parity check matrix can also
be obtained by performing row swaps and
column swaps on it. Here, ‘𝑃(N−K) x K ’
represents a parity matrix and ‘IN−K ’
represents an identity matrix.
By using the matrix 𝑃(N−K) x K , Generator
matrix ‘G’ can be obtained which is of the
form
G = IK PT
In this step, the received codeword is
assigned to the corresponding variable
nodes. These assigned values are passed as
messages from variable node to check
node.
Step2: Check Node Update
In this step, each check node checks the
parity check equation associated with it
from the variable node messages. If the
parity check equation is satisfied then its
send ‘0’ value otherwise ‘1’ value to
variable node. If all forms of the parity-
check equations are get satisfied, the
termination of the algorithm will occur.

Now, the encoding of the information bits
or message bits is done by the following
form
C = [u] . [G]
Here, ‘C’ represents the codeword of size
N, ‘u’ is the message vector of size K and
‘G’ is the generator matrix. This codeword
is the encoded message that is modulated
using BPSK in which {0, 1} {-1, 1}
transformation occurs and transmitted over
AWGN channel [9] [10].
Step 3: Variable Node Update
In this step, each variable node gets a
value from check nodes. Now each
variable node decides that the original
received bit is correct or not by majority
voting from check nodes. If majority of
votes are different from the original
received bit then that the bit will be flipped
and update its value.
This updated value will be send as a
message to the check node. After this, step
2 and step 3 are repeated until
the parity-check equations are get satisfied
(or) until it reach the count of iterations
specified [12][13][14].

Algorithm Bit flipping Decoding

01: Procedure decode(r)

02:
03: K=0 →Initialization
04: for i = 1 : n do

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 International Journal of Electrical and Electronics communication
Volume 1 Issue 1

05: Mi = ri
06: end
07:
08: repeat
09: for j = 1 : m do →Check messages
10: for i = 1 : n do
11: 𝐸𝑖,𝑗 = 𝑖 ` ∈𝐵𝑖 ,𝑖 ` ≠𝑖 𝑀𝑖 ` 𝑚𝑜𝑑 2
12: end
13: end
14:
15: for i = 1 : n do →Bit messages
16: if the message 𝐸𝑖,𝑗 disagree with rithen
17: Mi = ( ri + 1 mod 2)
18: end
19: end
20:
21: for j = 1 : m do Test: are the parity-check equations are satisfied
22: 𝐿𝑗 = 𝑖 ` ∈𝐵𝑖 𝑀𝑖 ` 𝑚𝑜𝑑 2
23: end for
24: if all Lj = 0 or K = Kmaxthen
25: Finished
26: else
27: K=K+1
28: end
29: until Finished
30: end procedure

SIMULATION RESULTS These designs are simulated by using

LDPC encoder and decoder are designed Xilinx vivado and Questa Sim. The
in Verilog HDL language using Xilinx simulation results are given below.
vivado 14.2 and HDL Designer 2015.1a.

Fig. 2: Simulation results of LDPC Encoder

In the above figure, when the reset becomes low. When the reset becomes
becomes high, the encoded output low, the message 00110111 is encoded as
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 International Journal of Electrical and Electronics communication
Volume 1 Issue 1

0011011100110010. The encoded output will be different for different messages.

Fig. 3: Simulation results of LDPC Decoder

In the above figure, when the reset
becomes high, the decoded output
becomes low. When the reset becomes
low, the received codeword
0011011100010010 is decoded as
0011011100110010. In the received
codeword, there is an error at the 11th bit
which is decoded by using Bit Flipping
algorithm.
To get ASIC Model of design, the designs
should be synthesized to get the netlist file.
In this paper, to synthesize the designs,
Xilinx Vivado and Leonardo Spectrum are
used. The net list obtained by using Xilinx
vivado is dumped into the FPGA to see the
performance of the designs. The net list
obtained by using Leonardo Spectrum can
be used to generate ASIC model of the
design. RTL and Synthesized designs of
the designs obtained by using Xilinx
Vivado are shown in fig 4, 5, 6, 7. RTL
and Gate Level designs of the designs
obtained by using Leonardo Spectrum are
shown in fig 8, 9, 10, 11.

Fig. 4: RTL Design of LDPC Encoder in Xilinx

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Fig. 5: RTL design of LDPC Decoder in Xilinx

Fig. 6: Synthesized Design of LDPC Encoder in Xilinx

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Fig. 7: Synthesized Design of LDPC Decoder in Xilinx

Fig. 8: RTL Design of LDPC Encoder in Leonardo Spectrum

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Fig. 9: RTL Design of LDPC Decoder in Leonardo Spectrum

Fig. 10: Gate Level Design of LDPC Encoder in Leonardo Spectrum

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Volume 1 Issue 1

Fig. 11: Gate Level Design of LDPC Decoder in Leonardo Spectrum

The synthesized designs using Xilinx
vivado are dumped into Nexys 4DDR
FPGA. The utilization reports, when the
designs are tested on Nexys 4DDR
XC7A100TCSG324-2LFPGA are given
below
techniques over AWGN Channel is shown
in fig 14. For block lengths (200, 400),
(300, 600), the performance is shown in
fig 15. For block lengths (500, 1000),
(600, 1200), the performance is shown in
fig 16.

Fig. 12: Utilization report of LDPC

Encoder

Fig. 13: Utilization report of LDPC

Decoder
Fig. 14: Performance for different
The performance of an LDPC Decoder modulation techniques
while using different modulation
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 International Journal of Electrical and Electronics communication
Fig. 15: Performance for Block lengths
(200,400), (300,600)
Fig. 16: Performance for Block lengths
(500, 1000), (600, 1200)
Fig. 17: Output in FPGA
Conclusion:
In this paper, LDPC Decoding is done by
using Bit Flipping Algorithm. For a
regular LDPC matrix of 8x16 whose row
weight is 4 and column weight is 2, and
having a code rate of ½, LDPC Encoder
and Decoder are designed by using
Verilog technique in Xilinx vivado 14.2
and HDL Designer 2015.1a. These designs
31 Page 22-32 © MAT Journals 2017. All Rights Reserved
Volume 1 Issue 1
are simulated Using Xilinx Vivado 14.2
and Questa Sim 10.4c. These designs are
synthesized usingXilinx Vivado 14.2 and
Leonardo Spectrum 2014b.4and also
implemented on Nexys 4-
DDRXC7A100TCSG324-2L FPGA.
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low density parity check codes. IEEE 14. AartiTak, 2015. Implementation of
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