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Acer AL2032W

Service Guide
Service guide files and updates are available on the
CSD web: for more information,
Please refer to http://csd.acer.com.tw/

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Copyright

Copyright © 2004 by Acer Incorporated. All rights reserved. No part of this publication may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in
any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the
prior written permission of Acer Incorporated.

Disclaimer
The information in this guide is subject to change without notice. Acer Incorporated makes no representations or
warranties, either expresses or implied, with respect to the contents hereof and specifically disclaims any
warranties of merchantability or fitness for any particular purpose, Any Acer Incorporated software described in
this manual is sold or licensed “as is ”. Should the programs prove defective following their purchase, the buyer
(and not Acer Incorporated, its distributor, of its dealer) assumes the entire cost of all necessary servicing, repair,
and any incidental or consequential damages resulting from any defect in the software.

Acer is a registered trademark of Acer Corporation.


Intel is a registered trademark of Intel Corporation.
Pentium and Pentium II/III are trademarks of Intel Corporation.
Other brand and product names are trademarks and/or registered trademarks of their respective holders.

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Conventions

The following conventions are used in this manual:

Screen messages Denotes actual messages that appear on


screen
Note Gives bits and pieces of additional information
related to the current topic.
Warning Alerts you to any damage that might result
from doing or not doing specific actions.
Caution Gives precautionary measures to avoid
possible hardware or software problems.
Important Reminds you to do specific actions relevant to
the accomplishment of procedures.

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Preface

Before using this information and the product it supports, please read the following general information.
1. this Service Guide provides you with all technical information relating to the BASICCONFIGURATION
decided for Acer’s “global” product offering. To better fit local market requirements and enhance product
competitiveness, your regional office MAY have decided to extend the functionality of a machine (e.g.
add-on card, modem, or extra memory capability). These LOCALIZED FEATURES will NOT be covered
in this generic service guide. In such cases, please contact your regional offices or the responsible
personnel/channel to provide you with further technical details.
2. please not WHEN ORDERING FRU PARTS, that you should check the most up-to-date information
available on your regional web or channel. If, for whatever reason, a part number change is made, it will
not be noted in the printed Service Guide, for ACER-AUTHORIZED SERVICE PROVIDERS, your Acer
office may have a DIFFERENT part number code to those given in the FRU list of this printed Service
Guide. You MUST use the list provided by your regional Acer office to order FRU parts for repair and
Service of customer machines.

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WARNING: (FOR FCC CERTIFIED MODELS)

NOTE: this equipment has been tested and found to comply with the limits for a Class B digital device,
pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy,
and if not installed and used in accordance with the instructions, may cause harmful interference to radio
communications. However, there is no guarantee that interference will not occur in a particular installation. If this
equipment does cause harmful interference to radio or television reception,
Which can be determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures:
1. Reorient or relocate the receiving antenna.
2. Increase the separation between the equipment and receiver.
3. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
4. Consult the dealer or an experienced radio/TV technician for help.

NOTICE:
1. The changes or modifications not expressly approved by the party responsible for compliance could void
the user’s authority to operate the equipment.
2. Shielded interface cables and AC power cord, if any, must be used in order to comply with the emission limits.
3. The manufacturer is not responsible for any radio or TV interference caused by unauthorized modification to
this equipment. It is the responsibility of the user to correct such interference.

As an ENERGY STAR® Partner our company has determined that this product meets the ENERGY STAR®
guidelines for energy efficiency.

WARNING:

To prevent fire or chock hazard, do not expose the monitor to rain or moisture. Dangerously high voltages are
present inside the monitor. Do not open the cabinet. Refer servicing to qualified personnel only.

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PRECAUTIONS

Do not use the monitor near water, e.g. near a bathtub, washbowl, kitchen sink, laundry tub,
Swimming pool or in a wet basement.

Do not place the monitor on an unstable trolley, stand, or table. If the monitor falls, it can injure a person and
cause serious damage to the appliance. Use only a trolley or stand recommended by the manufacture or
sold with the monitor. If you mount the monitor on a wall or shelf, use a mounting kit approved by the
manufacture and follow the kit instructions.
Slots and openings in the back and bottom of the cabinet area provided for ventilation. To ensure reliable
operation of the monitor and to protect it from overheating, be sure these openings are not blocked or
covered. Do not place the monitor on a bed, sofa, rug or similar surface. Do not place the monitor near or
over a radiator or heat register. Do not place the monitor in a bookcase or cabinet unless proper ventilation
is provided.
The monitor should be operated only from the type of power source indicated on the label. If you are not
sure of the type of power supplied to your home, consult your dealer or local power company.
The monitor is equipped with a three-pronged grounded plug, a plug with a third (grounding) pin. This plug
will fit only into a grounded power outlet as a safety feature. If your outlet does not accommodate the
three-wire plug, have an electrician install the correct outlet, or use an adapter to ground the appliance
safely. Do not defeat the safety purpose of the grounded plug.
Unplug the unit during a lightning storm or when it will not be used for long periods of time. This will protect
the monitor from damage due to power surges.
Do not overload power strips and extension cords. Overloading can result in fire or electric shock.
Never push any object into the slot on the monitor cabinet. It could short circuit parts causing a fire or
electric shock. Never spill liquids on the monitor.
Do not attempt to service the monitor yourself; opening or removing covers can expose you to dangerous
voltages and other hazards. Please refer all servicing to qualified service personnel.
To ensure satisfactory operation, use the monitor only with UL listed computers which have appropriate
configured receptacles marked between 100-240V AC, Min. 3.5A.
The wall socket shall be installed near the equipment and shall be easily accessible.
For use only with the attached power adapter (output 12V DC) which have UL,CSA listed license

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SPECIAL NOTES ON LCD MONITORS

The following symptoms are normal with LCD monitor and do not indicate a problem.

NOTES

Due to the nature of the fluorescent light, the screen may flicker during initial use. Turn off the Power Switch
and then turn it on again to make sure the flicker disappears.
You may find slightly uneven brightness in the screen depending on the desktop pattern you use.
The LCD screen has effective pixels of 99.99% or more. It may include blemishes of 0.01% or less such as a
missing pixel or a pixel lit all of the time.
Due to the nature of the LCD screen, an afterimage of the previous screen may remain after switching the
image, when the same image is displayed for hours. In this case, the screen is recovered slowly by changing
the image or turning off the Power Switch for hours.

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Table of contents
Chapter 1 MONITOR FEATURE ………………………………………………………….9

Chapter 2 OPERATING INSTRUTION …………………………………………………….15

Chapter 3 Machine assembly ……………………………………………………………21

Chapter 4 TROBLE SHOOTING ………………………………………………………….27

Chapter 5 CONNECTOR INFORMATION ……………………………………………….29

Chapter 6 FRU LIST ………………………………………………………………………..30

Chapter 7 SCHEMATIC DIAGRAM …………………………………………………………31

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Chapter 1
Monitor Feature

Driving system TFT Color LCD


Size 20.1” wide
Pixel pitch 0.258 mm
Viewable angle 178(H) x 178 (V) degree
Brightness LG panel: 300 cd/m2(typ)
Contrast Ratio 600:1 (typ)
LCD Panel Response time 16ms (Tr+Tf)
Video R,G,B Analog & DVI box (optional)
Input Separate Sync H/V TTL
H-Frequency 31-81KHZ
V-Frequency 50-75HZ
Display Color 16.7 million Colors
Maximum Dot Clock ® 162MHz
Max Resolution 1680X1050@60HZ
Plug & Play VESA DDC2B
ON Mode <75W
EPA ENERGY STAY OFF Mode <3W
Audio output Rated Power 5.0W rms(Per channel)
Input Connector D-Sub 15 pin, or DVI-D cable
Input Video Signal Analog : 0.7Vp-p,75OHM
Horizontal : 433.4mm
Screen Size (Active) Vertical : 270.9mm
Power Source 90~240 Vac, 50~60HZ

Environmental Operating Temp : 5 to 40 degree ;


Considerations Storage Temp : -20 to 60 degree ;
Operating Humidity : 15% to 85%
Weight (N.W.) 6.8kg
Dimension 510.3(W) x 443.9(H) x 206.6D) mm

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* Power Switch
* MENU/ENTER
* / Volume
* / Volume
* Auto Adjust KEY
Switch

* Contrast/brightness
* Focus
* Clock
* H.Position
* W.Position
* Language
* OSD Color temperature
* OSD Position & Timeout
* Auto Config
* Input
* Information
Function * Reset
External Controls : * Exit
Regulatory Compliance cUL, FCC, TUV, CE, ISO13406-2

Timeings
The product has 29 memory modes in total. 19 modes are preset and 10 modes
are user definable.

MODE NO. 1 2 3 4
RESOLUTION 720 x 400 640 x 480 640x480 640 x 480

Dot clock(MHz) 28.321 25.175 30.24 31.5

fh 31.469kHz 31.469kHz 35.0kHz 37.861kHz

H-Total ( us ) 31.78(900dots) 31.778 (800 dots) 28.571(864 dots) 26.413 (832 dots)
H-Sync ( us ) 3.813(108dots) 3.813 (96 dots) 2.116 (64 dots) 1.270(40 dots)

H-B-P ( us ) 1.907(54dots) 1.907 (48 dots) 3.175 (96 dots) 4.064(128 dots)
H-Active ( us ) 25.42(720dots) 25.422 (640 dots) 21.164 (640 dots) 20.317(640 dots)

H-F-P ( us ) 0.636(18dots) 0.636 (16 dots) 2.116 (64 dots) 0.762(24 dots)

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fv 70Hz(70.087) 60Hz (59.940) 66.7 HZ (66.667) 72.809Hz
V-Total (ms ) 14.27(449 lines) 16.683 (525 lines ) 15.000 (525 lines ) 13.735(520 lines)

V-Sync ( ms ) 0.064(2 lines) 0.064 (2 lines ) 0.086 (3 lines ) 0.079(3 lines)


V-B-P (ms ) 1.112(35 lines) 1.049 (33 lines ) 1.114 (39 lines ) 0.739(28 lines)

V-Active ( ms ) 12.71(400 lines) 15.253 (480 lines ) 13.714 (480 lines ) 12.678(480 lines)
V-F-P ( ms ) 0.384(12 lines) 0.317 ( 10 lines) 0.086 (3 lines ) 0.237(9 lines)

SYNC. H/V -/+ -/- +/+ -/-


POLARITY Or -/-

SEP . SYNC Y Y Y Y

MODE NO. 5 6 7 8
RESOLUTION 640 x 480 800 x 600 800 x 600 800 x 600

Dot clock(MHz) 31.5 36 40 49.5

fh 37.500kHz 35.16kHz 37.879kHz 46.875kHz

H-Total ( us ) 26.667(840 dots) 28.44(1024 dots) 26.40 (1056 dots) 21.333 (1056dots)
H-Sync ( us ) 2.032 (64 dots) 2.00(72 dots) 3.200 (128 dots) 1.616 (80 dots)

H-B-P ( us ) 3.810 (120 dots) 3.56(128 dots) 2.200 ( 88 dots) 3.232 (160 dots)
H-Active ( us ) 20.317 (640 dots) 22.22(800 dots) 20.00 ( 800 dots) 16.162 (800 dots)

H-F-P ( us ) 0.508 (16 dots) 0.67(24 dots) 1.000 (40 dots) 0.323 (16 dots)

fv 75Hz (75) 56.25 60Hz (60.316) 75Hz (75.000)


V-Total (ms ) 13.333 (500 lines) 17.78(625 lines) 16.58 (628 lines) 13.333 (625lines)

V-Sync ( ms ) 0.080 (3 lines) 0.06(2 lines) 0.106 (4 lines) 0.064 (3 lines)


V-B-P (ms ) 0.427 (16 lines) 0.63(22 lines) 0.607 (23 lines) 0.448 (21 lines)

V-Active ( ms ) 12.80 (480 lines) 17.07(600 lines) 15.84 (600 lines) 12.80 (600lines)
V-F-P ( ms ) 0.027 ( 1 line ) 0.03( 1 line) 0.026 (1 line ) 0.021 (1 line )

SYNC. H/V -/- +/+ +/+ +/+


POLARITY

SEP . SYNC Y Y Y Y

MODE NO. 9 10 11 12
RESOLUTION 800 x 600 832 x 624 1024 x 768 1024 x 768

Dot clock(MHz) 50 57.283 65 75

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fh 48.077kHz 49.72kHz 48.363kHz 56.48kHz

H-Total ( us ) 20.80 (1040dots) 20.11(1152 dots) 20.677(1344 dots) 17.71(1328 dots)


H-Sync ( us ) 2.400 ( 120 dots) 1.12(64 dots) 2.092(136 dots) 1.81(136 dots)

H-B-P ( us ) 1.280 (64 dots) 3.91(224 dots) 2.462(160 dots) 1.92(144 dots)
H-Active ( us ) 16.00 (800 dots) 14.52( 832 dots ) 15.754(1024 dots) 13.65(1024 dots)

H-F-P ( us ) 1.120 (56 dots) 0.56(32 dots ) 0.369(24 dots) 0.32(24 dots)

fv 72Hz (72.188) 74.55Hz 60.004Hz 70.07Hz


V-Total (ms ) 13.85 (666 lines) 13.41(667 lines) 16.666(806 lines) 14.27(806 lines)

V-Sync ( ms ) 0.125 (6 lines) 0.06(3 lines) 0.124(6 lines) 0.11(6 lines)


V-B-P (ms ) 0.478 (23 lines) 0.78(39 lines) 0.600(29 lines) 0.51(29 lines)

V-Active ( ms ) 12.48 (600 lines) 12.55 (624 lines) 15.880(768 lines) 13.60(768 lines)
V-F-P ( ms ) 0.770 ( 37 line ) 0.02(1 line) 0.062(3 lines) 0.05(3 lines)

SYNC. H/V +/+ +/+ -/- -/-


POLARITY

SEP . SYNC Y Y Y Y

MODE NO. 13 14 15 16
RESOLUTION 1024 x 768 1280 x 1024 1280 x 1024 1152 x 864

Dot clock(MHz) 78.75 108 135 108

fh 60.02kHz 63.981kHz 79.976KHz 67.5 KHz

H-Total ( us ) 16.66(1312 dots) 15.630 (1688 dots) 12.504 (1688 dots) 14.815(1600 dots)
H-Sync ( us ) 1.22 (96 dots) 1.037 (112 dots) 1.067 (144 dots) 1.185(128 dots)

H-B-P ( us ) 2.23 (176 dots) 2.296 (248 dots) 1.837 (248 dots) 2.370(256 dots)
H-Active ( us ) 13.00 (1024 dots) 11.852 (1280 dots) 9.481 (1280dots) 10.667(1152 dots)

H-F-P ( us ) 0.20 (16 dots) 0.444 (48 dots) 0.119 (16 dots) 0.593(64 dots)

fv 75.03Hz 60.020Hz 75.025 Hz 75.06 Hz


V-Total (ms ) 13.33 (800 lines) 16.661 (1066 lines) 13.329 (1066 lines) 13.333(900 lines)

V-Sync ( ms ) 0.05 (3 lines) 0.047 ( 3 lines) 0.038 (3 lines) 0.044(3 lines)


V-B-P (ms ) 0.47 (28 lines) 0.594 ( 38 lines) 0.475 (38 lines) 0.474(32 lines)

V-Active ( ms ) 12.80 (768 lines) 16.005 (1024 lines) 12.804(1024 lines) 12.800(864 lines)
V-F-P ( ms ) 0.02 (1 lines) 0.016 (1 line ) 0.013 (1 lines) 0.015(1 lines)

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SYNC. H/V -/- +/+ +/+ +/+
POLARITY

SEP . SYNC Y Y Y Y
17"
MODE NO. 17 18 19 20
RESOLUTION 1280 x 960 1600 x 1200 1280 x 720

Dot clock(MHz) 108 162 74.176

fh 60.000 KHz 75.000 KHz 44.955KHz

H-Total ( us ) 16.667 (1800dots) 13.333 (2160 dots) 22.244 (1650dots)


H-Sync ( us ) 1.037 ( 112 dots) 1.185 ( 192 dots) 0.539 ( 40 dots)

H-B-P ( us ) 2.889 (312 dots) 1.877 (304 dots) 2.966 (220 dots)
H-Active ( us ) 11.852 (1280 dots) 9.877 (1600 dots) 17.256 (1280 dots)

H-F-P ( us ) 0.889 (96 dots) 0.395 (64 dots) 1.483 (110 dots)

fv 60.00Hz 60.00 Hz 59.94Hz


V-Total (ms ) 16.667 (1000 lines) 16.667 (1250 lines) 16.683 (750 lines)

V-Sync ( ms ) 0.050 (3 lines) 0.040 (3 lines) 0.111 (5 lines)


V-B-P (ms ) 0.600 (36 lines) 0.613 (46 lines) 0.445 (20 lines)

V-Active ( ms ) 16.000 (960 lines) 16.000 (1200 lines) 16.016 (720 lines)
V-F-P ( ms ) 0.017 ( 1 line ) 0.013 ( 1 line ) 0.111 (5 lines)

SYNC. H/V +/+ +/+ +/+


POLARITY

SEP . SYNC Y Y HDTV

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Monitor Block Diagram

+3.3V_I/O_MALIBU +2.5V_DDR +3.3V_LVDSA +1.8V_DVI +1.8V_ADC +3.3V_PLL POWERSWITCH


AIC1563(U2)
+1.8V_CORE +3.3V_LBADC +3.3V_LVDSB +3.3V_LVDS +3.3V_DVI +3.3V_ADC (U3) +2.5V
DIGITALDDC (U4) +3.3V
24AA02 (U12) +12VFROM
(U6) +1.8V
POWERBOARD
SDA/SCL
DVI INPUT
( CN8) RX2, RX1, RX0 , RXC /RESET
RESET MAX809_1(U8)
ANALOGDDC
24AA02 (U10)
GM1601 (U5) I2C
MSTRSCL/SDA 24LC32SN(U7)
SDA/SCL
VGAINPUT
( CN7 ) RED, GREEN, BLUE, SDA/SCL

FSDATA,FSADDR,FSBKSEL0/1 FRAMESTORE
FSCLK-/+,FSDQM MT46V2M32LG-4( U1)

TXA0+/-, TXA1+/-, TXA2+/-,TXA3+/-, TXAC+/- TOPANEL


MEMORYI/F TXB0+/-,TXB1+/-, TXB2+/-, TXB3+/-, TXBC+/- (CN2)
39VF020( XU1) OCMADDR[0..19],OCMDATA[0..7]

KEYCONTROL
LBADC_RETURN/ IN1 / IN2 / IN3 (CN4)

MUTE PWM1

VOLUME

AUDIOIN( L/R) SPKR0+/-


AUDIO SPEAK
TPA3002D2( U9) ( CN6)
SPKL0+/-

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PCB CONDUCTOR VIEW
Main Board

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Button Board

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Chapter 2
OPERATING INSTRUCTIONS

Front Panel Definition


This Section defines the front panel User Interface for Led Indictor and Key function.
Key Definition:
There are five keys defined in this system and described bellows.
* Adjusting display settings

External Controls
Power on/off

1 POWER Blue: power on
Orange: in sleep mode

OSD Press to view OSD.



2
Function Press again to enter a selection in OSD.

If OSD is active, press to select or adjust OSD options. If OSD



3 UP/ PLUS is inactive, press once, then press the buttons marked or
to adjust the volume.

If OSD is active, press to select or adjust OSD options. If OSD


DOWN /

4
MINUS
is inactive, press once, then press the buttons marked or
to adjust the volume.

If OSD is active, press to exit a selection in OSD. If OSD is



5 AUTO inactive, press and the monitor will automatically optimize the
position, focus and clock of your display.

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OSD Menu

Picture
Brightness:
This adjusts the brightness of the picture on the screen.
Contrast:
This adjusts dark and light shades of color relative to each other to
achieve a comfortable contrast.
Color temp. :
There are three ways of adjusting color:
Warm (Reddish white)
Cool (Bluish white)
User : You can adjust the colors red, green and blue to the intensity
you desire.
Focus:
This removes any horizontal distortion and makes the picture clear
and sharp.
Clock:
If there are any vertical stripes seen on the background of the screen
this renders them less noticeable by minimizing their size. It also
changes the size of the horizontal screen.
H-Position:
This adjusts the horizontal screen position.
V-Position:
This adjusts the vertical screen position.

Audio
Volume: Adjusts the volume.

Mute : on /off

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Option
Auto Config. :
System runs auto-configuration.
Reset:
Recall to default settings.

Information:
This shows brief information on the screen.

Setting
Language:
Select the OSD menu language from
English, French, German, Italian, Spanish, Simplified Chinese,
Traditional Chinese, Japanese and Russian.
OSD H. Position
OSD V. Position
OSD Time-out
This changes the position of the OSD window on the screen and staying
time.

LED Definition
The system equips one dual color (blue/amber) led to indict system status and defined as bellows :

LED Color System Status

Blue System in normal operation mode

Amber System in power-saving mode

Dark System in power-off mode

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LOGO :
When the monitor is power on, the LOGO will be showed in the center, and disappear slowly.

HOW TO OPTIMIZE THE DOS-MODE

Plug and play

Plug & play DDC2B feature

This monitor is equipped with VESA DDC2B capabilities according to the VESA DDC STANDARD. It allows the
monitor to inform the host system of its identity and, depending on the level of DDC used, communicate
additional information about its display capabilities. The communication channel is defined in two levels, DDC2B.
The DDC2B is a bi-directional data channel based on the I2C protocol. The host can request EDID information
over the DDC2B channel.

THIS MONITOR WILL APPEAR TO BE NON-FUNCTIONAL IF THERE IS NO VIDEO INPUT SIGNAL. IN


ORDER FOR THIS MONITOR TO OPERATE PROPERLY, THERE MUST BE A VIDEO INPUT SIGNAL.

This monitor meets the Green monitor standards as set by the Video Electronics Standards Association(VESA)
and/or the United States Environmental Protection Agency (EPA) and The Swedish Confederation Employees
(NUTEK). This feature is designed to conserve electrical energy by reducing power consumption when there is
no video-input signal present. When there is no video input signal this monitor, following a time-out period, will
automatically switch to an OFF mode. This reduces the monitor’s internal power supply consumption. After the
video input signal is restored, full power is restored and the display is automatically redrawn. The appearance is
similar to a “Screen Saver” feature except the display is completely off. The display is restored by pressing a key
on the keyboard, or clicking the mouse.

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USING THE RIGHT POWER CORD

The accessory power cord for the Northern American region is the wallet plug with NEMA 5-15 style and is UL
listed and CSA labeled. The voltage rating for the power cord shall be 125 volt AC.
Supplied with units intended for connection to power outlet of personal computer: Please use a cord set
consisting of a minimum No. 18 AWG, type SJT or SVT three conductors flexible cord. One end terminates with a
grounding type attachment plug, rated 10A, 250V,CEE-22 male configuration. The other end terminates with a
molded-on type connector body, rated 10A, 250V, having standard CEE-22 female configuration.
Please note that power supply card needs to use VDE 0602, 0625, 0821 approval power cord in European
counties.

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Chapter 3
Machine assembly
This chapter contains step-by-step procedures on how to assemble the monitor for
maintenance and trouble shooting
NOTE : 1. The screws for the different components vary in size. During the disassembly process, group the
screws with the corresponding to avoid mismatch when putting back the components.
2. Note : The monitor surface is susceptible to scratching! Therefore, lay the monitor on a soft surface
when mounting or removing the base.
3. Wear gloves.

Front View : ( unit : mm )

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Real View :

Top View :

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Side View : ( unit : mm )

Assembly process
Picture Description

1. Get the panel and put it on the table


carefully.

1. Fix left and right bracket (BKT) on the


panel.

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1. Get bezel and put it on the table
2. Assemble panel into bezel

1. Lock screw * 3 pcs to fasten bezel and


left side bracket (BKT)

.
2. Lock screw * 3 pcs to fasten bezel and
right side bracket (BKT).

1. Insert LCD cable in panel connector

1. Assemble speaker on the bezel

1. Tidy speaker cable as picture shows.

1. Assemble PCB BKT on the L/R of BKT


2. Tidy cable as picture shows

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1. Get inverter and insert cable

2. Insert button cable in main board


connector

1. Lock 4*pcs screw to fasten m/b and


PCB BKT

1. First to lock 4*pcs screw to fasten


Inverter board on the PCB BKT

2. Get m/b and insert speaker cable, then


assemble it on the

1. Lock 4 pcs screw to fasten m/b on the


pcb BKT

1. Insert INV-M/B cable, then tidy button


cable and inv-m/b

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1. Lock screw*2pcs to fasten panel hold

1. insert LCD cable in m/b connector

1. Assemble shielding and pcb BKT


2. Lock 7pcs screw to fasten shielding
3. Insert ccft cable L/R of into inverter/b
connector

1. Stick al foil *2pcs on ccft connector of


pcb shielding

1. Lock io nut 2pcs in VGA connector

1. Assemble button/b and back cover

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1. Insert button/b cable in button/b
connector

1. Assembly back cover and bezel


2. Lock screw * 6 pcs to fasten and back
cover

1. Lock screw*2 pcs to fasten bezel and


PCB shielding.

2. Assembly DVI box, if necessary.

1. Assembly stand base and back cover.


2. lock screw *6 pcs to fix it.

1. Assembly VESA cover and back cover.

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Chapter 4

TROUBLE SHOOTING

This chapter provides trouble shooting information forAL2032

1. No Power
No Power

Check Adaptor Power NO


Change Adaptor Power
Output =18V
Board

OK

Check Scalar Module

Output

L4 =5V? NO
Change Scalar Module Board
U4 #2 = 3.3V ?

L 13 = 1.8V ?

OKKK

Check Power Button NO


Check Cable Yes
Change Cable
From Scalar/B(CN5) Open ?

to Button/B(CN1)

NO

Change Switch or Button Board

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2. No Characters , Missing one color

NoCharacters
Missing one color

Check CN4 No
Change Adaptor
12Vdc Output

OK

Check L4 No Check or Change


5Vdc Output U2 , Q6 , D3

OK

Check U6(pin2) No Check or Change


1.8Vdc Output U6

OK

Check U4(pin2) No Check or Change


3.3Vdc Output U4

OK

No Check Inverter From Check CN2 to Panel


Change Inverter Board
Scaler board OK ? Signal Output

No OK
No
Check or Change Check X  
Tal
Change X1
Cable Or Panel 14.318 Mhz ?

OK

No Check H , V
Change VGA Cable
SYNC ?

OK

Change U5

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3. No audio

No Audio

No
Check Input source Check Input Signal

Or Change CN9 CN9 OK ?

OK

No
Check CN6 to Speaker Change Speaker or

OK ? CN6(Cable)

OK

No
Check U12(Pin9)
Change U12 or U9
& U9 OK ?

OK

Check U9Pin1(Mute)
No
Change Q9 or U9
& Q10 & U9 OK ?

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Chapter 5
Connector Information
Phonejack stereo
PIN1. AC power cord : CEE22 typed connector
PIN2. Audio cable
PIN3. Audio : Line-in receptacle

J1
1

2
3

PHONEJACK STEREO

Video signal connector 15P Mini D-Sub connector x 1

CN6
10
1
6
2
7
3
8
4
9
5

DB15HD
16 17
11

12

13

14

15

PIN MNEMO SIGNAL


1 RV Red Video
2 GV Green Video
3 BV Blue Video
4 NC None
5 GND Ground(DDC return)
6 RG Red GND
7 GG Green GND
8 BG Blue GND
9 +5V + 5V (for DDC)
10 SG Sync GND
11 NC None
12 SDA DDC Data
13 HS Horizontal Sync
14 VS Vertical Sync
15 SCL DDC Clock

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Proprietary connecting of DVI box
The 44 pin of proprietary DVI box is defined as follows:

1 RX2- 23 SCART_FUNC
2 RX2+ 24 KEY3
3 RX1- 25 SCART
RGB_CON
4 RX1+ 26 SCL5V
5 RX0- 27 nYCOEN
6 RX0+ 28 SDA5V
7 RXC- 29 NVDSW_SEL
8 RXC+ 30 HSCL
9 GND 31 REST
10 GND 32 HSDA
11 Y0 33 DVI_ DETECT
12 Y1 34 CORD_ RESET
13 Y2 35 CORD_DETECT
14 Y3 36 ADO_L
15 Y4 37 DETECT
16 Y5 38 AGND
17 Y6 39 IR0
18 Y7 40 ADO_R
19 LLC VPC 41 V51R
20 KEY1 42 GND
21 GND 43 V12
22 KEY2 44 V12

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Chapter 6
FRU (Field Replaceable Unit) list

This chapter gives you the FRU (Field Replaceable Unit) listing in global configurations of AL2032W. Refer to this
chapter whenever ordering for parts to repair or for RMA (Return Merchandise Authorization).
NOTE : Please note WHEN ORDERING FRU PARTS, that you should check the most up-to-date information available on
your regional web or channel(http://aicsl.acer.com.tw/spl/). For whatever reasons a part number change is made, it
will not be noted in the printed Service Guide. For ACER-AUTHORIZED CERVICE PROVIDERS, your Acer
office may have a DIFFERENT part number code to those given in the FRU list of this printed Service Guide. You
MUST use the local FRU list provided by your regional Acer office to order FRU parts repair and service of
customer machines.
NOTE: To scrap or to return the defective parts, you should follow the local government ordinance or regulations on how
best to dispose it, or follow the rules set by your regional Acer office on how to return it.

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AL2032W Exploded Diagram

35 Chapter 6

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Chapter 7
SCHEMATIC DIAGRAM
Main Board Circuit

+1.8V_CORE

V
5 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/
2/ V
F 5 F 6/ F F F 6/ F F 6/ F F
u 2/ u u u 6/ u 6/ u u 6/ u u
7 1 F 0 1 11 51 F 7 1 61 F 3 1 61
8 2 F
4 0. u 5 0. 4 0. F 3 0. u F 3 0. 3 0.
F u 5 0. 4 0.
5 2 u 4 1. 1 1 u 1 0 1. u 1 1
u 5 1. 1 1
C 7 22 1 5 8 1 4 91 2 1
5 C 10 C C 3 0. C 1 0 3 0. C C 2 . 4
10 C C
C C 1 C 1 1 0 C
C C C +3.3V_LBADC CN8
+1.8V_DVI
GND +2.5V_DDR +3.3V_I/O_MALIBU +2.5V_DDR 1 2
+1.8V_CORE +3.3V_LVDSB +3.3V_LVDSA +3.3V_LVDS FSVREF +3.3V_DVI +1.8V_ADC+3.3V_ADC +3.3V_PLL RX2- 1 2 RX2+
3 4
RX1- 3 5 4 6 RX1+
RX0- 5 7 6 8 RX0+
6/ 6/ 6/ 6/ RXC- 7 9 8 10 RXC+
V V 6/ 6/ U5
5 5 6/ 6/ F 6/ F 6/ 6/ 6/ F 6/ 6/ F 9 11 10 12
2/ 2/ u u 6/ u 0 333
F F 9 1. F 0 1. F F F 8 1u. F
2 1. 7 71 11 6 6 7 1 0 6 1 61 01 1 3 7 3 C4 C6 C8 C1 22 A4 4 B4 4 31 3 3 32 3 3 3 3 32 3 2 2 2 23 3 3
2 23 021 7 Y0 11 12 Y1
F F u F u 2 u 2 u u u F F u
0 1.
F
1111111 12 22 2 2 2 2 2ABC 2 2
1 11 222 1 4 52 0 10 13 14
u u 4 1 u 3 1
2 0. 10 1 1 10 9 1 01
3 0. 6 1 2 0 7 1u 6 1u u 4 0 1 1 2 CDD DCC E 2 6 8 91 11986 34 23 3 3 4 21 31 31 GM1601 Y2 13 14 Y3
7 22 5 22 2 0. 51
2 0. 2 0. 1 0. 1 . 1 2 0. 2 0.
4 0 8 1. C K UU L T T L K K T U U KK D D A A A A D AWA YC H J M P L T V R Y A A AWF E AAA AAA A JW DDDD CCCCC AA ABDE F FGHH J J 15 16
3 4 1 1 1 C 1 C 1 1 1 0 C 1 1 C 10
1 416PBGA Y4 15 17 16 18 Y5
C C C C C C C C C Y6 17 18 Y7
C C C 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. L 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 3. 3. 3. 3. 3. 3. S FF 8. 8. 8. 8. 3. 3. 3. 3. 3. 8. 8. 3. 3. 3. 3. LL LSSSS 19 20
GND 1_ 1_ 1_ 1_ 1_ 1_ 1_ 1_ 1_ 1_ 1_ 1_ 1_ DL 3_ 3_ 3_ 3_ 3_ 3_ 3_ 3_ 3_ 3_ 3_ 3- 2_ 2_ 2_ 2_ 2_ 2_ 2_ 2_ 2_ 2_ 2_ 2_ 2_ 2_ 2_ 3_ 3_ 3_ 3_ 3_ 3_ D EE 1_ 1_ 1_ 1_ 3_ 3_ 3_ 3_ 3_ 1_ 1_ 3_ 3_ 3_ 3_ LL L FSDATA[0..31] LLC_VPC KEY1
+3.3V_I/O_MALIBU V RR PPPDDD D FSDATA[0..31] 5 19 21 20 22
EEEEEEEEEEEEE_ D
OI OI OI OI OI OI OI OI OI OI OI C SSSSSSSSSSSSSSS BBB AAA L_ VV I I I I I I I I I CC CCCC R_ 3_ F_ DS SD D
DD E24 21 23 22 24 KEY2
R R R R R R R R R R R R R 81 A FFFFFFFFFFFFFFF SSS SSS 3 SS VVVV
DDDD
VVVVV
DDDDD DD DDDD
D
3 A3 33 _3 _3 _3 _3 FSDATA0 E25 FSDATAU0 FSDATAU0 RN11 1 8 FSDATA0 SCART_FUNC 23 24 KEY3
OOOOOOOOOOOOOA B DDD DDD 3 FF AA AAAA 3 25 26
6/ 6/ N4 CCCCCCCCCCCCCD L VVV VVV D ADA3 3 3 3 FSDATA1 E26 FSDATAU1 FSDATAU1 33 2 7 FSDATA1 SCART_RGB_CON 25 27 26 28
MSTR_SCL
6/ F 6/ 6/ F R170 0/6/NC N3 DVI_SCL D L LL L LL
D D D D DA AD DA AD FSDATA2 G26 FSDATAU2 FSDATAU2 3 6 FSDATA2 nYCOEN 27 28 MSTR_SDA
u 6/ 6/ 6/ u R171 0/6/NC V D DVD 29 30
V V 6/ 6/ F 1. F F F 1. A8 DVI_SDA V V DV VD DV VD FSDATA3 G24 FSDATAU3 FSDATAU3 4 5 FSDATA3 nVDSW_SEL 29 30 TT_I2CSCL
5 5 F 6/ u u u F F u V 8 31 32
F 4 0 u u RN12 1
2/ 2/ u u F 31 1. 1. 1. 1. 1. 3 0 RX0+ B8 RX0+ FSDATA4 H26 FSDATAU4 FSDATAU4 FSDATA4 nRESET 31 32 TT_I2CSDA
4 1 7 1. u 7 0. 3 6 33 2 7 33 34
6F
4 u
5F
5u 6 0. 60 2 1. 1 1 70 5 0 10 8 0 00 1 RX0- A9 RX0- FSDATA5 H24 FSDATAU5 FSDATAU5
6
FSDATA5 DVI DETECT 33 35 34 36
CARD_RESET
1 1 7 C 1 1 5 5 6 C RX1+ FSDATA6 J25 3 ADO_L 8
C 22 C 22 C C 1 0 C 1 1 1 1 1 RX1+ B9 FSDATAU6 FSDATAU6
58
FSDATA6 CARD DETECT 35 36
38
C C C C C C RX1- A10 RX1- FSDATA7 T26 FSDATAU7 FSDATAU7 RN74 1 FSDATA7 TVBOX_DETECT 37 37 38
39 40 ADO_R 8
RX2+ B10 RX2+ FSDATA8 R25 FSDATAU8 FSDATAU10 33 2 7 FSDATA10 IR1
GND
RX2- A6 RX2- FSDATA9 P24 3 6 41 39 40 42
FSDATAU9 FSDATAU11 FSDATA11
+1.8V_DVI +3.3V_DVI RXC+ RXC+ FSDATA10 P26 4 5 V5IR 43 41 42 44
B6 FSDATAU10 FSDATAU9 FSDATA9 43 44
RXC- D5 RXC- FSDATA11 N24 FSDATAU11 FSDATAU8 FSDATA8
C5 NO_CONNECT FSDATA12 N26 FSDATAU12 FSDATAU14 RN6 1 8 FSDATA14
B11 NO_CONNECT FSDATA13 M25 FSDATAU13 FSDATAU15 33 2 7 FSDATA15 V12
6/ 6/ +3.3V_DVI 3 1841 44P
F 6/ 6/ 6/ R54 249R/6 1% REXT FSDATA14 L24 FSDATAU14 FSDATAU12 6 FSDATA12 GND
6/ 6/ V F 6/ 6/
u F 5 F u F FSDATA15 L25 FSDATAU15 FSDATAU13 RN134 1 58 FSDATA13 GND
1 1. F
u u F
u 2/ u 3 1. F F u
6 4 u u 33 2 7
1 0 91 6 1
5 . 21 4F 7 1
5 . 10 9 1 51 2 1
6 . 3 BLUE- B1 FSDATA16 M26 FSDATAU16 FSDATAU16 FSDATA16 AGND
C 5 0. 1 0 5 0. 5u 1 0 C 4 0. 5 0. 1 0 B2 BLUE- FSDATA17 M24 FSDATAU17 FSDATAU17 3 6 FSDATA17
1 1 1 1 3 BLUE+
C C C C 22 C C C C TXD
R131 0/6
C1 BLUE+ FSDATA18 N25 FSDATAU18 FSDATAU18 4 5 FSDATA18 FSBKSEL1 5
3 GREEN- C2 GREEN- FSDATA19 N23 FSDATAU19 FSDATAU19 RN9 1 8 FSDATA19
GND GND RXD R132 0/6 GREEN+ FSDATA20 P25 FSDATAU20 FSDATAU20 33 2 7 FSDATA20
3 GREEN+ D1
3 RED- D2 RED- FSDATA21 R26 FSDATAU21 FSDATAU21 3 6 FSDATA21 FSBKSEL0 5
3 RED+ C3 RED+ FSDATA22 R24 FSDATAU22 FSDATAU22 4 5 FSDATA22
3 SOG A1 SOG FSDATA23 K24 FSDATAU23 FSDATAU23 FSDATA23
+3.3V_PLL N2 NO_CONNECT FSDATA24 J26 FSDATAU24 FSDATAU28 RN5 1 8 FSDATA28
+3.3V_PLL 3 VGA_SCL N1 VGA_SCL FSDATA25 H25 FSDATAU25 FSDATAU26 33 2 7 FSDATA26
22pF/6 3 VGA_SDA L4 VGA_SDA FSDATA26 G23 FSDATAU26 FSDATAU25 3 6 FSDATA25
C67 3 AHS
C68 L3 AHSYNC FSDATA27 G25 FSDATAU27 FSDATAU24 RN44 1 58 FSDATA24
22pF/6 R4 AVSYNC FSDATA28 F24 FSDATAU28 FSDATAU29 33 2 7 FSDATA29
3 AVS
EXTCLK FSDATA29 F25 FSDATAU29 FSDATAU30 3 6 FSDATA30
FSDATA30 F26 FSDATAU30 FSDATAU31 4 5 FSDATA31
X1 14.318MHz FSDATA31 FSDATAU31 FSDATAU27 FSDATA27
G4
XTAL G3 XTAL FSADDR[0..11] 5
TCLK F1 TCLK FSADDRU6 RN3 1 8 FSADDR6
2 7
K3 NO_CONNECT AD25 FSADDRU5 33 FSADDR5
Route (VIN1/ADC_IN1, ADC1_RETURN) and FSADDRU0 FSADDRU4 3 6 FSADDR4
K2 NO_CONNECT FSADDR0 AD26
R77 3K3/6 ACS_RSET_HD ACS_RSET_HD FSADDR1 AC24 FSADDRU1 FSADDRU9 4 5 FSADDR9
(VIN2/ADC_IN2, ADC2_RETURN) as differential
C19 FSADDR2 AC25 FSADDRU2 FSBKSELU1 RN2 1 8 FSBKSEL1
tracks close to each other and ground the B19 VRED0 FSADDR3 AB26 FSADDRU3 FSBKSELU0 33 2 7 FSBKSEL0
return track of each pair very close to the GND VRED1 FSADDR4 AA24 FSADDRU4 FSADDRU8 3 6 FSADDR8
A19
D18 VRED2 FSADDR5 AA25 FSADDRU5 FSADDRU7 4 5 FSADDR7
Malibu D12 ball and ground pin VRED3 FSADDR6 FSADDRU6
C18 AA26
Optional Filter Caps in between a pair on LBADC differential tracks close B18 VRED4 FSADDR7 Y24 FSADDRU7 FSADDRU0 R36 33R/6 FSADDR0
to the Malibu chip A18 VRED5 FSADDR8 AB25 FSADDRU8 FSADDRU1 RN8 R35 33R/6 FSADDR1
1 8
C17 VRED6 FSADDR9 AC26 FSADDRU9 FSADDRU11 FSADDR11
2 7
VRED7 FSADDR10 AB24 FSADDRU10 FSADDRU10 33 FSADDR10
3 6
R78 A23 FSADDR11 FSADDRU11 FSADDRU3 FSADDR3
4 5
10K/6 C22 VGRN0 U24 FSADDRU2 FSADDR2
B22 VGRN1 FSCLKp U23 FSCLKU+ FSCLK+ FSCLK+ 5
A22 VGRN2 FSCLKn FSCLKU- FSCLK- FSCLK- 5
GND D21 VGRN3 L26
C21 VGRN4 FSDQS FSDQSU R34 33R/6
FSDQS 5
B21 VGRN5 T25
A21 VGRN6 FSDQM0 U25 FSDQMU0
FSDQM[0..3] 5
VGRN7 FSDQM1 U26 FSDQMU1 Place Series term ination resistors on all address and
B25 FSDQM2 T24 FSDQMU2 /FSWEU RN10 1 8 /FSWE control lines (RN601,RN603,RN605) very close to U600
/FSWE 5 5
/FSRAS
A25 VBLU0 FSDQM3 V26 FSDQMU3 /FSRASU 33 2 7 /FSRAS
3 /FSCAS 5
D24 VBLU1 FSWE V25 /FSWEU /FSCASU 6 /FSCAS
C24 VBLU2 FSCAS V24 /FSCASU FSCKEU 4 5 FSCKE FSCKE 5
B24 VBLU3 FSRAS W26 /FSRASU FSDQMU0 RN1 1 8 FSDQM0 Unloaded trace im pedance on this interface is 90 Ohm
A24 VBLU4 FSCKE Y25 FSCKEU FSDQMU3 33 2 7 FSDQM3 Loaded trace im pedace w ith DRAM load is 65 Ohm (for 2.5 inch total trace
C23 VBLU5 FSBKSEL0 Y26 FSBKSELU0 FSDQMU1 3 6 FSDQM1
VBLU6 FSBKSEL1 FSBKSELU1 FSDQMU2 4 5 FSDQM2 length)
B23
VBLU7
A20
R37 B20 VCLK Place Series term ination resistors on bidirectional lines-DATA and DQS
10K/6 C20 VODD (RN600,RN602,RN604,RN606,R605) m idw ay betw een U600 anf U700
D19 VVS AC18
D20 VHS_CSYNC GPIO_G06_B0 AD18
Max trace length on this interfce is 2.5 inches
GND B17 VDV GPIO_G06_B1 AE18
Minim ize trace length difference betw een DQS and data and
VCLAMP GPIO_G06_B2 AF18
C26 GPIO_G06_B3 AE19 am ong the data lines
7 PWM0 PWM0 C25 PWM0 A3+ AF19 TXA3+
T105 PWM1 TXA3-
7 PWM1 T106 D26 PWM1 A3- AE20
D25 PWM2 AC+ AF20 TXAC+ R603, R604 very close to U600
OCM_TIMER1 AC- TXAC-
A12 FSCLK+, FSCLK- should be routed like a differentail pair
GND B12 LBADC_IN3 AD21
SCART_FUNC C12 LBADC_IN2 GPIO_G05_B0 AD22
SCART_RGB_CON
GND D12 LBADC_IN1 GPIO_G05_B3 AE21
TXA2+ +3.3V_DIG
LBADC_RETURN A2+ AF21
C16 A2- AE22 TXA2-
Y0 B16 SVDATA0 A1+ AF22 TXA1+
Y1 A16 SVDATA1 A1- AE23 TXA1-
CN3 +5V Y2 TXA0+
D15 SVDATA2 A0+ AF23 R173
Y3 C15 SVDATA3 A0- TXA0-
1
TXD Y4 B15 SVDATA4 AD23 +3.3V_DIG
2 T101 10K/6
RXD Y5 A15 SVDATA5 GPIO_G04_B0 AD24 MENU
3
Y6 D14 SVDATA6 GPIO_G04_B1 AE24 SEL
4 PWR
Y7 SVDATA7 GPIO_G04_B2 AF24
T103 DOWN
A17 GPIO_G04_B3 AF25
4606-04-04P-R/NS T102 A14 SVDV GPIO_G04_B4 UP
AF26
B14 SVODD GPIO_G04_B5 AE25 LED_G
GND T104 LED_R +3.3V_DIG
C14 SVVSYNC GPIO_G04_B6 AE26 ADO_C 8 R128 R33
D16 SVHSYNC GPIO_G04_B7 ADO_C
LLC_VPC SVCLK AE8 nYCOEN 10K/6 10K/6
GPIO_G07_B0 AF8 nVDSW_SEL
GPIO_G07_B1 R172
M1 AC9
M2 OCM_UDO GPIO_G07_B2 nRESET
AD9 DVI DETECT 10K/6
OCM_UDI GPIO_G07_B3 AE9
GPIO_G07_B4 CARD DETECT
AF9 CARD_RESET
K1 GPIO_G07_B5 AD10
/RESET TVBOX_DETECT
M4 /RESET GPIO_G07_B6 AE10 TUNER12V_KEY TUNER12V_KEY 7
IR1 M3 IR1 GPIO_G07_B7
GND IR0 P4 IR0
MSTR_SCL MSTR_SCL MSTR_SCL
MSTR_SDA P3 AF10
MSTR_SDA MSTR_SDA LVDS_SHIELD[0] AC11
LVDS_SHIELD[1] AD11
LVDS_SHIELD[2] AE11
R3 LVDS_SHIELD[3] AF11
6 /OCM_WE /OCM_WE R2 /OCM_WE B3+ TXB3+
/OCM_RE AF12 TXB3-
6 /OCM_RE R1 /OCM_RE B3- AE12
T107/OCM_CS /ROM_CS BC+ TXBC+
6 /ROM_CS L1 AF13
T108 L2 /OCM_INT2 BC- TXBC-
T109 /OCM_INT1
P2
T110 /OCM_CS2
P1
T111 T4 /OCM_CS1 AE13
/OCM_CS0 LVDS_SHIELD[4] AD14
FSVREF LVDS_SHIELD[5] AF14
6 OCMADDR[0..19] B2+ TXB2+
+1.8V_ADC OCMADDR19 T3 AE14 TXB2-
OCMADDR19 B2- AF15
OCMADDR18 T2 OCMADDR18 B1+ TXB1+
OCMADDR17 T1 AE15 TXB1-
C38 OCMADDR17 B1- AF16
C39 OCMADDR16 U4 OCMADDR16 B0+ TXB0+
C63 C62 OCMADDR15 U3 AE16 TXB0-
0.1uF/6 OCMADDR15 B0-
0.1uF/6 OCMADDR14 U2 OCMADDR14
0.1uF/6 0.1uF/6 OCMADDR13 U1 OCMADDR13 CN2
OCMADDR12 V4 OCMADDR12 AC7 T115
OCMADDR11 V3 R48 0/6 +3.3V_DIG TXA0- 1 2 TXA0+
GND OCMADDR11 DCLK AF17 T116 1 2
+3.3V_ADC OCMADDR10 V2 OCMADDR10 GPIO_14/DHS TXA1- 3 4 TXA1+
GND AD16 5 3 4
OCMADDR9 V1 OCMADDR9 GPIO_15/DVS R59 10K/6 TXA2- 6 TXA2+
AD7 7 5 6 8
OCMADDR8 W3 OCMADDR8 GPIO_16/DEN MUTE MUTE 8 +3.3V_LVDS
9 7 8 10
OCMADDR7 W2 OCMADDR7 TXAC- 9 10 TXAC+
C70 C168 C175 C171 C169 OCMADDR6 W1 +3.3V_LVDS TXA3- 11 12 TXA3+
Y3 OCMADDR6 +3.3V_DIG 11 12
OCMADDR5 OCMADDR5 TXB0- 13 14 TXB0+
22uF/25V 0.1uF/6 0.1uF/6 0.1uF/6 0.1uF/6 Y2 15 13 14 16
OCMADDR4 OCMADDR4 R52 2K7/6 15 16
Y1 AD8 17 18
OCMADDR3 OCMADDR3 GPIO_G08_B5/JTAG_RESET JTAG_TRST TXB1- 17 18 TXB1+ C
OCMADDR2 AA3 AF7 R15 TXB2- 19 20 TXB2+ N/
OCMADDR2 GPIO_G08_B4/JTAG_TDO AE7 19 20 64/
+3.3V_PLL OCMADDR1 AA2 10K/6/NC TXBC- 21 22 TXBC+
OCMADDR1 GPIO_G08_B3 AF6 21 22 K1
GND OCMADDR0 AA1 OCMADDR0 GPIO_G08_B2/JTAG_TDI TXB3- 23 24 TXB3+ R10
AE6 25 23 24 26
GPIO_G08_B1/JTAG_MODE AD6 25 26
GPIO_G08_B0/JTAG_CLK R129 0/6/NC 27 28 LCDVCC
6/ 6/ AF5 +3.3V_DIG R130 0/6/NC 29 27 28 30
C77 6/ 6/ 6/ GPIO_G09_B5 TT_I2CSDA +5V +3.3V_DIG LCDVCC
6/ F 6/ F AB3 AE5 29 30
F u F F u F F KEY1 OCMDATA15 GPIO_G09_B4 TT_I2CSCL
u u u AB2 AD5 R63 10K/6 3
22uF/25V u1 4 1. u
8 1 5 1. 0 1 61 KEY2 OCMDATA14 GPIO_G09_B3 LCDVCC 1
7 7 61 7 . 6 7 . 6 . AB1
25V 7 0. 1 0 7 . 1 0 10 1 0 10 KEY3 AC5 R16 1841 30P R
1 C 10 C C AC3 OCMDATA13 GPIO_G09_B2 AF4 C
C C C C RIGHT OCMDATA12 GPIO_G09_B1 VGA_CAB PANEL_VCC N/
LEFT T112 AC2 AE4 VGA_CAB 3 GND GND
OCMDATA11 GPIO_G09_B0 0/6/NC 6/
GND T113 AC1 T117 R174 0
+3.3V_LVDSA OCMDATA10 R175
+3.3V_LVDS T114 AD1
AE1 OCMDATA9 0/6
6 OCMDATA[0..7] OCMDATA8 0/6/NC
C47 AF1 A26
OCMDATA7 OCMDATA7 PPWR PPWR PPWR 7 GND
C44 C131 C132 AD2 B26 GND
C133 OCMDATA6 OCMDATA6 PBIAS PBIAS PANEL_VCC
0.1uF/6 AE2 PBIAS 7
OCMDATA5 OCMDATA5
22uF/25V 0.1uF/6 0.1uF/6 AF2 AC17 R82 2K7/6
0.1uF/6 OCMDATA4 OCMDATA4 NO_CONNECT R84 0/6
25V AD3 AC16 U7
OCMDATA3 OCMDATA3 OEXTR OEXTR R42 3K3/6
AE3 AD15 R81 2K7/6 8 1 V
OCMDATA2 5
+3.3V_LVDSB GND AF3 OCMDATA2 D_GND 7 VCC A0 2 2/ 6/
OCMDATA1
GND AD4 OCMDATA1 GND 6 WP A1 3 F
u
F
u
OCMDATA0 MSTR_SCL
OCMDATA0
GND 5 SCK A2 4
R85
2 22 11
1 0.
MSTR_SDA SI VSS 1
C C
C52 C144 C142 C148 +3.3V_DIG 24LC32-SN 0/6/NC
SSS GND SOIC8 GND GND
22uF/25V 0.1uF/6 0.1uF/6 0.1uF/6 DDD S L L S SD DS SD
L
L DDD VVV D SS DDDDDDD D LL LD
P L PDDDD I2C address: A2H and A3H
25V D_ N N N _L _L _L VL S S N NNNNNN
N R_ P_ F_ S_ S_ D_ D_
G_ G_ G_ A A A _ VF VF G GGGGGG D DD DD DD _
G GND
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D 81 33 3 3 33 33 33 3
DDDDDDDDDDDDDDDDDDDD BBB 3 3 3 3 EE DAADAAA NNNNNNN C 33 33 33 3 +5V
NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNA NNNNNNNNNNNNNNNNNNNN S S S A A A D R R _ _ _ _ _ _ _ G_ G_ G_ G_ G_ G_ G_ D ADAADAD 3
GND G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ S G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ D D D S S S S V V C C C C C C C VI VI VI VI VI VI VI A SSSSSSS
S VVV SSS S SS DDDDDDD B SSSSSSS C
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDV DDDDDDDDDDDDDDDDDDDD L L L VVV V F F AAAAAAA DDDDDDD L VVVVVVV
34 5 90 9 7 C 1 /RESET /RESET
3 4 55 55 511167 00 22 32 22 22 33303044443 5 45556662 33 34 410777 0 11 1 12 1 1 64 11 3 V OUT
+5V 1 1 11 11 111111 11 11 11 11 11 11111111111 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 17 CCC CCD D 2 2 4 4 2 5 1 4 4 7 7 7 7 1 1 5 1 324 24 24 C76 C78 C80
A U L MP R UMNR P N NR K L MMN P T U L N R L T T K L N PB K T K N T MN RR K P UMR PMMP R P L A A A A A A A KW B D E A E C E A B C D A D B D FGHH J J K
+3.3V_ADC 0.1uF/6 0.1uF/6 0.1uF/6 D
N
G
U8
R150 R151 MAX809_0
GND GND GND 2
10K/6
10K/6 6/
K
6/ 6/ 6/ 6/
6/ 6/
K K
less R94 to CN6 pin 11 GND
3 3 K K K K 3 3
LED_G R152 4K7/6 2 Q12 43
5
3
5 3 6 33
5
3
7 3 83
5
3 9 30 3
5 6
R101,R103 net swap
MMBT3904L 1 1 5 1 5 1 1
R R 1 R 1 R R CN5
R R
3 MENU R161 1K/6
LED_R R153 4K7/6 2 Q13 1 R162 1K/6 10
SEL
MMBT3904L R163 1K/6 9
PWR
R164 1K/6 8
DOWN
7
UP R165 1K/6
1 6
RIGHT R166 1K/6
5
LEFT R167 1K/6
4
R168 220R/6
3
R169 220R/6
2
1
6/ 6/ 6/ 6/ 6/ 6/ 6
F F F F F F F/
u u u u u
3 1 41 u 7 1 u 4501-10-10P-R
81
9 0. 9 . 9 . 5 1. 61
9 . 9 . 8 1.
C
1 0
C
1 0 19 0
C C
10
C
1 09 0
C C1 TO BUTTON BOARD
2.0mm pitch PROJECT : M0TW
Junction from A 90° E&T Quanta Computer Inc.
change to B GND
4607-11Pin Title
04. gm1601
Size Document Number Rev
M0TW A
04. gm1601
Date: Tuesday , September 14, 2004 Sheet 4 of 8

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12V_A +12V C204 0.1uF/6
L20 CX000800000/1206
C205 0.1uF/6 SPKRO+
SPKRO-

12V_A
CN9 1 12V_A
5 6
lef t_inR109 0/6 L22 LIN_L 0
4 6 2
CX000800000/1206 6/ 0 1/
3 2 6/ 6/ 0
V F 1/ F 0
2 R110 0/6 5 u 0 p F
p 0
L23 RIN_R 1. 0 0 0
ZD005D100 2/ 0 0 0 0 6/ V
CX000800000/1206 0 0 0 8 F 5
1 F
u 0 0
4
1 0
5 0 u 2/
8 2 6 1
6
C C 2 2 6 8 7 0 3 1 6 F
C
N/ 6/ 7 1 0 C C 0
1 X 7 0. u
6 2
6/ N/ 6/ C L 0
0 L C C 2
3 F 6/ 6/ F F C71 X C74
C
6/ p p
1 p K K 0
2 2 0 C 0.01uF/6
1 0 4 F 1. 1. 1 2
C 2
2 1 p 5 5
4
0 2
1 0 2 0.01uF/6
1 0 3 1
1
C 2
2 1
1 1 C C U9 8 7 6 5 4 3 2 1 0 9 8 7
R R 4 4 4 4 4 4 4 4 4 3 3 3
AGND AGND AGND AGND AGND AGND
+12V + R R + + R R - - R R R -
R T T T T
AGND S C C U U D D U U C C S
1 B C C O O N N O O C C B 36 C82
R79 10K/6 SDZ V V G G R R V V 1u/8
P P R R P P P P VCLAMPR
L
4 RIN C75 1u/8 2 35
0 RIN+ MODEB
3 9
3
MUTE R75 4K7/6 2 T AGND C79 1u/8 3 34 12V_A
4 MUTE B RIN- MODE
0M
1M AGND C83 1u/8 4 33
6/ Q V2P5 AVCC
K 1
0 AGND C85 1u/8 5 32
1 LIN- VAROUTR 6/ V
6 F 5
7 6 31 u 2/
LIN C95 1u/8 4 1.
R LIN+ VAROUTL 8 0 6 F
u
8 2
7 30 C C 2
AVDDREF NC
8 29 C87 0.1uF/6 L21 CX000800000/1206
VREF AVDD
9 28 C96 220pF/6
VARDIFF COSC
10 27 R87 120K/6
VARMAX ROSC
GND
VOLUME 11 26 AGND AGND
7 VOLUME VOL AGND
12 25 C99 1u/8
6/ AGND VCLAMPL
F L L L L L L
+5V u + + - -
1. + C C T T D D T T C C -
0 L C C U U N N U U C C L
S V V O O G G O O V V S
7 B P P L L P P L L P P B
L36 9 AGND
CX000800000/1206 C TPA3003D2
6/ 6/ 3 4 5 6 7 8 9 0 1 2 3 4
1 1 1 1 1 1 1 2 2 2 2 2
F F
u u
1. 1.
0 0
0 C103 0.01uF/6 C106 0.01uF/6
9 0
9 2 6
1 0 CN6
C U12 C 2 6/
6/ 1/ 6
AGND AGND F 0 F SPKRO+
1 u 0 2 u V 1
16 1. 0 1/ 1. 5 SPKRO-
2Y 1 VCC V 0 0 2/ 2
2 15 5 0 0 0 0 SPKLO+
2Y 0 2Z 2/ 0 0 0 F 3
ADO_L 3 14 RIN 9 F 8 0 5 1 u SPKLO-
4 ADO_L 3Y 1 1Z 0 u 4 0 0 0 1 2 4
LIN 4 13 ADO_R 0 4 0 8 C 2
3Z 1Y 1 ADO_R 4 1 2 1 0 5 0 1
C 2 C 2 X 2 C
L L 0
LIN_L C202 1u/8 5 12 C201 1u/8 RIN_R 12V_A C 0 12V_A 4501-04-04P-R
6 3Y 0 1Y 0 11 6/ 6/ X
E S1 F F C
7 10 p p
VEE S2 0 0
8 9 ADO_C 0 0
GND S3 ADO_C 4 0
1 0
2
1 1
1 1
74HCT4053
C C
SPKLO-
PROJECT : M0TW
SPKLO+
Quanta Computer Inc.
Title
AGND
08. Audio
Size Document Number Rev
M0TW A
08. Audio
Date: Tuesday , September 14, 2004 Sheet 8 of 8

+2.5V_DDR

V V 6 6 6
/ 6
/ 6 6 6
/ 6
/ 6
/ 6 6 6
/ 6
/ 6
/
5 5 / / / / / /
0 2 4 2 9 F 0 F 1 F 5 F 4 F 3 F 2 F 3 F F F F 9 F 7 F 6 F
2 / 2 / 2 u 3 u 3 u C u C u C u C u 1 u u u u 1 u 1 u C u
C F
u C F
u C 1
. C 1
. C 1
.
0
1
.
0
1
. 1
.
1
.
0 C 1
. 7 1
.
2 0 8 1
. 8 1
. C 1
.
0 C 1
.
0
1
.
0
2 2 0 0 0 0 0 2 0 1 0
2 2 C C C

GND

4 FSDATA[0..31]
+2.5V_DDR FSVREF

U1
4 2 9 7 3 9 6 5 5 5 5 6 8
2 8 1 2 5 6 7 7 8 9 1 3 6 9 5
97 FSDATA0
4 FSADDR[0..11] QQ Q QQ QQ Q QQ D D D D F
FSADDR0 31 D D D D D D D D D D D D D D E DQ0 98 FSDATA1
FSADDR1 32 A0 D D D D D D D D D D V V V V R DQ1 100 FSDATA2
V V V V V V V V V V V
FSADDR2 33 A1 DQ2 1 FSDATA3
FSADDR3 34 A2 DQ3 3 FSDATA4
FSADDR4 47 A3 DQ4 4 FSDATA5 +2.5V_DDR
FSADDR5 48 A4 DQ5 6 FSDATA6
FSADDR6 49 A5 DQ6 7 FSDATA7
FSADDR7 50 A6 DQ7
FSADDR8 51 A7
FSADDR9 45 A8/AP
FSADDR10 36 A9 R3 FSVREF
FSADDR11 37 A10 10K/6 1%
A11 60 FSDATA8
DQ8 61 FSDATA9
FSBKSEL0 29 DQ9 63 FSDATA10 FSVREF
4 FSBKSEL0 FSBKSEL1 30 BA0 DQ10 64 FSDATA11
4 FSBKSEL1 BA1 DQ11 68 FSDATA12
FSCLK- 54 DQ12 69 FSDATA13 C1
4 FSCLK- FSCLK+ CLK DQ13
55 71 FSDATA14 R1
4 FSCLK+ FSCKE CLK DQ14
53 72 FSDATA15 10K/6 1% 0.1uF/6
4 FSCKE CKE DQ15
28
GND /FSRAS CS
27
4 /FSRAS /FSCAS RAS
26
4 /FSCAS /FSWE CAS
25 9 FSDATA16 GND
4 /FSWE DQS WE DQ16
94 10 FSDATA17
4 FSDQS DQS DQ17 12 FSDATA18 GND
FSDQM0 23 DQ18 13 FSDATA19
4 FSDQM[0..3] FSDQM1 56 DM0 DQ19 17 FSDATA20
FSDQM2 24 DM1 DQ20 18 FSDATA21
FSDQM3 57 DM2 DQ21 20 FSDATA22 FSCLK+
DM3 DQ22 21 FSDATA23
DQ23 R4
38
NC 140R/6 1%
39
40 NC FSCLK-
41 NC
42 NC 74 FSDATA24 Place R704 termination close to
43 NC DQ24 75 FSDATA25 corresponding U600 Pins
44 NC DQ25 77 FSDATA26
87 NC DQ26 78 FSDATA27
88 NC DQ27 80 FSDATA28
89 NC DQ28 81 FSDATA29
90 NC DQ29 83 FSDATA30
91 NC DQ30 84 FSDATA31
93 DNC
NC QQ Q QQ QQ Q Q L
DQ31
PROJECT : M0TW
S S S S S S S S S S S S S
S S S S S S S S S
V V V V V V V V V
S S S S
V V V V
C
M Quanta Computer Inc.
MT46V2M32LG-4 Place series termination resistors very Title
1 9 2 0 6 2 2 9 6 6 6 5 2
TQFP-100 5 1 1 6 7 7 8 9 9 1 4 6 8 5 close to U600
05. Frame Store
Size Document Number Rev
GND
05. Frame Store
MOTW A

Date: Thursday , September 02, 2004 Sheet 5 of 8

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+1.8V_CORE +1.8V_DVI
+3.3V_ADC +1.8V_ADC
+3.3V_PLL L12
CX000800000/1206
+3.3V_LVDSA L14
CX000800000/1206
+3.3V_LVDS
L18
CX000800000/1206
L6 +3.3V_LBADC
CX000800000/1206
L9 +3.3V_DVI
CX000800000/1206
L11 +3.3V_DIG
CX000800000/1206
+3.3V_LVDSB
L19
CX000800000/1206
L7
CX000800000/1206 +3.3V_I/O_MALIBU
L10
CX000800000/1206
L26
CX000800000/1206

H5 H6 H1

2 9 2 9 2 9
3 8 3 8 3 8
4 1 7 4 1 7 4 1 7
5 6 5 6 5 6

MTH276D126 MTH276D126 MTH276D126


GND GND GND GND GND GND
H2 H4 H3
2 9 2 9 2 9
3 8 3 8 3 8
4 1 7 4 1 7 1
4 7
5 6 5 6 5 6
MTH276D126 MTH276D126 MTH276D126
GND GND AGND AGND GND GND

VGA_SCL VGA_SCL 4
VGA_SDA VGA_SDA 4

VGA_CAB 4
VGA_5V
CN7 R106 0/6/NC
7 GND
1
R101 100R/6 VGASCL 15 5
10
14 4 R88 20R/6 1% C89 0.01uF/6
VGA_5V +5V C90 0.01uF/6 BLUE+ 4
9 BLUE- 4
13 3 A-BLUE
D8 8 R90 20R/6 1% C91 0.47uF/6
R102 100R/6VGASDA SOG 4
12 2 A-GREEN R91 20R6 1% C92 0.01uF/6 GREEN+ 4
DAN202U 7 C69 0.01uF/6 GREEN- 4
1 2 11 1 A-RED R93 20R/6 1% C94 0.01uF/6 RED+ 4
6 C93 0.01uF/6
RED- 4
% % %
1 1 1
3 6/
6 6/ 6/ %
1 R R % 1 %
5 5 R 1 1
7 7 5 6/ 6/ 6/
7
R R R
6 6 6
DB15 HD GND 4 5 5 5 RGB SIGNAL GNDs at 2-mm from respective
0 0 3
A-HS 0 1 0 3
C88
1
R R 1 9
8 8 2
9
RGB series Capacitors
R R R
R86 R98 A-VS R
0.1uF/6 GNDGNDGND
U10 10K/6 10K/6 GNDGND GND
1
A0 VCC
8 Near VGA pins
2 7 GND
3 A1 WP 6
4 A2 SCL 5 R95 0/6
GND SDA R97 22R/6 R94 0/6 AHS 4
A-VS AVS 4
24C02 3
D6 U11
GND 3
GND D7
5.6V/NC A-HS 1 13
ANALOG DDC R96 22R/6
2 1A 6A 12
5.6V/NC 1Y 6B
3 3 3 11
1 6/ 6/ 4 2A 5A 10
S C C F
p F
p 2Y 5B
1 N/ N/ N/ 7 7
5 6/ V V
6
4
0
4
8
5
3A
+3.3V
GND GND 0 R 6 5 . 0 0 6
1 0
1 4 5. D 5
1 1
8 3Y 14
R 5 D C C
1 1 9 4Y VCC 7
4A GND
6/
SN74LVC14A/NC F
u
PROJECT : M0TW
GND 7 1.
0
1 0
C
Quanta Computer Inc.
GNDGND
Title
03. Graphic Inputs
Size Document Number Rev
M0TW A
03. Graphic Inputs
Date: Friday , September 10, 2004 Sheet 3 of 8

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+3.3V_DIG
+3.3V_DIG Socke t for a X8 Flash (64/128/256/512K) and
R40 10K/6/NC PROM JETm em ory Em ulator
R43 10K/6
R67 10K/6 XU1
OCMADDR18 1 21 OCMDATA7
V 6/ A18 DQ7
/OCM_WE 5 F OCMADDR17 30 20 OCMDATA6
4 /OCM_WE /OCM_RE 2/ u OCMADDR16 A17 DQ6 OCMDATA5
2 19
4 /OCM_RE 0 F 9 1. OCMADDR15 A16 DQ5 OCMDATA4
/OCM_CS 6 u 5 0 3 18
4 /ROM_CS C 2
2 C OCMADDR14 29 A15 DQ4 17 OCMDATA3
OCMADDR13 28 A14 DQ3 15 OCMDATA2
GND OCMADDR12 4 A13 DQ2 14 OCMDATA1
OCMADDR11 25 A12 DQ1 13 OCMDATA0
OCMADDR10 23 A11 DQ0
OCMADDR9 26 A10
OCMADDR8 27 A9 22 /ROM_CS
OCMADDR7 5 A8 CE# 24 /OCM_RE
OCMADDR6 6 A7 OE# 31 /OCM_WE
OCMADDR5 7 A6 WE#
OCMADDR4 8 A5 +3.3V_DIG
OCMADDR3 9 A4 32
OCMADDR2 10 A3 VCC
OCMADDR1 11 A2 16
OCMADDR0 12 A1 VSS
OCMADDR[0..19] A0
4 OCMADDR[0..19] GND
A28F001
29LV040B
OCMDATA[0..7]
4 OCMDATA[0..7]

+3.3V_DIG

R68 10K/6
R69 10K/6 10: LOW (Use TCLK)
R70 10K/6/NC 11: LOW (s et all dis play output to '0')
R62 10K/6/NC 12: LOW
R55 10K/6/NC 13: LOW(disable s erial inte rface de bug)
R47 10K/6 14: LOW
R50 10K/6/NC 15: LOW
16: HIGH (use crystal)
OCMADDR8 Firmware_By pass R56 10K/6 17: LOW (8bit bus w ith OCM acces s e xte rnal ROM )
OCMADDR9 DDC2BI R51 10K/6/NC 18: HIGH
OCMADDR13 Serial_Interf ace_Debug1 R61 10K/6 19: LOW
OCMADDR14 Serial_Interf ace_Debug2 R64 10K/6
OCMADDR15 Serial_Interf ace_Debug3 R73 10K/6
OCMADDR16 INT_OSC
OCMADDR18 8-BIT_FLASH2
OCMADDR17 R65 10K/6 8-BIT_FLASH1 GND
OCMADDR19 R80 10K/6 8-BIT_FLASH3
OCMADDR10 R41 10K/6 TCLK
OCMADDR11 R46 10K/6 OUTPUTS_ZERO
OCMADDR12 R71 10K/6 OUTPUTS_ZERO
GND

PROJECT : M0TW
Quanta Computer Inc.
Title
06. Memory I/F
Size Document Number Rev
A
06. Memory I/F M0TW
Date: Thursday , September 02, 2004 Sheet 6 of 8

D1 1SS355

6
0
2
1/ U2
0 5 6 7 8
+18V
18V 8 1 O
BOOST DC R18 47R/6 S
/
1
L2 CX000800000/1206 2 7 2 A
R 0
IS DE 1
4
6 3 9
6 S
VCC CF R22 330K/6 QD L30
D2
5 4 N C22
4 3 2 1 0.1uF/6 +12V Q21
6/ + V FB GND 1SS355
6/ F 5 6/ CX000800000/1206 C189 L31 V12
F u 2/ 1 8
6/ p 8 1. u F R149
F 8 0 0 6/ AIC1563 p 2 7
p C 0 V 0 1u/8
0 2 + 5 4 1 F 2 0 % 3 6
7 0 2 1 2/ 1 u 3 2 1 Q7 4K7/6 CX000800000/1206
0 2
2 1 C u C 1 1
2 0.
8/ GND C 1 6/
1 4 5
C 0 u GND 2 2N3906
5 0 C 1 K R148 0/6/NC
1 1 6 3 0
C GND 2 2 4 C190 C192
C R24 3K/6 1% R 2 4 TUNER12V_KEY 3 SI9435 0.1uF/6 V 0.1uF/6
GND 6/ R147 4K7/6 2 Q20 6
K 3 1/
C33 2200pF/6 1 MMBT3904L 1 u
0 +5V 9 0
GND 2 L3 2 1 47UH L4 1 3
R25 R C 3
CX000800000/1206 GND
1
1K/6 1%
GND
GND GND
1 6/
D3 F V
18V 6/ u 6
1. 1/ V
RB081L-20 4 F 5 0 6 u 6
GND 3 p 3 3 0 1/
CN4 20268-04 C 0
0 C C 3
3 3 u
6 0 0 0
1 2 3
6 1 3
7
7 2 2 GND C
8 GND
8 3 GND
9
9 4 L37 CX000800000/1206 GND
5

GND

D20 1SS355

+5V
18V 6
V5IR 0 U20
2
1/
L35 0 5 6 7 8
4500-07
CX000800000/1206 +18V 8 1
BOOST DC O
7 R143 47R/6 S
/
6 0 7 2 A
4 0
5 1 IS DE 1
R 4
4 ADJ 6 3 9
VCC CF R144 330K/6 D21 3 S
3 ON/OFF 2 D C188
V Q N
2 + 5 4 1SS355 0.1uF/6 +12V
GND 5 FB GND 6/ 4 3 2 1
1 2/
u F
p
CN1 0 6
6/ 6/ 0 0 / AIC1563 4 0
8 1 F 8 2 %
F
p F 1 u 8/ 1 1 1
p C 1 1. C Q22
9 0 0 0 8 u 6/
0 2 1 2 1 0 1 GND
2 1 2 1 C 2
8 GND 5 K
0 MMST3906
C C 1 4 4
1 2
C R
GND 6/
+5V R142 8K2/6 1%
U6 +1.8V_CORE K
GND 1
C183 2200pF/6 6
GND 4 L34 2 1 47UH L32
1
L15 CX000800000/1206 R141 R CX000800000/1206
3 2 L13
VIN VOUT
R72 CX000800000/1206 953R/6 1%
1 1 V
ADJ/GND D22 6
6/ 1/
330R/6 1% 7 u
+ + V RB081L-20 F 8 0
V AIC1084/TO252 5 6/ u 1 3
2/ 1 C 3
5 u
GND 5 F 6 .
2/ 0 8 p
1 0 8 0
1 u R74 6 0 0 1
6 0 5 1 2 C 0 C
C 0
1 C 1
GND GND GND
+3.3V_ADC
148R/6 1% GND

R11 10K/6/NC GND

100K/6
R126 0/6 R12
VOLUME 8

6/
F R127 +5V
PWM1 4K7/6/NC u
3 1. L33 CX000800000/1206/NC
4 PWM1 R9 2 Q3 0 1K/6/NC
MMBT3904L/NC
0
1 +5V +18V
1 C
U4 +3.3V_ADC
GND L28
GND GND
L8 CX000800000/1206 CX000800000/1206/NC
3 2 L29
VIN VOUT
+12V
1 R57 PANEL_VCC
ADJ/GND CX000800000/1206
C23 R17 Q4
200/6 1% V L1
+ 5 1 8
+ AIC1084/TO252 2/
V u 1u/8 4K7/6 2 7
5 0 3 6
2/ R58 3 0 CX000800000/1206
8 u 5 1 4 5
+5V 4 0 C R19 0/6/NS
C 0
1 330/6 1% + C16
R6 4K7/6/NC C9 0.1uF/6
3 C25
R29 4K7/6 2 Q5 SI9435 0.1uF/6 330uF/16V
R7 0/6 ON/OFF GND 4 PPWR
MMBT3904L
25V
Q2 MMST3906/NC GND
1
4 PBIAS R10 GND
GND GND
4K7/6/NC

GND

U3 +2.5V_DDR
+5V 0.8A Max
+5V L5 CX000800000/1206
3 2
VIN VOUT
1 R38
R8 1K/6 R5 10K/6 ADJ ADJ/GND
200/6 1%
+V
5 +V
6/ 2/ LT1117/TO223 5
F 2/
u u
3 u 0 0
1. 1 0 R39
PWM0 2 Q1 0 4 1 3 0
4 PWM0 R2 4K7/6 C 200/6 1% 4 1
MMBT3904L C
7
1
C
GND PROJECT : M0TW
GND
GND
Quanta Computer Inc.
Title
POWER
Size Document Number Rev
M0TW A
07. Power
Date: Tuesday , September 14, 2004 Sheet 7 of 8

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