Features

®
1• High-performance, Low-power AVR 8-bit Microcontroller
2• Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
3• High Endurance Non-volatile Memory segments
– 32K Bytes of In-System Self-programmable Flash program memory
– 1024 Bytes EEPROM
– 2K Byte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM –
8-bit
Data retention: 20 years at 85°C/100 years at 25°C
(1)

– Optional Boot Code Section with Independent Lock Bits

Microcontroller
In-System Programming by On-chip Boot Program
True Read-While-Write Operation with 32K Bytes
– Programming Lock for Software Security
1• JTAG (IEEE std. 1149.1 Compliant) Interface In-System
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support Programmable
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
2• Peripheral Features Flash
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels ATmega32
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
ATmega32L
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
1• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down,
Standby and Extended Standby
2• I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
3• Operating Voltages
– 2.7 - 5.5V for ATmega32L Note: Not Recommended for new
– 4.5 - 5.5V for ATmega32 designs.
4• Speed Grades
– 0 - 8 MHz for ATmega32L
– 0 - 16 MHz for ATmega32
5• Power Consumption at 1 MHz, 3V, 25C for ATmega32L
– Active: 1.1 mA
– Idle Mode: 0.35 mA
– Power-down Mode: < 1 µA
 2503O–AVR–07/09

Pin Figure 1. Pinout ATmega32

C
o (XCK/T0)
(T1)
PB0
PB1
n (INT2/AIN0)
(OC0/AIN1)
PB2
PB3
f (SS)
(MOSI)
PB4
PB5
i (MISO) PB6
(SCK) PB7
g
u
r
a (RXD)
(TXD)
PD0
PD1
t (INT0) PD2
(INT1) PD3
i (OC1B) PD4
o (OC1A)
(ICP1)
PD5
PD6
n
s
 TQFP/MLF

(AIN0/INT2)
(AIN1/OC0)

(XCK/T0)

(ADC0)
(ADC1)
(ADC2)
(ADC3)
(SS)

(T1)

PB4PB3PB2PB1PB0GNDVCCPA0PA1PA2PA3
(MOSI) PB5 PA4 (ADC4)
(MISO) PB6 PA5 (ADC5)
(SCK) PB7 PA6 (ADC6)
RESET PA7 (ADC7)
VCC AREF
GND GND
XTAL2 AVCC
XTAL1 PC7 (TOSC2)
(RXD) PD0 PC6 (TOSC1)
(TXD) PD1 PC5 (TDI)
(INT0) PD2 PC4 (TDO)
VCCGND
(INT1) PD3

PD4
PD5
PD6
PD7

(SCL) PC0
(SDA) PC1
(TCK) PC2
(TMS) PC3

Note:
Bottom pad should
(ICP1)
(OC1B)
(OC1A)

(OC2)

be soldered to ground.
 2 ATmega32(L)
2
5
ATmega32(L)
ed on the
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Ov T enhanced
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er h architecture.
e
vie By executing
powerful
w A instructions
T
in a single
m
clock cycle,
e
the
g
ATmega32
Blo a achieves
ck 3 throughputs
2
Dia approaching
gra i 1 MIPS per
m s MHz allowing
the system
designer to
a
optimize
power con-
l
sumption
o
versus
w
processing
-
speed.
p
o
w Figure 2.
e Block
r Diagram
PA0 - PA7
C PC7
VCC
M
O
S

8
-
b
i GND

m AVCC
i
c
r AREF

o PR
CO
c
o
n PR

t
r
INST
o RE

l
l INST

e DE

r
CO
L
b
a
s AV
 PORTB DRIVERS/BUF

PB0 - PB7

2503
O–
AVR–
07/09