CC 430 F 6137

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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125

CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
CC430F613x, CC430F612x, CC430F513x MSP430™ SoC With RF Core

1 Device Overview
1.1
1
Features
• True System-on-Chip (SoC) for Low-Power – Serial Onboard Programming, No External
Wireless Communication Applications Programming Voltage Needed
• Wide Supply Voltage Range: – Embedded Emulation Module (EEM)
3.6 V Down to 1.8 V • High-Performance Sub-1 GHz RF Transceiver
• Ultra-Low Power Consumption Core
– CPU Active Mode (AM): 160 µA/MHz – Same as in CC1101
– Standby Mode (LPM3 RTC Mode): 2.0 µA – Wide Supply Voltage Range: 2 V to 3.6 V
– Off Mode (LPM4 RAM Retention): 1.0 µA – Frequency Bands: 300 MHz to 348 MHz,
– Radio in RX: 15 mA, 250 kbps, 915 MHz 389 MHz to 464 MHz, and 779 MHz to 928 MHz
• MSP430™ System and Peripherals – Programmable Data Rate From 0.6 kBaud to
500 kBaud
– 16-Bit RISC Architecture, Extended Memory, up
to 20-MHz System Clock – High Sensitivity (–117 dBm at 0.6 kBaud,
–111 dBm at 1.2 kBaud, 315 MHz, 1% Packet
– Wake up From Standby Mode in Less
Error Rate)
Than 6 µs
– Excellent Receiver Selectivity and Blocking
– Flexible Power-Management System With SVS
Performance
and Brownout
– Programmable Output Power up to +12 dBm for
– Unified Clock System With FLL
All Supported Frequencies
– 16-Bit Timer TA0, Timer_A With Five
– 2-FSK, 2-GFSK, and MSK Supported, Also
Capture/Compare Registers
OOK and Flexible ASK Shaping
– 16-Bit Timer TA1, Timer_A With Three
– Flexible Support for Packet-Oriented Systems:
Capture/Compare Registers
On-Chip Support for Sync Word Detection,
– Hardware Real-Time Clock (RTC) Address Check, Flexible Packet Length, and
– Two Universal Serial Communication Interfaces Automatic CRC Handling
(USCIs) – Support for Automatic Clear Channel
– USCI_A0 Supports UART, IrDA, SPI Assessment (CCA) Before Transmitting (for
– USCI_B0 Supports I2C, SPI Listen-Before-Talk Systems)
– 12-Bit Analog-to-Digital Converter (ADC) With – Digital RSSI Output
Internal Reference, Sample-and-Hold, and – Suited for Systems Targeting Compliance With
Autoscan Features (CC430F613x and EN 300 220 (Europe) and
CC430F513x Only) FCC CFR Part 15 (US)
– Comparator – Suited for Systems Targeting Compliance With
– Integrated LCD Driver With Contrast Control for Wireless M-Bus Standard EN 13757‑4:2005
up to 96 Segments (Only CC430F61xx) – Support for Asynchronous and Synchronous
– 128-Bit AES Security Encryption and Decryption Serial Receive or Transmit Mode for Backward
Coprocessor Compatibility With Existing Radio
– 32-Bit Hardware Multiplier Communication Protocols
– 3-Channel Internal DMA • Device Comparison Summarizes the Available
Family Members
1.2 Applications
• Wireless Analog and Digital Sensor Systems • AMR or AMI Metering
• Heat Cost Allocators • Smart Grid Wireless Networks
• Thermostats
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018 www.ti.com
1.3 Description
The TI CC430 family of ultra-low-power system-on-chip (SoC) microcontrollers with integrated RF
transceiver cores consists of several devices that feature different sets of peripherals targeted for a wide
range of applications. The architecture, combined with five low-power modes, is optimized to achieve
extended battery life in portable measurement applications. The devices feature the powerful MSP430
16‑bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The CC430 family provides a tight integration between the microcontroller core, its peripherals, software,
and the RF transceiver, making these true SoC solutions easy to use as well as improving performance.
The CC430F61xx series are microcontroller SoC configurations that combine the excellent performance of
the state-of-the-art CC1101 sub-1 GHz RF transceiver with the MSP430 CPUXV2, up to 32KB of in-
system programmable flash memory, up to 4KB of RAM, two 16-bit timers, a high-performance 12-bit ADC
with eight external inputs plus internal temperature and battery sensors on CC430F613x devices, a
comparator, USCIs, a 128-bit AES security accelerator, a hardware multiplier, a DMA, an RTC module
with alarm capabilities, an LCD driver, and up to 44 I/O pins.
The CC430F513x series are microcontroller SoC configurations that combine the excellent performance of
the state-of-the-art CC1101 sub-1 GHz RF transceiver with the MSP430 CPUXV2, up to 32KB of in-
system programmable flash memory, up to 4KB of RAM, two 16-bit timers, a high-performance 12-bit ADC
with six external inputs plus internal temperature and battery sensors, a comparator, USCIs, a 128-bit
AES security accelerator, a hardware multiplier, a DMA, an RTC module with alarm capabilities, and up to
30 I/O pins.
For complete module descriptions, see the CC430 Family User's Guide.
Device Information (1)

PART NUMBER PACKAGE BODY SIZE (2)
CC430F6137IRGC VQFN (64) 9 mm × 9 mm
CC430F5137IRGZ VQFN (48) 7 mm × 7 mm
(1) For the most current part, package, and ordering information, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
2 Device Overview Copyright © 2009–2018, Texas Instruments Incorporated

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CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
1.4 Functional Block Diagrams

Figure 1-1 shows the CC430F613x functional block diagram.
XIN XOUT P1.x,P2.x P3.x,P4.x P5.x RF_XIN RF_XOUT
(32 kHz) (26 MHz)
2x8 2x8 1x8
I/O Ports I/O Ports I/O Ports

MCLK ACLK REF P1, P2 P3, P4 P5
Unified
2x8 I/Os 2x8 I/Os 1x8 I/Os Packet
Clock Comp_B ADC12
Voltage Handler
System SMCLK Reference PA PB
DMA 1x16 I/Os 1x16 I/Os Digital RSSI
Controller Carrier Sense
PQI,CA
3 Channel LQI
MAB
Bus
Control MDB
Logic
Sub-1 GHz
CPUXV2 Radio
incl. 16 (CC1101)
Registers SYS
Flash RAM
Watchdog
32KB 4KB CRC16 MPY32 CPU Interface
16KB 2KB Port
EEM Mapping
(S: 3+1) Controller
Modem
MDB
JTAG
Interface MAB
Frequency
Spy-Bi- Synthesizer
Wire
Power USCI_A0 LCD_B
AES128
Mgmt TA0 TA1 (UART,
IrDA, SPI) 96 RF, Analog
RTC_A Security
LDO, 5 CC 3 CC Segments TX and RX
Encryption,
SVM, SVS, Registers Registers USCI_B0 1,2,3,4 Decryption
Brownout 2
(SPI, I C ) Mux
RF_P RF_N
Copyright © 2017, Texas Instruments Incorporated
Figure 1-1. CC430F613x Functional Block Diagram
Copyright © 2009–2018, Texas Instruments Incorporated Device Overview 3

CC430F5137, CC430F5135, CC430F5133

XIN XOUT P1.x,P2.x P3.x,P4.x P5.x RF_XIN RF_XOUT
(32 kHz) (26 MHz)
2x8 2x8 1x8

MCLK ACLK REF P1,P2 P3,P4 P5
Unified
Clock Comp_B
Voltage Handler
System SMCLK Reference PA PB
DMA 1x16 I/Os 1x16 I/Os Digital RSSI
PQI, LQI
3 Channel CCA
MAB
Bus
Control MDB
Logic
Sub-1 GHz
CPUXV2 Radio
incl. 16 (CC1101)
Registers SYS
Flash RAM
Watch-
dog CPU Interface
32KB 4KB CRC16 MPY32
32KB 2KB Port
EEM 16KB 2KB Mapping
(S: 3+1) Controller
Modem
MDB
JTAG
Interface MAB
Frequency
Spy-Bi- Synthesizer
Wire
Power USCI_A0 LCD_B
AES128
Mgmt TA0 TA1 (UART,
IrDA, SPI) 96 RF, Analog
RTC_A Security
LDO, 5 CC 3 CC Segments TX and RX
Encryption,
SVM, SVS, Registers Registers USCI_B0 1,2,3,4 Decryption
Brownout 2
(SPI, I C ) Mux
RF_P RF_N
4 Device Overview Copyright © 2009–2018, Texas Instruments Incorporated

CC430F5137, CC430F5135, CC430F5133

XIN XOUT P1.x,P2.x P3.x P5.x RF_XIN RF_XOUT
(32 kHz) (26 MHz)
2x8 1x8 1x2

MCLK ACLK REF P1,P2 P3 P5
Unified
Clock Comp_B ADC12
Voltage Handler
System SMCLK Reference PA
DMA 1x16 I/Os Digital RSSI
PQI, LQI
3 Channel CCA
MAB
Bus
Control MDB
Logic
Sub-1 GHz
CPUXV2 Radio
incl. 16 (CC1101)
Registers SYS
Flash RAM
Watchdog
32KB 4KB CRC16 MPY32 CPU Interface
16KB 2KB Port
EEM 8KB Mapping
(S: 3+1) Controller
Modem
MDB
JTAG
Interface MAB
Frequency
Spy-Bi- Synthesizer
Wire
Power USCI_A0
AES128
Mgmt TA0 TA1 (UART,
IrDA, SPI) RF, Analog
RTC_A Security
LDO, 5 CC 3 CC TX and RX
Encryption,
SVM, SVS, Registers Registers USCI_B0 Decryption
Brownout 2
(SPI, I C)
RF_P RF_N
Copyright © 2009–2018, Texas Instruments Incorporated Device Overview 5

CC430F5137, CC430F5135, CC430F5133
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from September 6, 2013 to September 17, 2018 Page
• Document format and organization changes throughout, including addition of section numbering ....................... 1
• Added Device Information table .................................................................................................... 2
• Added Section 1.4 and moved all functional block diagrams to it .............................................................. 3
• Added Section 3, Device Comparison, and moved Table 3-1 to it ............................................................. 7
• Added Section 3.1, Related Products ............................................................................................. 7
• Added Section 4, Terminal Configuration and Functions, and moved all pinouts and terminal functions tables to it ... 8
• Added typical conditions statements at the beginning of Section 5, Specifications ....................................... 17
• Added Section 5, Specifications, and moved all electrical and timing specifications to it ................................. 17
• Added Section 5.2, ESD Ratings.................................................................................................. 17
• Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Section 5.19, PMM, Brownout
Reset (BOR) ......................................................................................................................... 29
• Updated notes (1) and (2) and added note (3) in Section 5.25,Wake-up Times From Low-Power Modes and
Reset ................................................................................................................................. 31
• Removed ADC12DIV from the formula for the TYP value in the second row of the tCONVERT parameter in
Section 5.36, 12-Bit ADC, Timing Parameters (removed because ADC12CLK is after division)......................... 39
• For the tEN_CMP parameter in Section 5.42, Comparator_B: Removed "CBPWRMD = 10" from the Test
Conditions in the first row; added second row with Test Conditions of "CBPWRMD = 10" and a MAX value of
100 µs................................................................................................................................. 44
• Changed the test conditions "RF crystal oscillator only" and added note in Section 5.48, Current Consumption,
Reduced-Power Modes ............................................................................................................ 46
• Corrected the link for DN013 Programming Output Power on CC1101 ..................................................... 56
• Changed all instances of "bootstrap loader" to "bootloader" throughout document ........................................ 65
• Corrected spelling of NMIIFG in Table 6-8, System Module Interrupt Vector Registers ................................... 70
• Added Section 8, Device and Documentation Support, and moved Device Nomenclature, ESD Caution, and
Trademarks sections to it ......................................................................................................... 112
• Added Section 9, Mechanical, Packaging, and Orderable Information ..................................................... 118
6 Revision History Copyright © 2009–2018, Texas Instruments Incorporated

CC430F5137, CC430F5135, CC430F5133
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison (1) (2)

USCI
PROGRAM SRAM CHANNEL ADC12_A COMP_B

DEVICE Timer_A (3)
LCD_B CHANNEL I/O PACKAGE
(KB) (KB) A: CHANNELS CHANNELS
B:
UART, LIN,
SPI, I2C
IrDA, SPI
8 ext,
CC430F6137 32 4 5, 3 96 seg 1 1 8 44 64 RGC
4 int
8 ext,
CC430F6135 16 2 5, 3 96 seg 1 1 8 44 64 RGC
4 int
(4)
CC430F6127 32 4 5, 3 96 seg 1 1 N/A 8 44 64 RGC
CC430F6126 32 2 5, 3 96 seg 1 1 N/A 8 44 64 RGC
CC430F6125 16 2 5, 3 96 seg 1 1 N/A 8 44 64 RGC
(4) 6 ext,
CC430F5137 32 4 5, 3 N/A 1 1 6 30 48 RGZ
4 int
6 ext,
CC430F5135 16 2 5, 3 N/A 1 1 6 30 48 RGZ
4 int
6 ext,
CC430F5133 8 2 5, 3 N/A 1 1 6 30 48 RGZ
4 int
(1) For the most current device, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website
at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 5, 3 represents two instantiations of Timer_A, the first instantiation
having 5 capture/compare registers and PWM output generators, and the second instantiation having 3 capture/compare registers and
PWM output generators, respectively.
(4) N/A = not available
3.1 Related Products

For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless
connectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless
possibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for CC430F6137 Review products that are frequently purchased or used in
conjunction with this product.
Reference Designs for CC430F6137 TI Designs Reference Design Library is a robust reference design
library that spans analog, embedded processor, and connectivity. Created by TI experts to
help you jump start your system design, all TI Designs include schematic or block diagrams,
BOMs, and design files to speed your time to market. Search and download designs at
ti.com/tidesigns.
Copyright © 2009–2018, Texas Instruments Incorporated Device Comparison 7

CC430F5137, CC430F5135, CC430F5133
4 Terminal Configuration and Functions

4.1 Pin Diagrams
Figure 4-1 shows the pinout for the CC430F613x devices in the 64-pin RGC package.
P2.5/PM_SVMOUT/CB5/A5/VREF+/VeREF+
P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREF-
P2.7/PM_ADC12CLK/PM_DMAE0/CB7/A7
P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0
P2.1/PM_TA1CCR0A/CB1/A1
P2.6/PM_ACLK/CB6/A6
RST/NMI/SBWTDIO
TEST/SBWTCK
P5.1/XOUT
PJ.3/TCK
P5.0/XIN
DVCC
AVCC
AVSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P1.7/PM_UCA0CLK/PM_UCB0STE/R03 1 48 PJ.2/TMS
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF 2 47 PJ.1/TDI/TCLK
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23 3 46 PJ.0/TDO
LCDCAP/R33 4 45 GUARD
COM0 5 44 R_BIAS
P5.7/COM1/S26 6 43 AVCC_RF
P5.5/COM3/S24 8 41 RF_N
CC430F613x
P5.4/S23 9 40 RF_P
VCORE 10 39 AVCC_RF
DVCC 11 38 AVCC_RF
P1.4/PM_UCB0CLK/PM_UCA0STE/S22 12 37 RF_XOUT
P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21 13 36 RF_XIN
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20 14 35 P5.2/S0
P1.1/PM_RFGDO2/S19 15 34 P5.3/S1
P1.0/PM_RFGDO0/S18 16 33 P4.0/S2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P4.1/S3
P3.0/PM_CBOUT0/PM_TA0CLK/S10
P3.7/PM_SMCLK/S17
P3.3/PM_TA0CCR2A/S13
P4.6/S8
P4.2/S4
P3.6/PM_RFGDO1/S16
P4.5/S7
P4.3/S5
DVCC
P4.7/S9
P4.4/S6
VSS
Exposed die
attached pad
CAUTION: The LCDCAP/R33 must be connected to VSS if not used.

NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default
mapping. See Table 6-6 for details.
Figure 4-1. 64-Pin RGC Package (Top View), CC430F613x
8 Terminal Configuration and Functions Copyright © 2009–2018, Texas Instruments Incorporated

CC430F5137, CC430F5135, CC430F5133
Figure 4-2 shows the pinout for the CC430F612x devices in the 64-pin RGC package.
P2.0/PM_CBOUT1/PM_TA1CLK/CB0
P2.1/PM_TA1CCR0A/CB1
P2.5/PM_SVMOUT/CB5
P2.4/PM_RTCCLK/CB4
P2.7/PM_DMAE0/CB7
P2.6/PM_ACLK/CB6
RST/NMI/SBWTDIO
TEST/SBWTCK
P5.1/XOUT
PJ.3/TCK
P5.0/XIN
DVCC
AVCC
AVSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P1.7/PM_UCA0CLK/PM_UCB0STE/R03 1 48 PJ.2/TMS
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF 2 47 PJ.1/TDI/TCLK
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23 3 46 PJ.0/TDO
LCDCAP/R33 4 45 GUARD
COM0 5 44 R_BIAS
P5.5/COM3/S24 8 41 RF_N
CC430F612x
P5.4/S23 9 40 RF_P
VCORE 10 39 AVCC_RF
DVCC 11 38 AVCC_RF
P1.4/PM_UCB0CLK/PM_UCA0STE/S22 12 37 RF_XOUT
P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21 13 36 RF_XIN
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20 14 35 P5.2/S0
P1.1/PM_RFGDO2/S19 15 34 P5.3/S1
P1.0/PM_RFGDO0/S18 16 33 P4.0/S2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P4.1/S3
P3.0/PM_CBOUT0/PM_TA0CLK/S10
P3.7/PM_SMCLK/S17
P4.6/S8
P4.2/S4
P3.6/PM_RFGDO1/S16
P4.5/S7
P4.3/S5
DVCC
P4.7/S9
P4.4/S6
VSS
Exposed die
attached pad
CAUTION: The LCDCAP/R33 must be connected to VSS if not used.

Figure 4-2. 64-Pin RGC Package (Top View), CC430F612x
Copyright © 2009–2018, Texas Instruments Incorporated Terminal Configuration and Functions 9

CC430F5137, CC430F5135, CC430F5133
Figure 4-3 shows the pinout for the CC430F513x devices in the 48-pin RGZ package.
P2.5/PM_SVMOUT/CB5/A5/VREF+/VeREF+
P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREF-
RST/NMI/SBWTDIO
TEST/SBWTCK
P5.1/XOUT
PJ.2/TMS
PJ.3/TCK
P5.0/XIN
DVCC
AVCC
AVSS
48 47 46 45 44 43 42 41 40 39 38 37
P2.2/PM_TA1CCR1A/CB2/A2 1 36 PJ.1/TDI/TCLK
P2.1/PM_TA1CCR0A/CB1/A1 2 35 PJ.0/TDO
P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0 3 34 GUARD
P1.7/PM_UCA0CLK/PM_UCB0STE 4 33 R_BIAS
P1.6/PM_UCA0TXD/PM_UCA0SIMO 5 32 AVCC_RF
P1.5/PM_UCA0RXD/PM_UCA0SOMI 6 31 AVCC_RF
CC430F513x
VCORE 7 30 RF_N
DVCC 8 29 RF_P
P1.4/PM_UCB0CLK/PM_UCA0STE 9 28 AVCC_RF
P1.3/PM_UCB0SIMO/PM_UCB0SDA 10 27 AVCC_RF
P1.2/PM_UCB0SOMI/PM_UCB0SCL 11 26 RF_XOUT
P1.1/PM_RFGDO2 12 25 RF_XIN
13 14 15 16 17 18 19 20 21 22 23 24
P3.1/PM_TA0CCR0A
P1.0/PM_RFGDO0
P3.4/PM_TA0CCR3A
P3.2/PM_TA0CCR1A
P2.7/PM_ADC12CLK/PM_DMAE0
P3.7/PM_SMCLK
P3.5/PM_TA0CCR4A
P2.6/PM_ACLK
P3.3/PM_TA0CCR2A
P3.6/PM_RFGDO1
P3.0/PM_CBOUT0/PM_TA0CLK
DVCC
VSS
Exposed die
attached pad
Figure 4-3. 48-Pin RGZ Package (Top View), CC430F513x

CC430F5137, CC430F5135, CC430F5133
4.2 Signal Descriptions

Table 4-1 describes the signals for the CC430F613x and CC430F612x devices. See Table 4-2 for the
CC430F513x devices.
Table 4-1. CC430F613x and CC430F612x Terminal Functions

TERMINAL
I/O (1) DESCRIPTION
NAME NO.
General-purpose digital I/O with port interrupt and mappable secondary function
P1.7/ PM_UCA0CLK/
1 I/O Default mapping: USCI_A0 clock input/output; USCI_B0 SPI slave transmit enable
PM_UCB0STE/ R03
Input/output port of lowest analog LCD voltage (V5)
P1.6/ PM_UCA0TXD/ Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
2 I/O
PM_UCA0SIMO/ R13/LCDREF Input/output port of third most positive analog LCD voltage (V3 or V4)
External reference voltage input for regulated LCD voltage
P1.5/ PM_UCA0RXD/
3 I/O Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in
PM_UCA0SOMI/ R23
Input/output port of second most positive analog LCD voltage (V2)
LCD capacitor connection
LCDCAP/ R33 4 I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: Must be connected to VSS if not used.
COM0 5 O LCD common output COM0 for LCD backplane
General-purpose digital I/O
P5.7/ COM1/ S26 6 I/O LCD common output COM1 for LCD backplane
LCD segment output S26
P5.4/ S23 9 I/O
VCORE 10 Regulated core power supply
DVCC 11 Digital power supply
P1.4/ PM_UCB0CLK/ Default mapping: USCI_B0 clock input/output
12 I/O
PM_UCA0STE/ S22 Default mapping: USCI_A0 SPI slave transmit enable
P1.3/ PM_UCB0SIMO/ Default mapping: USCI_B0 SPI slave in master out
13 I/O
PM_UCB0SDA/ S21 Default mapping: USCI_B0 I2C data
P1.2/ PM_UCB0SOMI/ Default mapping: USCI_B0 SPI slave out master in
14 I/O
PM_UCB0SCL/ S20 Default mapping: UCSI_B0 I2C clock
P1.1/ PM_RFGDO2/ S19 15 I/O Default mapping: Radio GDO2 output
General-purpose digital I/O with mappable secondary function
P3.7/ PM_SMCLK/ S17 17 I/O Default mapping: SMCLK output
(1) I = input, O = output

CC430F5137, CC430F5135, CC430F5133
Table 4-1. CC430F613x and CC430F612x Terminal Functions (continued)

TERMINAL
I/O (1) DESCRIPTION
NAME NO.
P3.5/ PM_TA0CCR4A/ S15 19 I/O Default mapping: TA0 CCR4 compare output or capture input
P3.0/ PM_CBOUT0/ PM_TA0CLK/ Default mapping: Comparator_B output
24 I/O
S10 Default mapping: TA0 clock input
P4.7/ S9 26 I/O
P4.6/ S8 27 I/O
P4.5/ S7 28 I/O
P4.4/ S6 29 I/O
P4.3/ S5 30 I/O
P4.2/ S4 31 I/O
P4.1/ S3 32 I/O
P4.0/ S2 33 I/O
P5.3/ S1 34 I/O
P5.2/ S0 35 I/O
RF_XIN 36 I Input terminal for RF crystal oscillator, or external clock input
RF_XOUT 37 O Output terminal for RF crystal oscillator
AVCC_RF 38 Radio analog power supply
RF Positive RF input to LNA in receive mode
RF_P 40
I/O Positive RF output from PA in transmit mode
RF Negative RF input to LNA in receive mode
RF_N 41
I/O Negative RF output from PA in transmit mode
RBIAS 44 External bias resistor for radio reference current
GUARD 45 Power supply connection for digital noise isolation
PJ.0/ TDO 46 I/O
Test data output port

CC430F5137, CC430F5135, CC430F5133
Table 4-1. CC430F613x and CC430F612x Terminal Functions (continued)

TERMINAL
I/O (1) DESCRIPTION
NAME NO.
PJ.1/ TDI/ TCLK 47 I/O
Test data input or test clock input
PJ.2/ TMS 48 I/O
Test mode select
PJ.3/ TCK 49 I/O
Test clock
Test mode pin – select digital I/O on JTAG pins
TEST/ SBWTCK 50 I
Spy-Bi-Wire input clock
Reset input active low
RST/NMI/ SBWTDIO 51 I/O Nonmaskable interrupt input
Spy-Bi-Wire data input/output
AVSS 53 Analog ground supply for ADC12
P5.1/ XOUT 54 I/O
Output terminal of crystal oscillator XT1
P5.0/ XIN 55 I/O
Input terminal for crystal oscillator XT1
AVCC 56 Analog power supply
Default mapping: ADC12CLK output
P2.7/ PM_ADC12CLK/
57 I/O Default mapping: DMA external trigger input
PM_DMAE0/ CB7 (/A7)
Comparator_B input CB7
Analog input A7 – 12-bit ADC (CC430F613x only)
Default mapping: ACLK output
P2.6/ PM_ACLK/ CB6 (/A6) 58 I/O
Default mapping: SVM output
P2.5/ PM_SVMOUT/ CB5 Comparator_B input CB5
59 I/O
(/A5/ VREF+/ VeREF+) Analog input A5 – 12-bit ADC (CC430F613x only)
Output of reference voltage to the ADC (CC430F613x only)
Input for an external reference voltage to the ADC (CC430F613x only)
Default mapping: RTCCLK output
P2.4/ PM_RTCCLK/ CB4 Comparator_B input CB4
60 I/O
(/A4/ VREF-/ VeREF-) Analog input A4 – 12-bit ADC (CC430F613x only)
Negative terminal for the ADC reference voltage for both sources, the internal reference
voltage, or an external applied reference voltage (CC430F613x only)
Default mapping: TA1 CCR2 compare output or capture input
P2.3/ PM_TA1CCR2A/ CB3 (/A3) 61 I/O
Default mapping: Comparator_B output
P2.0/ PM_CBOUT1/ PM_TA1CLK/
64 I/O Default mapping: TA1 clock input
CB0 (/A0)
Ground supply
VSS, Exposed die attach pad CAUTION: The exposed die attach pad must be connected to a solid ground plane as
this is the ground connection for the chip.

CC430F5137, CC430F5135, CC430F5133
Table 4-2 describes the signals for the CC430F513x devices. See Table 4-1 for the CC430F613x and
CC430F612x devices.
Table 4-2. CC430F513x Terminal Functions

TERMINAL
I/O (1) DESCRIPTION
NAME NO.
P2.2/ PM_TA1CCR1A/ CB2/ A2 1 I/O
Analog input A2 – 12-bit ADC
Default mapping: Comparator_B output
P2.0/ PM_CBOUT1/ PM_TA1CLK/
3 I/O Default mapping: TA1 clock input
CB0/ A0
P1.7/ PM_UCA0CLK/
4 I/O Default mapping: USCI_A0 clock input/output
PM_UCB0STE
Default mapping: USCI_B0 SPI slave transmit enable
P1.6/ PM_UCA0TXD/ General-purpose digital I/O with port interrupt and mappable secondary function
5 I/O
PM_UCA0SIMO Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
P1.5/ PM_UCA0RXD/
6 I/O Default mapping: USCI_A0 UART receive data
PM_UCA0SOMI
Default mapping: USCI_A0 SPI slave out master in
VCORE 7 Regulated core power supply
P1.4/ PM_UCB0CLK/
9 I/O Default mapping: USCI_B0 clock input/output
PM_UCA0STE
Default mapping: USCI_A0 SPI slave transmit enable
P1.3/ PM_UCB0SIMO/
10 I/O Default mapping: USCI_B0 SPI slave in master out
PM_UCB0SDA
Default mapping: USCI_B0 I2C data
P1.2/ PM_UCB0SOMI/
11 I/O Default mapping: USCI_B0 SPI slave out master in
PM_UCB0SCL
Default mapping: UCSI_B0 I2C clock
P1.1/ PM_RFGDO2 12 I/O
Default mapping: Radio GDO2 output
P3.7/ PM_SMCLK 14 I/O
Default mapping: SMCLK output
P3.5/ PM_TA0CCR4A 16 I/O
P3.0/ PM_CBOUT0/ PM_TA0CLK 21 I/O Default mapping: Comparator_B output
Default mapping: TA0 clock input
(1) I = input, O = output

CC430F5137, CC430F5135, CC430F5133
Table 4-2. CC430F513x Terminal Functions (continued)

TERMINAL
I/O (1) DESCRIPTION
NAME NO.
P2.7/ PM_ADC12CLK/
23 I/O Default mapping: ADC12CLK output
PM_DMAE0
Default mapping: DMA external trigger input
P2.6/ PM_ACLK 24 I/O
Default mapping: ACLK output
RF_XIN 25 I Input terminal for RF crystal oscillator, or external clock input
RF_XOUT 26 O Output terminal for RF crystal oscillator
RF Positive RF input to LNA in receive mode
RF_P 29
I/O Positive RF output from PA in transmit mode
RF Negative RF input to LNA in receive mode
RF_N 30
I/O Negative RF output from PA in transmit mode
RBIAS 33 External bias resistor for radio reference current
GUARD 34 Power supply connection for digital noise isolation
PJ.0/ TDO 35 I/O
Test data output port
PJ.1/ TDI/ TCLK 36 I/O
Test data input or test clock input
PJ.2/ TMS 37 I/O
Test mode select
PJ.3/ TCK 38 I/O
Test clock
Test mode pin – select digital I/O on JTAG pins
TEST/ SBWTCK 39 I
Spy-Bi-Wire input clock
Reset input active low
RST/NMI/ SBWTDIO 40 I/O Nonmaskable interrupt input
Spy-Bi-Wire data input/output
AVSS 42 Analog ground supply for ADC12
P5.1/ XOUT 43 I/O
Output terminal of crystal oscillator XT1
P5.0/ XIN 44 I/O
Input terminal for crystal oscillator XT1
AVCC 45 Analog power supply
Default mapping: SVM output
P2.5/ PM_SVMOUT/ CB5/ Comparator_B input CB5
46 I/O
A5/ VREF+/ VeREF+ Analog input A5 – 12-bit ADC
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
Default mapping: RTCCLK output
P2.4/ PM_RTCCLK/ CB4/ Comparator_B input CB4
47 I/O
A4/ VREF-/ VeREF- Analog input A4 – 12-bit ADC
Negative terminal for the ADC reference voltage for both sources, the internal reference
voltage, or an external applied reference voltage

CC430F5137, CC430F5135, CC430F5133
Table 4-2. CC430F513x Terminal Functions (continued)

TERMINAL
I/O (1) DESCRIPTION
NAME NO.
Ground supply
VSS, Exposed die attach pad The exposed die attach pad must be connected to a solid ground plane as this is
the ground connection for the chip.

CC430F5137, CC430F5135, CC430F5133
5 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
5.1 Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage applied at DVCC and AVCC pins to VSS –0.3 4.1 V
VCC + 0.3
Voltage applied to any pin (excluding VCORE, RF_P, RF_N, and R_BIAS) (2) –0.3 V
(4.1 V Maximum)
(2)
Voltage applied to VCORE, RF_P, RF_N, and R_BIAS –0.3 2.0 V
Input RF level at pins RF_P and RF_N 10 dBm
Diode current at any device terminal ±2 mA
Storage temperature, Tstg (3) –55 150 °C
Maximum junction temperature, TJ 95 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage range applied at all DVCC and PMMCOREVx = 0
1.8 3.6
AVCC pins (1) during program execution and (default after POR)
flash programming with PMM default settings,
Radio is not operational with PMMCOREVx = 0 PMMCOREVx = 1 2.0 3.6
or 1 (2) (3)
Supply voltage range applied at all DVCC and PMMCOREVx = 2 2.2 3.6
AVCC pins (1) during program execution, flash
VCC programming, and radio operation with PMM PMMCOREVx = 3 2.4 3.6 V
default settings (2) (3)
Supply voltage range applied at all DVCC and
AVCC pins (1) during program execution, flash
PMMCOREVx = 2,
programming and radio operation with
SVSHRVLx = SVSHRRRLx = 1 2.0 3.6
PMMCOREVx = 2, high-side SVS level lowered
or SVSHE = 0
(SVSHRVL = SVSMHRRL = 1) or high-side SVS
disabled (SVSHE = 0) (2) (3) (4)
VSS Supply voltage applied at the exposed die attach VSS and AVSS pin 0 V
TA Operating free-air temperature –40 85 °C
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.21 threshold parameters for
the exact values and further details.
(4) Lowering the high-side SVS level or disabling the high-side SVS might cause the LDO to operate out of regulation, but the core voltage
will still stay within its limits and is still supervised by the low-side SVS, ensuring reliable operation.
Copyright © 2009–2018, Texas Instruments Incorporated Specifications 17
CC430F5137, CC430F5135, CC430F5133
Recommended Operating Conditions (continued)

MIN NOM MAX UNIT
TJ Operating junction temperature –40 85 °C
(5)
CVCORE Recommended capacitor at VCORE 470 nF
CDVCC/
Capacitor ratio of capacitor at DVCC to capacitor at VCORE 10
CVCORE
PMMCOREVx = 0
0 8
(default condition)
fSYSTEM Processor (MCLK) frequency (6) (see Figure 5-1) PMMCOREVx = 1 0 12 MHz
PMMCOREVx = 2 0 16
PMMCOREVx = 3 0 20
PINT Internal power dissipation VCC × IDVCC W
(VCC – VIOH) ×
PIO I/O power dissipation of I/O pins powered by DVCC W
IIOH + VIOL × IIOL
PMAX Maximum allowed power dissipation, PMAX > PIO + PINT (TJ – TA) / θJA W
(5) A capacitor tolerance of ±20% or better is required.
(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
20
3
System Frequency - MHz
16
2 2, 3
12
1 1, 2 1, 2, 3
0 0, 1 0, 1, 2 0, 1, 2, 3
0
1.8 2.0 2.2 2.4 3.6
Supply Voltage - V
NOTE: The numbers within the fields are the supported PMMCOREVx settings.
Figure 5-1. Maximum System Frequency
18 Specifications Copyright © 2009–2018, Texas Instruments Incorporated

CC430F5137, CC430F5135, CC430F5133
5.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)

EXECUTION
PARAMETER VCC PMMCOREVx 1 MHz 8 MHz 12 MHz 16 MHz 20 MHz UNIT
MEMORY
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
0 0.23 0.26 1.35 1.60
(4)
1 0.25 0.28 1.55 2.30 2.65
IAM, Flash Flash 3V mA
2 0.27 0.30 1.75 2.60 3.45 3.90
3 0.28 0.32 1.85 2.75 3.65 4.55 5.10
0 0.18 0.20 0.95 1.10
(5)
1 0.20 0.22 1.10 1.60 1.85
IAM, RAM RAM 3V mA
2 0.21 0.24 1.20 1.80 2.40 2.70
3 0.22 0.25 1.30 1.90 2.50 3.10 3.60
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
(4) Active mode supply current when program executes in flash at a nominal supply voltage of 3 V.
(5) Active mode supply current when program executes in RAM at a nominal supply voltage of 3 V.
5.5 Typical Characteristics – Active Mode Supply Currents
5
VCC = 3.0 V
PMMVCOREx = 3
IAM – Active Mode Supply Current – mA
3
PMMVCOREx = 2
2
PMMVCOREx = 1
1
PMMVCOREx = 0
0
0 5 10 15 20
MCLK Frequency – MHz
Figure 5-2. Active Mode Supply Current vs MCLK Frequency

CC430F5137, CC430F5135, CC430F5133
5.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
TEMPERATURE (TA)
PARAMETER VCC PMMCOREVx –40°C 25°C 60°C 85°C UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
2.2 V 0 80 100 80 100 80 100 80 100
ILPM0,1MHz Low-power mode 0 (3) (4)
µA
3V 3 90 110 90 110 90 110 90 110
2.2 V 0 6.5 11 6.5 11 6.5 11 6.5 11
ILPM2 Low-power mode 2 (5) (4)
µA
3V 3 7.5 12 7.5 12 7.5 12 7.5 12
0 1.8 2.0 2.6 3.0 4.0 4.4 5.9
Low-power mode 3, crystal 1 1.9 2.1 3.2 4.8

ILPM3,XT1LF 3V µA
mode (6) (4) 2 2.0 2.2 3.4 5.1
3 2.0 2.2 2.9 3.5 4.8 5.3 7.4
0 0.9 1.1 2.3 2.1 3.7 3.5 5.6
Low-power mode 3, 1 1.0 1.2 2.3 3.9

ILPM3,VLO 3V µA
VLO mode (7) (4) 2 1.1 1.3 2.5 4.2
3 1.1 1.3 2.6 2.6 4.5 4.4 7.1
0 0.8 1.0 2.2 2.0 3.6 3.4 5.5
1 0.9 1.1 2.2 3.8
ILPM4 Low-power mode 4 (8) (4)
3V µA
2 1.0 1.2 2.4 4.1
3 1.0 1.2 2.5 2.5 4.4 4.3 7.0
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting =
1 MHz operation, DCO bias generator enabled.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz

CC430F5137, CC430F5135, CC430F5133
5.7 Typical Characteristics – Low-Power Mode Supply Currents
5 5
VCC = 3.0 V
VCC = 3.0 V
ILPM3,XT1LF - LPM3 Supply Current - µA
4 4
ILPM4 - LPM4 Supply Current - µA

3 3
PMMCOREVx = 3
2 2
PMMCOREVx = 0 PMMCOREVx = 3
1 1
PMMCOREVx = 0
0 0
-40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80
TA - Free-Air Temperature - °C TA - Free-Air Temperature - °C
Figure 5-3. LPM3 Supply Current vs Temperature Figure 5-4. LPM4 Supply Current vs Temperature

CC430F5137, CC430F5135, CC430F5133
5.8 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
TEMPERATURE (TA)
PARAMETER VCC PMMCOREVx –40°C 25°C 60°C 85°C UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
0 2.2 2.4 3.5 4.9
Low-power mode 3
ILPM3 1 2.3 2.5 3.7 5.3
(LPM3) current, LCD 4-
LCD, 3V µA
mux mode, external 2 2.4 2.6 3.9 5.6
ext. bias
biasing (3) (4)
3 2.4 2.6 4.0 5.8
Low-power mode 3 0 3.1 3.3 4.0 4.3 5.8 7.4
ILPM3 (LPM3) current, LCD 4- 1 3.2 3.4 4.5 6.2
LCD, mux mode, internal 3V µA
int. bias biasing, charge pump 2 3.3 3.5 4.7 6.5
disabled (3) (5) 3 3.3 3.5 4.3 4.8 6.7 8.9
0 4.0
2.2 V 1 4.1
Low-power mode 3
2 4.2
(LPM3) current, LCD 4-
ILPM3
mux mode, internal 0 4.2 µA
LCD,CP
biasing, charge pump
1 4.3
enabled (3) (6) 3V
2 4.5
3 4.5
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
(4) LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
(5) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
(6) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
5.9 Thermal Resistance Characteristics, CC430F51xx

PACKAGE VALUE
Low-K board 98°C/W
θJA Junction-to-ambient thermal resistance, still air 48 QFN (RGZ)
High-K board 28°C/W
5.10 Thermal Resistance Characteristics, CC430F61xx

PACKAGE VALUE
Low-K board 83°C/W
θJA Junction-to-ambient thermal resistance, still air 64 QFN (RGC)
High-K board 26°C/W

CC430F5137, CC430F5135, CC430F5133
5.11 Digital Inputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
1.8 V 0.80 1.40
VIT+ Positive-going input threshold voltage V
3V 1.50 2.10
1.8 V 0.45 1.00
VIT– Negative-going input threshold voltage V
3V 0.75 1.65
1.8 V 0.3 0.8
Vhys Input voltage hysteresis (VIT+ – VIT–) V
3V 0.4 1.0
For pullup: VIN = VSS
RPull Pullup or pulldown resistor 20 35 50 kΩ
For pulldown: VIN = VCC
CI Input capacitance VIN = VSS or VCC 5 pF
(1) (2)
Ilkg(Px.y) High-impedance leakage current See 1.8 V, 3 V ±50 nA
Ports with interrupt capability [see
External interrupt timing (external trigger block diagram (Section 1.4) and
t(int) 1.8 V, 3 V 20 ns
pulse duration to set interrupt flag) (3) terminal function descriptions
(Section 4.2)]
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).

CC430F5137, CC430F5135, CC430F5133
5.12 Digital Outputs

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
(2)
I(OHmax) = –1 mA, PxDS.y = 0 VCC – 0.25 VCC
1.8 V
High-level output voltage, I(OHmax) = –3 mA, PxDS.y = 0 (3) VCC – 0.60 VCC
VOH V
reduced drive strength (1) I(OHmax) = –2 mA, PxDS.y = 0 (2) VCC – 0.25 VCC
3V
I(OHmax) = –6 mA, PxDS.y = 0 (3) VCC – 0.60 VCC
(2)
I(OLmax) = 1 mA, PxDS.y = 0 VSS VSS + 0.25
1.8 V
Low-level output voltage, I(OLmax) = 3 mA, PxDS.y = 0 (3) VSS VSS + 0.60
VOL V
reduced drive strength (1) I(OLmax) = 2 mA, PxDS.y = 0 (2) VSS VSS + 0.25
3V
I(OLmax) = 6 mA, PxDS.y = 0 (3) VSS VSS + 0.60
1.8 V
High-level output voltage, I(OHmax) = –10 mA, PxDS.y = 1 (3) VCC – 0.60 VCC
VOH V
full drive strength I(OHmax) = –5 mA, PxDS.y = 1 (2)
VCC – 0.25 VCC
3V
1.8 V
Low-level output voltage, I(OLmax) = 10 mA, PxDS.y = 1 (3) VSS VSS + 0.60
VOL V
full drive strength I(OLmax) = 5 mA, PxDS.y = 1 (2)
VSS VSS + 0.25
3V
VCC = 1.8 V,
16
Port output frequency (4) (5)
PMMCOREVx = 0
fPx.y CL = 20 pF, RL MHz
(with load) VCC = 3 V,
25
PMMCOREVx = 2
VCC = 1.8 V,
16
PMMCOREVx = 0
fPort_CLK Clock output frequency CL = 20 pF (5) MHz
VCC = 3 V,
25
PMMCOREVx = 2
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
(4) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
(5) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

CC430F5137, CC430F5135, CC430F5133
5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
25 8
V CC = 3.0 V V CC = 1.8 V
IOL - Typical Low-Level Output Current - mA

P4.3 P4.3 TA = 25°C
7
20 TA = 25°C
6
TA = 85°C
TA = 85°C 5
15
10
3
2
5
1
0 0
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2
V OL - Low-Level Output Voltage - V V OL - Low-Level Output Voltage - V
Figure 5-5. Typical Low-Level Output Current vs Low-Level Figure 5-6. Typical Low-Level Output Current vs Low-Level
Output Voltage Output Voltage
0 0
V CC = 3.0 V V CC = 1.8 V
IOH - Typical High-Level Output Current - mA
P4.3 P4.3
-1
-5
-2
-3
-10
-4
-15
-5
TA = 85°C
TA = 85°C
-6
-20
TA = 25°C
TA = 25°C -7
-25 -8
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2
V OH - High-Level Output Voltage - V V OH - High-Level Output Voltage - V
Figure 5-7. Typical High-Level Output Current vs High-Level Figure 5-8. Typical High-Level Output Current vs High-Level

CC430F5137, CC430F5135, CC430F5133
5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
60 25
V CC = 3.0 V TA = 25°C V CC = 1.8 V

P4.3 P4.3
TA = 25°C
50
TA = 85°C 20
40 TA = 85°C
15
30
10
20
5
10
0 0
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2
V OL - Low-Level Output Voltage - V V OL - Low-Level Output Voltage - V
Figure 5-9. Typical Low-Level Output Current vs Low-Level Figure 5-10. Typical Low-Level Output Current vs Low-Level
0 0
V CC = 3.0 V V CC = 1.8 V
P4.3 P4.3
-10
-5
-20
-10
-30
-15 TA = 85°C
-40
TA = 85°C -20 TA = 25°C

-50
TA = 25°C
-60 -25
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2
V OH - High-Level Output Voltage - V V OH - High-Level Output Voltage - V
Figure 5-11. Typical High-Level Output Current vs High-Level Figure 5-12. Typical High-Level Output Current vs High-Level

CC430F5137, CC430F5135, CC430F5133
5.15 Crystal Oscillator, XT1, Low-Frequency Mode (1)

fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1, 0.075
TA = 25°C
Differential XT1 oscillator crystal fOSC = 32768 Hz, XTS = 0,
ΔIDVCC.LF current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2, 3V 0.170 µA
drive setting, LF mode TA = 25°C
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3, 0.290
TA = 25°C
XT1 oscillator crystal frequency,
fXT1,LF0 XTS = 0, XT1BYPASS = 0 32768 Hz
LF mode
XT1 oscillator logic-level square-
fXT1,LF,SW XTS = 0, XT1BYPASS = 1 (2) (3)
10 32.768 50 kHz
wave input frequency, LF mode
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0, 210
Oscillation allowance for fXT1,LF = 32768 Hz, CL,eff = 6 pF
OALF kΩ
LF crystals (4) XTS = 0,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0 (6) 2
Integrated effective load XTS = 0, XCAPx = 1 5.5
CL,eff pF
capacitance, LF mode (5) XTS = 0, XCAPx = 2 8.5
XTS = 0, XCAPx = 3 12.0
XTS = 0, Measured at ACLK,
Duty cycle, LF mode 30% 70%
fXT1,LF = 32768 Hz
Oscillator fault frequency,
fFault,LF XTS = 0 (8) 10 10000 Hz
LF mode (7)
fOSC = 32768 Hz, XTS = 0,
TA = 25°C, CL,eff = 6 pF
tSTART,LF Start-up time, LF mode 3V ms
fOSC = 32768 Hz, XTS = 0,
TA = 25°C, CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this datasheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For XT1DRIVEx = 0, CL,eff ≤ 6 pF
• For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF
• For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF
• For XT1DRIVEx = 3, CL,eff ≥ 6 pF
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.

CC430F5137, CC430F5135, CC430F5133
5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V 6 9.4 14 kHz
dfVLO/dT VLO frequency temperature drift Measured at ACLK (1) 1.8 V to 3.6 V 0.5 %/°C
dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK (2) 1.8 V to 3.6 V 4 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
5.17 Internal Reference, Low-Frequency Oscillator (REFO)

IREFO REFO oscillator current consumption TA = 25°C 1.8 V to 3.6 V 3 µA
fREFO REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz
Full temperature range 1.8 V to 3.6 V ±3.5%
REFO absolute tolerance calibrated
TA = 25°C 3V ±1.5%
(1)
dfREFO/dT REFO frequency temperature drift Measured at ACLK 1.8 V to 3.6 V 0.01 %/°C
dfREFO/dVC (2)
REFO frequency supply voltage drift Measured at ACLK 1.8 V to 3.6 V 1.0 %/V
C
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%
tSTART REFO start-up time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
5.18 DCO Frequency

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1)
fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz
fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz
(1)
(1)
(1)
(1)
fDCO(7,31) DCO frequency (7, 31) (1) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz
Frequency step between range
SDCORSEL SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio
DCORSEL and DCORSEL + 1
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
CC430F5137, CC430F5135, CC430F5133
DCO Frequency (continued)

Frequency step between tap DCO
SDCO SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio
and DCO + 1
Duty cycle Measured at SMCLK 40% 50% 60%
dfDCO/dT DCO frequency temperature drift fDCO = 1 MHz 0.1 %/°C
dfDCO/dVCC DCO frequency voltage drift fDCO = 1 MHz 1.9 %/V
100
VCC = 3.0 V
TA = 25°C
10
fDCO – MHz
DCOx = 31
1
DCOx = 0
0.1
0 1 2 3 4 5 6 7
DCORSEL
Figure 5-13. Typical DCO Frequency
5.19 PMM, Brownout Reset (BOR)

V(DVCC_BOR_IT–) BORH on voltage, DVCC falling level | dDVCC/dt | < 3 V/s 1.45 V
V(DVCC_BOR_IT+) BORH off voltage, DVCC rising level | dDVCC/dt | < 3 V/s 0.80 1.30 1.50 V
V(DVCC_BOR_hys) BORH hysteresis 50 250 mV
tRESET Pulse duration required at RST/NMI pin to accept a reset 2 µs
5.20 PMM, Core Voltage

VCORE3(AM) Core voltage, active mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.90 V
VCORE1(AM) Core voltage, active mode, PMMCOREV = 1 2 V ≤ DVCC ≤ 3.6 V 1.60 V
VCORE3(LPM) Core voltage, low-current mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.94 V
VCORE1(LPM) Core voltage, low-current mode, PMMCOREV = 1 2 V ≤ DVCC ≤ 3.6 V 1.64 V

CC430F5137, CC430F5135, CC430F5133
5.21 PMM, SVS High Side

SVSHE = 0, DVCC = 3.6 V 0
nA
I(SVSH) SVS current consumption SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 1.5 µA
SVSHE = 1, SVSHRVL = 0 1.53 1.60 1.67
SVSHE = 1, SVSHRVL = 1 1.73 1.80 1.87
V(SVSH_IT–) SVSH on voltage level (1) V
SVSHE = 1, SVSHRVL = 2 1.93 2.00 2.07
SVSHE = 1, SVSHRVL = 3 2.03 2.10 2.17
SVSHE = 1, SVSMHRRL = 0 1.60 1.70 1.80
SVSHE = 1, SVSMHRRL = 1 1.80 1.90 2.00
SVSHE = 1, SVSMHRRL = 2 2.00 2.10 2.20
SVSHE = 1, SVSMHRRL = 3 2.10 2.20 2.30
V(SVSH_IT+) SVSH off voltage level (1) V
SVSHE = 1, SVSMHRRL = 4 2.25 2.35 2.50
SVSHE = 1, SVSMHRRL = 5 2.52 2.65 2.78
SVSHE = 1, SVSMHRRL = 6 2.85 3.00 3.15
SVSHE = 1, SVSMHRRL = 7 2.85 3.00 3.15
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 2.5
tpd(SVSH) SVSH propagation delay µs
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 20
SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 12.5
t(SVSH) SVSH on or off delay time µs
SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 100
dVDVCC/dt DVCC rise time 0 1000 V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the CC430 Family User's Guide on recommended settings and use.
5.22 PMM, SVM High Side

SVMHE = 0, DVCC = 3.6 V 0
nA
I(SVMH) SVMH current consumption SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 200
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 1.5 µA
SVMHE = 1, SVSMHRRL = 0 1.60 1.70 1.80
SVMHE = 1, SVSMHRRL = 1 1.80 1.90 2.00
SVMHE = 1, SVSMHRRL = 2 2.00 2.10 2.20
SVMHE = 1, SVSMHRRL = 3 2.10 2.20 2.30
V(SVMH) SVMH on or off voltage level (1) SVMHE = 1, SVSMHRRL = 4 2.25 2.35 2.50 V
SVMHE = 1, SVSMHRRL = 5 2.52 2.65 2.78
SVMHE = 1, SVSMHRRL = 6 2.85 3.00 3.15
SVMHE = 1, SVSMHRRL = 7 2.85 3.00 3.15
SVMHE = 1, SVMHOVPE = 1 3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 2.5
tpd(SVMH) SVMH propagation delay µs
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 20
SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 12.5
t(SVMH) SVMH on or off delay time µs
SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 100
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the CC430 Family User's Guide on recommended settings and use.

CC430F5137, CC430F5135, CC430F5133
5.23 PMM, SVS Low Side

SVSLE = 0, PMMCOREV = 2 0 nA
I(SVSL) SVSL current consumption SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 1.5 µA
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 2.5
tpd(SVSL) SVSL propagation delay µs
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 20
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 12.5
t(SVSL) SVSL on or off delay time µs
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 100
5.24 PMM, SVM Low Side

SVMLE = 0, PMMCOREV = 2 0 nA
I(SVML) SVML current consumption SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200 nA
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 1.5 µA
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5
tpd(SVML) SVML propagation delay µs
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 12.5
t(SVML) SVML on or off delay time µs
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 100
5.25 Wake-up Times From Low-Power Modes and Reset

PMMCOREV = SVSMLRRL = n fMCLK ≥ 4.0 MHz 5
Wake-up time from LPM2, LPM3, or
tWAKE-UP-FAST (where n = 0, 1, 2, or 3), µs
LPM4 to active mode (1) fMCLK < 4.0 MHz 6
SVSLFP = 1
PMMCOREV = SVSMLRRL = n
Wake-up time from LPM2, LPM3, or
tWAKE-UP-SLOW (where n = 0, 1, 2, or 3), 150 165 µs
LPM4 to active mode (2) (3)
SVSLFP = 0
Wake-up time from RST or BOR
tWAKE-UP-RESET 2 3 ms
event to active mode (4)
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance
mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in
the Power Management Module and Supply Voltage Supervisor chapter of the CC430 Family User's Guide.
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low
current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the
Power Management Module and Supply Voltage Supervisor chapter of the CC430 Family User's Guide.
(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the
performance mode settings as for LPM2, LPM3, and LPM4.
(4) This value represents the time from the wake-up event to the reset vector execution.
5.26 Timer_A
Internal: SMCLK or ACLK,
fTA Timer_A input clock frequency External: TACLK, 1.8 V, 3 V 25 MHz
Duty cycle = 50% ±10%
All capture inputs,
tTA,cap Timer_A capture timing 1.8 V, 3 V 20 ns
Minimum pulse duration required for capture

CC430F5137, CC430F5135, CC430F5133
5.27 USCI (UART Mode) Clock Frequency

PARAMETER TEST CONDITIONS MIN MAX UNIT
fUSCI USCI input clock frequency External: UCLK, fSYSTEM MHz
fBITCLK BITCLK clock frequency (equals baud rate in MBaud) 1 MHz
5.28 USCI (UART Mode)

PARAMETER VCC MIN MAX UNIT
2.2 V 50 600
tτ UART receive deglitch time (1) ns
3V 50 600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
5.29 USCI (SPI Master Mode) Clock Frequency

PARAMETER TEST CONDITIONS MIN MAX UNIT
fUSCI USCI input clock frequency fSYSTEM MHz
5.30 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-14
and Figure 5-15)
PARAMETER TEST CONDITIONS PMMCOREVx VCC MIN MAX UNIT
1.8 V 55
0
3V 38
tSU,MI SOMI input data setup time ns
2.4 V 30
3
3V 25
1.8 V 0
0
3V 0
tHD,MI SOMI input data hold time ns
2.4 V 0
3
3V 0
1.8 V 20
0
UCLK edge to SIMO valid, 3V 18
tVALID,MO SIMO output data valid time (2) ns
CL = 20 pF 2.4 V 16
3
3V 15
1.8 V –10
0
(3)
3V –8
tHD,MO SIMO output data hold time CL = 20 pF ns
2.4 V –10
3
3V –8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-14 and Figure 5-15.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
14 and Figure 5-15.

CC430F5137, CC430F5135, CC430F5133
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-14. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI tLO/HI
tHD,MI
tSU,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-15. SPI Master Mode, CKPH = 1

CC430F5137, CC430F5135, CC430F5133
5.31 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-16
and Figure 5-17)
PARAMETER TEST CONDITIONS PMMCOREVx VCC MIN MAX UNIT
1.8 V 11
0
3V 8
tSTE,LEAD STE lead time, STE low to clock ns
2.4 V 7
3
3V 6
1.8 V 3
0
STE lag time, Last clock to STE 3V 3
tSTE,LAG ns
high 2.4 V 3
3
3V 3
1.8 V 66
0
STE access time, STE low to 3V 50
tSTE,ACC ns
SOMI data out 2.4 V 36
3
3V 30
1.8 V 30
0
STE disable time, STE high to 3V 23
tSTE,DIS ns
SOMI high impedance 2.4 V 16
3
3V 13
1.8 V 5
0
3V 5
tSU,SI SIMO input data setup time ns
2.4 V 2
3
3V 2
1.8 V 5
0
3V 5
tHD,SI SIMO input data hold time ns
2.4 V 5
3
3V 5
1.8 V 76
0
UCLK edge to SOMI valid, 3V 60
tVALID,SO SOMI output data valid time (2) ns
CL = 20 pF 2.4 V 44
3
3V 40
1.8 V 18
0
3V 12
tHD,SO SOMI output data hold time (3) CL = 20 pF ns
2.4 V 10
3
3V 8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-16 and Figure 5-17.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-16
and Figure 5-17.

CC430F5137, CC430F5135, CC430F5133
tSTE,LEAD tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI tLO/HI tSU,SI

tHD,SI
SIMO
tHD,SO
tSTE,ACC tVALID,SO tSTE,DIS
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 0
tSTE,LEAD tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI tLO/HI
tHD,SI
tSU,SI
SIMO
tHD,MO
tSTE,ACC tVALID,SO tSTE,DIS
SOMI
Figure 5-17. SPI Slave Mode, CKPH = 1

CC430F5137, CC430F5135, CC430F5133
5.32 USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
Internal: SMCLK, ACLK
fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz
fSCL SCL clock frequency 2.2 V, 3 V 0 400 kHz
fSCL ≤ 100 kHz 4.0
tHD,STA Hold time (repeated) START 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
fSCL ≤ 100 kHz 4.7
tSU,STA Setup time for a repeated START 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
tHD,DAT Data hold time 2.2 V, 3 V 0 ns
tSU,DAT Data setup time 2.2 V, 3 V 250 ns
fSCL ≤ 100 kHz 4.0
tSU,STO Setup time for STOP 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
2.2 V 50 600
tSP Pulse duration of spikes suppressed by input filter ns
3V 50 600
tHD,STA tSU,STA tHD,STA tBUF
SDA
tLOW tHIGH tSP

SCL
tSU,DAT tSU,STO
tHD,DAT
Figure 5-18. I2C Mode Timing

CC430F5137, CC430F5135, CC430F5133
5.33 LCD_B Operating Conditions

PARAMETER CONDITIONS MIN NOM MAX UNIT
Supply voltage range, charge LCDCPEN = 1, 0000 < VLCDx ≤ 1111
VCC,LCD_B,CP en,3.6 2.2 3.6 V
pump enabled, VLCD ≤ 3.6 V (charge pump enabled, VLCD ≤ 3.6 V)
Supply voltage range, charge LCDCPEN = 1, 0000 < VLCDx ≤ 1100
VCC,LCD_B,CP en,3.3 2.0 3.6 V
pump enabled, VLCD ≤ 3.3 V (charge pump enabled, VLCD ≤ 3.3 V)
Supply voltage range, internal
VCC,LCD_B,int. bias LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V
biasing, charge pump disabled
Supply voltage range, external
VCC,LCD_B,ext. bias LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V
biasing, charge pump disabled
Supply voltage range, external
LCD voltage, internal or
VCC,LCD_B,VLCDEXT LCDCPEN = 0, VLCDEXT = 1 2.0 3.6 V
external biasing, charge pump
disabled
External LCD voltage at
LCDCAP/R33, internal or
VLCDCAP/R33 LCDCPEN = 0, VLCDEXT = 1 2.4 3.6 V
external biasing, charge pump
disabled
Capacitor on LCDCAP when LCDCPEN = 1, VLCDx > 0000 (charge
CLCDCAP 4.7 4.7 10 µF
charge pump enabled pump enabled)
fLCD = 2 × mux × fFRAME with
fFrame LCD frame frequency range 0 100 Hz
mux = 1 (static), 2, 3, 4
fACLK,in ACLK input frequency range 30 32 40 kHz
CPanel Panel capacitance 100-Hz frame frequency 10000 pF
VR33 Analog input voltage at R33 LCDCPEN = 0, VLCDEXT = 1 2.4 VCC + 0.2 V
VR03 +
LCDREXT = 1, LCDEXTBIAS = 1, 2/3 ×
VR23,1/3bias Analog input voltage at R23 VR13 VR33 V
LCD2B = 0 (VR33 –
VR03)
VR03 +
Analog input voltage at R13 LCDREXT = 1, LCDEXTBIAS = 1, 1/3 ×
VR13,1/3bias VR03 VR23 V
with 1/3 biasing LCD2B = 0 (VR33 –
VR03)
VR03 +
Analog input voltage at R13 LCDREXT = 1, LCDEXTBIAS = 1, 1/2 ×
VR13,1/2bias VR03 VR33 V
with 1/2 biasing LCD2B = 1 (VR33 –
VR03)
VR03 Analog input voltage at R03 R0EXT = 1 VSS V
Voltage difference between
VLCD – VR03 LCDCPEN = 0, R0EXT = 1 2.4 VCC + 0.2 V
VLCD and R03
External LCD reference
VLCDREF/R13 voltage applied at VLCDREFx = 01 0.8 1.2 1.5 V
LCDREF/R13

CC430F5137, CC430F5135, CC430F5133
5.34 LCD_B Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
VLCDx = 0000, VLCDEXT = 0 2.4 V to 3.6 V VCC
LCDCPEN = 1, VLCDx = 0001 2 V to 3.6 V 2.54
VLCD LCD voltage V
LCDCPEN = 1, VLCDx = 1101 2.2 V to 3.6 V 3.26
LCDCPEN = 1, VLCDx = 1110 2.2 V to 3.6 V 3.32
LCDCPEN = 1, VLCDx = 1111 2.2 V to 3.6 V 3.38 3.6
Peak supply currents due to
ICC,Peak,CP LCDCPEN = 1, VLCDx = 1111 2.2 V 200 µA
charge pump activities
CLCDCAP = 4.7µF,
Time to charge CLCD when
tLCD,CP,on LCDCPEN = 0→1, 2.2 V 100 500 ms
discharged
VLCDx = 1111
Maximum charge pump load
ICP,Load LCDCPEN = 1, VLCDx = 1111 2.2 V 50 µA
current
LCD driver output LCDCPEN = 1, VLCDx = 1000,
RLCD,Seg 2.2 V 10 kΩ
impedance, segment lines ILOAD = ±10 µA
LCD driver output LCDCPEN = 1, VLCDx = 1000,
RLCD,COM 2.2 V 10 kΩ
impedance, common lines ILOAD = ±10 µA

CC430F5137, CC430F5135, CC430F5133
5.35 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
AVCC and DVCC are connected together,
Analog supply voltage,
AVCC AVSS and DVSS are connected together, 2.2 3.6 V
full performance
V(AVSS) = V(DVSS) = 0 V
V(Ax) Analog input voltage range (2) All ADC12 analog input pins Ax 0 AVCC V
fADC12CLK = 5.0 MHz, ADC12ON = 1, 2.2 V 125 155
Operating supply current into
IADC12_A REFON = 0, SHT0 = 0, SHT1 = 0, µA
AVCC terminal (3) 3V 150 220
ADC12DIV = 0
Only one terminal Ax can be selected at
CI Input capacitance 2.2 V 20 25 pF
one time
RI Input MUX ON resistance 0 V ≤ VAx ≤ AVCC 10 200 1900 Ω
(1) The leakage current is specified by the digital I/O input leakage.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See Section 5.40 and Section 5.41.
(3) The internal reference supply current is not included in current consumption parameter IADC12_A.
5.36 12-Bit ADC, Timing Parameters

For specified performance of ADC12 linearity
parameters using an external reference 0.45 4.8 5.0
voltage or AVCC as reference (1)
fADC12CLK ADC conversion clock For specified performance of ADC12 linearity 2.2 V, 3 V MHz
0.45 2.4 4.0
parameters using the internal reference (2)
For specified performance of ADC12 linearity
0.45 2.4 2.7
parameters using the internal reference (3)
Internal ADC12
fADC12OSC ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 4.2 4.8 5.4 MHz
oscillator (4)
REFON = 0, Internal oscillator,
2.2 V, 3 V 2.4 3.1
fADC12OSC = 4.2 MHz to 5.4 MHz
tCONVERT Conversion time µs
External fADC12CLK from ACLK, MCLK or 13 ×
SMCLK, ADC12SSEL ≠ 0 1 / fADC12CLK
RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
tSample Sampling time 2.2 V, 3 V 1000 ns
τ = (RS + RI) × CI (5)
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(5) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance

CC430F5137, CC430F5135, CC430F5133
5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as
Reference Voltage
1.4 V ≤ dVREF ≤ 1.6 V (2) ±2.0
EI Integral linearity error (1) 2.2 V, 3 V LSB
1.6 V < dVREF (2) ±1.7
ED Differential linearity error (1) See (2)
2.2 V, 3 V ±1.0 LSB
dVREF ≤ 2.2 V (2) 2.2 V, 3 V ±1.0 ±2.0
EO Offset error (3) LSB
dVREF > 2.2 V (2) 2.2 V, 3 V ±1.0 ±2.0
EG Gain error (3) See (2)
2.2 V, 3 V ±1.0 ±2.0 LSB
dVREF ≤ 2.2 V (2) 2.2 V, 3 V ±1.4 ±3.5
ET Total unadjusted error LSB
dVREF > 2.2 V (2) 2.2 V, 3 V ±1.4 ±3.5
(1) Parameters are derived using the histogram method.
(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ – VR–, VR+ < AVCC, VR– > AVSS.
Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling capacitors,
10 µF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. Also see the CC430 Family User's Guide.
(3) Parameters are derived using a best fit curve.
5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
PARAMETER TEST CONDITIONS (1) VCC MIN TYP MAX UNIT
Integral linearity ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz ±1.7
EI 2.2 V, 3 V LSB
error (2) ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±2.5
ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz –1.0 +2.0
Differential
ED ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 2.7 MHz 2.2 V, 3 V –1.0 +1.5 LSB
linearity error (2)
ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz –1.0 +2.5
ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz ±1.0 ±2.0
EO Offset error (3) 2.2 V, 3 V LSB
ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±1.0 ±2.0
ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz ±1.0 ±2.0 LSB
EG Gain error (3) 2.2 V, 3 V
ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±1.5% (4) VREF
Total unadjusted ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz ±1.4 ±3.5 LSB
ET 2.2 V, 3 V
error ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±1.5% (4) VREF
(1) The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = VR+ – VR–.
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.
(4) The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this
mode the reference voltage used by the ADC12_A is not available on a pin.

CC430F5137, CC430F5135, CC430F5133
5.39 12-Bit ADC, Temperature Sensor and Built-In VMID (1)

(2) (3) ADC12ON = 1, INCH = 0Ah, 2.2 V 680

VSENSOR See mV
TA = 0°C 3V 680
(3)
2.2 V 2.25
TCSENSOR See ADC12ON = 1, INCH = 0Ah mV/°C
3V 2.25
Sample time required if ADC12ON = 1, INCH = 0Ah, 2.2 V 30
tSENSOR(sample) µs
channel 10 is selected (4) Error of conversion result ≤ 1 LSB 3V 30
AVCC divider at channel 11,
ADC12ON = 1, INCH = 0Bh 0.48 0.5 0.52 VAVCC
VAVCC factor
VMID
2.2 V 1.06 1.1 1.14
AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh V
3V 1.44 1.5 1.56
Sample time required if ADC12ON = 1, INCH = 0Bh,
tVMID(sample) 2.2 V, 3 V 1000 ns
channel 11 is selected (5) Error of conversion result ≤1 LSB
(1) The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of
the temperature sensor.
(2) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
(3) The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can
be computed from the calibration values for higher accuracy.
(4) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
(5) The on time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
1000
950
Typical Temperature Sensor Voltage (mV)
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Ambient Temperature (°C)
Figure 5-19. Typical Temperature Sensor Voltage

CC430F5137, CC430F5135, CC430F5133
5.40 REF, External Reference

Positive external reference
VeREF+ VeREF+ > VREF–/VeREF– (2) 1.4 AVCC V
voltage input
Negative external reference
VREF–/VeREF– VeREF+ > VREF–/VeREF– (3) 0 1.2 V
voltage input
(VeREF+ – Differential external reference
VeREF+ > VREF–/VeREF– (4) 1.4 AVCC V
VREF–/VeREF–) voltage input
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC12CLK = 5 MHz, ADC12SHTx = 1h, 2.2 V, 3 V ±8.5 ±26
IVeREF+ Conversion rate 200 ksps
Static input current µA
IVREF–/VeREF- 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC12CLK = 5 MHz, ADC12SHTx = 8h, 2.2 V, 3 V ±1
Conversion rate 20 ksps
Capacitance at VREF+ or
CVREF+/- VREF- terminal, external 10 µF
reference (5)
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. Also see the CC430 Family User's Guide.

CC430F5137, CC430F5135, CC430F5133
5.41 REF, Built-In Reference

REFVSEL = 2 for 2.5 V,
3V 2.41 ±1.5%
REFON = REFOUT = 1, IVREF+= 0 A
Positive built-in reference REFVSEL = 1 for 2 V,
VREF+ 3V 1.93 ±1.5% V
voltage output REFON = REFOUT = 1, IVREF+= 0 A
REFVSEL = 0 for 1.5 V,
2.2 V, 3 V 1.45 ±1.5%
REFON = REFOUT = 1, IVREF+= 0 A
REFVSEL = 0 for 1.5 V, reduced performance 1.8
AVCC minimum voltage, REFVSEL = 0 for 1.5 V 2.2
AVCC(min) Positive built-in reference V
active REFVSEL = 1 for 2 V 2.3
REFVSEL = 2 for 2.5 V 2.8
Operating supply current into REFON = 1, REFOUT = 0, REFBURST = 0 3V 100 140 µA
IREF+
AVCC terminal (2) (3) REFON = 1, REFOUT = 1, REFBURST = 0 3V 0.9 1.5 mA
REFVSEL = 0, 1, or 2,
Load-current regulation, IVREF+ = +10 µA or –1000 µA,
IL(VREF+) 2500 µV/mA
VREF+ terminal (4) AVCC = AVCC(min) for each reference level,
REFON = REFOUT = 1
Capacitance at VREF+
CVREF+ REFON = REFOUT = 1 20 100 pF
terminals, internal reference
IVREF+ = 0 A,
Temperature coefficient of ppm/
TCREF+ REFVSEL = 0, 1, or 2, 30 50
built-in reference (5) °C
REFON = 1, REFOUT = 0 or 1
AVCC = AVCC(min) to AVCC(max),
Power supply rejection ratio
PSRR_DC TA = 25 °C, REFVSEL = 0, 1, or 2, 120 300 µV/V
(DC)
AVCC = AVCC(min) to AVCC(max)
Power supply rejection ratio TA = 25 °C, f = 1 kHz, ΔVpp = 100 mV,
PSRR_AC 6.4 mV/V
(AC) REFVSEL = 0, 1, or 2,
AVCC = AVCC(min) to AVCC(max),
REFVSEL = 0, 1, or 2, 75
REFOUT = 0, REFON = 0 → 1
Settling time of reference
tSETTLE AVCC = AVCC(min) to AVCC(max), µs
voltage (6)
CVREF = CVREF(maximum),
75
REFVSEL = 0, 1, or 2,
REFOUT = 1, REFON = 0 → 1
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one
smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as,
used as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as the reference for
the conversion and uses the smaller buffer.
(2) The internal reference current is supplied from the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an analog-to-digital conversion. REFOUT = 0
represents the current contribution of the smaller buffer. REFOUT = 1 represents the current contribution of the larger buffer without
external load.
(3) The temperature sensor is provided by the REF module. Its current is supplied from the AVCC terminal and is equivalent to IREF+ with
REFON = 1 and REFOUT = 0.
(4) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace or other causes.
(5) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
(6) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.

CC430F5137, CC430F5135, CC430F5133
5.42 Comparator_B
VCC Supply voltage 1.8 3.6 V
1.8 V 40
CBPWRMD = 00 2.2 V 30 50
Comparator operating supply
IAVCC_COMP current into AVCC, Excludes 3V 40 65 µA
reference resistor ladder
CBPWRMD = 01 2.2 V, 3 V 10 30
CBPWRMD = 10 2.2 V, 3 V 0.1 0.5
Quiescent current of local reference
IAVCC_REF CBREFACC = 1, CBREFLx = 01 22 µA
voltage amplifier into AVCC
VIC Common mode input range 0 VCC – 1 V
CBPWRMD = 00 ±20
VOFFSET Input offset voltage mV
CBPWRMD = 01 or 10 ±10
CIN Input capacitance 5 pF
On (switch closed) 3 4 kΩ
RSIN Series input resistance
Off (switch open) 30 MΩ
CBPWRMD = 00, CBF = 0 450
ns
tPD Propagation delay, response time CBPWRMD = 01, CBF = 0 600
CBPWRMD = 10, CBF = 0 50 µs
CBPWRMD = 00, CBON = 1,
0.35 0.6 1.0
CBF = 1, CBFDLY = 00
0.6 1.0 1.8
tPD,filter Propagation delay with filter active µs
1.0 1.8 3.4
1.8 3.4 6.5
CBON = 0 to CBON = 1,
1 2
Comparator enable time, settling CBPWRMD = 00 or 01
tEN_CMP µs
time CBON = 0 to CBON = 1,
100
CBPWRMD = 10
tEN_REF Resistor reference enable time CBON = 0 to CBON = 1 0.3 1.5 µs
VIN ×
VIN = reference into resistor ladder,
VCB_REF Reference voltage for a given tap (n + 1) V
n = 0 to 31
/ 32

CC430F5137, CC430F5135, CC430F5133
5.43 Flash Memory

PARAMETER TJ MIN TYP MAX UNIT
DVCC(PGM/ERASE) Program and erase supply voltage 1.8 3.6 V
IPGM Average supply current from DVCC during program 3 5 mA
IERASE Average supply current from DVCC during erase 2 6.5 mA
IMERASE, IBANK Average supply current from DVCC during mass erase or bank erase 2 6.5 mA
(1)
tCPT Cumulative program time 16 ms
Program and erase endurance 104 105 cycles
tRetention Data retention duration 25°C 100 years
(2)
tWord Word or byte program time 64 85 µs
tBlock, 0 Block program time for first byte or word (2) 49 65 µs
Block program time for each additional byte or word, except for last byte or
tBlock, 37 49 µs
1–(N–1) word (2)
tBlock, N Block program time for last byte or word (2) 55 73 µs
Erase time for segment erase, mass erase, and bank erase when
tErase 23 32 ms
available (2)
MCLK frequency in marginal read mode
fMCLK,MGR 0 1 MHz
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word write, individual byte write, and block write modes.
(2) These values are hardwired into the state machine of the flash controller.
5.44 JTAG and Spy-Bi-Wire Interface

PARAMETER VCC MIN TYP MAX UNIT
fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 µs
(1)
tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) 2.2 V, 3 V 1 µs
tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 µs
2.2 V 0 5 MHz
fTCK TCK input frequency, 4-wire JTAG (2)
3V 0 10 MHz
Rinternal Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 80 kΩ
(1) Tools that access the Spy-Bi-Wire interface need to wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.

CC430F5137, CC430F5135, CC430F5133
5.45 RF1A CC1101-Based Radio Parameters
5.46 Recommended Operating Conditions

VCC Supply voltage range during radio operation 2.0 3.6 V
PMMCOREVx Core voltage range, PMMCOREVx setting during radio operation 2 3
300 348
RF range 389 (1) 464 MHz
779 928
2-FSK 0.6 500
Data rate 2-GFSK, OOK, and ASK 0.6 250 kBaud
(Shaped) MSK (also known as differential offset QPSK) (2) 26 500
RF crystal frequency 26 26 27 MHz
Total tolerance including initial tolerance, crystal loading, aging,
RF crystal tolerance ±40 ppm
and temperature dependency. (3)
RF crystal load capacitance 10 13 20 pF
RF crystal effective series resistance 100 Ω
(1) If using a 27-MHz crystal, the lower frequency limit for this band is 392 MHz.
(2) If using optional Manchester encoding, the data rate in kbps is half the baud rate.
(3) The acceptable crystal tolerance depends on frequency band, channel bandwidth, and spacing. Also see DN005 -- CC11xx Sensitivity
versus Frequency Offset and Crystal Accuracy.
5.47 RF Crystal Oscillator, XT2

TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PARAMETER MIN TYP MAX UNIT
Start-up time (2) 150 810 µs
Duty cycle 45% 50% 55%
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
(2) The start-up time depends to a very large degree on the used crystal.
5.48 Current Consumption, Reduced-Power Modes

RF crystal oscillator only (2) 100 µA
Current consumption IDLE state (including RF crystal oscillator) 1.7
mA
FSTXON state (only the frequency synthesizer is running) (3) 9.5
(2) To measure the current, follow this sequence:
• Enable XT2 with XOSC_FORCE_ON = 1.
• Set radio to sleep mode.
• Disable XT2 clock requests from any module.
(3) This current consumption is also representative of other intermediate states when going from IDLE to RX or TX, including the calibration
state.

CC430F5137, CC430F5135, CC430F5133
5.49 Current Consumption, Receive Mode

TA = 25°C, VCC = 3 V (unless otherwise noted) (1) (2)
DATA RATE
PARAMETER FREQ (MHz) TEST CONDITIONS TYP UNIT
(kBaud)
Input at –100 dBm (close to
17
sensitivity limit)
1.2
Input at –40 dBm (well
16
above sensitivity limit)
17
Register settings optimized for sensitivity limit)
315 38.4
reduced current Input at –40 dBm (well
16
18
sensitivity limit)
250
16.5
18
sensitivity limit)
1.2
17
18
Current Register settings optimized for sensitivity limit)
433 38.4 mA
consumption, RX reduced current Input at –40 dBm (well
17
18.5
sensitivity limit)
250
17
16
sensitivity limit)
1.2
15
16
Register settings optimized for sensitivity limit)
868, 915 38.4
reduced current (3) Input at –40 dBm (well
15
16
sensitivity limit)
250
15
(2) Reduced current setting (MDMCFG2.DEM_DCFILT_OFF = 1) gives a slightly lower current consumption at the cost of a reduction in
sensitivity. See Section 5.55 through Section 5.58 for additional details on current consumption and sensitivity.
(3) For 868 or 915 MHz, see Figure 5-20 for current consumption with register settings optimized for sensitivity.

CC430F5137, CC430F5135, CC430F5133
19 19
TA = 85°C TA = 85°C
TA = 25°C TA = 25°C
TA = -40°C TA = -40°C
Radio Current (mA)
Radio Current (mA)

18 18
17 17
16 16
-100 -80 -60 -40 -20 -100 -80 -60 -40 -20
Input Power (dBm) Input Power (dBm)
1.2 kBaud GFSK 38.4 kBaud GFSK
19 19
TA = 85°C TA = 85°C
TA = 25°C TA = 25°C
TA = -40°C TA = -40°C
Radio Current (mA)
Radio Current (mA)
18 18
17 17
16 16
-100 -80 -60 -40 -20 -100 -80 -60 -40 -20
250 kBaud GFSK 500 kBaud MSK
Figure 5-20. Typical RX Current Consumption Over Temperature and Input Power Level, 868 MHz,
Sensitivity-Optimized Setting

CC430F5137, CC430F5135, CC430F5133
5.50 Current Consumption, Transmit Mode

TA = 25°C, VCC = 3 V (unless otherwise noted) (1) (2)
FREQUENCY PATABLE OUTPUT

PARAMETER TYP UNIT
[MHz} SETTING POWER (dBm)
0xC0 maximum 26
0xC4 +10 25
315
0x51 0 15
0x29 –6 15
0xC0 maximum 33
0xC6 +10 29
433
0x50 0 17
0x2D –6 17
Current consumption, TX mA
0xC0 maximum 36
0xC3 +10 33
868
0x8D 0 18
0x2D –6 18
0xC0 maximum 35
0xC3 +10 32
915
0x8D 0 18
0x2D –6 18
(2) Reduced current setting (MDMCFG2.DEM_DCFILT_OFF = 1) gives a slightly lower current consumption at the cost of a reduction in
sensitivity. See Section 5.55 through Section 5.58 for additional details on current consumption and sensitivity.

CC430F5137, CC430F5135, CC430F5133
5.51 Typical TX Current Consumption, 315 MHz

OUTPUT VCC 2V 3V 3.6 V
PATABLE
PARAMETER POWER UNIT
SETTING TA 25°C 25°C 25°C
(dBm)
0xC0 maximum 27.5 26.4 28.1
0xC4 +10 25.1 25.2 25.3
0x51 0 14.4 14.6 14.7
0x29 –6 14.2 14.7 15.0

PATABLE
SETTING TA 25°C 25°C 25°C
(dBm)
0xC0 maximum 33.1 33.4 33.8
0xC6 +10 28.6 28.8 28.8
0x50 0 16.6 16.8 16.9
0x2D –6 16.8 17.5 17.8

PATABLE
SETTING TA –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C
(dBm)
0xC0 maximum 36.7 35.2 34.2 38.5 35.5 34.9 37.1 35.7 34.7
Current 0xC3 +10 34.0 32.8 32.0 34.2 33.0 32.5 34.3 33.1 32.2
mA
consumption, TX 0x8D 0 18.0 17.6 17.5 18.3 17.8 18.1 18.4 18.0 17.7
0x2D –6 17.1 17.0 17.2 17.8 17.8 18.3 18.2 18.1 18.1

PATABLE
SETTING TA –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C
(dBm)
0xC0 maximum 35.5 33.8 33.2 36.2 34.8 33.6 36.3 35.0 33.8
Current 0xC3 +10 33.2 32.0 31.0 33.4 32.1 31.2 33.5 32.3 31.3
mA
consumption, TX 0x8D 0 17.8 17.4 17.1 18.1 17.6 17.3 18.2 17.8 17.5
0x2D –6 17.0 16.9 16.9 17.7 17.6 17.6 18.1 18.0 18.0

CC430F5137, CC430F5135, CC430F5133
5.55 RF Receive, Overall

(2)
Digital channel filter bandwidth 58 812 kHz
25 MHz to 1 GHz –68 –57
Spurious emissions (3) (4)
dBm
Above 1 GHz –66 –47
RX latency Serial operation (5) 9 bit
(2) User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0 MHz crystal)
(3) Typical radiated spurious emission is –49 dBm measured at the VCO frequency
(4) Maximum figure is the ETSI EN 300 220 limit
(5) Time from start of reception until data is available on the receiver data output pin is equal to 9 bit.
5.56 RF Receive, 315 MHz

2-FSK, 1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless
otherwise noted)
DATA RATE
PARAMETER TEST CONDITIONS TYP UNIT
(kBaud)
0.6 14.3-kHz deviation, 58-kHz digital channel filter bandwidth –117
1.2 5.2-kHz deviation, 58-kHz digital channel filter bandwidth (2) –111
Receiver sensitivity 38.4 20-kHz deviation, 100-kHz digital channel filter bandwidth (3) –103 dBm
(4)
250 127-kHz deviation, 540-kHz digital channel filter bandwidth –95
500 MSK, 812-kHz digital channel filter bandwidth (4) –86
(2) Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF =1. The typical current consumption is then
reduced by approximately 2 mA close to the sensitivity limit. The sensitivity is typically reduced to –109 dBm.
(4) MDMCFG2.DEM_DCFILT_OFF =1 cannot be used for data rates ≥ 250kBaud.
5.57 RF Receive, 433 MHz

2-FSK, 1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless
otherwise noted)
DATA RATE
(kBaud)
0.6 14.3-kHz deviation, 58-kHz digital channel filter bandwidth –114
1.2 5.2-kHz deviation, 58-kHz digital channel filter bandwidth (2) –111
Receiver sensitivity 38.4 20-kHz deviation, 100-kHz digital channel filter bandwidth (3) –104 dBm
(4)
250 127-kHz deviation, 540-kHz digital channel filter bandwidth –93
500 MSK, 812-kHz digital channel filter bandwidth (4) –85
(4) MDMCFG2.DEM_DCFILT_OFF =1 cannot be used for data rates ≥ 250kBaud.

CC430F5137, CC430F5135, CC430F5133
5.58 RF Receive, 868 or 915 MHz

1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless otherwise
noted)
0.6-kBaud data rate, 2-FSK, 14.3-kHz deviation, 58-kHz digital channel filter bandwidth (unless otherwise noted)
Receiver sensitivity –115 dBm
1.2-kBaud data rate, 2-FSK, 5.2-kHz deviation, 58-kHz digital channel filter bandwidth (unless otherwise noted)
–109
Receiver sensitivity (2) 2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2, dBm
–109
Gaussian filter with BT = 0.5
Saturation FIFOTHR.CLOSE_IN_RX =0 (3) –28 dBm
Adjacent channel Desired channel 3 dB above the sensitivity limit, 100- –100-kHz offset 39
dB
rejection kHz channel spacing (4) +100-kHz offset 39
IF 152 kHz, desired channel 3 dB above the sensitivity
Image channel rejection 29 dB
limit
±2-MHz offset –48 dBm
Blocking Desired channel 3 dB above the sensitivity limit (5)
38.4-kBaud data rate, 2-FSK, 20-kHz deviation, 100-kHz digital channel filter bandwidth (unless otherwise noted)
–102
Receiver sensitivity (6) 2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2, dBm
–101
dB
Image channel rejection IF 152 kHz, desired channel 3 dB above the sensitivity limit 23 dB
250-kBaud data rate, 2-FSK, 127-kHz deviation, 540-kHz digital channel filter bandwidth (unless otherwise noted)
–90
(7)
Receiver sensitivity 2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2, dBm
–90
dB
Image channel rejection IF 304 kHz, desired channel 3 dB above the sensitivity limit 18 dB
500-kBaud data rate, MSK, 812-kHz digital channel filter bandwidth (unless otherwise noted)
Receiver sensitivity (7) –84 dBm
Image channel rejection IF 355 kHz, desired channel 3 dB above the sensitivity limit –2 dB
reduced by approximately 2 mA close to the sensitivity limit. The sensitivity is typically reduced to –107 dBm
(3) See DN010 Close-in Reception with CC1101.
(4) See Figure 5-21 for blocking performance at other offset frequencies.
(7) MDMCFG2.DEM_DCFILT_OFF = 1 cannot be used for data rates ≥ 250kBaud.

CC430F5137, CC430F5135, CC430F5133
80 60
70
50
60
50 40
Selectivity (dB)
Blocking (dB)
40
30
30
20
20
10 10
0
0
-10
-20 -10
-40 -30 -20 -10 0 10 20 30 40 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
Offset (MHz) Offset (MHz)
NOTE: 868.3 MHz, 2-FSK, 5.2-kHz deviation, IF is 152.3 kHz, digital channel filter bandwidth is 58 kHz
Figure 5-21. Typical Selectivity at 1.2-kBaud Data Rate
80 50
70
40
60
50 30
Selectivity (dB)
Blocking (dB)
40
20
30
10
20
10 0
0
-10
-10
-20 -20
-40 -30 -20 -10 0 10 20 30 40 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
NOTE: 868 MHz, 2-FSK, 20 kHz deviation, IF is 152.3 kHz, digital channel filter bandwidth is 100 kHz
Figure 5-22. Typical Selectivity at 38.4-kBaud Data Rate

CC430F5137, CC430F5135, CC430F5133
80 50
70
40
60
50 30
Selectivity (dB)
Blocking (dB)
40
20
30
10
20
10 0
0
-10
-10
-20 -20
-40 -30 -20 -10 0 10 20 30 40 -3 -2 -1 0 1 2 3
NOTE: 868 MHz, 2-FSK, IF is 304 kHz, digital channel filter bandwidth is 540 kHz
Figure 5-23. Typical Selectivity at 250-kBaud Data Rate
80 50
70
40
60
50 30
Selectivity (dB)
Blocking (dB)
40
20
30
10
20
10 0
0
-10
-10
-20 -20
-40 -30 -20 -10 0 10 20 30 40 -3 -2 -1 0 1 2 3
NOTE: 868 MHz, 2-FSK, IF is 355 kHz, digital channel filter bandwidth is 812 kHz
Figure 5-24. Typical Selectivity at 500-kBaud Data Rate

CC430F5137, CC430F5135, CC430F5133
5.59 Typical Sensitivity, 315 MHz, Sensitivity Optimized Setting

DATA RATE VCC 2V 3V 3.6 V
PARAMETER UNIT
(kBaud) TA –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C
1.2 –112 –112 –110 –112 –111 –109 –112 –111 –108
Sensitivity,
38.4 –105 –105 –104 –105 –103 –102 –105 –104 –102 dBm
315 MHz
250 –95 –95 –92 –94 –95 –92 –95 –94 –91

PARAMETER UNIT
1.2 –111 –110 –108 –111 –111 –108 –111 –110 –107
Sensitivity,
38.4 –104 –104 –101 –104 –104 –101 –104 –103 –101 dBm
433 MHz
250 –93 –94 –91 –93 –93 –90 –93 –93 –90

PARAMETER UNIT
1.2 –109 –109 –107 –109 –109 –106 –109 –108 –106
Sensitivity, 38.4 –102 –102 –100 –102 –102 –99 –102 –101 –99
dBm
868 MHz 250 –90 –90 –88 –89 –90 –87 –89 –90 –87
500 –84 –84 –81 –84 –84 –80 –84 –84 -80

PARAMETER UNIT
1.2 –109 –109 –107 –109 –109 –106 –109 –108 –105
Sensitivity, 38.4 –102 –102 –100 –102 –102 –99 –103 –102 –99
dBm
915 MHz 250 –92 –92 –89 –92 –92 –88 –92 –92 –88
500 –87 –86 –81 –86 –86 –81 –86 –85 –80

CC430F5137, CC430F5135, CC430F5133
5.63 RF Transmit
PTX = +10 dBm (unless otherwise noted)
FREQUENCY
(MHz)
315 122 + j31
Differential load impedance (2) 433 116 + j41 Ω
868, 915 86.5 + j43
315 +12
Output power, highest 433 Delivered to a 50-Ω single-ended load from CC430 reference +13
dBm
setting (3) 868 design RF matching network +11
915 +11
Output power, lowest Delivered to a 50-Ω single-ended load from CC430 reference
–30 dBm
setting (3) design RF matching network
Second harmonic –56
433
Third harmonic –57
Harmonics, radiated (4) (5) (6) 868 dBm
915
Frequencies below 960 MHz < –38
315 +10 dBm CW
Frequencies above 960 MHz < –48
Frequencies below 1 GHz –45
433 +10 dBm CW
Frequencies above 1 GHz < –48
Harmonics, conducted dBm
868 +10 dBm CW
Other harmonics < –71
915 +11 dBm CW (7)
Other harmonics < –47
315 +10 dBm CW
Frequencies below 1 GHz < –54
433 +10 dBm CW
Frequencies from 47 to 74, 87.5 to 118,
Spurious emissions, < –63
174 to 230, 470 to 862 MHz
conducted, harmonics not dBm
included (8) Frequencies below 1 GHz < –46
868 +10 dBm CW
Frequencies from 47 to 74, 87.5 to 118,
< –56
174 to 230, 470 to 862 MHz
915 +11 dBm CW
TX latency (9) Serial operation 8 bits
(2) Differential impedance as seen from the RF port (RF_P and RF_N) towards the antenna. Follow the CC430 reference designs available
from the TI website.
(3) Output power is programmable, and the full range is available in all frequency bands. Output power may be restricted by regulatory
limits. Also see AN050 Using the CC1101 in the European 868MHz SRD Band and DN013 Programming Output Power on CC1101,
which gives the output power and harmonics when using multilayer inductors. The output power is then typically +10 dBm when
operating at 868 or 915 MHz.
(4) The antennas used during the radiated measurements (SMAFF-433 from R.W.Badland and Nearson S331 868/915) play a part in
attenuating the harmonics.
(5) Measured on EM430F6137RF900 with CW, maximum output power
(6) All harmonics are below –41.2 dBm when operating in the 902 to 928 MHz band.
(7) Requirement is –20 dBc under FCC 15.247.
(8) All radiated spurious emissions are within the limits of ETSI. Also see DN017 CC11xx 868/915 MHz RF Matching.
(9) Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports

CC430F5137, CC430F5135, CC430F5133
5.64 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
PATABLE SETTING
OUTPUT POWER (dBm)
315 MHz 433 MHz 868 MHz 915 MHz
–30 0x12 0x05 0x03 0x03
–12 0x33 0x26 0x25 0x25
–6 0x29 0x2D 0x2D 0x2D
0 0x51 0x50 0x8D 0x8D
10 0xC4 0xC4 0xC3 0xC3
Maximum 0xC0 0xC0 0xC0 0xC0

CC430F5137, CC430F5135, CC430F5133
5.65 Typical Output Power, 315 MHz (1)

VCC 2V 3V 3.6 V
PARAMETER PATABLE SETTING UNIT
TA 25°C 25°C 25°C
0xC0 (maximum) 11.9 11.8 11.8
0xC4 (10 dBm) 10.3 10.3 10.3
Output power, 315 MHz 0xC6 (default) 9.3 dBm
0x51 (0 dBm) 0.7 0.6 0.7
0x29 (–6 dBm) –6.8 –5.6 –5.3

VCC 2V 3V 3.6 V
TA 25°C 25°C 25°C
0xC0 (maximum) 12.6 12.6 12.6
0xC4 (10 dBm) 10.3 10.2 10.2
Output power, 433 MHz 0xC6 (default) 10.0 dBm
0x50 (0 dBm) 0.3 0.3 0.3
0x2D (–6 dBm) –6.4 –5.4 –5.1

VCC 2V 3V 3.6 V
TA –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C
0xC0 (maximum) 11.9 11.2 10.5 11.9 11.2 10.5 11.9 11.2 10.5
0xC3 (10 dBm) 10.8 10.1 9.4 10.8 10.1 9.4 10.7 10.1 9.4
Output power,
0xC6 (default) 8.8 dBm
868 MHz
0x8D (0 dBm) 1.0 0.3 –0.3 1.1 0.3 –0.3 1.1 0.3 –0.3
0x2D (–6 dBm) –6.5 –6.8 –7.3 –5.3 –5.8 –6.3 –4.9 –5.4 –6.0

VCC 2V 3V 3.6 V
TA –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C
0xC0 (maximum) 12.2 11.4 10.6 12.1 11.4 10.7 12.1 11.4 10.7
0xC3 (10 dBm) 11.0 10.3 9.5 11.0 10.3 9.5 11.0 10.3 9.6
Output power,
0xC6 (default) 8.8 dBm
915 MHz
0x8D (0 dBm) 1.9 1.0 0.3 1.9 1.0 0.3 1.9 1.1 0.3
0x2D (–6 dBm) –5.5 –6.0 –6.5 –4.3 –4.8 –5.5 –3.9 –4.4 –5.1

CC430F5137, CC430F5135, CC430F5133
5.69 Frequency Synthesizer Characteristics

MIN figures are given using a 27MHz crystal. TYP and MAX figures are given using a 26MHz crystal.
Programmed frequency resolution (2) 26- to 27-MHz crystal 397 fXOSC / 216 412 Hz
(3)
Synthesizer frequency tolerance ±40 ppm
50-kHz offset from carrier –95
RF carrier phase noise dBc/Hz
1-MHz offset from carrier –107
PLL turnon and hop time (4) Crystal oscillator running 85.1 88.4 88.4 µs
(5)
PLL RX to TX settling time 9.3 9.6 9.6 µs
PLL TX to RX settling time (6) 20.7 21.5 21.5 µs
PLL calibration time (7) 694 721 721 µs
(2) The resolution (in Hz) is equal for all frequency bands.
(3) Depends on crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth and
spacing.
(4) Time from leaving the IDLE state until arriving in the RX, FSTXON, or TX state, when not performing calibration.
(5) Settling time for the 1-IF step from RX to TX
(6) Settling time for the 1-IF step from TX to RX
(7) Calibration can be initiated manually or automatically before entering or after leaving RX or TX.

CC430F5137, CC430F5135, CC430F5133
5.70 Typical RSSI_offset Values

RSSI_OFFSET (dB)
DATA RATE (kBaud)
433 MHz 868 MHz
1.2 74 74
38.4 74 74
250 74 74
500 74 74
0 0
1.2kBaud 250kBaud
-20 -20
38.4kBaud 500kBaud
RSSI Readout (dBm)
RSSI Readout (dBm)

-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
-120 -100 -80 -60 -40 -20 0 -120 -100 -80 -60 -40 -20 0
Figure 5-25. Typical RSSI Value vs Input Power Level for Different Data Rates at 868 MHz

CC430F5137, CC430F5135, CC430F5133
6 Detailed Description
6.1 Sub-1 GHz Radio
The implemented sub-1 GHz radio module is based on the industry-leading CC1101, requiring very few
external components. Figure 6-1 shows a high-level block diagram of the implemented radio.
Radio Control
Demodulator
ADC
RX FIFO
LNA
ADC
Interface to MCU
Packet Handler
RF_P 0 Frequency
Synthesizer
RF_N 90
PA
TX FIFO
Modulator
RC OSC BIAS XOSC
RBIAS RF_XIN RF_XOUT

Figure 6-1. Sub-1 GHz Radio Block Diagram
The radio features a low-IF receiver. The received RF signal is amplified by a low-noise amplifier (LNA)
and down-converted in quadrature to the intermediate frequency (IF). At IF, the I/Q signals are digitized.
Automatic gain control (AGC), fine channel filtering, demodulation bit, and packet synchronization are
performed digitally.
The transmitter part is based on direct synthesis of the RF. The frequency synthesizer includes a
completely on-chip LC VCO and a 90° phase shifter for generating the I and Q LO signals to the down-
conversion mixers in receive mode.
The 26-MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for
the ADC and the digital part.
A memory mapped register interface is used for data access, configuration, and status request by the
CPU.
The digital baseband includes support for channel configuration, packet handling, and data buffering.
For complete module descriptions, see the CC430 Family User's Guide.
Copyright © 2009–2018, Texas Instruments Incorporated Detailed Description 61

CC430F5137, CC430F5135, CC430F5133
6.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses. The peripherals can be
managed with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
6.3 Operating Modes

The CC430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
62 Detailed Description Copyright © 2009–2018, Texas Instruments Incorporated

CC430F5137, CC430F5135, CC430F5133
6.4 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh–0FF80h
(see Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
asd
Table 6-1. Interrupt Sources, Flags, and Vectors

SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
System Reset
Power-Up
External Reset
WDTIFG, KEYV (SYSRSTIV) (1) (2) Reset 0FFFEh 63, highest
Watchdog Time-out, Password
Violation
Flash Memory Password Violation
System NMI
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62
Vacant Memory Access
JMBOUTIFG (SYSSNIV) (1) (3)
JTAG Mailbox
User NMI
NMI
NMIIFG, OFIFG, ACCVIFG (SYSUNIV) (1) (3) (Non)maskable 0FFFAh 61
Oscillator Fault
Flash Memory Access Violation
Comparator_B Comparator_B Interrupt Flags (CBIV) (1) Maskable 0FFF8h 60
Watchdog Interval Timer Mode WDTIFG Maskable 0FFF6h 59
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) Maskable 0FFF4h 58
UCB0RXIFG, UCB0TXIFG, I2C Status Interrupt
USCI_B0 Receive or Transmit Maskable 0FFF2h 57
Flags (UCB0IV) (1)
ADC12_A
ADC12IFG0 ... ADC12IFG15 (ADC12IV) (1) Maskable 0FFF0h 56
(Reserved on CC430F612x)
TA0 TA0CCR0 CCIFG0 Maskable 0FFEEh 55
TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0 Maskable 0FFECh 54
TA0IFG (TA0IV) (1)
Radio Interface Interrupt Flags (RF1AIFIV)
RF1A CC1101-based Radio Maskable 0FFEAh 53
Radio Core Interrupt Flags (RF1AIV)
DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) Maskable 0FFE8h 52
TA1 TA1CCR0 CCIFG0 Maskable 0FFE6h 51
TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1 Maskable 0FFE4h 50
TA1IFG (TA1IV) (1)
(1)
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV) Maskable 0FFE2h 49
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV) (1) Maskable 0FFE0h 48
LCD_B
LCD_B Interrupt Flags (LCDBIV) (1) Maskable 0FFDEh 47
(Reserved on CC430F513x)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_A Maskable 0FFDCh 46
RT0PSIFG, RT1PSIFG (RTCIV) (1)
AES AESRDYIFG Maskable 0FFDAh 45
0FFD8h 44
Reserved Reserved (4) ⋮ ⋮
0FF80h 0, lowest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space.
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, reserve these locations.

CC430F5137, CC430F5135, CC430F5133
6.5 Memory Organization

Table 6-2 summarizes the memory map of the devices.
Table 6-2. Memory Organization

CC430F6137 CC430F6135
CC430F6127 CC430F6126 (1) CC430F6125 CC430F5133 (1)
CC430F5137 (1) CC430F5135 (1)
Main Memory Total
32KB 32KB 16KB 8KB
(flash) Size
Main: Interrupt
00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h
vector
Main: code 32KB 32KB 16KB 8KB
Bank 0
memory 00FFFFh–008000h 00FFFFh–008000h 00FFFFh–00C000h 00FFFFh–00E000h
Total
RAM 4KB 2KB 2KB 2KB
Size
2KB
Sect 1 not available not available not available
002BFFh–002400h
2KB 2KB 2KB 2KB
Sect 0
0023FFh–001C00h 0023FFh–001C00h 0023FFh–001C00h 0023FFh–001C00h
128 B 128 B 128 B 128 B
Device 001AFFh–001A80h 001AFFh–001A80h 001AFFh–001A80h 001AFFh–001A80h
Descriptor 128 B 128 B 128 B 128 B
001A7Fh–001A00h 001A7Fh–001A00h 001A7Fh–001A00h 001A7Fh–001A00h
128 B 128 B 128 B 128 B
Info A
0019FFh–001980h 0019FFh–001980h 0019FFh–001980h 0019FFh–001980h
128 B 128 B 128 B 128 B
Info B
Information 00197Fh–001900h 00197Fh–001900h 00197Fh–001900h 00197Fh–001900h
memory (flash) 128 B 128 B 128 B 128 B
Info C
128 B 128 B 128 B 128 B
Info D
00187Fh–001800h 00187Fh–001800h 00187Fh–001800h 00187Fh–001800h
512 B 512 B 512 B 512 B
BSL 3
512 B 512 B 512 B 512 B
Bootloader BSL 2
(BSL) memory
(flash) 512 B 512 B 512 B 512 B
BSL 1
512 B 512 B 512 B 512 B
BSL 0
4KB 4KB 4KB 4KB
Peripherals
000FFFh–0h 000FFFh–0h 000FFFh–0h 000FFFh–0h
(1) All memory regions not specified here are vacant memory, and any access to them causes a Vacant Memory Interrupt.

CC430F5137, CC430F5135, CC430F5133
6.6 Bootloader (BSL)

The BSL enables users to program the flash memory or RAM using various serial interfaces. Table 6-3
lists the pin requirements. Access to the device memory through the BSL is protected by a user-defined
password. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK
pins. For a complete description of the features of the BSL and its implementation, see MSP430
Programming With the Bootloader (BSL).
Table 6-3. UART BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION
RST/NMI/SBWTDIO Entry sequence signal
TEST/SBWTCK Entry sequence signal
P1.6 Data transmit
P1.5 Data receive
VCC Power supply
VSS Ground supply
6.7 JTAG Operation
6.7.1 JTAG Standard Interface

The CC430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-4 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide. For a complete description of the features of the JTAG interface and its
implementation, see MSP430 Programming With the JTAG Interface.
Table 6-4. JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
PJ.3/TCK IN JTAG clock input
PJ.2/TMS IN JTAG state control
PJ.1/TDI/TCLK IN JTAG data input, TCLK input
PJ.0/TDO OUT JTAG data output
TEST/SBWTCK IN Enable JTAG pins
RST/NMI/SBWTDIO IN External reset
VCC Power supply
VSS Ground supply

CC430F5137, CC430F5135, CC430F5133
6.7.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the CC430 family supports the two wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-5
lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the
features of the JTAG interface and its implementation, see MSP430 Programming With the JTAG
Interface.
Table 6-5. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
TEST/SBWTCK IN Spy-Bi-Wire clock input
RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output
VCC Power supply
VSS Ground supply
6.8 Flash Memory

The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features
of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (Info A to
Info D) of 128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments Info A to Info D can be erased individually, or as a group with the main memory segments.
Segments Info A to Info D are also called information memory.
• Segment A can be locked separately.
6.9 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data are lost. Features of the RAM include:
• RAM has n sectors of 2KB each.
• Each sector 0 to n can be completely disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.

CC430F5137, CC430F5135, CC430F5133
6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the CC430 Family User's Guide.
6.10.1 Oscillator and System Clock

The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an
internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator
(REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator.
The UCS module is designed to meet the requirements of both low system cost and low-power
consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction
with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal
frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than 5 µs. The UCS
module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, the internal
low-frequency oscillator (VLO), or the trimmed low-frequency oscillator (REFO).
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
6.10.2 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection.
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-
on and power-off. The SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level
and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary
supply and core supply.
6.10.3 Digital I/O

Up to five 8-bit I/O ports are implemented: ports P1 through P5.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P5) or word-wise in pairs (PA and PB).

CC430F5137, CC430F5135, CC430F5133
6.10.4 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port pins
of ports P1 through P3 (see Table 6-6). Table 6-7 lists the default settings for all pins that support port
mapping.
Table 6-6. Port Mapping, Mnemonics and Functions

INPUT PIN FUNCTION OUTPUT PIN FUNCTION
VALUE PxMAPy MNEMONIC
(PxDIR.y = 0) (PxDIR.y = 1)
0 PM_NONE None DVSS
Comparator_B output (on TA0 clock
PM_CBOUT0 –
1 (1) input)
PM_TA0CLK TA0 clock input –
Comparator_B output (on TA1 clock
PM_CBOUT1 –
2 (1) input)
PM_TA1CLK TA1 clock input –
3 PM_ACLK None ACLK output
4 PM_MCLK None MCLK output
5 PM_SMCLK None SMCLK output
6 PM_RTCCLK None RTCCLK output
PM_ADC12CLK – ADC12CLK output
7 (1)
PM_DMAE0 DMA external trigger input –
8 PM_SVMOUT None SVM output
9 PM_TA0CCR0A TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
PM_UCA0RXD USCI_A0 UART RXD (direction controlled by USCI – input)
17 (2)
PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD USCI_A0 UART TXD (direction controlled by USCI – output)
18 (2)
PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
19 (3)
PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)
20 (4)
PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)
21 (4)
PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
22 (5)
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
23 PM_RFGDO0 Radio GDO0 (direction controlled by Radio)
(1) Input or output function is selected by the corresponding setting in the port direction register PxDIR.
(2) UART or SPI functionality is determined by the selected USCI mode.
(3) UCA0CLK function takes precedence over UCB0STE function. If the mapped pin is required as UCA0CLK input or output, USCI_B0 is
forced to 3-wire SPI mode even if 4-wire mode is selected.
(4) SPI or I2C functionality is determined by the selected USCI mode. In case the I2C functionality is selected the output of the mapped pin
drives only the logical 0 to VSS level.
(5) UCB0CLK function takes precedence over UCA0STE function. If the mapped pin is required as UCB0CLK input or output, USCI_A0 is
forced to 3-wire SPI mode even if 4-wire mode is selected.
CC430F5137, CC430F5135, CC430F5133
Table 6-6. Port Mapping, Mnemonics and Functions (continued)

VALUE PxMAPy MNEMONIC
26 Reserved None DVSS
Disables the output driver and the input Schmitt-trigger to prevent parasitic
31 (0FFh) (6) PM_ANALOG
cross currents when applying analog signals.
(6) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,
resulting in a read value of 31.
Table 6-7. Default Mapping

PIN PxMAPy MNEMONIC
P1.0/P1MAP0 PM_RFGDO0 None Radio GDO0
USCI_B0 SPI slave out master in (direction controlled by USCI),
P1.2/P1MAP2 PM_UCB0SOMI/PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI)
USCI_B0 SPI slave in master out (direction controlled by USCI),
P1.3/P1MAP3 PM_UCB0SIMO/PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI),
P1.4/P1MAP4 PM_UCB0CLK/PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
USCI_A0 UART RXD (direction controlled by USCI – input),
P1.5/P1MAP5 PM_UCA0RXD/PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
USCI_A0 UART TXD (direction controlled by USCI – output),
P1.6/P1MAP6 PM_UCA0TXD/PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 clock input/output (direction controlled by USCI),
P1.7/P1MAP7 PM_UCA0CLK/PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
P2.0/P2MAP0 PM_CBOUT1/PM_TA1CLK TA1 clock input Comparator_B output
P2.1/P2MAP1 PM_TA1CCR0A TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
P2.4/P2MAP4 PM_RTCCLK None RTCCLK output
P2.5/P2MAP5 PM_SVMOUT None SVM output
P2.6/P2MAP6 PM_ACLK None ACLK output
P2.7/P2MAP7 PM_ADC12CLK/PM_DMAE0 DMA external trigger input ADC12CLK output
P3.0/P3MAP0 PM_CBOUT0/PM_TA0CLK TA0 clock input Comparator_B output
P3.7/P3MAP7 PM_SMCLK None SMCLK output

CC430F5137, CC430F5135, CC430F5133
6.10.5 System Module (SYS)

The SYS module handles many of the system functions within the device. These functions include power
on reset and power up clear handling, NMI source selection and management, reset interrupt vector
generators (see Table 6-8), bootloader entry mechanisms, and configuration management (device
descriptors). SYS also includes a data exchange mechanism through JTAG called a JTAG mailbox that
can be used in the application.
Table 6-8. System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER ADDRESS INTERRUPT EVENT VALUE PRIORITY
No interrupt pending 00h
Brownout (BOR) 02h Highest
RST/NMI (POR) 04h
PMMSWBOR (BOR) 06h
Reserved 08h
Security violation (BOR) 0Ah
SVSL (POR) 0Ch
SVSH (POR) 0Eh
SVML_OVP (POR) 10h
SYSRSTIV, System Reset 019Eh
SVMH_OVP (POR) 12h
PMMSWPOR (POR) 14h
WDT time-out (PUC) 16h
WDT password violation (PUC) 18h
KEYV flash password violation (PUC) 1Ah
Reserved 1Ch
Peripheral area fetch (PUC) 1Eh
PMM password violation (PUC) 20h
Reserved 22h to 3Eh Lowest
SVMLIFG 02h Highest
SVMHIFG 04h
DLYLIFG 06h
DLYHIFG 08h
SYSSNIV, System NMI 019Ch VMAIFG 0Ah
JMBINIFG 0Ch
JMBOUTIFG 0Eh
VLRLIFG 10h
VLRHIFG 12h
NMIIFG 02h Highest
SYSUNIV, User NMI 019Ah OFIFG 04h
ACCVIFG 06h

CC430F5137, CC430F5135, CC430F5133
6.10.6 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU
intervention. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. Table 6-9 lists the available triggers for DMA
operation.
Table 6-9. DMA Trigger Assignments (1)

CHANNEL
TRIGGER
0 1 2
0 DMAREQ DMAREQ DMAREQ
1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG
5 Reserved Reserved Reserved
16 UCA0RXIFG UCA0RXIFG UCA0RXIFG
17 UCA0TXIFG UCA0TXIFG UCA0TXIFG
18 UCB0RXIFG UCB0RXIFG UCB0RXIFG
19 UCB0TXIFG UCB0TXIFG UCB0TXIFG
(2) (2)
24 ADC12IFGx ADC12IFGx ADC12IFGx (2)
29 MPY ready MPY ready MPY ready
30 DMA2IFG DMA0IFG DMA1IFG
31 DMAE0 DMAE0 DMAE0
(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not
cause any DMA trigger event when selected.
(2) Only on CC430F613x and CC430F513x. Reserved on CC430F612x.

CC430F5137, CC430F5135, CC430F5133
6.10.7 Watchdog Timer (WDT_A)

The primary function of the watchdog timer is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the timer can be configured as an interval timer and can generate
interrupts at selected time intervals.
6.10.8 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.10.9 Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
6.10.10 AES128 Accelerator

The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys
according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.
6.10.11 Universal Serial Communication Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA.
The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.
The USCI_Bn module provides support for SPI (3-pin or 4-pin) and I2C.
One USCI_A0 and one USCI_B0 modules are implemented.

CC430F5137, CC430F5135, CC430F5133
6.10.12 TA0
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities (see
Table 6-10). Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-10. TA0 Signal Connections

MODULE OUTPUT DEVICE OUTPUT
DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK
SIGNAL SIGNAL
PM_TA0CLK TACLK
ACLK (internal) ACLK
Timer NA
SMCLK (internal) SMCLK
RFCLK/192 (1) INCLK
PM_TA0CCR0A CCI0A PM_TA0CCR0A
DVSS CCI0B
CCR0 TA0
DVSS GND
DVCC VCC
ADC12 (internal) (2)
CBOUT (internal) CCI1B
CCR1 TA1 ADC12SHSx = {1}
DVSS GND
DVCC VCC
ACLK (internal) CCI2B
CCR2 TA2
DVSS GND
DVCC VCC
GDO1 from Radio
CCI3B
(internal) CCR3 TA3
DVSS GND
DVCC VCC
GDO2 from Radio
CCI4B
(internal) CCR4 TA4
DVSS GND
DVCC VCC
(1) If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.
(2) Only on CC430F613x and CC430F513x

CC430F5137, CC430F5135, CC430F5133
6.10.13 TA1
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support
multiple capture/compares, PWM outputs, and interval timing (see Table 6-11). TA1 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 6-11. TA1 Signal Connections

DEVICE OUTPUT
MODULE OUTPUT SIGNAL
DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK
SIGNAL
PZ
PM_TA1CLK TACLK
ACLK (internal) ACLK
Timer NA
SMCLK (internal) SMCLK
RFCLK/192 (1) INCLK
RF Async. Output
CCI0B RF Async. Input (internal)
(internal) CCR0 TA0
DVSS GND
DVCC VCC
CBOUT (internal) CCI1B
CCR1 TA1
DVSS GND
DVCC VCC
ACLK (internal) CCI2B
CCR2 TA2
DVSS GND
DVCC VCC
(1) If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.
6.10.14 Real-Time Clock (RTC_A)

The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit
timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by
software. Calendar mode integrates an internal calendar which compensates for months with less than
31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offset-
calibration hardware.
6.10.15 Voltage Reference (REF)

REF generates all of the critical reference voltages that can be used by the various analog peripherals in
the device. These peripherals include the ADC12_A, LCD_B, and COMP_B modules.
6.10.16 LCD_B (Only CC430F613x and CC430F612x)

The LCD_B driver generates the segment and common signals required to drive a liquid crystal display
(LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common
and segment signals are generated as defined by the mode. Static, 2-, 3-, and 4-mux LCDs are
supported. The module can provide a LCD voltage independent of the supply voltage with its integrated
charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The
module also provides an automatic blinking capability for individual segments.

CC430F5137, CC430F5135, CC430F5133
6.10.17 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
6.10.18 ADC12_A (Only CC430F613x and CC430F513x)

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit
SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored
without any CPU intervention.
6.10.19 Embedded Emulation Module (EEM) (S Version)

The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level

CC430F5137, CC430F5135, CC430F5133
6.10.20 Peripheral File Map

Table 6-12 lists the base address for the registers of each peripheral.
Table 6-12. Peripherals

OFFSET ADDRESS
MODULE NAME BASE ADDRESS
RANGE
Special Functions (see Table 6-13) 0100h 000h–01Fh
PMM (see Table 6-14) 0120h 000h–00Fh
Flash Control (see Table 6-15) 0140h 000h–00Fh
CRC16 (see Table 6-16) 0150h 000h–007h
RAM Control (see Table 6-17) 0158h 000h–001h
Watchdog (see Table 6-18) 015Ch 000h–001h
UCS (see Table 6-19) 0160h 000h–01Fh
SYS (see Table 6-20) 0180h 000h–01Fh
Shared Reference (see Table 6-21) 01B0h 000h–001h
Port Mapping Control (see Table 6-22) 01C0h 000h–007h
Port Mapping Port P1 (see Table 6-23) 01C8h 000h–007h
Port Mapping Port P2 (see Table 6-24) 01D0h 000h–007h
Port Mapping Port P3 (see Table 6-25) 01D8h 000h–007h
Port P1, P2 (see Table 6-26) 0200h 000h–01Fh
Port P3, P4 (see Table 6-27)
0220h 000h–01Fh
(P4 not available on CC430F513x)
Port P5 (see Table 6-28) 0240h 000h–01Fh
Port PJ (see Table 6-29) 0320h 000h–01Fh
TA0 (see Table 6-30) 0340h 000h–03Fh
TA1 (see Table 6-31) 0380h 000h–03Fh
RTC_A (see Table 6-32) 04A0h 000h–01Fh
32-Bit Hardware Multiplier (see Table 6-33) 04C0h 000h–02Fh
DMA Module Control (see Table 6-34) 0500h 000h–00Fh
DMA Channel 0 (see Table 6-35) 0510h 000h–00Fh
USCI_A0 (see Table 6-38) 05C0h 000h–01Fh
USCI_B0 (see Table 6-39) 05E0h 000h–01Fh
ADC12 (see Table 6-40)
0700h 000h–03Fh
(only CC430F613x and CC430F513x)
Comparator_B (see Table 6-41) 08C0h 000h–00Fh
AES Accelerator (see Table 6-42) 09C0h 000h–00Fh
LCD_B (see Table 6-43)
0A00h 000h–05Fh
(only CC430F613x and CC430F612x)
Radio Interface (see Table 6-44) 0F00h 000h–03Fh

CC430F5137, CC430F5135, CC430F5133
Table 6-13. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION ACRONYM OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h
Table 6-14. PMM Registers (Base Address: 0120h)

PMM control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
SVS high side control SVSMHCTL 04h
SVS low side control SVSMLCTL 06h
PMM interrupt flags PMMIFG 0Ch
PMM interrupt enable PMMIE 0Eh
PMM power mode 5 control PM5CTL0 10h
Table 6-15. Flash Control Registers (Base Address: 0140h)

Flash control 1 FCTL1 00h
Table 6-16. CRC16 Registers (Base Address: 0150h)

CRC data input CRC16DI 00h
CRC initialization and result CRCINIRES 04h
Table 6-17. RAM Control Registers (Base Address: 0158h)

RAM control 0 RCCTL0 00h
Table 6-18. Watchdog Registers (Base Address: 015Ch)

Watchdog timer control WDTCTL 00h
Table 6-19. UCS Registers (Base Address: 0160h)

UCS control 0 UCSCTL0 00h
UCS control 5 UCSCTL5 0Ah
UCS control 6 UCSCTL6 0Ch
UCS control 7 UCSCTL7 0Eh

CC430F5137, CC430F5135, CC430F5133
Table 6-20. SYS Registers (Base Address: 0180h)

System control SYSCTL 00h
Bootloader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh
Table 6-21. Shared Reference Registers (Base Address: 01B0h)

Shared reference control REFCTL 00h
Table 6-22. Port Mapping Control Registers (Base Address: 01C0h)

Port mapping key PMAPKEYID 00h
Port mapping control PMAPCTL 02h
Table 6-23. Port Mapping Port P1 Registers (Base Address: 01C8h)

Port P1.0 mapping P1MAP0 00h
Table 6-24. Port Mapping Port P2 Registers (Base Address: 01D0h)


CC430F5137, CC430F5135, CC430F5133
Table 6-25. Port Mapping Port P3 Registers (Base Address: 01D8h)

Table 6-26. Port P1, P2 Registers (Base Address: 0200h)

Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 pullup/pulldown enable P1REN 06h
Port P1 drive strength P1DS 08h
Port P1 selection P1SEL 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 selection P2SEL 0Bh
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh
Table 6-27. Port P3, P4 Registers (Base Address: 0220h)

Port P4 selection P4SEL 0Bh

CC430F5137, CC430F5135, CC430F5133
Table 6-28. Port P5 Registers (Base Address: 0240h)

Table 6-29. Port J Registers (Base Address: 0320h)

Port PJ input PJIN 00h
Port PJ output PJOUT 02h
Port PJ direction PJDIR 04h
Port PJ pullup/pulldown enable PJREN 06h
Port PJ drive strength PJDS 08h
Table 6-30. TA0 Registers (Base Address: 0340h)

TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 4 TA0CCTL4 0Ah
TA0 counter TA0R 10h
Capture/compare 0 TA0CCR0 12h
Capture/compare 4 TA0CCR4 1Ah
TA0 expansion 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh
Table 6-31. TA1 Registers (Base Address: 0380h)

TA1 control TA1CTL 00h
TA1 counter TA1R 10h
TA1 expansion 0 TA1EX0 20h
TA1 interrupt vector TA1IV 2Eh

CC430F5137, CC430F5135, CC430F5133
Table 6-32. Real-Time Clock Registers (Base Address: 04A0h)

RTC control 0 RTCCTL0 00h
RTC prescaler 0 control RTCPS0CTL 08h
RTC prescaler 1 control RTCPS1CTL 0Ah
RTC prescaler 0 RTCPS0 0Ch
RTC prescaler 1 RTCPS1 0Dh
RTC interrupt vector word RTCIV 0Eh
RTC seconds/counter 1 RTCSEC/RTCNT1 10h
RTC minutes/counter 2 RTCMIN/RTCNT2 11h
RTC hours/counter 3 RTCHOUR/RTCNT3 12h
RTC day of week/counter 4 RTCDOW/RTCNT4 13h
RTC days RTCDAY 14h
RTC month RTCMON 15h
RTC year low RTCYEARL 16h
RTC year high RTCYEARH 17h
RTC alarm minutes RTCAMIN 18h
RTC alarm hours RTCAHOUR 19h
RTC alarm day of week RTCADOW 1Ah
RTC alarm days RTCADAY 1Bh
Table 6-33. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control 0 MPY32CTL0 2Ch

CC430F5137, CC430F5135, CC430F5133
Table 6-34. DMA Module Control Registers (Base Address: 0500h)

DMA module control 0 DMACTL0 00h
DMA interrupt vector DMAIV 0Ah
Table 6-35. DMA Channel 0 Registers (Base Address: 0510h)

DMA channel 0 control DMA0CTL 00h
DMA channel 0 source address low DMA0SAL 02h
DMA channel 0 source address high DMA0SAH 04h
DMA channel 0 destination address low DMA0DAL 06h
DMA channel 0 destination address high DMA0DAH 08h
DMA channel 0 transfer size DMA0SZ 0Ah



CC430F5137, CC430F5135, CC430F5133
Table 6-38. USCI_A0 Registers (Base Address: 05C0h)

USCI control 1 UCA0CTL1 00h
USCI control 0 UCA0CTL0 01h
USCI baud rate 0 UCA0BR0 06h
USCI baud rate 1 UCA0BR1 07h
USCI modulation control UCA0MCTL 08h
USCI status UCA0STAT 0Ah
USCI receive buffer UCA0RXBUF 0Ch
USCI transmit buffer UCA0TXBUF 0Eh
USCI LIN control UCA0ABCTL 10h
USCI IrDA transmit control UCA0IRTCTL 12h
USCI IrDA receive control UCA0IRRCTL 13h
USCI interrupt enable UCA0IE 1Ch
USCI interrupt flags UCA0IFG 1Dh
USCI interrupt vector word UCA0IV 1Eh
Table 6-39. USCI_B0 Registers (Base Address: 05E0h)

USCI synchronous control 1 UCB0CTL1 00h
USCI synchronous control 0 UCB0CTL0 01h
USCI synchronous bit rate 0 UCB0BR0 06h
USCI synchronous bit rate 1 UCB0BR1 07h
USCI synchronous status UCB0STAT 0Ah
USCI synchronous receive buffer UCB0RXBUF 0Ch
USCI synchronous transmit buffer UCB0TXBUF 0Eh
USCI I2C own address UCB0I2COA 10h
USCI I2C slave address UCB0I2CSA 12h
USCI interrupt enable UCB0IE 1Ch
USCI interrupt flags UCB0IFG 1Dh
USCI interrupt vector word UCB0IV 1Eh

CC430F5137, CC430F5135, CC430F5133
Table 6-40. ADC12_A Registers (Base Address: 0700h)

Control 0 ADC12CTL0 00h
Interrupt flag ADC12IFG 0Ah
Interrupt enable ADC12IE 0Ch
Interrupt vector word ADC12IV 0Eh
ADC memory-control 0 ADC12MCTL0 10h
ADC memory-control 10 ADC12MCTL10 1Ah
ADC memory-control 11 ADC12MCTL11 1Bh
ADC memory-control 12 ADC12MCTL12 1Ch
ADC memory-control 13 ADC12MCTL13 1Dh
ADC memory-control 14 ADC12MCTL14 1Eh
ADC memory-control 15 ADC12MCTL15 1Fh
Conversion memory 0 ADC12MEM0 20h
Conversion memory 5 ADC12MEM5 2Ah
Conversion memory 6 ADC12MEM6 2Ch
Conversion memory 7 ADC12MEM7 2Eh
Conversion memory 13 ADC12MEM13 3Ah
Conversion memory 14 ADC12MEM14 3Ch
Conversion memory 15 ADC12MEM15 3Eh

CC430F5137, CC430F5135, CC430F5133
Table 6-41. Comparator_B Registers (Base Address: 08C0h)

Comp_B control 0 CBCTL0 00h
Comp_B interrupt CBINT 0Ch
Comp_B interrupt vector word CBIV 0Eh
Table 6-42. AES Accelerator Registers (Base Address: 09C0h)

AES accelerator control 0 AESACTL0 00h
Reserved 02h
AES accelerator status AESASTAT 04h
AES accelerator key AESAKEY 06h
AES accelerator data in AESADIN 008h
AES accelerator data out AESADOUT 00Ah
Table 6-43. LCD_B Registers (Base Address: 0A00h)

LCD_B control 0 LCDBCTL0 000h
LCD_B control 1 LCDBCTL1 002h
LCD_B blinking control LCDBBLKCTL 004h
LCD_B memory control LCDBMEMCTL 006h
LCD_B voltage control LCDBVCTL 008h
LCD_B port control 0 LCDBPCTL0 00Ah
LCD_B port control 1 LCDBPCTL1 00Ch
LCD_B charge pump control LCDBCTL0 012h
LCD_B interrupt vector word LCDBIV 01Eh
LCD_B memory 1 LCDM1 020h
LCD_B memory 2 LCDM2 021h
...
LCD_B memory 14 LCDM14 02Dh
LCD_B blinking memory 1 LCDBM1 040h
LCD_B blinking memory 2 LCDBM2 041h
...
LCD_B blinking memory 14 LCDBM14 04Dh

CC430F5137, CC430F5135, CC430F5133
Table 6-44. Radio Interface Registers (Base Address: 0F00h)

Radio interface control 0 RF1AIFCTL0 00h
Radio interface control 1 RF1AIFCTL1 02h
Radio interface error flag RF1AIFERR 06h
Radio interface error vector word RF1AIFERRV 0Ch
Radio interface interrupt vector word RF1AIFIV 0Eh
Radio instruction word RF1AINSTRW 10h
Radio instruction word, 1-byte auto-read RF1AINSTR1W 12h
Radio instruction word, 2-byte auto-read RF1AINSTR2W 14h
Radio data in RF1ADINW 16h
Radio status word RF1ASTATW 20h
Radio status word, 1-byte auto-read RF1ASTAT1W 22h
Radio status word, 2-byte auto-read RF1AISTAT2W 24h
Radio data out RF1ADOUTW 28h
Radio data out, 1-byte auto-read RF1ADOUT1W 2Ah
Radio data out, 2-byte auto-read RF1ADOUT2W 2Ch
Radio core signal input RF1AIN 30h
Radio core interrupt flag RF1AIFG 32h
Radio core interrupt edge select RF1AIES 34h
Radio core interrupt enable RF1AIE 36h
Radio core interrupt vector word RF1AIV 38h

CC430F5137, CC430F5135, CC430F5133
6.11 Input/Output Diagrams
6.11.1 Port P1 (P1.0 to P1.4) Input/Output With Schmitt Trigger

Figure 6-2 shows the port diagram. Table 6-45 summarizes the selection of the pin functions.
S18...S22
(not available on CC430F513x)
LCDS18...LCDS22
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
DVSS 0
DVCC 1 1
P1DIR.x 0
Direction
from Port Mapping 1 0: Input
1: Output
P1OUT.x 0
from Port Mapping 1

P1.0/P1MAP0(/S18)
P1DS.x
P1SEL.x P1.1/P1MAP1(/S19)
0: Low drive
P1.2/P1MAP2(/S20)
1: High drive
P1.3/P1MAP3(/S21)
P1IN.x P1.4/P1MAP4(/S22)
EN Bus
Keeper
to Port Mapping D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x Set
P1SEL.x Interrupt
Edge
P1IES.x Select
CC430F513x devices do not provide LCD functionality on port P1 pins.
Figure 6-2. Port P1 (P1.0 to P1.4) Diagram

CC430F5137, CC430F5135, CC430F5133
Table 6-45. Port P1 (P1.0 to P1.4) Pin Functions

CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x) x FUNCTION LCDS18 to
P1DIR.x P1SEL.x P1MAPx
LCDS22 (2)
P1.0 (I/O) I: 0; O: 1 0 X 0
(3) (3)
Mapped secondary digital function – see Table 6-6 0; 1 1 ≤ 30 0
P1.0/P1MAP/S18 0
Output driver and input Schmitt trigger disabled X 1 = 31 0
S18 (not available on CC430F513x) X X X 1
P1.1 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function – see Table 6-6 0; 1 (3) 1 ≤ 30 (3) 0
P1.1/P1MAP1/S19 1
P1.2 (I/O) I: 0; O: 1 0 X 0
P1.2/P1MAP2/S20 2
P1.3 (I/O) I: 0; O: 1 0 X 0
P1.3/P1MAP3/S21 3
P1.4 (I/O) I: 0; O: 1 0 X 0
P1.4/P1MAP4/S22 4
(1) X = don't care
(2) LCDSx not available in CC430F513x.
(3) According to mapped function – see Table 6-6.

CC430F5137, CC430F5135, CC430F5133

to LCD_B
(n/a CC430F513x)
Pad Logic
P1REN.x
DVSS 0
DVCC 1 1
P1DIR.x 0
Direction
1: Output
P1OUT.x 0
from Port Mapping 1

P1.5/P1MAP5(/R23)
P1DS.x
P1SEL.x P1.6/P1MAP6(/R13)
0: Low drive
P1.7/P1MAP7(/R03)
1: High drive
P1IN.x
EN Bus
Keeper
to Port Mapping D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x Set
P1SEL.x Interrupt
Edge
P1IES.x Select

CC430F5137, CC430F5135, CC430F5133

PIN NAME (P1.x) x FUNCTION
P1.5 (I/O) I: 0; O: 1 0 X
P1.5/P1MAP5/R23 5 Mapped secondary digital function – see Table 6-6 0; 1 (2) 1 ≤ 30 (2)
R23 (3) (not available on CC430F513x) X 1 = 31
P1.6 (I/O) I: 0; O: 1 0 X
P1.6/P1MAP6/R13/
6 Mapped secondary digital function – see Table 6-6 0; 1 (2) 1 ≤ 30 (2)
LCDREF
R13/LCDREF (3) (not available on CC430F513x) X 1 = 31
P1.7 (I/O) I: 0; O: 1 0 X
P1.7/P1MAP7/R03 7 Mapped secondary digital function – see Table 6-6 0; 1 (2) 1 ≤ 30 (2)
R03 (3) (not available on CC430F513x) X 1 = 31
(1) X = don't care
(3) Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.

CC430F5137, CC430F5135, CC430F5133

Figure 6-4 through Figure 6-6 show the port diagrams. Table 6-47 summarizes the selection of the pin
functions.
Pad Logic
To ADC12
(n/a CC430F612x)
INCHx = x
To Comparator_B
from Comparator_B
CBPD.x
P2REN.x
DVSS 0
DVCC 1 1
P2DIR.x 0
Direction
1: Output
P2OUT.x 0
from Port Mapping 1

P2.0/P2MAP0/CB0(/A0)
P2DS.x
P2SEL.x P2.1/P2MAP2/CB1(/A1)
0: Low drive
1: High drive
P2IN.x
EN Bus
Keeper
to Port Mapping D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x Set
P2SEL.x Interrupt
Edge
P2IES.x Select

CC430F5137, CC430F5135, CC430F5133
Pad Logic
To or from Reference
To ADC12
INCHx = x
To Comparator_B
from Comparator_B
CBPD.x
P2REN.x
DVSS 0
DVCC 1 1
P2DIR.x 0
Direction
1: Output
P2OUT.x 0
from Port Mapping 1

P2.4/P2MAP4/CB4(/A4/VREF-/VeREF-)
P2DS.x
P2SEL.x P2.5/P2MAP5/CB5(/A5/VREF+/VeRF+)
0: Low drive
1: High drive
P2IN.x
EN Bus
Keeper
to Port Mapping D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x Set
P2SEL.x Interrupt
Edge
P2IES.x Select
Figure 6-5. Port P2 (P2.4 and P2.5) Diagram

CC430F5137, CC430F5135, CC430F5133
Pad Logic
To ADC12
(n/a CC430F513x)
INCHx = x
To Comparator_B
(n/a CC430F513x)
from Comparator_B
CBPD.x
(n/a CC430F513x)
P2REN.x
DVSS 0
DVCC 1 1
P2DIR.x 0
Direction
1: Output
P2OUT.x 0
from Port Mapping 1

P2.6/P2MAP6(/CB6/A6)
P2DS.x
P2SEL.x P2.7/P2MAP7(/CB7/A7)
0: Low drive
1: High drive
P2IN.x
EN Bus
Keeper
to Port Mapping D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x Set
P2SEL.x Interrupt
Edge
P2IES.x Select
CC430F513x devices do not provide analog functionality on port P2.6 and P2.7 pins.
Figure 6-6. Port P2 (P2.6 and P2.7) Diagram

CC430F5137, CC430F5135, CC430F5133

P2DIR.x P2SEL.x P2MAPx CBPD.x
P2.0 (I/O) I: 0; O: 1 0 X 0
P2.0/P2MAP0/CB0 Mapped secondary digital function – see Table 6-6 0; 1 (2) 1 ≤ 30 (2) 0
0
(/A0) A0 (not available on CC430F612x) (3)
X 1 = 31 X
CB0 (4) X X X 1
P2.1 (I/O) I: 0; O: 1 0 X 0
(2) (2)
P2.1/P2MAP1/CB1 Mapped secondary digital function – see Table 6-6 0; 1 1 ≤ 30 0
1
(/A1) A1 (not available on CC430F612x) (3) X 1 = 31 X
CB1 (4) X X X 1
P2.2 (I/O) I: 0; O: 1 0 X 0
2
CB2 (4) X X X 1
P2.3 (I/O) I: 0; O: 1 0 X 0
3
CB3 (4) X X X 1
P2.4 (I/O) I: 0; O: 1 0 X 0
4
(/A4/VREF-/VeREF-) A4/VREF-/VeREF- (not available on CC430F612x) (3)
X 1 = 31 X
CB4 (4) X X X 1
P2.5 (I/O) I: 0; O: 1 0 X 0
5
(/A5/VREF+/VeREF+) A5/VREF+/VeREF+ (not available on CC430F612x) (3)
X 1 = 31 X
CB5 (4) X X X 1
P2.6 (I/O) I: 0; O: 1 0 X 0
(2) (2)
P2.6/P2MAP6(/CB6)
6 A6 (not available on CC430F612x and
(/A6) X 1 = 31 X
CC430F513x) (3)
CB6 (not available on CC430F513x) (4) X X X 1
P2.7 (I/O) I: 0; O: 1 0 X 0
P2.7/P2MAP7(/CB7)
7 A7 (not available on CC430F612x and
(/A7) X 1 = 31 X
CC430F513x) (3)
CB7 (not available on CC430F513x) (4) X X X 1
(1) X = don't care
(3) Setting P2SEL.x bit together with P2MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
(4) Setting the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input buffer
for that pin, regardless of the state of the associated CBPD.x bit.

CC430F5137, CC430F5135, CC430F5133

S10...S17
(n/a CC430F513x)
LCDS10...LCDS17
Pad Logic
P3REN.x
DVSS 0
DVCC 1 1
P3DIR.x 0
Direction
1: Output
P3OUT.x 0
from Port Mapping 1

P3.0/P3MAP0(/S10)
P3DS.x
P3SEL.x P3.1/P3MAP1(/S11)
0: Low drive
P3.2/P3MAP2(/S12)
1: High drive
P3.3/P3MAP3(/S13)
P3IN.x P3.4/P3MAP4(/S14)
P3.5/P3MAP5(/S15)
Bus P3.6/P3MAP6(/S16)
EN
Keeper P3.7/P3MAP7(/S17)
to Port Mapping D

CC430F5137, CC430F5135, CC430F5133

LCDS17 (2)
P3.0 (I/O) I: 0; O: 1 0 X 0
(3) (3)
P3.0/P3MAP0/S10 0
P3.1 (I/O) I: 0; O: 1 0 X 0
P3.1/P3MAP1/S11 1
P3.2 (I/O) I: 0; O: 1 0 X 0
P3.2/P3MAP7/S12 2
P3.3 (I/O) I: 0; O: 1 0 X 0
P3.3/P3MAP3/S13 3
P3.4 (I/O) I: 0; O: 1 0 X 0
P3.4/P3MAP4/S14 4
P3.5 (I/O) I: 0; O: 1 0 X 0
(3) (3)
P3.5/P3MAP5/S15 5
P3.6 (I/O) I: 0; O: 1 0 X 0
P3.6/P3MAP6/S16 6
P3.7 (I/O) I: 0; O: 1 0 X 0
P3.7/P3MAP7/S17 7
(1) X = don't care
(2) LCDSx not available in CC430F513x.

CC430F5137, CC430F5135, CC430F5133
6.11.5 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (CC430F613x and
CC430F612x Only)
S2...S9
LCDS2...LCDS9
Pad Logic
P4REN.x
DVSS 0
DVCC 1 1
P4DIR.x 0
Direction
1 0: Input
1: Output
P4OUT.x 0
DVSS 1
P4.0/S2
P4DS.x
P4SEL.x P4.1/S3
0: Low drive
P4.2/S4
1: High drive
P4.3/S5
P4IN.x P4.4/S6
P4.5/S7
Bus P4.6/S8
EN
Keeper P4.7/S9
Not Used D
Figure 6-8. Port P4 (P4.0 to P4.7) Diagram (CC430F613x and CC430F612x Only)

CC430F5137, CC430F5135, CC430F5133
Table 6-49. Port P4 (P4.0 to P4.7) Pin Functions (CC430F613x and CC430F612x Only)
P4DIR.x P4SEL.x
LCDS9
P4.0 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.0/P4MAP0/S2 0
DVSS 1 1 0
S2 X X 1
P4.1 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.1/P4MAP1/S3 1
DVSS 1 1 0
S3 X X 1
P4.2 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.2/P4MAP7/S4 2
DVSS 1 1 0
S4 X X 1
P4.3 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.3/P4MAP3/S5 3
DVSS 1 1 0
S5 X X 1
P4.4 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.4/P4MAP4/S6 4
DVSS 1 1 0
S6 X X 1
P4.5 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.5/P4MAP5/S7 5
DVSS 1 1 0
S7 X X 1
P4.6 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.6/P4MAP6/S8 6
DVSS 1 1 0
S8 X X 1
P4.7 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.7/P4MAP7/S9 7
DVSS 1 1 0
S9 X X 1
(1) X = don't care

CC430F5137, CC430F5135, CC430F5133
6.11.6 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger

Figure 6-9 and Figure 6-10 show the port diagrams. Table 6-50 summarizes the selection of the pin
functions.
Pad Logic
to XT1
P5REN.0
DVSS 0
DVCC 1 1
P5DIR.0 0
P5OUT.0 0
Module X OUT 1
P5.0/XIN
P5DS.x
P5SEL.0 0: Low drive
1: High drive
P5IN.0
EN Bus
Keeper
Module X IN D
Figure 6-9. Port P5 (P5.0) Diagram

CC430F5137, CC430F5135, CC430F5133
Pad Logic
to XT1
P5REN.1
DVSS 0
DVCC 1 1
P5DIR.1 0
P5OUT.1 0
Module X OUT 1
P5.1/XOUT
P5SEL.0 P5DS.x
0: Low drive
XT1BYPASS 1: High drive
P5IN.1
EN Bus
Keeper
Module X IN D
Figure 6-10. Port P5 (P5.1) Diagram
Table 6-50. Port P5 (P5.0 and P5.1) Pin Functions

P5DIR.x P5SEL.0 P5SEL.1 XT1BYPASS
P5.0 (I/O) I: 0; O: 1 0 X X
(2)
P5.0/XIN 0 XIN crystal mode X 1 X 0
XIN bypass mode (2) X 1 X 1
P5.1 (I/O) I: 0; O: 1 0 X X
P5.1/XOUT 1 XOUT crystal mode (3) X 1 X 0
P5.1 (I/O) (3) X 1 X 1
(1) X = don't care
(2) Setting P5SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.0 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.1 can be used as
general-purpose I/O.

CC430F5137, CC430F5135, CC430F5133
CC430F612x Only)
Figure 6-11 shows the port diagram. Table 6-51 and Table 6-52 summarize the selection of the pin
functions.
S0(P5.2)/S1(P5.3)/S23(P5.4)
LCDS0(P5.2)/LCDS1(P5.3)/LCDS23(P5.4)
Pad Logic
P5REN.x
DVSS 0
DVCC 1 1
P5DIR.x 0
P5OUT.x 0
DVSS 1
P5.2/S0
P5DS.x
P5SEL.x P5.3/S1
0: Low drive
P5.4/S23
1: High drive
P5IN.x
EN Bus
Keeper
Not Used D

CC430F5137, CC430F5135, CC430F5133
P5DIR.x P5SEL.x
LCDS1
P5.2 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.2/S0 2
DVSS 1 1 0
S0 X X 1
P5.3 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.3/S1 3
DVSS 1 1 0
S1 X X 1
(1) X = don't care
Table 6-52. Port P5 (P5.4) Pin Functions (CC430F613x and CC430F612x Only)
P5DIR.x P5SEL.x LCDS23
P5.4 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.4/S23 4
DVSS 1 1 0
S23 X X 1
(1) X = don't care

CC430F5137, CC430F5135, CC430F5133
CC430F612x Only)
S24(P5.5)/S25(P5.6)/S26(P5.7)
LCDS24(P5.5)/LCDS25(P5.6)/LCDS26(P5.7)
COM3(P5.5)/COM2(P5.6)/COM1(P5.7)
Pad Logic
P5REN.x
DVSS 0
DVCC 1 1
P5DIR.x
P5OUT.x
P5.5/COM3/S24
P5DS.x
P5SEL.x P5.6/COM2/S25
0: Low drive
P5.7/COM1/S26
1: High drive
P5IN.x
Bus
Keeper
P5DIR.x P5SEL.x
LCDS26
P5.5 (I/O) I: 0; O: 1 0 0
(2)
P5.5/COM3/S24 5 COM3 X 1 X
S24 (2) X 0 1
P5.6 (I/O) I: 0; O: 1 0 0
(2)
P5.6/COM2/S25 6 COM2 X 1 X
S25 (2) X 0 1
P5.7 (I/O) I: 0; O: 1 0 0
P5.7/COM1/S26 7 COM1 (2) X 1 X
S26 (2) X 0 1
(1) X = don't care
(2) Setting P5SEL.x bit disables the output driver and the input Schmitt trigger.

CC430F5137, CC430F5135, CC430F5133
6.11.9 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.0
DVSS 0
DVCC 1 1
PJDIR.0 0
DVCC 1
PJOUT.0 0
From JTAG 1
PJ.0/TDO
PJDS.0
From JTAG 0: Low drive
1: High drive
PJIN.0
Figure 6-13. Port PJ (PJ.0) Diagram

CC430F5137, CC430F5135, CC430F5133
6.11.10 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Pad Logic
PJREN.x
DVSS 0
DVCC 1 1
PJDIR.x 0
DVSS 1
PJOUT.x 0
From JTAG 1
PJ.1/TDI/TCLK
PJDS.x
From JTAG PJ.2/TMS
0: Low drive
PJ.3/TCK
1: High drive
PJIN.x
EN
To JTAG D
Figure 6-14. Port PJ (PJ.1 to PJ.3) Diagram
Table 6-54. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS OR
PIN NAME (PJ.x) x FUNCTION SIGNALS (1)
PJDIR.x
PJ.0 (I/O) (2) I: 0; O: 1
PJ.0/TDO 0
TDO (3) X
(2)
PJ.1 (I/O) I: 0; O: 1
PJ.1/TDI/TCLK 1
TDI/TCLK (3) (4)
X
PJ.2 (I/O) (2) I: 0; O: 1
PJ.2/TMS 2
TMS (3) (4)
X
PJ.3 (I/O) (2) I: 0; O: 1
PJ.3/TCK 3
TCK (3) (4)
X
(1) X = don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.

CC430F5137, CC430F5135, CC430F5133
6.12 Device Descriptor

Table 6-55 lists the content of the device descriptor tag-length-value (TLV) structure for CC430F613x and
CC430F513x device types.
Table 6-56 lists the content of the device descriptor tag-length-value (TLV) structure for CC430F612x
device types.
Table 6-55. Device Descriptor Table (CC430F613x and CC430F513x)
SIZE VALUE
DESCRIPTION ADDRESS
(bytes) F6137 F6135 F5137 F5135 F5133
Info length 01A00h 1 06h 06h 06h 06h 06h
CRC length 01A01h 1 06h 06h 06h 06h 06h
CRC value 01A02h 2 Per unit Per unit Per unit Per unit Per unit
Info Block Device ID 01A04h 1 61h 61h 51h 51h 51h
Device ID 01A05h 1 37h 35h 37h 35h 33h
Hardware revision 01A06h 1 Per unit Per unit Per unit Per unit Per unit
Firmware revision 01A07h 1 Per unit Per unit Per unit Per unit Per unit
Die record tag 01A08h 1 08h 08h 08h 08h 08h
Die record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah
Lot/wafer ID 01A0Ah 4 Per unit Per unit Per unit Per unit Per unit
Die Record
Die X position 01A0Eh 2 Per unit Per unit Per unit Per unit Per unit
Die Y position 01A10h 2 Per unit Per unit Per unit Per unit Per unit
Test results 01A12h 2 Per unit Per unit Per unit Per unit Per unit
ADC12 calibration tag 01A14h 1 11h 11h 11h 11h 11h
ADC12 calibration length 01A15h 1 10h 10h 10h 10h 10h
ADC gain factor 01A16h 2 Per unit Per unit Per unit Per unit Per unit
ADC offset 01A18h 2 Per unit Per unit Per unit Per unit Per unit
ADC 1.5-V reference
01A1Ah 2 Per unit Per unit Per unit Per unit Per unit
Temperature sensor 30°C
ADC 1.5-V reference
ADC12 01A1Ch 2 Per unit Per unit Per unit Per unit Per unit
Calibration
ADC 2.0-V reference
01A1Eh 2 Per unit Per unit Per unit Per unit Per unit
ADC 2.0-V reference
01A20h 2 Per unit Per unit Per unit Per unit Per unit
ADC 2.5-V reference
ADC 2.5-V reference
REF calibration tag 01A26h 1 12h 12h 12h 12h 12h
REF calibration length 01A27h 1 06h 06h 06h 06h 06h
REF
1.5-V reference factor 01A28h 2 Per unit Per unit Per unit Per unit Per unit
Calibration
2.0-V reference factor 01A2Ah 2 Per unit Per unit Per unit Per unit Per unit
2.5-V reference factor 01A2Ch 2 Per unit Per unit Per unit Per unit Per unit
Peripheral descriptor tag 01A2Eh 1 02h 02h 02h 02h 02h
Peripheral
Descriptor Peripheral descriptor length 01A2Fh 1 57h 57h 55h 55h 55h
(PD)
Peripheral descriptors 01A30h PD Length ... ... ... ... ...

CC430F5137, CC430F5135, CC430F5133
Table 6-56. Device Descriptor Table (CC430F612x)
SIZE VALUE
DESCRIPTION ADDRESS
(bytes) F6127 F6126 F6125
Info length 01A00h 1 06h 06h 06h
CRC length 01A01h 1 06h 06h 06h
CRC value 01A02h 2 Per unit Per unit Per unit
Info Block Device ID 01A04h 1 61h 61h 61h
Device ID 01A05h 1 27h 26h 25h
Hardware revision 01A06h 1 Per unit Per unit Per unit
Firmware revision 01A07h 1 Per unit Per unit Per unit
Die record tag 01A08h 1 08h 08h 08h
Die record length 01A09h 1 0Ah 0Ah 0Ah
Lot/wafer ID 01A0Ah 4 Per unit Per unit Per unit
Die Record
Die X position 01A0Eh 2 Per unit Per unit Per unit
Die Y position 01A10h 2 Per unit Per unit Per unit
Test results 01A12h 2 Per unit Per unit Per unit
Empty tag 01A14h 1 05h 05h 05h
Empty Descriptor Empty tag length 01A15h 1 10h 10h 10h
01A16h 16 undefined undefined undefined
REF calibration l 01A26h 1 12h 12h 12h
REF calibration length 01A27h 1 06h 06h 06h
REF Calibration 1.5-V reference factor 01A28h 2 Per unit Per unit Per unit
2.0-V reference factor 01A2Ah 2 Per unit Per unit Per unit
2.5-V reference factor 01A2Ch 2 Per unit Per unit Per unit
Peripheral descriptor tag 01A2Eh 1 02h 02h 02h
Peripheral Descriptor
Peripheral descriptor length 01A2Fh 1 55h 55h 55h
(PD)
Peripheral descriptors 01A30h PD Length ... ... ...

CC430F5137, CC430F5135, CC430F5133
7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 Application Circuits

Figure 7-1 shows a typical application circuit for the CC430F61xx. Table 7-1 lists the bill of materials.
108 Applications, Implementation, and Layout Copyright © 2009–2018, Texas Instruments Incorporated
CC430F5137, CC430F5135, CC430F5133
SMA STRAIGHT JACK, SMT
C29
L7
C28
L6
L5
C27
C26
L3
C24
C25
C23
L4
L2
L1
C3
C7
(May be added close to the respective pins
to reduce emissions at 5GHz to levels
C6
C2
C5
C1
required by ETSI.)
C4
C18
C17
C16
C22
26MHz
R1
(JTAG / SBW signals)
AVDD
C21
RF_XOUT
AVCC_RF
AVCC_RF
AVCC_RF
AVCC_RF
TDI/TCLK
GUARD
R_BIAS
RF_XIN
RF_N
RF_P
TMS
TDO
C20
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
TCK
TEST/SBWTCK
R2
nRST/NMI/SBWTDIO
VDD
DVCC
C15
C14
AVSS
C8
VDD
CC430F61xx
C9
DVCC
AVDD
AVCC
C13
C12
11
12
15
10
16
13
14
1
2
9
6
8
3
4
DVCC
VCORE
C10
C11
VDD
C19

For a complete reference design including layout, see the CC430 wireless development tools and the MSP430
Hardware Tools User's Guide.
Figure 7-1. Typical Application Circuit CC430F61xx
Copyright © 2009–2018, Texas Instruments Incorporated Applications, Implementation, and Layout 109
CC430F5137, CC430F5135, CC430F5133
Figure 7-2 shows a typical application circuit for the CC430F51xx. Table 7-1 lists the bill of materials.
SMA STRAIGHT JACK, SMT
C29
L7
C28
L6
L5
C27
C26
L3
C24
C25
C23
L4
L2
L1
C3
C7
(May be added close to the respective pins
to reduce emissions at 5GHz to levels
C6
C2
C5
C1
C4
required by ETSI.)
C22
C18
C17
C16
26MHz
R1 AVDD
C21
(JTAG / SBW signals)
AVCC_RF
AVCC_RF
RF_XOUT
AVCC_RF
AVCC_RF
TDI/TCLK
GUARD
R_BIAS
RF_XIN
RF_N
RF_P
TDO
34
31
30
27
28
36
35
32
29
26
25
33
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
C8
TMS
C20
VDD
TCK
C9
DVCC
TEST/SBWTCK
R2
nRST/NMI/SBWTDIO
VDD
CC430F51xx
DVCC
C15
C14
AVSS
AVDD
AVCC
C13
C12
12
10
11
2
5
6
8
9
3
4
7
1
DVCC
VCORE
C10
C11
VDD
C19

For a complete reference design including layout, see the CC430 wireless development tools and the MSP430
Hardware Tools User's Guide.
Figure 7-2. Typical Application Circuit CC430F51xx
110 Applications, Implementation, and Layout Copyright © 2009–2018, Texas Instruments Incorporated
CC430F5137, CC430F5135, CC430F5133
Table 7-1. Bill of Materials

Components For 315 MHz For 433 MHz For 868 or 915 MHz Comment
C1, C3, C4, C5, C7,
100 nF Decoupling capacitors
C9, C11, C13, C15
C8, C10, C12, C14 10 µF Decoupling capacitors
C2, C6, C16, C17,
2 pF Decoupling capacitors
C18
C19 470 nF VCORE capacitor
C20 2.2 nF RST decoupling cap (optimized for SBW)
C21, C22 27 pF Load capacitors for 26 MHz crystal (1)
R1 56 kΩ R_BIAS (±1% required)
R2 47 kΩ RST pullup
L1, L2 Capacitors: 220 pF 0.016 µH 0.012 µH
L3, L4 0.033 µH 0.027 µH 0.018 µH
L5 0.033 µH 0.047 µH 0.015 µH
(2) (2)
L6 dnp dnp 0.0022 µH
L7 0.033 µH 0.051 µH 0.015 µH
C23 dnp (2) 2.7 pF 1 pF
C24 220 pF 220 pF 100 pF
C25 6.8 pF 3.9 pF 1.5 pF
C26 6.8 pF 3.9 pF 1.5 pF
C27 220 pF 220 pF 1.5 pF
C28 10 pF 4.7 pF 8.2 pF
C29 220 pF 220 pF 1.5 pF
(1) The load capacitance CL seen by the crystal is CL = 1 / ((1 / C21) + (1 / C22)) + Cparasitic. The parasitic capacitance Cparasitic includes pin
capacitance and PCB stray capacitance. It can typically be estimated to be approximately 2.5 pF.
(2) dnp = do not populate
Copyright © 2009–2018, Texas Instruments Incorporated Applications, Implementation, and Layout 111
CC430F5137, CC430F5135, CC430F5133
8 Device and Documentation Support

8.1 Getting Started and Next Steps
For an introduction to the MSP430™ family of devices and the tools and libraries that are available to help
with your development, visit the Getting Started page.
8.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. Figure 8-1 provides a legend for reading the
complete device name.
112 Device and Documentation Support Copyright © 2009–2018, Texas Instruments Incorporated
CC430F5137, CC430F5135, CC430F5133
MSP 430 F 5 438 A I ZQW T -EP
Processor Family Optional: Additional Features
MCU Platform Optional: Tape and Reel
Device Type Packaging
Series Optional: Temperature Range
Feature Set Optional: A = Revision
Processor Family CC = Embedded RF Radio

MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
MCU Platform 430 = MSP430 low-power microcontroller platform
Device Type Memory Type Specialized Application
C = ROM AFE = Analog Front End
F = Flash BQ = Contactless Power
FR = FRAM CG = ROM Medical
G = Flash or FRAM (Value Line) FE = Flash Energy Meter
L = No Nonvolatile Memory FG = Flash Medical
FW = Flash Electronic Flow Meter
Series 1 = Up to 8 MHz 5 = Up to 25 MHz
2 = Up to 16 MHz 6 = Up to 25 MHz with LCD
3 = Legacy 0 = Low-Voltage Series
4 = Up to 16 MHz with LCD
Feature Set Various levels of integration within a series
Optional: A = Revision N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging http://www.ti.com/packaging
Optional: Tape and Reel T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 8-1. Device Nomenclature
Copyright © 2009–2018, Texas Instruments Incorporated Device and Documentation Support 113
CC430F5137, CC430F5135, CC430F5133
8.3 Tools and Software

The CC430 microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties.
Design Kits and Evaluation Modules
CC430 Sub-GHz RF Experimenter's Board The MSP-EXPCC430RFx Experimenter Kit is a complete
sub-GHz development platform for the CC430 devices from the MSP430 family of ultra-low-
power microcontrollers. The kit provides two sub-GHz wireless modules: the MSP-
EXP430F6137Rx Base Board with the CC430F6137, and the MSP-EXP430F5137Rx
Satellite Board with the CC430F5137.
Chronos: Wireless Development Tool in a Watch The eZ430-Chronos is a highly integrated, wearable
wireless development system based for the CC430 in a sports watch. It may be used as a
reference platform for watch systems, a personal display for personal area networks, or as a
wireless sensor node for remote data collection.
Sub-1 GHz RF Spectrum Analyzer Tool The MSP-SA430-SUB1GHZ Spectrum Analyzer is CC430-
based reference design that can be used to implement an easy and affordable tool to
jumpstart RF development in the sub-GHz frequency range. More and more electronic
devices include a built-in RF link. RF transceivers are inexpensive - but the equipment to
design and debug such systems is not. The CC430-based spectrum analyzer provides an
affordable development tool that reduces the time needed on expensive measurement
equipment.
Software
MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 design resources,
MSP430Ware software also includes a high-level API called MSP Driver Library. This library
makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
CC430F613x Code Examples C Code examples that configure each of the integrated peripherals for
various application needs.
ULP (Ultra-Low Power) Advisor ULP (Ultra-Low Power) Advisor is a tool for guiding developers to write
more efficient code to fully utilize the unique ultra-low power features of MSP430 and
MSP432 microcontrollers. Aimed at both experienced and new microcontroller developers,
ULP Advisor checks your code against a thorough ULP checklist to squeeze every last nano
amp out of your application.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers Code
Composer Studio is an integrated development environment (IDE) that supports all MSP
microcontroller devices. Code Composer Studio comprises a suite of embedded software
utilities used to develop and debug embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment, debugger, profiler, and many other
features.
GCC - Open Source Compiler for MSP430 Microcontrollers TI has partnered with Red Hat to bring
you a new and fully supported open source compiler as the successor to the community
driven MSPGCC. This free GCC 4.9 compiler supports all MSP430 devices and has no code
size limit. In addition, this compiler can be used stand-alone or selected within Code
Composer Studio v6.0 or later.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which allows users to quickly begin application development on MSP
low-power microcontrollers (MCU).
MSP-GANG Production Programmer The MSP Gang Programmer is a device programmer that can
program up to eight identical devices at the same time. The MSP Gang Programmer
connects to a host PC using a standard RS-232 or USB connection and provides flexible
programming options that allow the user to fully customize the process.
CC430F5137, CC430F5135, CC430F5133
8.4 Documentation Support

The following documents describe the CC430F613x, CC430F612x, and CC430F513x devices. Copies of
these documents are available on the Internet at www.ti.com.
Receiving Nofication of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (for links to the product folder, see Section 8.5). In the upper right corner, click the
"Alert me" button. This registers you to receive a weekly digest of product information that has changed (if
any). For change details, check the revision history of any revised document.
Errata
CC430F6137 Device Erratasheet Describes the known exceptions to the functional specifications.
User's Guides
CC430 Family User's Guide Detailed information on the modules and peripherals available in this
device family.
Code Composer Studio for MSP430 User's Guide This user's guide describes how to use the TI Code
Composer Studio IDE with the MSP430 ultra-low-power microcontrollers.
MSP430™ Flash Device Bootloader (BSL) User's Guide The MSP430 bootloader (BSL, formerly
known as the bootstrap loader) allows users to communicate with embedded memory in the
MSP430 microcontroller during the prototyping phase, final production, and in service. Both
the programmable memory (flash memory) and the data memory (RAM) can be modified as
required. Do not confuse the bootloader with the bootstrap loader programs found in some
digital signal processors (DSPs) that automatically load program code (and data) from
external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultra-
low-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board
layout are important for a stable crystal oscillator. This application report summarizes crystal
oscillator function and explains the parameters to select the correct crystal for MSP430 ultra-
low-power operation. In addition, hints and examples for correct board layout are given. The
document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing cost-
effective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs: (1) Component-level ESD testing and system-level ESD testing, their differences
CC430F5137, CC430F5135, CC430F5133
and why component-level ESD rating does not ensure system-level robustness. (2) General
design guidelines for system-level ESD protection at different levels including enclosures,
cables, PCB layout, and on-board ESD protection devices. (3) Introduction to System
Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD
protection to achieve system-level ESD robustness, with example simulations and test
results. A few real-world system-level ESD protection design examples and their results are
also discussed.
DN005 CC11xx Sensitivity versus Frequency Offset and Crystal Accuracy This design note provides
plots of CC11xx (CC1100, CC1100E, CC1101, CC1110, and CC1111) sensitivity versus
frequency offset for different data rates. The required crystal accuracy is calculated from
these plots. The results are also applicable for CC430.
AN050 Using the CC1101 in the European 868 MHz SRD Band The CC1101 is a truly low cost, highly
integrated, and very flexible RF transceiver. The CC1101 is primarily designed for use in
low-power applications in the 315, 433, 868 and 915 MHz SRD/ISM bands. This application
note describes how to use the CC1101 in the European 863 – 870 MHz SRD frequency
bands in order to comply with EN 300 220 requirements. The application note is also
applicable for CC1110, CC1111, and CC430 SoCs as they use the same radio as CC1101.
DN010 Close-in Reception with CC1101 This document describes how the CC1100E and CC1101 can
be used in close-range applications. The chips have a saturation limit of approximately −15
dBm at 250 kbps, which might be a challenge for some short-range applications. Two
suggested solutions are presented, the first is a double-transmit scheme and the second is
to shift the receivers dynamic range during close-range reception.
DN013 Programming Output Power on CC1101 The CC1101 RF output power level is set by the
PATABLE register setting. This register setting also influences the power levels at the
different harmonics and the current consumption for the device. These parameters must
therefore be considered when choosing the optimal register settings. This document gives
complete CC1101 PA tables with typical output power, harmonics, and current consumption
for the different register settings at 25°C and 3.0 V supply voltage.
DN017 CC11xx 868/915 MHz RF Matching This design note gives a short introduction to RF matching
and important aspects when designing products using the CC11xx parts. Because all of the
CC11xx parts have the same RF front end, the same matching network can be used
between the radio and the antenna. TI provides a reference design for all CC11xx products.
These reference designs show recommended placement and values for decoupling
capacitors and components in the matching network.
CC430F5137, CC430F5135, CC430F5133
8.5 Related Links

Table 8-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
CC430F6137 Click here Click here Click here Click here Click here
8.6 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.7 Trademarks
MSP430, MSP430Ware, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.8 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.9 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
CC430F5137, CC430F5135, CC430F5133
9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
118 Mechanical, Packaging, and Orderable Information Copyright © 2009–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 8-Sep-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
CC430F5133IRGZ ACTIVE VQFN RGZ 48 52 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430
& no Sb/Br) F5133
CC430F5133IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430
& no Sb/Br) F5133
CC430F5133IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430
& no Sb/Br) F5133
& no Sb/Br) F5135
& no Sb/Br) F5135
& no Sb/Br) F5135
& no Sb/Br) F5137
& no Sb/Br) F5137
& no Sb/Br) F5137
CC430F6125IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS CU NIPDAU | Level-3-260C-168 HR -40 to 85 CC430F6125
& no Sb/Br) CU NIPDAUAG
CC430F6127IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS CU NIPDAU | Level-3-260C-168 HR -40 to 85 CC430F6127
CC430F6137IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS CU NIPDAU | Level-3-260C-168 HR -40 to 85 CC430F6137
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 8-Sep-2018
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Mar-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC430F6125IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
CC430F6127IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
CC430F6137IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Mar-2019
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CC430F6125IRGCR VQFN RGC 64 2000 350.0 350.0 43.0
CC430F6127IRGCT VQFN RGC 64 250 213.0 191.0 55.0
CC430F6137IRGCT VQFN RGC 64 250 213.0 191.0 55.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48 VQFN - 1 mm max height
7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
RGZ0048B SCALE 2.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
7.15 A
B
6.85
PIN 1 INDEX AREA
7.15
6.85
1 MAX
C
SEATING PLANE
0.05
0.00 0.08 C
2X 5.5
4.1 0.1
(0.2) TYP
13 24 EXPOSED
44X 0.5 THERMAL PAD
12
25
49 SYMM
2X
5.5
36 0.30
48X
1 0.18
0.1 C B A
48 37
0.05
PIN 1 ID SYMM
0.5
(OPTIONAL) 48X
0.3
4218795/B 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGZ0048B VQFN - 1 mm max height
( 4.1)
(1.115) TYP
(0.685)
TYP 37
48
48X (0.6)
1
36
48X (0.24)
(1.115)
TYP
44X (0.5)
(0.685)
SYMM 49 TYP
( 0.2) TYP (6.8)

VIA
(R0.05)
TYP
12 25
13 24
SYMM
(6.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:12X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK
METAL OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK
NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4218795/B 02/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGZ0048B VQFN - 1 mm max height
(1.37)
TYP
48 37
48X (0.6)
1
36
48X (0.24)
44X (0.5) (1.37)

TYP
SYMM 49
(R0.05) TYP (6.8)
9X
METAL ( 1.17)
TYP
12 25
13 24
SYMM
(6.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4218795/B 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
RGC 64 VQFN - 1 mm max height
9 x 9, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064B SCALE 1.500
VQFN - 1 mm max height
9.15 A
B
8.85
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8 C
SEATING PLANE
0.05 0.08 C
0.00
2X 7.5
EXPOSED SYMM (0.2) TYP
THERMAL PAD
17 32
16 33
SYMM 65
2X 7.5 4.25 0.1
60X
0.5
1 48 0.30
64X
64 49 0.18
PIN 1 ID
0.1 C A B
0.5
64X 0.05
0.3
4219010/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064B VQFN - 1 mm max height
( 4.25)
SYMM SEE SOLDER MASK

64X (0.6) DETAIL
64 49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP (1.18) TYP
(8.8)
SYMM 65
(0.695) TYP
( 0.2) TYP
VIA
16 33
17 32
(0.695) TYP
(1.18) TYP
(8.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
0.07 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK
EXPOSED METAL
SOLDER MASK EXPOSED SOLDER MASK
OPENING METAL OPENING
NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4219010/A 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064B VQFN - 1 mm max height
SYMM
64X (0.6) 64 49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
9X ( 1.19)
65
SYMM (8.8)
(1.39)
16 33
17 32
(1.39)
(8.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219010/A 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CC 430 F 6137

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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125

CC430F613x, CC430F612x, CC430F513x MSP430™ SoC With RF Core

Device Information (1)

2 Device Overview Copyright © 2009–2018, Texas Instruments Incorporated

1.4 Functional Block Diagrams

I/O Ports I/O Ports I/O Ports

Figure 1-1. CC430F613x Functional Block Diagram

Copyright © 2009–2018, Texas Instruments Incorporated Device Overview 3

Figure 1-2 shows the CC430F612x functional block diagram.

I/O Ports I/O Ports I/O Ports

Figure 1-2. CC430F612x Functional Block Diagram

4 Device Overview Copyright © 2009–2018, Texas Instruments Incorporated

Figure 1-3 shows the CC430F513x functional block diagram.

I/O Ports I/O Ports I/O Ports

Figure 1-3. CC430F513x Functional Block Diagram

Copyright © 2009–2018, Texas Instruments Incorporated Device Overview 5

Changes from September 6, 2013 to September 17, 2018 Page

6 Revision History Copyright © 2009–2018, Texas Instruments Incorporated

Table 3-1. Device Comparison (1) (2)

PROGRAM SRAM CHANNEL ADC12_A COMP_B

3.1 Related Products

Copyright © 2009–2018, Texas Instruments Incorporated Device Comparison 7

4 Terminal Configuration and Functions

CAUTION: The LCDCAP/R33 must be connected to VSS if not used.

Figure 4-1. 64-Pin RGC Package (Top View), CC430F613x

8 Terminal Configuration and Functions Copyright © 2009–2018, Texas Instruments Incorporated

CAUTION: The LCDCAP/R33 must be connected to VSS if not used.

Figure 4-2. 64-Pin RGC Package (Top View), CC430F612x

Copyright © 2009–2018, Texas Instruments Incorporated Terminal Configuration and Functions 9

Figure 4-3. 48-Pin RGZ Package (Top View), CC430F513x

10 Terminal Configuration and Functions Copyright © 2009–2018, Texas Instruments Incorporated

4.2 Signal Descriptions

Table 4-1. CC430F613x and CC430F612x Terminal Functions

(1) I = input, O = output

Table 4-1. CC430F613x and CC430F612x Terminal Functions (continued)

12 Terminal Configuration and Functions Copyright © 2009–2018, Texas Instruments Incorporated

Table 4-1. CC430F613x and CC430F612x Terminal Functions (continued)

Copyright © 2009–2018, Texas Instruments Incorporated Terminal Configuration and Functions 13

Table 4-2. CC430F513x Terminal Functions

(1) I = input, O = output

Table 4-2. CC430F513x Terminal Functions (continued)

Copyright © 2009–2018, Texas Instruments Incorporated Terminal Configuration and Functions 15

Table 4-2. CC430F513x Terminal Functions (continued)

16 Terminal Configuration and Functions Copyright © 2009–2018, Texas Instruments Incorporated

5.1 Absolute Maximum Ratings (1)

5.2 ESD Ratings

5.3 Recommended Operating Conditions

Recommended Operating Conditions (continued)

Figure 5-1. Maximum System Frequency

18 Specifications Copyright © 2009–2018, Texas Instruments Incorporated

FREQUENCY (fDCO = fMCLK = fSMCLK)

5.5 Typical Characteristics – Active Mode Supply Currents

Copyright © 2009–2018, Texas Instruments Incorporated Specifications 19

Low-power mode 3, crystal 1 1.9 2.1 3.2 4.8

Low-power mode 3, 1 1.0 1.2 2.3 3.9

20 Specifications Copyright © 2009–2018, Texas Instruments Incorporated

5.7 Typical Characteristics – Low-Power Mode Supply Currents

ILPM4 - LPM4 Supply Current - µA

Copyright © 2009–2018, Texas Instruments Incorporated Specifications 21

5.9 Thermal Resistance Characteristics, CC430F51xx

5.10 Thermal Resistance Characteristics, CC430F61xx