Proceedings of India International Conference on Power Electronics 2006

FPGA based digital platform for the control of

AC drives
N. Praveen Kumar and V.T. Ranganathan, Senior Member, IEEE
Department of Electrical Engineering
Indian Institute of Science
Bangalore-560012.
Email: praveeniisc@gmail.com, vtran@ee.iisc.ernet.in .

Abstract - This paper presents the new trend of FPGA

(Field programmable Gate Array) based digital platform
for the control of power electronic systems. There is a
rising interest in using digital controllers in power
electronic applications as they provide many advantages
over their analog counterparts. A board comprising of
Cyclone device EP1C12Q240C8 of Altera is used for
developing this platform. The details of this board are
presented. This developed platform can be used for the
controller applications such as UPS, Induction Motor
drives and front end converters. A real time simulation of
a system can also be done. An open-loop induction motor
drive has been implemented using this board and
experimental results are presented.

Index Terms. Digital platform, FPGA, induction motor,

V/f drive, PWM technique, switching frequency.

I. INTRODUCTION

T
Fig. 1. Block diagram of FPGA board

he control of power electronic applications such as AC
drives being complex, digital controllers such as
microprocessors, micro controllers or DSP processors are
needed. The development of ASIC/FPGA with several
thousands of logic gates and high logic density forms the
future digital platform for control. In recent years motor
control and power conversion employing ASIC/FPGA
technology are receiving increased attention because of their
ability to meet the need of complex modulation schemes and
high speed switching requirement [1].
In past two decades, various PWM strategies and control
schemes for power electronic applications have been
developed. With the advance of high frequency power
devices, complex modulation schemes can no longer be
realized even with most advanced DSPs because of high
speed switching requirement. Employing FPGA to realize
PWM strategies provides advantages such as simple hardware
and software design, high switching frequency. The
motivation of the present work is to develop a controller,
which will not only reduce the cost and size of the controller
but also improve the performance in terms of operating at
higher switching frequencies and being user friendly.
This paper presents the implementation of Open loop V/f
induction motor drive in the developed platform and
experimental results are included.
In the proposed IM motor control algorithm, a voltage source
inverter is used for controlling the speed of the motor in open
loop mode. FPGA based control platform is used for
implementation. The proposed method is tested on a 200V,
50Hz, 1500 rpm Induction motor and the relevant test results
are presented.
The organization of the paper is as follows. First the details of
the FPGA board are explained. Then the applications and
advantages of this digital platform are presented. The control
scheme and FPGA implementation and realization of the
controller is discussed. Finally the experimental results are
presented.

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Fig. 3. Configuration of FPGA device

The vertical and horizontal interconnects of varying speeds

provide signal interconnects to implement the custom logic.
The choice of an FPGA device for a given application is
based on the size required (number of logic elements), clock
speed and number of I/O pins. ALTERA EP1C12Q240C8 is
found to be suitable for the given platform. The resources in
Fig. 2. Block diagram of FPGA device
this device are listed in Table-I.

B. Configuration device

The configuration device is an EEPROM (EPCS4IN), which

is connected to a PC through a parallel port or USB port using
ByteblaserII or USB blaster cable. The design is done using
Quartus-II (Altera's design tool for FPGA) and the output file
of the compilation is downloaded through Byteblaster-II or
USB blaster cable to EEPROM. The arrangement for
configuring the FPGA is shown in Fig.3.

II. DETAILS OF THE FPGA BOARD

The digital platform consists of FPGA device and other

devices interfaced to FPGA as shown in Fig. 1. The devices
interfaced include configuration device (EEPROM), ADC Fig. 4. Block diagram of On-board clocknetwork
and DAC. Besides dedicated I/O pins are also provided.
C. On-board clock network
A. FPGA device
In an FPGA, different blocks of logic elements can operate at
The general architecture of an FPGA device is shown in
different clock frequencies. There are four clock inputs to the
Fig.2. The FPGA has logic elements arranged in rows and
chosen device. These clocks can be of different frequencies
columns as shown. Each logic element has certain hardware
and unsynchronized. PLL present inside the FPGA can be
resources, which will be utilized to realize the user logic [3].
used to multiply the frequency of any input clocks. The board
consists of two crystal oscillators both of 20 MHz frequency
as shown in Fig. 4

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D. Digital to Analog Converter
DAC on the board, DAC-7625U, is used to output the digital
variables in the controller in analog form. The DAC is a TTL
device working with +5V and -5V power supply. This SOIC
packaged 12-bit, 28-pin DAC of TEXAS has 4 channels with
conversion time of 10 µsec.
One of the main advantages of FPGAs is the reconfigurability
of the hardware as compared to DSP processors, in which the
hardware resources are fixed and cannot be reconfigured.
This reconfigurability is achieved by using a software tool
corresponding to that device.

E. Analog to Digital Converter

ADC on the board, AD7864AS-1 of Analog devices, is used

to convert the analog input signals from the system to digital
signals, which are used for further processing. This MQFP
packaged, 12-bit, 44-pin simultaneous ADC has 4 channels
with a conversion time of 1.6 µsec per channel. There are two
such ADCs on the board and hence the board can take 8-
analog inputs.

F. Digital I/Os Fig. 5. Block diagram for open loop v/f control of IM

Dedicated digital I/Os are necessary to interface to ADC,

DAC etc which are present on the board. Apart from that 56
I/O pins are provided for the user to interface application
specific hardware.

G. Power Supply requirements

The cyclone FPGA device requires 1.5V (VCCINT) for its

core and I/O voltage (VCCIO) can vary from 1.5V to 3.3V. In
this board 3.3V is chosen as I/O voltage for FPGA because
most of the interfacing devices on board operated at 3.3V
level or above. ADC requires single +5V for its operation.
DAC requires +5V, -5V, 2.5V, -2.5V for its operation. On
this basis of this requirements 5V and -5V is given as power
supply to the board and other levels needed are derived on the
board.
III. APPLICATIONS AND ADVANTAGES OF AN FPGA BOARD
As the name suggests, FPGA is field programmable and
hence can be used for many applications in contrast to ASIC
(Application Specific Integrated Circuits). The FPGA
platform can be used for power electronic applications such
as closed loop control of AC drives, unity power factor
correction converters, shunt active filters and control of
phase-controlled converters. Now a days work is also being
done in using FPGAs in real time simulations. The response
of such simulations is same as that of actual system itself.
The time taken for the execution of the control algorithm
depends on the A/D conversion time and the FPGA
propagation delay. The latter being quite low, the execution
time mainly depends upon the former. ADC requires 6.4 µs
conversion time for eight analog signals.
Fig. 6. Control block for V/f program
The bit length of the digital word is not limited in an FPGA
where as in the case of DSP processor or other processors it is
limited. It is easy to interface the peripherals. There are
different platforms such as VHDL programming or block
diagram schematic in which the programming of the chip can
be done.
The library of advanced FPGA devices usually includes a set
of processor cores to be used in complex applications. Such a
processor can be configured using a block of logic elements.
Both the software and hardware resources of such a core are
configurable.
IV. IMPLEMENTATION OF V/F DRIVE
In a speed control system, evidently the actual speed of the
motor should be measured through a sensor in order to
accurately control the speed. In many industrial drives, it is
desirable to avoid the installation of a sensor, from the point
of view of cost, installation problems, reliability, etc. Such
drives are referred to as open loop drives. No feedback
information is available from the motor and the drive control
has only the speed command to act upon. The voltage and
frequency have to be related to each other through the V/f

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program [2], [4]. This program generates the voltage

command using the frequency command as the input.
Therefore, the task of the drive control reduces to that of
generating the frequency command using speed command as
input. The block diagram is shown in Fig. 5. Since the rated
or full load slip of an induction motor is usually small, the
simplest approach for generating the frequency command is
to directly use the speed command as the frequency
command.

V. EXPERIMENTAL RESULTS

The complete experimental hardware used for testing the

proposed control scheme is shown in Fig. 5. This consists of a
squirrel cage induction motor fed by a three-phase voltage
source inverter. The details of the motor used are shown in
the Table-II. A photograph of the FPGA board that is used as
a controller is shown in Fig. 7. The inverter receives the
gating pulses from the FPGA controller. A sine-triangle based
PWM technique is employed for running the inverter. It can
be seen that, to obtain 200V rms line to line voltage at the
output of the inverter at unity modulation index, a DC bus
voltage of 326V is to be maintained. Therefore DC bus is
charged to the above-mentioned voltage and the program is
burned into FPGA. The sine values are stored in a table of
Fig. 7. Picture of the FPGA board ROM block with in FPGA. The three phase sinusoidal
references are generated from this table and are compared
The resulting drive control block diagram is shown in Fig. 6. with a triangular carrier wave in every sampling time for
With such an arrangement the motor will always run at a generating the gating pulses. The gating pulses generated by
speed, which is less than the commanded speed by the slip the board are routed to the inverter using an interface card.
speed corresponding to the prevailing load torque. If this The hardware involved in the inverter generates a dead time
speed error is accepted, then the system will run satisfactorily
of 2µsec in each of the three legs.
in the steady state. However, the above simple arrangement
may result in the motor pulling out when the speed command
is suddenly changed. A sudden change in the speed command
results in a huge current transient. This transient may be
acceptable provided the inverter can handle the resulting
transient over currents.
Therefore, in the drive control scheme of Fig. 6, the slow start
block is incorporated to prevent the sudden changes in the
frequency command f*. But in steady state f* will be equal to
w*. However, the speed of response of the drive to the
changes in the speed command is now very much limited.
This is not a drawback in many drives, as speed changes are
commanded only once in a while.

Fig. 8. (a) Output of the slow starter block (b) Frequency and voltage
ramping at 25Hz speed command
X-axis: Time in ms (500 ms/div)
Y-axis: Voltage in V (2 V/div)

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The inverter used can handle switching frequencies of up to 5

KHz. Therefore triangular carrier frequency is chosen as 4.88
KHz (which is derived from system clock) and hence the
inverter switching frequency is 4.88 KHz. The sampling time
is chosen as 102.4 µsec. The speed command is given
externally from a potentiometer to FPGA through a channel
of one of the ADCs. The results are presented when the speed
command to the controller is 25Hz. The ramping of voltage
and frequency of the R-phase reference sine wave while
starting the motor is shown in Fig. 8. The gating pulses
generated for R-phase and Y-phase are shown in Fig. 9.

Fig. 11 No Load Current Waveform at 25Hz speed command

X-axis: Time in ms (500 ms/div)
Y-axis: Current in A (2.5 A/div)

Fig. 9. PWM pulses generated for R and Y phases at 25Hz speed

command
X-axis: Time in ms (500 ms/div)
Y-axis: Voltage in V (5 V/div)

The line-to-line voltage waveform VRY is shown in Fig. 10. It

can be seen that there is no pulse of opposite polarity in line-
to-line voltage waveform. The waveform of motor current at Fig. 12 Current Waveform at 25Hz speed command at a load of 400 W.
no-load is shown in Fig. 11. The motor is loaded using a X-axis: Time in ms (10 ms/div)
Y-axis: Current in A (5 A/div)
motor-generator setup. The waveform of motor current under
load condition is shown in Fig. 12.
VI. CONCLUSIONS

FPGA based digital platform is more suitable for the control

applications in Power electronic systems. The use of FPGAs
in control applications not only increases the performance of
the system but also reduces the cost and size of the controller.
The resources consumed for the implementation of V/f drive
is around 1500 logic elements out of 12,060 logic elements
available. This platform can also be used for many
applications such as Front-end converters, closed loop control
of AC drives, uninterrupted power supplies, DC-to-DC
converters and phase-controlled rectifiers.

Fig. 10. Line voltage waveform VRY at 25Hz speed command
X-axis: Time in ms (500 ms/div)
Y-axis: Voltage in V (5 V/div); Line-to-line voltage: 326V/5V
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control IC for three phase PWM converters., IEEE Transaction on Power
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[2] S. Venugopal and G. Narayanan,. FPGA Based Digital Platform for

Control of Power Electronic Systems., National Power Electronic
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[3] Cyclone device family datasheet,. Altera FPGA manufacturer.,
www.altera.com.
[4] G. Narayanan, V. T. Ranganathan, Synchronized PWM strategies
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[5] G. Narayanan,.Synchronized pulse width modulation strategies based on
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