EE Lab Manuls Fast Nu

EL225-Electronic Devices and
Circuits
Lab Manual
Department of Electrical Engineering
FAST-NU, Lahore
Lab Manual of Electronic Devices and Circuits
Created by: Ms. Farrah Fayyaz, Mr. Aurangzeb
Date: August, 2005
Last Updated by: Ms. Aroosa Umair
Date: April, 2019
Approved by the HOD: Dr. S.M Sajid
Date: April, 2019
2
Table of Contents
S.# Title & Description of Experiment Page #
1 Diode Characteristics 5
2 Half wave Rectification 10
3 Full Wave Rectification 17
4 Clipping Circuits 24
5 Clamping Circuits 31
6 Regulated DC Power Supplies using Zener Diode 38
7 Design of DC Power Supply 44
8 BJT Characteristics 45
9 Voltage divider and collector feedback bias 49
10 Common emitter amplifier 58
11 Emitter follower amplifier 63
12 Design of BJT Amplifier 68
13 MOSFET transistor characteristics 69
14 DC biasing of MOSFET 78
15 Appendix A: Lab Evaluation Criteria 83
16 Appendix B: Safety around electricity 84
17 Appendix C: Guidelines on preparing lab reports 86
3
List of Equipment
Sr. No. Description
1 Oscilloscope 40 MHZ (CS-4135A)
2 Digital Multi-meter (Escort 3136A)
3 Function Generator 10 MHZ (EGC-3236A)
4 Digital Power Supply (Matrix MPS-3005 L-3)
5 Bread board
4
EXPERIMENT 1
DIODE CHARACTERISTICS
OBJECTIVE:
● To become familiar with the characteristics of a Silicon diode.
EQUIPMENT:
INSTRUMENTS
● DMM
COMPONENTS
● Resistors: 1 KΩ, 1 MΩ
● Diode: 1N4007
THEORY:
DIODE TEST
Many digital multi-meters have a diode test position that provides a convenient way to
test a diode. A typical DMM has a small diode symbol to mark the position of the function
switch. When set to diode test, the meter provides an internal voltage sufficient to forward
bias and reverse bias a diode. This internal voltage may vary among different makes of
DMM, but 2.5 to 3.5 V is a typical range of values. The meter provides a voltage reading
or other indication to show the condition of the diode under test.
With one polarity, the DMM should provide the barrier potential of the diode, while
the reverse connection should result in an ‘OL’ response to support the open-circuit
approximation.
I-V CHARACTERISTICS OF A DIODE
Figure 1.1 The IV Characteristics of a diode
The i-v characteristics of a silicon or germanium diode have the general shape shown in
Figure 1.1. The current through an ideal diode is given by the equation 1.1:
5
i = Is (ev/nVT - 1) (Eq 1.1)
where ‘v’ is the voltage drop across the junction, ‘Is’ is a constant called the saturation
current and depends on the temperature and the particular geometry and material of the
diode. ‘VT’ is a constant called the thermal voltage and its value at 27˚C is 25.2 mV. ‘n’ is
a constant and its value varies between 1 and 2 depending on the material and physical
structure of a diode. The diode’s response is directional and highly non-linear. When
forward biased, (i.e. v is positive) enormous currents can flow through the diode because
of the exponential dependence of i on v. When reverse biased, (i.e. v is negative) the current
approaches –Is. Is is typically very small. Thus the diode acts like a one-way valve i.e.
current can flow in one direction only. When forward biased, the positive end of the diode
is called the anode, and the negative end is called the cathode.
The cut-in-voltage is determined by extending a straight line tangent to the curve until
it hits the horizontal axis. The intersection with x-axis will determine the cut-in-voltage or
barrier voltage Vo.
DC RESISTANCE OF A DIODE
The DC or static resistance of a diode at any point on the characteristics is determined
by the ratio of the diode voltage at that point, divided by the diode current. That is,
RDC = VD/ID ohms (Eq 1.2)

AC RESISTANCE OF A DIODE
The AC or dynamic resistance, rD at a particular point on the forward i-v
characteristics of diode can be determined using a tangent line drawn on the characteristic
curves. The slope of this line is equal to 1/rD. So,
rD = Δ V / Δ I ohms (Eq 1.3)
It can be shown through differential calculus that the AC resistance of a diode in

the vertical-rise section of the characteristics is given by
rD= VT /ID ohms (Eq 1.4)
PRE LAB
1. Calculate ID for the circuit given in Figure 1.2 using constant voltage drop model
of a diode.
2. Calculate RDC for this value of ID.
PROCEDURE
PART 1: Diode test using diode measurement scale of DMM
6
a) Perform the diode test using DMM diode testing scale and record the values in
Table 1.1.
TABLE 1.1
DMM test for diode using diode measurement scale of DMM
Forward
Reverse
PART 2: Forward-bias diode characteristics
Figure 1.2 Forward bias diode characteristics
a) Construct the network of Figure 1.2.

b) Record the measured value of the resistor.
Rmeas = _____________
c) Increase the supply voltage until VR reads 0.1 V. Then measure VD and record in
Table 1.2. Calculate ID using the equation ID (mA)=VR/Rmeas.
TABLE 1.2
VR (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VD (V)
𝑉𝑅
ID = 𝑅 (mA)
𝑚𝑒𝑎𝑠
TABLE 1.3
7
VR (V) 1 2 3 4 5 6 7 8 9 10
VD (V)
𝑉𝑅
ID= 𝑅 (mA)
𝑚𝑒𝑎𝑠
d) Repeat step-c for the remaining values of VR in Table 1.3.

e) Plot ID versus VD for the figure 1.2. Finish off the curves by extending the lower
region of the curve to the intersection of the axis at ID = 0 mA and VD = 0 V. Label
each curve and clearly indicate data points.
PART 3: Reverse bias
Figure 1.3 Reverse bias diode characteristics

a) Construct the circuit of Figure 1.3 and record the measured value of R. Since the
reverse saturation current will be relatively small, a large resistance of 1 MΩ is
required if the voltage across R is to be of measurable dimensions.
Rmeas = _________________
b) Measure the voltage VR. Calculate the reverse saturation current from Is =
VR/(Rmeas||Rm). The internal resistance (Rm) of the DMM is included because of the
large magnitude of the resistance R. If internal resistance of DMM is unavailable,
use a typical value of 10 MΩ.
Rm = _________________
(Measured)VR = _________________
(Calculated) Is = _________________
c) Determine the DC resistance level of the diode using the equation RDC = (V-VR)/Is.
8
(Calculated) RDC = ________________
d) Is the resistance level sufficiently high to be considered open circuit equivalent if

appearing in series with resistors in the low kilo-ohm range?
POST LAB:
PART 4: DC Resistance
a) Plot ID versus VD for the Figure 1.2. Finish off the curves by extending the lower
region of the curve to the intersection of the axis at ID = 0 mA and VD = 0 V. Label
each curve and clearly indicate data points.
b) Using diode curve of Figure 1.3 determine the diode voltage at diode current levels
indicated in Table 1.4. Then determine the resistance at each current level.
TABLE 1.4
ID(mA) VD RDC
0.2
1
5
10
c) Are there any trends in DC resistance as the diode current increases and we move up
the vertical-rise section of the characteristics?
PART 5: AC Resistance
d) Using the equation rD=∆V/∆I, determine the AC resistance of the silicon diode by
drawing a tangent at ID = 9 mA using the diode curve of Figure 1.3.
(Calculated) rD = _________________
a) Determine the AC resistance at ID = 9 mA using the equation rD = VT/ID for the silicon
diode.
(Calculated) rD = ________________
b) How do the results of part (a) and (b) compare?
PART 6: Cut-in-voltage
Graphically determine the cut-in-voltage (barrier voltage) of the diode from its
characteristics as defined in the theory. Show the straight-line approximations on graph.
Vo = ________________
9
EXPERIMENT 2
HALF WAVE RECTIFICATION

OBJECTIVE:
● To become familiar with half-wave rectification
EQUIPMENT:
INSTRUMENTS
● Oscilloscope with probes
● Function generator
● DMM
COMPONENTS
● Resistors: 2.2 kΩ (2), 10kΩ
● Diode: 1N4007 (1)
● Capacitor 10uF
THEORY:
A rectifier circuit converts AC voltage into DC voltage. Diodes are used in rectifier
circuits because of their ability to conduct in one direction and block current in other
direction as shown in Figure 2.1.
The half-wave rectifier utilizes alternate half cycles of the sinusoidal input. The
half-wave signal of Figure-1 normally established by a network with a single diode has an
average or equivalent DC level equal to 31.8% of the peak value, Vm.
Figure 2.1Half wave rectification
In selecting diode for a rectifier design, the peak inverse voltage (PIV) or zener breakdown
voltage parameter must be considered carefully. For typical single-diode half wave
rectification systems, the required PIV level is equal to the peak value of the applied
sinusoidal signal. For the four-diode full-wave bridge rectification system, the required
PIV level is again peak value, but for a two-diode center tapped configuration, it is twice
the peak value of the applied signal. The PIV voltage is the maximum reverse-bias voltage
that a diode can handle before entering the breakdown region.
PRE-LAB
Read the procedure and draw all expected waveforms.
10
PROCEDURE
Determine the cut-in-voltage, Vo using the diode checking capability of the DMM.
Vo = ________________
PART 2: Half-wave Rectification
a) Construct a circuit of Figure 2.2. Record the measured value of the resistance.
Rmeas = _______________
b) Set the input to 1000 Hz, 8 Vp-p sinusoidal volts.
Figure 2.2 Half-wave rectifier
c) Trace the input on Figure 2.3 as seen on the oscilloscope.
Figure 2.3
d) Using cut-in-voltage of Part-1, determine the theoretical output voltage Vout for
Figure 2.2 and sketch the expected waveform on Figure 2.4 for one full cycle using
the same sensitivities used in part 2 (c). Indicate the maximum and minimum values
on the output waveform.
11
Vout in X-Y mode

Vout in voltage-time mode (Expected)
Figure 2.4
e) Using the oscilloscope with AC/DC switch to DC, obtain the voltage Vout and sketch
the waveform on Figure 2.5.
Vout in voltage-time mode(Observed) Vout in X-Y mode

Figure 2.5
f) Switch the AC/DC switch of oscilloscope to the AC position. What is the effect on
the output signal Vout? Does it appear that the area under the curve above the zero-
axis equals the area under the curve below the zero-axis? Discuss the effect of the AC
position on waveforms that have an average value over one full cycle.
g) Reverse the diode of Figure 2.2 and sketch the output waveform obtained on the
oscilloscope on Figure 2.6.
12

Figure 2.6
PART 3: Half-wave Rectification (continued)
Figure 2.7
b) Sketch the expected output waveform Vout on Figure 2.8. Mark the maximum and
minimum values of the waveform.
Vout in voltage-time mode(Expected) Vout in X-Y mode

Figure 2.8
c) Using the oscilloscope obtain the waveform for Vout and record on Figure 2.9.
13

Figure 2.9
d) Reverse the direction of the diode and record the resulting waveform on Figure 2.10
as obtained using the oscilloscope.
Figure 2.10
PART 4: Half-wave Rectification
a) Replace 2.2kΩ resistor with a 10uF capacitor in circuit of figure 2.2.

b) Using the oscilloscope obtain the waveform for Vout and record on Figure 2.11.
14

Figure 2.11
c) Now connect 2.2kΩ resistor in parallel with 10uF capacitor in circuit built in
above step.
d) Using the oscilloscope obtain the waveform for Vout and record on Figure 2.12.
Vout in X-Y mode

Vout in voltage-time mode(Observed)
Figure 2.12
e) Observe in DC setting and measure Vout peak and Vr (ripple voltage) as follow
Vout = ________________
Vr = ________________
f) Also measure VDC at output using multi meter.

VDC = ________________
15
g) Now replace 2.2k resistor with 10k resistor and repeat step d and e for Figure
2.13.
Vout in X-Y mode

Figure 2.13
Vout = ________________
Vr = ________________
POST LAB
a) How do the results of parts 2(d) and 2(e) compare?

b) Are the waveforms of Figure 2.8 and Figure 2.9 relatively close in appearance and
magnitude?
c) Compare the results of Figure 2.9 and Figure 2.10. What are the major differences
and why?
d) Compare the result of part 4 (e) and (f).
e) Calculate Vav for all observed values in the above performed experiment.
𝑉
f) Calculate 𝑟𝑝𝑒𝑎𝑘 using data achieved in above experiment for both cases.
𝑉 𝐷𝐶
g) Calculate Iav for both cases.
h) Calculate Imax for both cases.
16
EXPERIMENT 3
FULL WAVE RECTIFICATION

OBJECTIVE:
● To become familiar with the full-wave rectification
EQUIPMENT:
INSTRUMENTS
● DMM
● 24 V center-tapped transformer
COMPONENTS
● Resistors: 2.2 kΩ (4), 10kΩ
● Capacitors: 10uF
● Diode: 1N4007 (4)
THEORY:
The full-wave rectifier utilizes both halves of the input sinusoid. The full-wave rectified
signal of Figure 3.1 has twice the average or DC level of the half-wave signal, or 63.6% of
the peak value, Vm.
For large sinusoidal inputs (Vm>>VO, VO is the cut-in-voltage of the diode) the
forward-biased transition voltage of a diode can be ignored. However, for situations when
the peak value of the sinusoidal signal is not that much greater than V O, it can have a
noticeable effect on VDC.
Figure 3.1 Full wave rectification
Determine the cut-in-voltage, Vo using the diode checking capability of the DMM.
Vo = ________________
PART 2: Full-wave rectification (Bridge configuration)
17
a) Construct the full-wave bridge rectifier of Figure 3.2.
Figure 3.2 Full wave bridge rectifier

b) Sketch the expected output waveform Vout on Figure 3.3.

Figure 3.3
c) Using the oscilloscope obtain the waveform for Vout and record on Figure 3.4. Also
label the maximum and minimum values of the waveform.
18

Figure 3.4
d) Replace diodes D3 and D4 by 2.2 kΩ resistors. Sketch the expected output voltage
Vout on Figure 3.5. Label the magnitude of the maximum and minimum values.

Figure 3.5
e) Using oscilloscope, obtain the waveform for Vout and trace on Figure 3.6 indicating
the maximum and minimum values.
19
Figure 3.6
PART 3: Full-wave center-tapped configuration

a) Construct the circuit of Figure 3.7.
Figure 3.7 Full wave center-tapped
Measure the secondary voltages with the DMM set on AC and record this value
below:
(Measured) Vrms = __________
b) Using Vo of Part-1 for each diode sketch the expected output waveform Vout on
Figure 3.8.
20

Figure 3.8
c) Using the oscilloscope obtain the waveform for Vout and record on Figure 3.9.

Figure 3.9
Also label the maximum and minimum values of the waveform.
PART 4: Full-wave rectifier with filter capacitor:
a) Connect a capacitor in parallel with 2.2k resistor of figure 3.7.

b) Using the oscilloscope obtain the waveform for Vout and record on Figure 3.10.
21

Figure 3.10
c) Observe in DC setting and measure Vout peak and Vr(ripple voltage) as follow
Vout = ________________
Vr= ________________
d) Now replace 2.2k resistor with 10k resistor and repeat part b and c for Figure
3.11.

Figure 3.11
Vout = ________________
Vr= ________________
Compare the result of parts (c) and (d).
22
POST LAB
a) How do the waveforms of Parts 2(b) and 2(c) compare?

b) How do the waveforms of Figure 3.5 and Figure 3.6 compare?
c) What was the major effect of replacing the two diodes with resistors?
d) How do the waveforms of Parts 3(b) and 3(c) compare?
e) Explain the reason for difference in values of Vr in part 4 (c) and (d)?
f) Calculate Vav for all in observed values in the above performed experiment.
g) Calculate Iav.
h) Calculate Imax.
23
EXPERIMENT 4
CLIPPING CIRCUITS
OBJECTIVE:
● To become familiar with the function and operation of limiters
EQUIPMENT:
INSTRUMENTS
● DMM
COMPONENTS
● Resistor: 2.2 kΩ
● Diode: 1N4007 (2)
● Zener diode: (6.8 V)
THEORY:
The primary function of a limiter is to limit a portion of an applied alternating
signal. The process is typically performed by a resistor-diode combination. A DC source
can also be incorporated to provide additional shifts of the applied voltage.
A double limiter limits both the positive and negative peaks of an input waveform.
Single limiters limit either the positive or negative peak.
PROCEDURE:
Determine the cut-in-voltage for the diode using the diode-checking capability of
the DMM. Or assume VO = 0.7 V for silicon diode.
PART 2: Single limiter

a) Construct the limiting circuit of Figure 4.1. Give a sinusoidal input voltage with peak
value at least greater than VO. (Or give an input of 8 Vp-p sinusoidal at a frequency of
1000 Hz).
Figure 4.1
Vin (amplitude) = ____________

Vin (frequency) = ____________
b) Sketch the expected output waveform for vout on Figure 4.2. In particular find vout when
the applied signal is at its positive and negative peak and zero volts.
24

Figure 4.2
(Calculated) vout (amplitude) when vin is at +ve peak = _______________
(Calculated) vout (amplitude) when vin is at –ve peak = _______________
(Calculated) vout (amplitude) when vin is 0 V = _______________
c) Observe the output voltage using oscilloscope and trace the waveform on Figure 4.3.

Figure 4.3
d) Reverse the direction of diode in Figure 4.1 as shown in figure 4.4.
25
Figure 4.4
e) Sketch the expected output waveform for vout on Figure 4.5. In particular find vout when
the applied signal is at its positive and negative peak and zero volts.

Figure 4.5
(Calculated) vout (amplitude) when vin is at +ve peak = _______________
(Calculated) vout (amplitude) when vin is at –ve peak = _______________
(Calculated) vout (amplitude) when vin is 0 V = _______________
f) Observe the output voltage using oscilloscope and trace the waveform on Figure 4.6.

Figure 4.6
26
g) Replace the diode in Figure 4.4 with a 6.8 V zener diode and sketch the expected
output waveform in Figure 4.7.

Figure 4.7
h) Sketch the observed output waveform in Figure 4.8.

Figure 4.8
PART 3: Biased single limiter
a) Construct the biased single limiter circuit of Figure 4.9. Give an input voltage of
any amplitude at least greater than VO (or give 8 Vp-p at a frequency of 1000 Hz).
Figure 4.9 Biased single limiter
27

b) Sketch the expected output waveform for vout on Figure 4.10.

Figure 4.10
c) Observe the output voltage using oscilloscope and trace the waveform on Figure
4.11.

Figure 4.11
28
PART 4: Double limiter
a) Construct the double limiter circuit of Figure 4.12. Give a sinusoidal input voltage
of amplitude at least greater than VO (or give the sinusoidal input of 8 Vp-p at a
frequency of 1000 Hz).
Figure 4.12 Double limiter

b) Sketch the expected output waveform for vout on Figure 4.13.

Figure 4.13
29
c) Observe the output voltage using oscilloscope and trace the waveform on Figure
4.14.

Vout in X-Y mode
Figure 4.14
POST LAB:
a) How does the waveform of Figure 4.2 compare with the expected result of Figure
4.3?
b) How does the waveform of Figure 4.4 compare with the expected result of Figure
4.4?
c) How does the waveform of Figure 4.9 compare with the expected result of Figure
4.9?
d) How does the waveform of Figure 4.12 compare with the expected result of Figure
4.12?
30
EXPERIMENT 5
CLAMPING CIRCUITS
OBJECTIVE:
● To become familiar with the function and operation of clampers/ dc restorer
circuits
EQUIPMENT:
INSTRUMENTS
● DMM
COMPONENTS
● Resistors: 100 Ω, 1 kΩ, 100 kΩ
● Diode: 1N4007
● Capacitor: 1μf (2)
THEORY:
Clampers are designed to clamp an alternating signal to a specific level without
altering the peak-to-peak characteristics of the waveform. The best approach to the analysis
of clampers is to use a step-by-step approach. The first step should be an examination of
the network for that part of the input signal that forward biases the diode. With the diode
forward biased the voltage across the capacitor and across the output terminals can be
determined. For the rest of the analysis it is then assumed that the capacitor will hold on to
the charge and voltage level established during this interval of the input signal. The next
part of the input signal can then be analyzed to determine the effect of the stored voltage
across the capacitor and the open-circuit state of the diode.
The analysis of a clamper can be quickly checked by simply noting whether the
peak-to-peak voltage of the output signal is same as the peak-to-peak voltage of the applied
signal. This check is not sufficient to be sure the entire analysis was correct but it is a
characteristic of clampers that must be satisfied.
A voltage doubler is composed of two sections in cascade, a clamp and a peak
rectifier. When excited by a sinusoid the clamping section provides a clamped signal with
one peak clamped to zero volts, and other peak at twice the maximum amplitude. In
response the peak detector section provides a voltage of double the magnitude of input
sinusoid. Because the output voltage is double the input peak the circuit is called a voltage
doubler.
PROCEDURE:
Determine the cut-in-voltage for the diode using DMM. Or assume VO = 0.7 V.
VO = ________________
PART 2:
31
Figure 5.1 Clamping circuit

b) Set the input voltage equal to square wave of arbitrary levels i.e. –3 V and +2 V and
1 kHz.
c) Using the value of VO from Part-1, calculate VC and Vout for the interval of Vin that
causes the diode to be in the ON state.
(Calculated) VC = _________________
(Calculated) Vout = _________________
d) Using the results of Part 2(c), calculate the level of Vout after Vin switches to the other
level and turns diode OFF.
(Calculated) Vout = _________________
e) Using the results of Parts 2(c) and 2(d) sketch the expected waveform for Vout in
Figure 5.2 for one full cycle of Vin.

Figure 5.2
f) Use the oscilloscope to view output waveform Vout. Record the resulting waveform
in Figure 5.3.
32

Figure 5.3
g) Reverse the diode of Figure 5.1. Determine the levels of VC and Vout for the interval
of Vin that causes the diode to be in the ON state.
(Calculated) VC = _________________
(Calculated) Vout = _________________
h) Using the results of Part 2(g) calculate the level of Vout after Vin switches to the other
level and turns diode OFF.
(Calculated) Vout = _________________
i) Using the results of Parts 2(g) and 2(h) sketch the expected waveform for Vout on
Figure 5.4.

Figure 5.4
j) Using oscilloscope view output waveform Vout. Record the resulting waveform in
Figure 5.5.
33

Figure 5.5
PART 3: Effect of R
a) Determine the time constant (τ=RC) for the network of Figure 5.1 for the interval of
the input signal that causes the diode to assume the OFF state and be approximated
by an open circuit.
(Calculated) τ = _____________
b) Calculate the period of the applied signal and then determine half the period to
correspond with the time interval that the diode is in the OFF state during the first
cycle of the applied signal.
(Calculated) T = ___________
(Calculated) T/2 = ___________
c) The discharge period of an RC network is about 5τ. Calculate the time interval
established by 5τ using the result of Part 3(a) and compare to T/2 calculated in Part
3(b).
(Calculated) 5τ = _____________
d) Change R to 1 kΩ and calculate the new value of 5τ.

(Calculated) 5τ = _____________
e) How does the 5τ calculated in Part 5(d) compare to T/2 of the applied signal? How
would you expect the new value of R to affect the output waveform Vout?
f) For R=1 kΩ in Figure 5.1 give sinusoidal input. Record the output waveform on
Figure 5.6. Use waveform using DC position on oscilloscope.
34
Figure 5.6
g) Switch the input to square wave signal and observe the output. Record it in Figure
5.7.
Figure 5.7
h) Change R to 100 Ω and calculate the new value of 5τ.

(Calculated) 5τ = ____________
i) How does the 5τ calculated in the previous part compare to T/2 of the applied signal?
What effect will the lower value of R have on the waveform?
j) For R=100 Ω in Figure 5.1 and give sinusoidal input. Record the output waveform
on Figure 5.8. Observe waveform using DC position on oscilloscope.
35
Figure 5.8
k) Switch to square wave signal and record the observation in Figure 5.9.
Figure 5.9
PART 4: Voltage Doubler
Figure 5.10 Voltage doubler
b) Give a sinusoidal input of 8 Vp-p at f =1 kHz.

c) Draw the expected output voltage on Figure 5.11.
36
Figure 5.11
d) View vout on oscilloscope and trace the result on Figure 5.12.
Figure 5.12
POST LAB:
a) How will you compare the waveform of Figure 5.3 with the expected waveform of
Figure 5.2?
b) How will you compare the waveform of Figure 5.5 with the expected waveform of
Figure 5.4?
c) Thinking back to the clampers analyzed in this experiment why is it important for the
time interval specified by 5τ to be much larger than T/2 of the applied signal?
d) Comment on the resulting waveform of Figure 5.6 and 5.7. Is it distorted as you
expected it to appear? Why?
e) Comment on the resulting waveform of Figure 5.8 and 5.9. Compare it to the
waveforms for R= 100 kΩ and R = 1 kΩ?
f) Based on results of part 3 establish a relationship between 5τ and the period of the
waveform (T) that will ensure that the output waveform has the same characteristics
as the input. Note that the relation is between 5τ and T and not T/2.
g) Explain the behavior of the circuit shown in figure 5.10?
37
EXPERIMENT 6
REGULATED DC POWER SUPPLIES USING ZENER DIODE

OBJECTIVE:
● To design a regulated DC power supply using a zener shunt regulator
● To learn to use a three terminal IC voltage regulator
● To compare its characteristics with that of the zener shunt regulator.
EQUIPMENT:
INSTRUMENTS
● DMM
● DC Power Supply
COMPONENTS
● Resistors: 1k Ω
● Variable= 50k Ω
● Zener diode: 6.8V
● IC LM7805 (5V)
THEORY:
The schematic diagram of a zener shunt regulator is depicted in circuit diagram of figure
6.1. The unregulated power supply input Vs to the shunt regulator is obtained from a diode
bridge rectifier with filter capacitor. The zener diode employed in the circuit should have
a breakdown voltage that is a few volts higher than the lowest value Vsmin of the input
voltage Vs. The zener diode thus operates in the reverse breakdown region, and the voltage
Vo across it (the load voltage) is held fairly constant despite the fairly large voltage swing
of the input signal Vs.
Figure 6.1 Zener shunt regulator
The zener diode can be modeled as a voltage source VZo in series with a dynamic resistance
rz. Replacing the zener diode by this model, analysis of the circuit of Figure 6.2 below
yields the following expression for the output voltage Vo of the regulator:
38
Figure 6.2 Model for replacement of zener diode
𝑅 𝑧 𝑟
𝑉𝑜 = 𝑉𝑧𝑜 𝑅+𝑟 + 𝑉𝑠 𝑅+𝑟 − 𝐼𝐿 (𝑅 ∥ 𝑟𝑧 ) ( Eq 6.1)
𝑧 𝑧
LINE REGULATION
Line regulation means to observe change in output voltage while input voltage is varying
with no load. The line regulation of a voltage regulator is the ratio of the output voltage
ripple to the input voltage ripple. We have
∆𝑉𝑜 𝑟𝑧
𝐿𝑖𝑛𝑒 𝑟𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 = = 𝑅+𝑟 (Eq 6.2)
∆𝑉𝑠 𝑧
LOAD REGULATION
The load regulation means finding change in output voltage while input is fixed but load is
varying. The load regulation of a voltage regulator is the ratio of the change in output
voltage to the load current change that caused it. We have
∆𝑉𝑜
𝐿𝑜𝑎𝑑 𝑟𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 = = −(𝑟𝑧 ∥ 𝑅) ( Eq 6.3)
∆𝐼𝐿
The lower the line or load regulation, the better the voltage regulator. Note that increasing
the value of the resistor R lowers the line regulation. There is, however, a limit on how
large R can be. If R is too large the zener diode can come out of the breakdown and the
regulator will not work as intended. The value of R should be such that the zener diode
remains in breakdown even when the supply voltage is at its lowest i.e., when Vs = Vsmin.
Let IZmin be the minimum value of zener current IZ that will be tolerated. The value of IZmin
chosen should lie in the reverse breakdown region of the diode characteristic. Let ILmax be
the highest possible load current IL. To maintain the minimum zener current IZmin, we select
R as follows:
𝑉𝑆𝑚𝑖𝑛 −𝑉𝑍𝑜 −𝐼𝑍𝑚𝑖𝑛 𝑟𝑧

𝑅= (Eq 6.4)
𝐼𝑍𝑚𝑖𝑛 +𝐼𝐿𝑚𝑎𝑥
39
THREE TERMINAL VOLTAGE REGULATORS

The LM78XX is a series of three terminal IC voltage regulators that delivers positive
output voltages. The XX denotes the output voltage for example the LM7805 is a 5V
regulator chip. These IC voltage regulators have internal current limiting and other safety
features, and have characteristics that are far superior to zener shunt regulators. The three
terminals of the regulator are the input, ground, and output terminals. A three terminal
regulator can be substituted in place of the resistor R and the zener diode in the circuit of
Figure 6.1. The input terminal of the regulator connects to the unregulated power supply,
the output terminal to the load, and the ground terminal forms the common node.
PRE LAB:
1. Assume that the full-wave rectifier with capacitor filter that you designed in
experiment 4 is the input to a zener shunt regulator. Use the zener diode 6.8V
for your shunt regulator. The regulator should supply 6.8V to a load that has a
minimum resistance of 1KΩ. Choose an appropriate value for the zener series
resistor. Show all your design work and state any assumptions.
2. Determine the theoretical values for the line regulation and load regulation of your
regulator.
Note: The following are the specifications of the zener diode
Vz = 6.8V, IZmax = 5mA Use the zener resistance rz = 20Ω and IZK = 0.2mA to calculate
the value of Vzo for the zener diode model.
PROCEDURE:
PART 1:
LINE REGULATION
1. Connect the circuit as given below in figure 6.3.
Figure 6.3 Line regulation
3. Recode the values in the following Table 6.1. and Table 6.2:
TABLE 6.1
40
VS 5 6 6.5 7 7.5 8 8.5 9 9.5 10
Vout
VS 10.5 11 11.5 12 13 14 15 16 17 18
Vout
TABLE 6.2
VS 6 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 8.4

IZ
VS 8.8 9 9.5 10 10.5 11 11.5 12 13 14
IZ
3. Find the VZK =__________ (knee voltage) from the above readings
4. Find IZK = ________ (knee current) from the above readings.
5. Now find rZ = ∆Vout/∆IZ = ________________
6. Find Line regulation = ∆Vout/∆Vs
LOAD REGULATION
1. Connect circuit given in figure 6.4.
Figure 6.4 Load regulation

2. Record the values in following Table 6.3.
TABLE 6.3
41
RL 1K 5K 10K 20K 30K 40K 50K

VOUT
IL
3. Find Load regulation = ∆Vout/∆IL
PART 2:
LINE REGULATION
1. Replace the zener diode with one LM7805 voltage regulator IC in figure 6.3.
2. Pin configuration of LM7805 is given below in Figure 6.5.
Figure 6.5 Pin configuration of LM7805
3. Repeat Line Regulation for IC and record in following Table 6.4 and Table 6.5.
TABLE 6.4
VS 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11
Vout
VS 12 13 14 15 16 17 18 19 20
Vout
TABLE 6.5
V
6 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 8.4 8.8 9 9.5 10
S
IZ
4. Find the VZK =__________ (knee voltage) from the above readings,
5. Now find rZ = ∆Vout/∆IZ = ________________
42
6. Find Line regulation = ∆Vout/∆Vs =___________________
LOAD REGULATION
1. Replace the zener diode with one LM7805 voltage regulator IC in figure 6.4.
1. Repeat load regulation for IC and record the values in following Table 6.6.
TABLE 6.6
RL 1K 5K 10K 20K 30K 40K 50K

VOUT
IL
3. Find Load regulation = ∆Vout/∆IL
POST LAB:
a) Replace the zener diode in Figure 6.1 by its circuit model and derive Eq 6.1.
b) Draw characteristics for zener regulator and regulator IC (LM7805) separately
c) Find rz from graph for both cases.
d) Eq 6.4 specifies the value of the series resistor R. Explain how this equation is
obtained.
43
EXPERIMENT 7
DESIGN OF DC POWER SUPPLY

PROBLEM STATEMENT
Design a 6.8 V DC Power Supply with a AC Sinusoidal Voltage Source. The
Zener Diode is specified to have 𝑉𝑧 = 6.8 V 𝐼𝑧 = 5 𝑚𝐴 ,𝑟𝑧 = 20 Ω and 𝐼𝑧𝑘 =
0.2 𝑚𝐴.
● Draw the Circuit of Power Supply SLO 4.1

● Find the unknowns in the circuit. SLO 4.2
o Input Supply Voltage
o Resistor Value before Diode (if required)
o Average and RMS DC Voltage after Rectification
o Resistor Value if placed after rectification for step down
● Implement the circuit SLO 4.3
● Measure the Voltages and Current and write in the form of a table. SLO 4.4
● Compare the measured values with theoretical values and find the % error.
SLO 4.5
● Find and discuss limitations of the design Circuits SLO 4.6
o Load Regulation
o Line Regulation
o Minimum Value of RL for which diode still operates in breakdown region.
44
EXPERIMENT 8
BJT CHARACTERISTICS
OBJECTIVE:
● To observe the collector characteristics of BJT
EQUIPMENT:
INSTRUMETS
● DMM
COMPONENTS
● Resistors: 1 kΩ, 330 kΩ
● Variable Resistors: 5 kΩ, 1 MΩ
● Transistor: 2N3904 or equivalent
THEORY:
The BJT consists of three semiconductor regions: emitter (n-type), base (p-type),
and collector (n-type). Such a transistor is called an npn transistor. Another transistor, a
dual of the npn has a p-type emitter, an n-type base and a p-type collector and is
appropriately called a pnp transistor.
The transistor consists of two pn junctions, the emitter-base junction (EBJ) and the
collector-base junction (CBJ). Different modes of operation of the BJT are obtained
depending on the bias condition (forward or reverse) of each of these junctions.
The relationships between the voltages and the currents associated with a bipolar
junction transistor under various operating conditions determine its performance. These
relationships are collectively known as the characteristics of the transistor. These
characteristics are mentioned in the data sheet of the transistor given by the manufacturer.
It is one of the objectives of this laboratory experiment to experimentally measure these
characteristics and to compare them to their published values.
PROCEDURE:
b) Set the voltage VRB to 3.3 V by varying the 1 MΩ variable resistor. This adjustment
will set IB = VRB/RB to 10 μA as indicated in Table-1.
c) Then adjust VCE to 2 V by varying the 5 kΩ variable resistor as required by the first
reading of Table 8.1.
d) Measure the voltages VRC and VBE and record in Table 8.1.
45
Figure 8.1 To observe characteristics of BJT
e) Vary the 5 kΩ variable resistor to increase VCE from 2 V to the values appearing in
Table 8.1. Note that IB is maintained at 10 μA for a range of VCE levels.
f) For each value of VCE, measure and record VRC and VBE.
g) Repeat steps (b) through (f) for all values of VRB indicated in Table 8.1. Each VRB
will establish a different level of IB for the sequence of VCE values.
h) After all data have been obtained, compute the values of IC from IC=VRC/RC and IE
from IE=IC+IB. Use the measured resistor value for RC.
i) For each line of Table 8.1 calculate the corresponding levels of α and β using α=IC/IE
and β=IC/IB and complete the Table 8.1.
46
Table 8.1
RC (measured) =
VRB IB VCE VRC IC VBE IE

α β
(V) (μA) (V) (V) (mA) (V) (mA)
(calc) (calc)
(meas) (calc) (meas) (meas) (calc) (meas) (calc)
2
4
6
3.3 10 8
10
12
14
16
2
4
6
6.6 20 8
10
12
14
2
4
9.9 30 6
8
10
2
4
13.2 40
6
8
2
16.5 50 4
6
POST LAB:
47
1) Using data of Table 8.1, plot the collector characteristics of the transistor on graph
paper. This will be the plot of IC versus VCE for the various values of IB. Choose an
appropriate scale for IC and label each IB curve. VCE should be along x-axis and IC
should be along y-axis. You would get 5 curves for five different values of IB.
Extrapolate the graphs to meet the Origin.
Answer these questions by looking at the values from the table and from the graph:
a) Is there a significant variation in α and β from one region of characteristics to

another?
b) In which regions are the largest values of β found? Specify using the relative levels
of VCE and IC.
c) In which region are the smallest values of β found? Specify using the relative levels
of VCE and IC.
d) Find the largest and smallest levels of β and mark their locations on the graph paper
using notation βmax and βmin.
e) In general, did β increase or decrease with increase in IC?
f) In general, did β increase or decrease with increase in VCE?
2) Use a second graph paper to plot the VBE vs IB characteristics. Take VBE on the x-axis
and IB on the y-axis. Explain what the resulting curve means.
3) Use another graph paper to plot the VCE vs VBE characteristics. Take VBE along x-axis
and VCE along y-axis. Explain what the resulting curve means.
48
EXPERIMENT 9
VOLTAGE DIVIDER AND COLLECTOR FEEDBACK BIAS

OBJECTIVE:
● To determine the quiescent operating conditions of the voltage divider and collector
feedback bias BJT configurations
EQUIPMENT:
INSTRUMENTS
● DMM
COMPONENTS
● Resistors: 680 Ω, 1.8 kΩ, 2.2 kΩ (2), 3.3 kΩ, 6.8 kΩ, 33 kΩ, 390 kΩ, 1MΩ
● Transistors: C828, 2N3904
THEORY:
Bipolar transistors operate in three modes: cutoff, saturation and active. In each of
these modes, the physical characteristics of the transistor and the external circuit connected
to it uniquely specify the operating point of the transistor. In the cutoff mode, there is only
a small amount of reverse current from emitter to collector, making the devise an open
switch. In the saturation mode there is a maximum current flow from collector to emitter,
making the device a closed switch. The amount of this current depends upon the external
circuit connected to the transistor. Both of these modes are used in digital circuits.
Active region of the transistor characteristics is employed for amplification with
minimum distortion. A DC voltage is applied to the transistor, forward biasing the base-
emitter junction and reverse biasing the base-collector junction, typically establishing a
quiescent point near or at the center of the linear region.
In this experiment we will investigate two biasing networks: voltage divider bias
and collector feedback bias configuration.
VOLTAGE DIVIDER BIAS
The voltage-divider bias circuit employs a feedback arrangement that makes the
base-emitter and collector-emitter voltages primarily dependent on the external circuit
elements and not the beta of the transistor. Thus, even though the beta of the individual
transistors may vary considerably, the location of the Q-point on the load line will remain
essentially fixed.
COLLECTOR FEEDBACK BIAS
In collector feedback bias circuit the base resistor is connected to the collector
terminal of the transistor and not to fixed supply voltage Vcc. Thus the voltage across the
base resistance of the collector feedback configuration is a function of the collector voltage
and in turn to collector current. In particular this circuit demonstrates the principal of
negative feedback, in which the tendency of an output variable to increase or decrease will
result in a decrease or increase in the input variable respectively. For instance, if Ic
increases, Vc will reduce which will lower the level of IB, thus offsetting the increase of Ic.
The result is a design less sensitive to variations in its parameters.
49
PROCEDURE:
PART 1: Determining β
a) Construct the circuit of Figure 9.1 using 2N3904 transistor. Insert the measured
resistance values.
Figure 9.1 To determine β

RB(meas) =__________
RC(meas) =__________
RE(meas) =__________
b) Measure the voltages VB and VRC.
(Measured) VB = _________
(Measured) VRC = _________
c) Using the measured resistor values calculate the resulting base current,
IB = VRB / RB = (VCC – VB) / RB = _________
The voltage VRB was not measured directly for determining IB because of the loading
effect of the meter across the high resistance of RB.
d) Also calculate the collector current,

IC = VRC / RC = _________
e) Calculate β (=IC/IB) of the transistor and use this value for all the calculations in this
experiment.
β (3904) = ___________
50
f) Replace 2N3904 in the circuit of Figure 9.1 by C828 transistor. Repeat the above
steps to find β of this transistor.
(Measured) VB = _________
(Measured) VRC = _________
IB = _________
IC = _________
β (C828) = _________
PART 2: Voltage divider configuration
a) Construct the circuit of Figure 9.2 using 2N3904 transistor.
Figure 9.2 Voltage divider configuration
b) Record the measured value of each resistor.

R1meas = ___________
R2meas = ___________
RCmeas = ___________
REmeas = ___________
c) Using value of β determined in Part 1 for both transistors, calculate the theoretical
values of VB, VE, VC, VCE, IE, IC, and IB for the circuit of Figure 9.2 and record in
Table 9.1.
51
d) Measure VB, VE, VC and VCE and record in Table 9.2. Calculate currents IE and IC.
Also measure voltages VR1 and VR2 and calculate currents I1 and I2 (I1=VR1/R1 and
I2=VR2/R2) using measured resistor values. Calculate the current IB using Kirchhoff’s
current law (IB=I1-I2). Insert the calculated current levels for IE, IC and IB in Table
9.2.
e) Replace the 2N3904 transistor in your circuit of Figure 9.2 with C828 transistor.
Measure the voltages VB, VE, VCE, VRC, VR1 and VR2. Also calculate IC, IE I1, I2 and
determine IB using measured values of resistors. Record all the values in Table 9.2.
f) Calculate the percentage change in β, IC, VCE and IB from the data in Table 9.2 and
record your results in Table 9.3. Use following equations for your calculations:
%∆ β = x 100% %∆ Ic = x 100%
%∆ VCE = x 100% %∆ IB = x 100%
Table 9.1
Theoretical Calculated Values

VC VE
Transistor VB VCE IB IC IE
(volts (volts
Type (volts) (volts) (μA) (mA) (mA)
) )
2N3904
C828
Table 9.2
Measured Values Calc from measured values

Transistor VB VC VE VCE IB IC
IE (mA)
Type (volts) (volts) (volts) (volts) (μA) (mA)
2N3904
C828
Table 9.3
(Note: The calculations in Table 9.3 are for data in between the two rows of Table 9.2)
%∆β % ∆ IC % ∆ VCE % ∆ IB
52
PART 3: Collector feedback configuration
Figure 9.3 Collector feedback configuration
Record the measured value of each resistor.

RBmeas = ___________
RCmeas = ___________
b) Using value of β determined in Part 1 for both transistors, calculate the theoretical
values of IB, IC, VB, VC and VCE and record in Table 9.4.
c) Measure VB, VC and VCE and record in Table 9.5. Also calculate currents IB and IC
using measured resistance values and record in Table 9.4.
d) Replace the 2N3904 transistor in your circuit of Figure 9.3 with C828 transistor.
Measure the voltages VB, VC and VCE and insert in Table 9.5. Also calculate the
currents IB and IC using measured values of resistors. Insert the values of currents in
Table 9.5.
e) Calculate the percent change in β, IC, VCE and IB from the data in Table 9.4 and record
your results in Table 9.5. Use following equations for your calculations. Record your
results in Table 9.6
%∆ β = x 100% %∆ Ic = x 100%
53
%∆ VCE = x 100% %∆ IB = x 100%
Table 9.4
Transistor
VB VC VCE IB IC
Type
2N3904
C828
Table 9.5
Transistor VB VC VCE
IB (μA) IC (mA)
Type (volts) (volts) (volts)
2N3904
C828
Table 9.6
(Note: The calculations in Table-6 are for data in between the two rows of Table 9.5)
%∆β % ∆ IC % ∆ VCE % ∆ IB
PART 4: Collector Feedback Configuration (with RE)
54
Figure 9.4 Collector feedback configuration
Record the measured value of each resistor.

RBmeas = ___________
RCmeas = ___________
REmeas = ___________
b) Using value of β determined in Part 1 for both transistors, calculate the theoretical
values of IB, IC, IE, VB, VC and VCE and record in Table 9.7.
c) Measure VB, VC, VE and VCE and record in Table-8. Also calculate currents IB, IC and
IE using measured resistance values and record in Table 9.8.
d) Replace the 2N3904 transistor in your circuit of Figure 9.4 with C828 transistor.
Measure the voltages VB, VC, VE and VCE and insert in Table 9.8. Also calculate the
currents IB, IC and IE using measured values of resistors. Insert the current values in
Table 9.8.
e) Calculate the percent change in β, IC, VCE and IB from the data in Table 9.8 and record
your results in Table 9.9. Use following equations for your calculations.
%∆ β = x 100% %∆ Ic = x 100%
55
%∆ VCE = x 100% %∆ IB = x 100%
Table 9.7
Transistor
VB VC VCE IB IC
Type
2N3904
C828
Table 9.8
Transistor VB VC VE VCE
IB (μA) IC (mA) IE (mA)
Type (volts) (volts) (volts) (volts)
2N3904
C828
Table 9.9
(Note: The calculations in Table-9 are for data in between the two rows of Table 9.8)
%∆β % ∆ IC % ∆ VCE % ∆ IB
56
POST LAB:
a) For the three configurations investigated in this experiment, how does the Q point
location (defined by IC and VCE) change when the 2N3904 transistor was replaced
by C828?
b) Which configuration appears to have the better stability factor?
c) How do the calculated and measured values of Table 9.1 and Table 9.2 compare for
C828 transistor?
d) How do the calculated and measured values of Table 9.3 and Table 9.4 compare for
C828 transistor?
e) How do the calculated and measured values of Table 9.4 and Table 9.5 compare for
2N3904 transistor?
f) How do the calculated and measured values of Table 9.7 and Table 9.8 compare for
2N3904 transistor?
g) How do the calculated and measured values of Table 9.7 and Table 9.8 compare for
C828 transistor?
57
EXPERIMENT 10
COMMON EMITTER AMPLIFIER

OBJECTIVE:
● The objective is to measure the ac and dc voltages in a common-emitter amplifier
● To obtain measured values of voltage amplification (Av), input resistance (Ri) and
output resistance (Ro) for loaded and unloaded operation
EQUIPMENT:
INSTRUMENTS
● Oscilloscope
● DMM
● Function Generator
COMPONENTS
● Resistors: 1 kΩ (2), 3.3 kΩ (2), 12 kΩ, 56 kΩ
● Capacitors: 10 μF (2), 100μF
THEORY:
The common emitter amplifier configuration provides large voltage gain (typically
tens to hundreds) and provides moderate input and output resistance. The ac signal voltage
gain is defined as
Av = Vo/Vin ( Eq 10.1)
The input resistance, Ri is the resistance of the amplifier as seen by the input signal.
The output resistance, Ro is the resistance seen from load looking into the output of the
amplifier.
For the voltage divider dc bias configuration, all dc bias voltages can be
approximately determined without knowing the exact value of transistor beta. The
transistor ac dynamic resistance re, can be calculated using equation 10.2:
re = VT/IE (Eq 10.2)
AC VOLTAGE GAIN: The ac voltage gain of a common emitter amplifier (under no-
load) can be calculated using equation 10.3:
Av = -Rc/re (Eq 10.3)
AC INPUT RESISTANCE: The ac input resistance is calculated using equation 10.4:

Ri = R1||R2||(β+1)(re) (Eq 10.4)
AC OUTPUT RESISTANCE: The ac output resistance is calculated using equation 10.5:

Ro = Rc …… (Eq 10.5)
58
PROCEDURE:
PART 1: Common-emitter dc bias

a) Construct the circuit as shown in Figure 10.1.
Figure 10.1 Common emitter dc bias

b) Record the measured values of all the resistors.
R1=_____________
R2=_____________
RC=_____________
RE=_____________
c) Calculate dc bias values of the circuit. Record calculated values below:
(Calculated) VB = ____________
(Calculated) VE = ____________
(Calculated) VC = ____________
(Calculated) IE = ____________
(Calculated) re = ____________
d) Measure the dc voltages
(Measured) VB = ____________
(Measured) VE = ____________
(Measured) VC = ____________
59
e) Calculate the dc emitter current using measured values of VE and RE

IE=VE/RE
IE = ____________
f) Calculate the ac dynamic resistance, re using IE calculated from measured values

re = VT/IE
re = ____________
PART 2: AC Voltage Gain
a) Calculate the amplifier voltage gain for a bypassed emitter using Equation 10.3.
(Calculated) Av = ____________
b) Apply an ac input signal, Vsig=10mVp at f=1 kHz. Observe and measure the ac output
voltage, Vout on the oscilloscope.
(Measured) Vout = ____________
c) Calculate the circuit no-load voltage gain using measured values.

Av =Vout/Vsig
(Measured) Av = ____________
d) Using the oscilloscope observe and record input waveform, Vsig and output voltage
waveform, Vout in Figure 10.2
Figure 10.2
60
PART 3: AC Input Resistance
a) Calculate Ri using Equation 10.4.

(Calculated) Ri = ___________
b) To measure RI connect an input measurement resistor, Rx=1 kΩ as shown in Figure

10.3. Apply input voltage Vsig = 10 m𝑉𝑝−𝑝 and measure Vin for an undistorted output.
Figure 10.3 AC input resistance
c) Solving for Vin using
we get,
(Measured) Ri = _____________
PART 4: AC Output Resistance
a) Calculate Ro using Equation 10.5.

(Calculated) Ro = ____________
b) Remove input measurement resistor, Rx. For input of Vsig,p-p=20mV, measure the
output voltage, Vout.
(Measured, unloaded output voltage) Vout = ____________
c) Now connect load RL=3.3 kΩ and measure Vout.
61
(Measured, loaded output voltage) VL = ____________
d) The output resistance can be obtained from
for which
Ro = __________
62
EXPERIMENT 11
EMITTER FOLLOWER AMPLIFIER

OBJECTIVE:
● To measure the dc and ac voltages in emitter follower (common-collector) amplifier
● To measure the values of voltage amplification (Av), input resistance (Ri) and
output resistance (Ro)
EQUIPMENT:
INSTRUMENTS:
● Oscilloscope
● DMM
● Function Generator
COMPONENTS:
● Resistors: 120 Ω, 1 kΩ, 12 kΩ, 33 kΩ, 100 kΩ
● Capacitors: 10 μF (2)
THEORY:
The main purpose of the common-collector (CC) or emitter follower (EF) amplifier
is to connect a source having a large resistance Rs to a load with a relatively low resistance.
It provides nearly unity voltage gain, high input and low output resistance.
AC VOLTAGE GAIN: The ac voltage gain of a CC amplifier can be calculated using eq.
11.1.
( Eq 11.1)
AC INPUT IMPEDANCE: The ac input resistance is given in eq. 11.2.
Ri = R1 || R2 || ( β+1 ) [re + (ro || RL)] (Eq 11.2)
AC OUTPUT RESISTANCE: The ac output resistance is in eq. 11.3.
Ro = re (Eq 11.3)
ignoring the source resistance.
63
PROCEDURE:
PART 1: DC Bias
a) Calculate dc bias values for the EF circuit of Figure 11.1 and record below.
Figure 11.1 DC bias
(Calculated) VB = ____________
(Calculated) VE = ____________
(Calculated) VC = ____________
(Calculated) IE = ____________
b) Calculate re using re=VT/IE (Eq 11.4)

(Calculated) re = ____________
c) Connect the circuit of Figure 11.1. Set Vcc = +10 V. Measure the dc bias of the circuit
measuring values of
(Measured) VB = ____________
(Measured) VE = ____________
(Measured) VC = ____________
64
d) Determine the dc emitter current using measured values of VE and RE

IE = VE/RE
IE = ____________
e) Determine the ac dynamic resistance, re using IE calculated from measured values
re = ____________
f) Compare the dc voltages, current IE and dynamic resistance re calculated in step-a,
with the values obtained in step-b.
PART 2: AC Voltage Gain

a) Calculate the ac voltage gain of the CE amplifier in Figure 11.1 using Equation 11.1.
(Calculated) Av = ____________
b) Apply an ac input signal, Vsig = 1Vp and frequency =1k. Measure the resulting ac
output voltage, Vout.
(Measured) Vout = ____________
c) Determine the circuit ac voltage gain using the following equation:
Av = Vout/Vsig
(Measured)Av = ____________
d) Compare the voltage gain calculated in step-a, with that measured in step-b.
e) Using the oscilloscope observe and record input waveform, Vsig and output voltage
waveform, Vout in Figure 11.2
Figure 11.2
PART 3: Input Resistance, Ri
a) Obtain the ac input resistance of the EF amplifier in Figure 11.1 using Equation 11.2.
(Calculated) Ri = ____________
65
b) To measure Ri connect input measurement resistor, Rx = 100 kΩ as shown in Figure

11.3. Apply input voltage Vsig = 1Vp and measure Vin for an undistorted output.
Figure 11.3 To measure input resistance
(Measured) Vin = ____________

c) Determine Ri using
we get,
(Measured) Ri = ____________
Remove resistor Rx.
d) Compare the ac input resistance calculated in step-a with that measured in step-b.
PART 4: Output Resistance, Ro
a) Determine the ac output resistance of the CC amplifier using Equation 11.3.

(Calculated) Ro = ____________
b) For an input of Vsig= 0.1 Vp at frequency, f =1 kHz measure the output voltage,
Vout when no load is connected.
(Measured, unloaded) Vout = ____________
c) Now connect load RL=120 Ω and measure VL

(Measured, loaded) VL = ____________
66
d) The output resistance can be determined from
for which
Ro = ____________
e) Compare the CC output impedance calculated in step-(a) from that measured in step-
(b).
EXPERIMENT 12
67
DESIGN OF BJT AMPLIFIER

PROBLEM STATEMENT
Design the bias network of a common emitter amplifier to establish a current
𝐼𝐸 = 1𝑚𝐴 using a power supply of 𝑉𝑐𝑐 = 12 𝑉. The thermal voltage VT at room
temperature is 25𝑚𝑉.Find the experimental value 𝛽 of the given transistor if β is used in
calculations. . Input Voltage Signal which is to be amplified is 20 mV Peak to Peak at 1
KHz.
1. Draw the circuit of CE amplifier with Emitter Resistance and Bypass Capacitor.
SLO 4.1
2. Find all the unknown parameters in the drawn circuit. SLO 4.2
3. Implement the circuit on Bread board. SLO 4.3
o Check Breadboard connections
o DMM and Oscilloscope knowledge
4. Measure all dc voltages and currents which were calculated in (2). Compare the
measured with theoretical values and find % error. Show all your measurements in
the form of a table. SLO 4.4
5. Find the below parameters both from theoretical and measured values. Explain the
behavior of amplifier in terms of the results obtained. SLO 4.5
o 𝑟𝑒 , 𝐴𝑣 , 𝑅𝑖𝑛 , 𝑅𝑜
6. Find the Maximum Input Voltage Swing which can be applied at base. How can
we improve the gain and input resistance of the amplifier? SLO 4.6
EXPERIMENT 13
68
MOSFET TRANSISTOR CHARACTERISTICS

OBJECTIVE:
● The objective is to familiarize with the basic regions of operation of a MOSFET
transistor
EQUIPMENT:
INSTRUMENTS:
● Dual DC Power Supply
● DMM
COMPONENTS:
● CD4007
● Resistors
THEORY
The MOSFET device is a four terminal device with connections for the drain, gate, source,
and body as shown in the symbol in Fig 13.1. However, a more common symbol used to
identify the MOSFET is shown in Fig 13.2 and is what will be used in this experiment. The
MOSFET devices used in this lab have the body internally connected to the source such
that the body terminal is not externally accessible. Shown in these figures 13.1 and 13.2
are N-channel MOSFETs.
Figure 13.1 MOSFET Figure 13.2 MOSFET
To study the MOSFET we connect two external voltage sources to the device as shown in
Figure 13.3. These provide a drain-source voltage VDS and a gate-source voltage VGS.
Figure 13.3 How to connect two external voltages to the device

The voltage VDS may cause drain-source current IDS to flow provided a path exists from
the drain to the source inside the device. This internal current path can be controlled by the
gate-source voltage VGS. For a sufficiently high VGS, an internal current path, called the
channel, is established between the drain and the source. The higher the VGS value the easier
it is to flow for the drain-source current IDS. Note that the only DC current in the MOSFET
is IDS since the gate is internally insulated from the channel.
69
By operating the MOSFET in particular bias regions, based on the VGS, VDS, and IDS values,
it can be used to perform a variety of functions. The two regions that the MOSFET device
can operate in are the ohmic (linear or triode) and saturation(active) regions. Both of these
regions will be explored in this experiment through the exploration of a few of the
MOSFET device implementations. These regions can be graphically represented. Shown
in Figure 13.4 is the MOSFET IDS / VDS curve for constant values of VGS. Notice that, the
ohmic (triode) region exists where VDS is very small and the curve is nearly linear, hence
another name for the region, the linear region. As VDS increases, the curve begins to flatten.
When VDS is equal to the saturation voltage, VD(SAT), the device enters the saturation region.
This voltage, VD(SAT), is determined by the voltage VGS of the MOSFET along with a
physical parameter of the MOSFET called the threshold voltage VT.
Figure 13.4 Characteristics curves for MOSFET
For a MOSFET, VD(SAT)=VGS–VT, and for VDS(SAT)≥VD≥0, the device is in the

ohmic(linear or triode) region of operation, and for VDS≥VD(SAT)≥0, the device is in the
saturation region of operation. The current flowing through the device in the ohmic(linear
or triode) region of operation is given by the following equation 13.1:
𝑊 1
𝐼𝐷𝑆 = 𝑢𝑜 𝐶𝑜𝑥 [(𝑉𝐺𝑆 − 𝑉𝑡 )𝑉𝐷𝑆 − 2 (𝑉𝐷𝑆 )2 ] ( Eq 13.1)
𝐿
Given the VGS and VDS values as well as the physical MOSFET sizing W/L and the physical
parameter uoCox, the current IDS can be found for the ohmic(linear or triode) region. The
W/L parameter is the width of the device divided by its length and the fabrication process
of the device determines the physical parameter uoCox. In this region of operation, the
70
MOSFET acts as a voltage controlled resistor where the value of drain-source resistance
can be found by taking the partial derivative of IDS with respect to VDS as shown below in
equation 13.2:
𝜕𝐼𝐷𝑆 𝑊 1
[𝑢𝑜 𝐶𝑜𝑥 [(𝑉𝐺𝑆 − 𝑉𝑡 )𝑉𝐷𝑆 − 2 (𝑉𝐷𝑆 )2 ]]
𝜕𝑉𝐷𝑆 𝐿
𝑊 1
= 𝑢𝑜 𝐶𝑜𝑥 ((𝑉𝐺𝑆 − 𝑉𝑡 ) − 𝑉𝐷𝑆 ) = (Eq 13.2)
𝐿 𝑟𝑜ℎ𝑚𝑖𝑐
The device can also be operated in the saturation region. This region is primarily used for
amplification of an input signal. However, amplification will be studied in subsequent
experiments; in this experiment we are limiting the discussion to DC bias conditions in the
saturation region of operation. The current 𝐼𝐷𝑆 in the saturation region of operation can be
found from the following Eq. 13.3 (for simplicity, λ is assumed to be zero):
1 𝑊
𝐼𝐷𝑆 = 𝑢𝑜 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑡 )2 ( Eq 13.3)
2 𝐿
In this region, the device acts as a voltage-controlled current source, hence its use as an
amplifier. The current source created is not ideal and is shunted by a small signal equivalent
resistance referred to as rds. The small signal resistance rds will be studied in more detail
later. For this experiment, the concern is with find the current IDS based on the values of
VGS and VDS.
Figure 13.5 Diode connected MOSFET
In the saturation region, the MOSFET can be connected to act similar to a diode. The
MOSFET is commonly called diode-connected when configured as in Figure 13.5. The
voltage across the device can be set to provide a reference voltage that may be needed in a
particular application. The equation to find the voltage across the device can be found by
solving equation 13.4 below for VGS since the VGS of the device is equal to VDS. This
equation for VMOSDIODE is shown below in Eq. 13.4:
𝐼𝐷
𝑉𝑀𝑂𝑆𝐷𝐼𝑂𝐷𝐸 = 𝑉𝑡 + √1 𝑊 ( Eq 13.4)
𝑢 𝑜 𝐶𝑜𝑥 ( )
2 𝐿
71
By diode-connecting the device, the saturation region is virtually guaranteed. Knowing the
IDS, W/L, and uoCox the voltage VMOSDIODE can be found.
In laboratory you will use the MOSFET Chip CD4007. The NMOS has
μoCox=166.67μA/V2, W/L=3 and VT = 1.2V. Assume VA =1/λ =100V.
The Pin Diagram of the CD4007 Chip is in Figure 13.6.
Figure 13.6 Pin diagram of the CD4007 chip
72
PRE LAB:
1. For the MOSFET shown in Figure 13.3, solve for the drain-source current IDS,
indicate the region of operation, and, if necessary, solve for the drain-source
resistance rohmic for the following conditions.
a) VGS = 3V ; VDS = 0.5V

b) VGS = 5V ; VDS = 0.5V
c) VGS = 2V ; VDS = 3V.
2. Desiring a MOSFET resistor with a resistance of 100kΩ, find the value of VGS
needed to create this resistor given VDS=0V.
3. For the MOSFET shown in Fig 13.7, solve for VDS=VMOSDIODE and the value of R.
(Hint: Write a KCL equation at the drain of the MOSFET and use Equations 13.3
and 13.4.)
Figure 13.7 MOSFET
PROCEDURE:
KEY POINTS:
1. You will be using CD4007 MOSFET array as in this experiment. This array
contains three NMOS and three PMOS transistors as shown in Fig 13.6.
2. The bulk (or substrates) of all NMOS transistors are connected to the VSS (pin 7)
and all PMOS substrates are connected to VDD (pin 14). When using this array pin
7 should be connected to the most negative supply voltage or to the source of the
transistor. Pin 14 is the substrate of the PMOS and must be connected to the most
positive supply voltage in the circuit.
3. CD4007 MOSFET array should not be connected to circuits with the power on
because high transient voltages may cause permanent damage. Therefore, do not
apply input signals until you have connected PIN 7 and 14; otherwise, serious
damage to the device could result.
73
4. It should be mentioned that the transistor characteristics of CD4007 could vary

considerably from chip to chip. The transistors may come from a different batch,
what can explain why the threshold voltage, the trans-conductance parameter and
the output resistance is different.
PRECAUTION: MOSFET transistors are very susceptible to breakdown due to

electrostatic discharge. It is recommended that you always ground yourself before picking
up the MOSFET chip. Do not touch any of the pins of the chip.
Note: Use jumper wires as possible as short on your board to connect the pins of the
transistors.
PART A:
a) Verify the values of the resistors that you are going to use by measuring their
resistances with a multi-meter. Make sure that all resistors are within 2% of their
marked values. This will assure that your current measurements are accurate
b) Prepare the power supply for VGS to ensure a DC voltage of +4V (before connecting
to the circuit. Prepare the other power supply for VDS to ensure a DC voltage of 0V
(before connecting to the circuit.
c) Observe the schematic shown in Fig 13.8. Notice that the numbers correspond to
the pin connections on the CD4007 chip.
d) Connect the circuit as shown in Fig 8. Measure and record the drain current IDS as
VDS is varied from 0V to +5V with VGS = 4V. Take data points in 0.2V increments
in order to have a sufficient number of values since these will be used to plot
IDS/VDS.
Figure 13.8 Numbers correspond to the pin connections

e) Repeat the above mentioned procedure in part (d) for VGS = 3V, and VGS = 2V as
shown in Table 13.1.
74
Table 13.1
IDS
VDS VGS = 2V VGS = 3V VGS = 4V
0.4
0.8
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
5
f) With VDS = 5V, determine the value of VGS in Figure 13.9 at which the current IDS
becomes negligible; assume for the purposes here that this means 5uA. This value
of VGS is close to the threshold voltage, VT, of the transistor for the MOSFET we
are working with.
Figure 13.9 To determine VGS at which IDS becomes negligible

PART B:
75
a) Connect the circuit as shown in Fig 13.9 with the ohmmeter across the drain and
source. Again, note the pin connections to the CD4007 chip. Vary VGS and notice
the change in resistance values. Measure and record the values of resistance for VGS
= 1.5V, 2V, 3V, 4V, and 5V in Table 13.2.
Table 13.2
VGS rohmic(measured)
1.5V
2V
3V
4V
5V
b) Using Equation 13.2 for the drain-source resistance rohmic for a MOSFET in the
ohmic(linear or triode) region of operation, find the resistance of the MOSFET for
the following conditions given; kn = 166.67μA/V2, W/L=3, VT = 1.2V and VDS=0.
Compare these with the values obtained above. Complete a table of results
compiling the measured and calculated values in Table 13.2 and Table 13.3.
Table 13.3
VGS rohmic(calculated)
1.5V
2V
3V
4V
5V
PART C:
a) Prepare a DC current supply to a value of 100u A to the circuit as shown in Fig
13.10. (Hint: Use the R value that you found on pre lab step 4 ). If necessary (if IDS
≠ 100 uA) vary the DC current supply IDS (by varying the Potentiometer) to 100
uA.
Figure 13.10 To measure voltage across MOSFET
76
b) Measure and record to voltage across the MOSFET and RPOT as shown Fig 13.10.
c) Now vary the DC current supply IDS (by varying the Potentiometer) to the following
values: 75 uA, and 50 uA. Measure and record the values of RPOT and VDS for each
condition in Table 13.4.
Table 13.4
IDS RPOT(measured) VDS(measured)
100uA
75uA
50uA
d) Using Equation 13.4 for the voltage of a diode-connected MOSFET, calculate the
voltages for the following conditions given in Table 13.5. Compare these values
with those obtained above. Complete a table of results compiling the measured and
calculated values.
Table 13.5
IDS RPOT(calculated) VDS(calculated)
100uA
75uA
50uA
POST LAB:
a) Using the data collected in “Part a” plot a family of curves for the three values of
VGS overlaid on the same graph. There should be one curve for each of the three
values of VGS (2V, 3V and 4V). Label each curve with the appropriate VGS values
and label approximately where the ohmic(linear or triode) and saturation regions
exist.
b) Why would it be necessary to create a resistor from a MOSFET in “part c”? Name
some advantages of doing so.
c) Why would a MOSFET be connected like a diode in “part c”? Would the voltage
set by the MOSFET be helpful in circuit design?
77
EXPERIMENT 14
DC BIASING OF MOSFET
OBJECTIVE:
● In this lab, we will be studying basic MOSFET circuits; we will design and analyze
some DC biasing circuits.
EQUIPMENT:
INSTRUMENTS
● DMM
● Dual power supply
COMPONENTS
● Resistors: 100kΩ, 10kΩ (3), 100 kΩ potentiometer
● CD4007 chip
THEORY:
THE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR
(MOSFET)
The physical configuration of MOSFET is as follow in Figure 14.1:
Figure 14.1 Physical configuration of MOSFET
The source and drain regions are a different semiconductor type than the bulk or body. In
the n MOSFET the source and drain regions are n-type, the bulk/body is p-type. In the p
MOSFET the source and drain regions are p-type, the bulk or body is n-type. Between the
source and the drain is the gate. But the gate is not directly connected to the silicon.
Between the gate and the silicon is a very thin silicon-dioxide insulator, which is at the
surface of the device.
The n MOSFET works as follows: First, assume the bulk is grounded so VB = 0. Then a
positive voltage is applied between the gate and the source, with the gate voltage larger
than the source voltage. This pulls electrons out of the source towards the surface of the
device. However, since at the surface, below the gate, there is an insulating oxide, the
electrons build up along the surface just below the gate and the oxide. This build-up of
electrons forms a conducting channel (which is actually called the ‘channel’) between the
source and drain. The electrons in the channel can then be pulled into the drain by a drain
voltage that is higher (more positive) than the source voltage.
There are two main operational modes: saturation, and linear/triode. Our basic
configuration and equation for saturation in the n MOSFET (VB = VS, VGS > Vt and VDS
>= VGS - Vt) is:
78
1 𝑊
𝐼𝐷 = 𝐾𝑛′ (𝑉𝐺𝑆 − 𝑉𝑡 )2 (1 + 𝜆. 𝑉𝐷𝑆 ) (Eq 14.1)
2 𝐿
The parameter λ is typically very small and can often be neglected. In this lab, unless said
otherwise, assume the parameter λ is zero.
Our basic equation for the linear/triode region in the n MOSFET (VB = VS, VGS > Vt and
VDS <= VGS - Vt) is:
𝑊 1
𝐼𝐷 = 𝐾𝑛′ [(𝑉𝐺𝑆 − 𝑉𝑡 )𝑉𝐷𝑆 − 2 (𝑉𝐷𝑆 )2 ] (Eq 14.2)
𝐿
The DC gate current is zero (IG = 0), the DC source current is equal to the drain current: IS
= ID
BIASING:
The common-source amplifier with a NMOS transistor is shown in Figure 14.2. The
biasing is done by fixing the gate voltage with a voltage divider and also by using a source
resistor RS. The source resistor gives negative feedback and stabilizes the bias current as a
function of temperature variations and transistor characteristics. This is a popular biasing
scheme for discrete transistor circuits. Other biasing methods are possible, such as using a
drain-to-gate feedback resistor, or using a constant-current source. The latter one is popular
in integrated circuits. We will focus on the first method, illustrated in Figure 14.2.
Figure 14.2 Common source amplifier with a NMOS transistor
BIASING: Rule of Thumb while designing a circuit

For proper biasing we can use the following rule-of-thumb. We select the source resistor
value such that the voltage VS at the source terminal is about one third to one fifth of the
power supply VDD. The resistance RD is chosen such that the drain voltage VD is about in
79
the middle of VDD and VS. These two conditions give us the resistor values of RS and RD
for a specified drain current. The gate voltage can then be easily calculated as follows.
Since the transistor is operating in the saturation region (see previous lab), we know that
the current-voltage relationship is given by,
1 𝑊
𝐼𝐷 = 𝐾′ (𝑉𝐺𝑆 − 𝑉𝑡 )2 VDS > VGS - Vt (Eq 14.3)
2 𝑛 𝐿
To obtain certain bias current ID we need to apply gate-source voltage VGS equal to
2𝐼
𝑉𝐺𝑆 = 𝑉𝑡 + √ ′ 𝐷𝑊 (Eq 14.4)
𝐾 𝑛𝐿
The corresponding gate voltage VG is then equal to
2𝐼
VG = VGS + VS = 𝑉𝑠 + 𝑉𝑡 + √ ′ 𝐷𝑊 (Eq 14.5)
𝐾 𝑛𝐿
Once the gate voltage VG is known, one can find the values of the resistor RG1 and RG2. We
choose the resistors such that the parallel resistor is relatively large to ensure a large input
resistance of the amplifier and prevent loading of the signal source Rin=RG1||RG2.
The factor (VGS-Vt) is called the saturation voltage and corresponds to the minimal drain-
source voltage required to keep the transistor in saturation. It is sometimes called the
overdrive voltage.
2𝐼
𝑉𝐺𝑆 − 𝑉𝑡 = √ ′ 𝐷𝑊 = 𝑉𝐷𝑆𝑎𝑡 (Eq 14.6)
𝐾 𝑛𝐿
PRE LAB:
Your task is to design the NMOS circuit given in Figure 14.2 with a bias current ID =
0.6mA. The source voltage VS should be 3V and the drain voltage VD should be chosen
such that it is in the middle of VS and VDD. The input resistance should be Rin larger than
15 kΩ. The NMOS transistor (CD4007 array) has the following characteristics: Vt = 1.2V
𝐾𝑛′ .W/L=0.7mA/V2
λ=0.004V-1 (note: since source-bulk terminal are shorted you won't need to use to calculate
the threshold voltage).
a) Find the value of VD.
b) Find the resistor values RS, and RD. Select values that are available in the lab.
c) Using the actual resistor value of RS find VS and VG.
d) Find the values of the resistors RG1, and RG2.
80
e) What is the total DC power dissipation in the amplifier? (Hint: power

dissipation is VDD x Itotal).
PROCEDURE:
You will be using the CD4007 MOSFET array that contains three NMOS and three
PMOS transistors as shown in figure 13.6 of previous experiment.
Note: The key point to remember when using this array is that the substrate of the NMOS
(bulk connection) is connected to pin 7 and should always be connected to the most
negative supply voltage. Pin 14 is the substrate of the PMOS and must be connected to the
most positive supply voltage in the circuit.
The goal of this experiment is to bias the transistor of Figure 14.2 according to the hand
calculations made in pre-lab. After building the circuit you will verify the biasing voltages
and currents.
PART A:
Build the circuit of Figure 14.2 (RG1 = 100kΩ, RG2 = 100kΩ variable, RS = 5KΩ(two 10kΩ
in parallel combination) and RD = 10kΩ). Use the transistor between the pins 3, 4 and 5.
Notice that we have connected the bulk (pin 7) to the source (pin 5) of the NMOS transistor.
This can be done since we are only using a single NMOS transistor in the array. For the
biasing resistor RG2 use 100kΩ potentiometer.
Measure the DC voltage at the drain. It is important is position the drain voltage VD around
9 or 10 V. Adjust the potentiometer RG2 so that VD is around 9V. After adjusting the gate
voltage, measure the gate and source voltages. Measure ID and record
VD = __________
VG = __________
VS = __________
VGS = __________
ID = __________
PART B:
CURRENT MIRRORS:
81
Figure 14.3 Current mirrors
a) Connect the circuit as given in Figure 14.3

b) Use 1 kΩ resistors for RREF and RL.
c) The measure voltage across RREF and calculate the current, IREF
d) Also measure the “output” current IO.
e) Record readings in the Table 14.1 for different values of RREF and RL.
Table 14.1
RREF 1 kΩ 500Ω
IREF IREF IREF IREF
RL IO IO
(calculated) (measured) (calculated) (measured)
1 kΩ
500Ω
0Ω
POST LAB:
Compare the results of table1 for following cases:
a) Values of IREF and IO for different values of RREF.

b) Values of IREF and IO for different values of RL.
82
Appendix A: Lab Evaluation Criteria

Labs with projects
1. Experiments and their report 50%
a. Experiment 60%
b. Lab report 40%
2. Quizzes (3-4) 15%
3. Final evaluation 35%
a. Project Implementation 60%
b. Project report and quiz 40%
Labs without projects

1. Experiments and their report 50%
a. Experiment 60%
b. Lab report 40%
2. Quizzes (3-4) 20%
3. Final Evaluation 30%
i. Experiment 60%
ii. Lab report, pre and post
experiment quiz 40%
Notice:
Copying and plagiarism of lab reports is a serious academic misconduct. First instance of
copying may entail ZERO in that experiment. Second instance of copying may be eported
to DC. This may result in awarding FAIL in the lab course.
83
Appendix B: Safety around Electricity

In all the Electrical Engineering (EE) labs, with an aim to prevent any unforeseen accidents
during conduct of lab experiments, following preventive measures and safe practices shall
be adopted:
● Remember that the voltage of the electricity and the available electrical current in
EE labs has enough power to cause death/injury by electrocution. It is around
50V/10 mA that the “cannot let go” level is reached. “The key to survival is to
decrease our exposure to energized circuits.”
● If a person touches an energized bare wire or faulty equipment while grounded,
electricity will instantly pass through the body to the ground, causing a harmful,
potentially fatal, shock.
● Each circuit must be protected by a fuse or circuit breaker that will blow or “trip”
when its safe carrying capacity is surpassed. If a fuse blows or circuit breaker trips
repeatedly while in normal use (not overloaded), check for shorts and other faults
in the line or devices. Do not resume use until the trouble is fixed.
● It is hazardous to overload electrical circuits by using extension cords and multi-
plug outlets. Use extension cords only when necessary and make sure they are
heavy enough for the job. Avoid creating an “octopus” by inserting several plugs
into a multi-plug outlet connected to a single wall outlet. Extension cords should
ONLY be used on a temporary basis in situations where fixed wiring is not feasible.
● Dimmed lights, reduced output from heaters and poor monitor pictures are all
symptoms of an overloaded circuit. Keep the total load at any one time safely below
maximum capacity.
● If wires are exposed, they may cause a shock to a person who comes into contact
with them. Cords should not be hung on nails, run over or wrapped around objects,
knotted or twisted. This may break the wire or insulation. Short circuits are usually
caused by bare wires touching due to breakdown of insulation. Electrical tape or
any other kind of tape is not adequate for insulation!
● Electrical cords should be examined visually before use for external defects such
as: Fraying (worn out) and exposed wiring, loose parts, deformed or missing parts,
damage to outer jacket or insulation, evidence of internal damage such as pinched
or crushed outer jacket. If any defects are found the electric cords should be
removed from service immediately.
● Pull the plug not the cord. Pulling the cord could break a wire, causing a short
circuit.
● Plug your heavy current consuming or any other large appliances into an outlet that
is not shared with other appliances. Do not tamper with fuses as this is a potential
fire hazard. Do not overload circuits as this may cause the wires to heat and ignite
insulation or other combustibles.
● Keep lab equipment properly cleaned and maintained.
● Ensure lamps are free from contact with flammable material. Always use lights
bulbs with the recommended wattage for your lamp and equipment.
● Be aware of the odor of burning plastic or wire.
84
● ALWAYS follow the manufacturer recommendations when using or installing new

lab equipment. Wiring installations should always be made by a licensed electrician
or other qualified person. All electrical lab equipment should have the label of a
testing laboratory.
● Be aware of missing ground prong and outlet cover, pinched wires, damaged
casings on electrical outlets.
● Inform Lab engineer / Lab assistant of any failure of safety preventive measures
and safe practices as soon you notice it. Be alert and proceed with caution at all
times in the laboratory.
● Conduct yourself in a responsible manner at all times in the EE Labs.
● Follow all written and verbal instructions carefully. If you do not understand a
direction or part of a procedure, ASK YOUR LAB ENGINEER / LAB
ASSISTANT BEFORE PROCEEDING WITH THE ACTIVITY.
● Never work alone in the laboratory. No student may work in EE Labs without the
presence of the Lab engineer / Lab assistant.
● Perform only those experiments authorized by your teacher. Carefully follow all
instructions, both written and oral. Unauthorized experiments are not allowed.
● Be prepared for your work in the EE Labs. Read all procedures thoroughly before
entering the laboratory. Never fool around in the laboratory. Horseplay, practical
jokes, and pranks are dangerous and prohibited.
● Always work in a well-ventilated area.
● Observe good housekeeping practices. Work areas should be kept clean and tidy
at all times.
● Experiments must be personally monitored at all times. Do not wander around the
room, distract other students, startle other students or interfere with the laboratory
experiments of others.
● Dress properly during a laboratory activity. Long hair, dangling jewelry, and loose
or baggy clothing are a hazard in the laboratory. Long hair must be tied back, and
dangling jewelry and baggy clothing must be secured. Shoes must completely
cover the foot.
● Know the locations and operating procedures of all safety equipment including fire
extinguisher. Know what to do if there is a fire during a lab period; “Turn off
equipment, if possible and exit EE lab immediately.”
85
Appendix C: Guidelines on Preparing Lab Reports

Each student will maintain a lab notebook for each lab course. He will write a report for
each experiment he performs in his notebook according to the following format.
LAB REPORT FORMAT
Your report must include following:
1. Introduction: Introduce area explored in the experiment.

2. Objective: What are the learning goals of the experiment?
3. Measurements: In your own words write how the experiment is performed (Do
not copy/paste the procedure).
a. Issues: Which technical issues were faced during the performance of the
experiment and how they were resolved?
b. Graphs, if any
4. Conclusions: What conclusions can be drawn from the measurements?
5. Applications: Suggest a real world application where this experiment may apply.
6. Answers to post lab questions (if any).
Sample Lab Report
Introduction
An RC circuit is a first order circuit that utilizes a capacitor as an energy storage element
whereas a resistor as an energy wastage element. RC circuits are building blocks of
electronic devices and their thorough understanding is important in comprehending
advance engineering systems such as transistors and transmission lines.
An RC circuit can be operated with both DC and AC sources. In this lab we study transient
response of RC circuits with a square wave as a DC source. During the DC operation of an
RC circuit the voltage across the capacitor or the resistor show energy storing (capacitor
charging) and dissipating (capacitor discharging via resistor) mechanisms of the circuit.
The capacitor charging or discharging curves then lead to determine time constant of the
circuit where the time constant signifies time required by the RC circuit to store or waste
energy.
Objective:
To study transient response of a series RC circuit
86
Measurements:
The circuit used for the experiment is shown in Fig. 1. Both input (a square wave) and
output (voltage across capacitor) waveforms are monitored on an oscilloscope. The
capacitor charging is observed during "on" part of the square waveform whereas the
capacitor discharging is observed during "off" part of the square waveform (Draw graphs).
We measure the time constant from the capacitor charging or discharging curve. While
keeping the capacitor value constant, we also measure time constants with various resistor
values (Table 1).
Fig.1. The circuit used in the experiment
TABLE I. Time constant as a function of the resistor values
Resistance
270 Ω 330 Ω 470 Ω 1 kΩ 2.2 kΩ 3.3 kΩ
(Nominal)
Resistance
(Measured)
Time constant
(Calculated)
Time constant
(Measured)
Capacitance
(Measured)
Issues:
Mention any issue(s) you encountered during the experiment and how they were resolved
Conclusions:
From the measurements following conclusions can be drawn:
a) The capacitor charging and discharging curves are exponential.

b) The time constant is directly proportional to the resistor value.
87
Both of the above conclusions are also easily verifiable by solving differential equation
for the RC circuit.
Applications:
An RC circuit can be employed for a camera flash. The capacitor discharges through the
flash light during a picture taking event.
Required Graphs:
Use separate graph paper for plotting all required graph.
88

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EL225-Electronic Devices and

Department of Electrical Engineering

Created by: Ms. Farrah Fayyaz, Mr. Aurangzeb

Date: August, 2005

Last Updated by: Ms. Aroosa Umair

Date: April, 2019

Approved by the HOD: Dr. S.M Sajid

Date: April, 2019

S.# Title & Description of Experiment Page #

2 Half wave Rectification 10

3 Full Wave Rectification 17

6 Regulated DC Power Supplies using Zener Diode 38

7 Design of DC Power Supply 44

9 Voltage divider and collector feedback bias 49

10 Common emitter amplifier 58

11 Emitter follower amplifier 63

12 Design of BJT Amplifier 68

13 MOSFET transistor characteristics 69

15 Appendix A: Lab Evaluation Criteria 83

16 Appendix B: Safety around electricity 84

17 Appendix C: Guidelines on preparing lab reports 86

Sr. No. Description

1 Oscilloscope 40 MHZ (CS-4135A)

2 Digital Multi-meter (Escort 3136A)

3 Function Generator 10 MHZ (EGC-3236A)

4 Digital Power Supply (Matrix MPS-3005 L-3)

I-V CHARACTERISTICS OF A DIODE

Figure 1.1 The IV Characteristics of a diode

i = Is (ev/nVT - 1) (Eq 1.1)

RDC = VD/ID ohms (Eq 1.2)

rD = Δ V / Δ I ohms (Eq 1.3)

It can be shown through differential calculus that the AC resistance of a diode in

rD= VT /ID ohms (Eq 1.4)

PART 2: Forward-bias diode characteristics

Figure 1.2 Forward bias diode characteristics

a) Construct the network of Figure 1.2.

d) Repeat step-c for the remaining values of VR in Table 1.3.

PART 3: Reverse bias

Figure 1.3 Reverse bias diode characteristics

(Calculated) RDC = ________________

d) Is the resistance level sufficiently high to be considered open circuit equivalent if

HALF WAVE RECTIFICATION

Figure 2.1Half wave rectification

PART 2: Half-wave Rectification

b) Set the input to 1000 Hz, 8 Vp-p sinusoidal volts.

Figure 2.2 Half-wave rectifier

c) Trace the input on Figure 2.3 as seen on the oscilloscope.

Vout in X-Y mode

Vout in voltage-time mode(Observed) Vout in X-Y mode

Vout in voltage-time mode(Observed) Vout in X-Y mode

Vout in voltage-time mode(Expected) Vout in X-Y mode

Vout in voltage-time mode(Observed) Vout in X-Y mode

Vout in voltage-time mode(Observed) Vout in X-Y mode

PART 4: Half-wave Rectification

a) Replace 2.2kΩ resistor with a 10uF capacitor in circuit of figure 2.2.

Vout in voltage-time mode(Observed) Vout in X-Y mode

Vout in X-Y mode

f) Also measure VDC at output using multi meter.

Vout in X-Y mode

a) How do the results of parts 2(d) and 2(e) compare?

FULL WAVE RECTIFICATION

Figure 3.1 Full wave rectification

a) Construct the full-wave bridge rectifier of Figure 3.2.