INDIAN INSTITUTE OF TECHNOLOGY, KANPUR

VLSI SYSTEM DESIGN (EEE619A)

PROJECT REPORT

DESIGN OF 4 BIT BARREL SHIFTER

SUBMITTED BY: KUMAR GAURAV (18104131)

INSTRUCTOR: PROF. SHAFI QURESHI

Contents
1. INTRODUCTION .................................................................................................... 3
1.1. BLOCK DIAGRAM ................................................................................................. 3
1.2. BARREL SHIFTER ................................................................................................. 4
2. TRANSMISSION GATES ....................................................................................... 5
2.1. SYMBOL .................................................................................................................. 5
2.2. SCHEMATIC ........................................................................................................... 6
2.3. LAYOUT .................................................................................................................. 7
2.4. SIMULATION .......................................................................................................... 8
3. BARREL SHIFTER ................................................................................................. 9
3.1. SYMBOL .................................................................................................................. 9
3.2. SCHEMATIC ......................................................................................................... 10
3.3. LAYOUT ................................................................................................................ 11
3.4. LAYOUT (OPTIMIZED) ...................................................................................... 12
3.5. DRC CHECK ......................................................................................................... 13
3.6. LVS CHECK .......................................................................................................... 14
3.7. PEX FILE CREATION.......................................................................................... 15
4. SIMULATION RESULT ....................................................................................... 16
4.1. SIMULATION ........................................................................................................ 16
4.2. POST LAYOUT SIMULATION ........................................................................... 17
4.2.1. SYMBOL ................................................................................................................ 17
4.2.2. SOURCE NETLIST FILE ..................................................................................... 18
4.2.3. PRE-LAYOUT WAVEFORMS ............................................................................. 19
4.2.4. POST LAYOUT WAVEFORMS........................................................................... 20
4.2.5. POWER CALCULATION..................................................................................... 21
4.2.6. FALL TIME MEASUREMENT............................................................................ 21
4.2.7. RISE TIME MEASUREMENT ............................................................................. 22
4.2.8. DELAY OF THE CIRCUIT .................................................................................. 22
4.2.9. COMPARISON TABLE OF RESULTS ............................................................... 23
5. CONCLUSION ....................................................................................................... 23
6. REFERENCE: ............................................................................................................... 23
 1. INTRODUCTION

Barrel shifter is a basic circuit that shifts the given data input. In this report
we discuss a 4-bit barrel shifter circuit in which the data is shifted by ‘n’ bits
where ‘n’ is the user input. The circuit is designed such that the shift operation
is performed in a single clock cycle depending on the select input (i.e. n).

1.1. BLOCK DIAGRAM

The basic block diagram of a barrel shifter is as shown in the figure.

Fig 1. Block diagram of 4-bit Barrel shifter

The above block has the following

• Inputs: Input data bits (A0, A1, A2 and A3), Shift Bits (C0, C1, C2 and C3)
• Power inputs: VDD, GND.
• Outputs: Output data (B0, B1, B2 and B3).
A 4-bit input data is given to the circuit. The number of bits by which the data is
to be shifted is specified by the shift inputs. (i.e. if the data is to be shifted by 0
bit, shift input C0 will be enabled, by 1 bit then C1 will be enabled and so on).
The 4-bit Shifted data is obtained at the output. We have added buffers to drive
the load.

1.2. BARREL SHIFTER

The Barrel shifter is used mainly in arithmetic and logic units where
shifting or rotating of data is required. The circuit consists of SIXTEEN
transmission gates connected as shown in the figure.

Figure 2: Barrel shifter using transmission gates

There will be a propagation delay associated with each transmission gate, since each
transmission gate has PMOS device, NMOS device and inverter.
2. Transmission Gates

A Transmission gate is a combination of a PMOS pass gate and a NMOS

pass gate in parallel. Since NMOS passes logic lows well and PMOS
passes logic highs well, combining both produces a transmission gate that
passes both logic levels efficiently. The Propagation delay-times of this
CMOS transmission gate is estimated as
tPHL = tPLH = 0.7 . (Rn // Rp) . CLoad

The capacitance on the S input of the transmission gate is the input capacitance
of the NMOS device (Cinn). The capacitance on the S’ input is the input

capacitance of the PMOS device (Cinp).

2.1. SYMBOL
 Figure 3: Symbol of transmission gate

2.2. SCHEMATIC

The Schematic of a transmission gate is as shown in the figure.

Figure 4: Schematic of transmission gate

2.3. LAYOUT
The layout of a transmission gate is shown in the figure. The layout is
laid in such a manner to avoid any crossing of routing in similar
layers. VDD and GND connections are given using Metal 1.
 Figure 5: Layout of transmission gate

2.4. SIMULATION

The above schematic is simulated using a test input and the resulting wave
forms are as shown in the figure.

From the figure it is seen that when the transmission gate is enabled ( C in
the figure) the output follows the input. i.e. The transmission gate passes both
logic levels efficiently.

Figure 5: Layout of transmission gate

 3. BARREL SHIFTER

3.1. SYMBOL

Figure 6: Symbol of barrel shifter

The Input data is given at A3A2A1A0. The shift data is given at S3S2S1S0. The
Power pins are VDD and GND. The Output is obtained at B3B2B1B0 .
3.2. SCHEMATIC
The schematic of barrel shifter is shown in the figure.

Figure 6: Schematic of 4-bit barrel

3.3. Layout
The layout of the shifter circuit is as shown in the figure

Figure 7: Layout of 4-bit barrel (design 1)

3.4. Layout (Optimized)
The optimized layout of the 4-bit Barrel shifter circuit is as shown in
the figure

Figure 8: Layout of 4-bit barrel (optimized)

In the layout VDD and GND connections are given using Metal 2. The inputs A3 A2A1A0 are
connected using Metal 1. The outputs 𝐵3 𝐵2 𝐵1 𝐵0 are connected using metal 1.

3.5. DRC CHECK

Figure 9: DRC results of 4-bit Barrel Shifter

 3.6. LVS CHECK

In this layout vs Schemetic result is shown and it is found to

be matched successfully.

Figure 10: DRC results of 4-bit Barrel Shifter

Now we generate a pex file and then it’s ready for post layout simulation.
3.7. PEX FILE CREATION

In this pex file is shown . This file is needed to be update later in order
to compare with the netlist generated in schematic in post layout
simulation.

Figure 11: Pex file creation of 4-bit Barrel Shifter

4. SIMULATION RESULT
4.1. Simulation

In this we have shown the simulation result from Schematic circuit

diagram .All input waveforms, control waveforms and output waveforms
are ploted. Also instantaneous power is also shown.

Figure 12: Simulation result 4-bit Barrel Shifter (Schematic)

 4.2. POST LAYOUT SIMULATION

4.2.1.SYMBOL

In this symbol is drawn to carry out post layout simulation our 4-bit Barrel Shifter.

Figure 13: Symbol drawn for post layout of 4-bit Barrel Shifter
4.2.2.SOURCE NETLIST FILE

In this , we have to compare the netlist file generated with the pex file
and if the pins are not in order then we make them in order same as
shown in this figure below . After editing the plex file and now we
import that pes file here. Now it is ready for post layout simulation.

Figure 14: Netlist file of 4-bit Barrel Shifter

4.2.3.Pre-Layout Waveforms
This is the pre-Layout simulation shown of all input output of 4-bit Barrel
Shifter.

Figure 15: Pre Layout Simulation waveforms of 4-bit Barrel Shifter

4.2.4. Post Layout Waveforms

In this we have shown the post layout waveforms of 4-bit

Barrel shifter.

Figure 16: Post Layout Simulation waveforms of 4-bit Barrel Shifter

4.2.5.Power Calculation

Average Power calculated for all four periods.

Figure 17:Power calculation

4.2.6.Fall time measurement

Figure 18: Fall time calculation

4.2.7.Rise time measurement

Figure 19: Rise time calculation

4.2.8.Delay of the circuit

Figure : Delay time calculation

4.2.9. Comparison Table of results

5. CONCLUSION

• 4 bit barrel shifter is used to shift data by 0 to 3 bits in 1 clock cycle .

• The circuit designed here is only for rotate ( left ) operation . But with
few modifications in the circuit connections , it can be used for rotate
right operation as well as for shift operations with sign bit extension .

• The barrel shifter was designed with considerations for minimum delay

6. REFERENCE:
nd
1. CMOS circuit design, layout and simulation, 2 edition by R. Jacob Baker.
2. Basic VLSI design by Douglas A Pucknell, Kamran Eshraghan