Faculty of electronic engineering

English I
Computer Engineering module

Circuits - possible exam questions

Questions chosen and answered by:

• Ivan Damnjanovic (15543)

• Nikola Milovanovic (15755)

Document formatting done in LATEX by:

• Nikola Milovanovic (15755)

Grammatical correction orchestrated by:

• Ivan Damnjanovic (15543)

supervised by
Dr. Nadezda Stojkovic

December 8, 2017
1 Pipelining Processor
This is an electronic circuit showing how a pipelining processor should look like.
The processor given on the schematic has 5 pipelining stages: the Instruction
Fetch (IF) stage, the Instruction Decode (ID) stage, the Execution (EX) stage,
the Memory Evaluation (ME) stage, and the Write Back (WB) stage. Thus, 4 sets
of pipelining registers separate these stages and they are labeled IF/ID, ID/EX,
EX/ME and ME/WB accordingly. The Program Counter (PC) holds the address
of the next instruction to be executed, and this address gets incremented as each
new instruction arrives. If there is a branching instruction being executed, then
the PC value is directly changed to the address of the jump destination. The PC
addresses the Instruction Memory (IM) and the given instruction is loaded into
the Instruction Register (IR), which is located within the IF/ID set of registers.
The IR addresses the Register Field (RF) and specifies the instruction operands.
These operands are used as inputs to the Arithmetic-Logic Unit (ALU), and some
operation is performed on them, depending on what the instruction is. If the given
instruction is Load or Store, then the Data Memory (DM) is also accessed and
addressed by the ALU operation result. Finally, either the ALU result or the DM
output are written into the RF, in the appropriate register.

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2 Dynamic Random-Access Memory (DRAM)
This is a schematic of a conventional DRAM (Dynamic Random-Access Memory)
integrated circuit that consists of DRAM cell groups, with each group memorizing
exactly one byte. It is necessary to implement hardware logic which allows the user
to select one byte via its unique address. Byte groups themselves are organized
into a matrix of order 2N × 2M . For instance, let N = 14 and M = 12. The
number of bytes necessary to address every byte in this DRAM IC is 26, and its
capacity is 64 megabytes. Instead of using 26 address pins (one pin per bit line),
it is possible to use an improved design method with less address pins. To make
this work, we must introduce two new registers: one for saving the row address,
and the other for saving the column address. The idea is that we can use pins
to address the row and then those same pins to address the column in exclusive
time intervals. We can achieve this if we first write the row address into the
row address register, under the short impulse of the RAS (Row Address Strobe)
signal and then write the column address into the column address register under
the impulse of the CAS (Column Address Strobe) signal. This way, the number of
necessary address pins is determined by the greater of N and M . In our example,
that would be 14. When a row is addressed, all of its bytes are emptied into the
sense amplifier circuits. After that, the column address is decoded, the specific
column is selected and the byte is available on the output buffer. The process of
reading a row is destructive, which means that the entire content of the row gets
deleted. However, sense amplifiers are constructed to simultaneously refresh row
content. The process of writing byte information is nearly identical, with a few
minor differences. A DRAM is a volatile memory, since it can’t hold data in the
absence of electricity.