I/O Interfacing

I/O Interface

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 80x86 I/O Instructions

IN

OUT

INS

OUTS

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 80x86 I/O Instructions
• reads from an I/O device (IN).

• transfers information to an I/O device (OUT).

• Instructions are also provided to transfer strings of data between

memory and I/O.
– INS and OUTS, found except the 8086/8088

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 80x86 I/O Instructions

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 Modes of I/O Instructions
• Direct I/O
• Indirect I/O
• String

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 Modes of I/O Instructions
• Direct I/O – the port address is one of the operands.
– Address must be 00-FFh.
• IN AL, 27h

– Data flows through the accumulator

• MOV AX, BX
• OUT 26h, AX ; move 16-bit data from AX to port
; 26h (AL to 26h and AH to 27h)

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 Modes of I/O Instructions
• Indirect I/O – the port address is preloaded into DX
– Address can be 0000-FFFFh

• String I/O – allows data to pass directly through the accumulator

(from I/O device to memory)

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 I/O Interface
• I/O devices connect to processor through PORTS

• Ports are:
 registers (part of the I/O interface)
 8, 16, or 32 bits wide
Addressed in the range 0000-FFFFh
Accessed with 2 instructions – IN, OUT

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 Ways to Differentiate I/O
• Memory-Mapped versus I/O-Mapped Ports
 address of 80x86 processors is divided into 1M, 4GB,
or 64GB of memory space and 64K of I/O space.

Memory
Space
20-, 32-, or 64-bit

I/O Space

address
address

16-bit
M/IO’ = 0

M/IO’ = 1

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 IO-Mapped I/O & Memory-Mapped I/O

IO-Mapped I/O

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 IO-Mapped I/O & Memory-Mapped I/O

Memory-Mapped I/O

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 I/O Interfacing

VCC

0
1

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 I/O Interfacing

Vcc
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 Basic I/O Interface

• The basic input device (to the microprocessor) is

a set of tri-state buffers.
• The basic output device (from the
microprocessor) is a set of latches.

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 Basic Input Interface

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 Basic Output Interface

•In this case, the data from the OUT instruction is latched using SEL.

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 Why Buffers

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 I/O Design in 8086

Any μP-based system when data is sent out by μP, the data on the
data-bus must be latched by the receiver/output device

Memories have internal latches–store data

Latching System must be designed for ports

Data provided by the μP is available only for short period of time

(50-1000ns) data must be latched else it will be lost

When data comes in from a port/memory, data must be input

through a tri-state buffer

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 I/O Design in 8086

 Interfacing input devices like switches require buffers.

 Interfacing output devices like LEDs require latches.

 Programmable Peripheral Interface (PPI) device provides

these features

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 8255
Programmable
Peripheral Interface

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 8255- PPI

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 8255- PPI
Intel has developed several peripheral control chips for 80x86
family
–provide complete I/O interface to x86 chip

8255 PPI
PPI provides 3, 8-bit I/O ports (A, B and C) in one package
Chip can be directly interfaced to the data bus of 8086.

Other Peripheral Devices

8253/8254 –Programmable Interval Timer (PIT)
8259 –Programmable Interrupt Controller (PIC)
8237 –Direct memory Access Controller (DMAC)
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 8255- PPI
• 82C55 programmable peripheral interface (PPI) is a
popular, low-cost interface component

• The PPI has 24 pins for I/O, programmable in groups of 12

pins (Group A and B)

• The groups operate in three distinct modes of operation

(Mode 0, Mode 1 and Mode 2)

• The 82C55 (CMOS version) requires wait states if operated

with a processor using higher than an 8 MHz clock.

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 Pin Diagram of 8255

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 Internal block diagram of 8255

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 8255- PPI
 The three I/O ports (labeled A, B, and C) are programmed
as groups.
 group A connections consist of port A (PA7–PA0) and the
upper half of port C (PC7–PC4)

 group B consists of port B (PB7–PB0) and the lower half

of port C (PC3–PC0)

 82C55 is selected by its CS pin for programming and

reading/writing to a port.

 For 82C55 to be read or written, the CS input must be logic

0 and the correct I/O address must be applied to the A1 and
A0 pins.
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 Selection of ports

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 Programming of 8255- PPI
 8255 is programmed through a 8 bit control Register (two internal
command byte).

 Bit position 7 of control Register selects either simple I/O mode

command or Bit set reset (BSR) command.

 Simple I/O mode command programs functions of group

A and B.

 Bit set reset (BSR) command sets (1) or resets (0) the
individual bits of port C only if the 8255 is programmed in
mode 1 or 2.

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 Control word Format

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 Control word Format

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 Modes of operation of 8255

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 Interfacing with 8086

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 Mode 0

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 Example

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 Example

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 Handshaking signal

PROCESSOR

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 MODE 1 (Strobed I/O mode)

• Two groups – Group A and group B are available for strobe

data transfer.
• Each group contains one 8 bit data I/O port and one four bit
control / data port.
• Both the input and outputs are latched.
• Out of 8-bit port C , PC0- PC2 are used to generate control
signals for port B and PC3- PC5 are used to generate control
signals for port A.
• The lines PC6- PC7 may be used as independent data lines.

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 MODE 2 (Strobed Bidirectional I/O mode)

• A single 8-bit port in Group A is available.

• The 8 bit port is bidirectional and additionally a 5-bit
control port is available..
• Both the input and outputs are latched.
• The 5-bit control port C , PC3- PC7 are used to generate/
accept handshake signals for port A.
• Three I/O lines are available at port C, PC2- PC0.

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 BIT Set Reset (BSR) mode

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 BIT Set Reset (BSR) mode

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 Example

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 Interfacing

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 Example

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 Example

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 Example
MOV AL, 01H
CR EQU 06H
OUT CR, AL
MOV AL, 80H
MOV AL, 03H
OUT CR, AL
OUT CR, AL
REPEAT: MOV AL, 00H
MOV AL, 04H
OUT CR, AL
OUT CR, AL
MOV AL, 03H
CALL delay_1ms
OUT CR, AL
JUMP REPEAT
MOV AL, 05H
OUT CR, AL
CALL delay_1ms
MOV AL, 01H
OUT CR, AL
MOV AL, 02H
OUT CR, AL
MOV AL, 05H
OUT CR, AL
CALL delay_1ms
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 Display Interfacing

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 Display Interfacing

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