A NEW TOPOLOGY ON TWENTY ONE LEVEL

MULTILEVEL INVERTER WITH REDUCED

SWITCHES.
PHASE –II REPORT

Submitted by

AHALYA.R

(1701PD2001)

Under the Guidance of

Mrs.G.KRITHIGA, M.E.,

ASSISTANT PROFESSOR

FACULTY OF ENGINEERING AND TECHONOLGY

DEPARMENT OF ELECTRICAL ENGINEERING

PRIST UNIVERSITY

THANJAVUR-613 403

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A NEW TOPOLOGY ON TWENTY ONE LEVEL
MULTILEVEL INVERTER WITH REDUCED
SWITCHES.
PHASE -II REPORT

Submitted by

AHALYA.R

(1701PD2001)

Under the Guidance of

Mrs.G.KRITHIGA, M.E.,

ASSISTANT PROFESSOR

FACULTY OF ENGINEERING AND TECHONOLGY

DEPARMENT OF ELECTRICAL ENGINEERING

PRIST UNIVERSITY

THANJAVUR-613 403

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 FACULTY OF ENGINERING AND TECHNOLOGY

DEPARMENT OF ELECTRICAL ENGINEERING

PRIST UNIVERSITY

THANJAVUR-613 403

This is to certify that the project titled “A NEW TOPOLOGY ON TWENTY ONE LEVEL
MULTILEVEL INVERTER WITH REDUCED SWITCHES” is bonafide record of work done by

AHALYA.R (Reg:No:1701PD2001) In p a r t i al fulfillment of the requirements for the award

of the degree of Master of Technology in Electrical and Electronics Engineering of PRIST
UNIVERSITY.

Internal Guide Head of the Department

Submitted for the University Examination held on ………………….

INTERNAL EXAMINER EXTERNAL EXAMINER

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 ACKNOWLEDGEMENT
I have a deep inner urge to record my gratitude to the helping hands who
contributed to the successful completion of my project work.

I express my thanks to Founder and Chancellor Prof. P. Murugesan of

PRIST University, Thanjavur for making all arrangements for the successful
completion of my studies.

And I whole heartedly thank our Vice-Chancellor Dr. N. Ethirajulu, of

PRIST University, for making all arrangements for the successful completion of
my studies.

I have great pleasure to thank our Dean- Faculty of Engineering and

Technology Prof. Vijayakumar PRIST University Thanjavur for the concern
shown in giving approval for my project, support and guidance.

I have great pleasure in dedicating my warm and sincere thanks to our

esteemed Project coordinator and Head of the department
Dr.P.Avirajamanjula - Electrical & Electronics Engineering, PRIST University,
Thanjavur for her invaluable guidance and motivation throughout the project.

To record my gratitude and whole hearted thanks to the Project

Coordinator Dr.P.Avirajamanjula Department of Electrical and Electronics
Engineering, PRIST University, Thanjavur for her encouragement and guidance
to complete the project.

I whole heartedly thank my Project Guide Mrs.G.Krithiga, Department

of Electrical and Electronics Engineering, PRIST University, Thanjavur for her
helping hand and kind guidance to make my project phase-II to be successful.

And I also extend my sincere thanks to all teaching, non-teaching faculty

members, family members and friends who directly or indirectly helped in the
completion of this project.

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 ABSTRACT

In this paper, a new topology on Multilevel Inverter is designed with

reduced number of switches and DC sources. This makes the circuit simple and
reduces the switching loses due to large number of switches in the conventional
topologies.

The Multilevel inverters are known for their high power capability and
reliability. The increase in number of levels improves the power quality but it also
increases the complexity in control and cost, which will increase the switching
losses also.

Hence there is a need for research in the multilevel inverter topology to

have reduced number of switches for increased levels than the conventional and
pre-proposed topologies. The purpose of this paper is to design the new topology
on multilevel inverter with reduced switching devices.

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 TABLE OF CONTENTS

CHAPTER NO. TITLE PAGE NO.

ABSTRACT iii
LIST OF TABLES vi
LIST OF FIGURES vii

1 INTRODUCTION
1.1 GENERAL 1
1.2 LITERATURE REVIEW 3

2 MULTILEVEL INVERTER OVERVIEW

2.1 INTRODUCTION 6
2.1.1 Inverter 6
2.2 MULTILEVEL INVERTER 7
2.2.1 Diode clamped Multilevel Inverter 7
2.2.2 Flying capacitor Multilevel Inverter 9
2.2.3 A Cascaded Multilevel Inverter 9
3 PROPOSED TOPOLOGY ON MULTILEVEL INVERTER
3.1 INTRODUCTION 11
3.2 CIRCUIT DIAGRAM OF PROPOSED TOPOLOGY 11
3.3 WORKING OF THE PROPOSED TOPOLOGY 12
4 SWITCHING TABLE
4.1 INTRODUCTION 19
4.2 SWITCHING TABLE 19

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CHAPTER NO. TITLE PAGE NO.

5 SIMULATION RESULTS
5.1 INTRODUCTION 21
5.2 CIRCUIT DIAGRAM IN MATLAB SIMULINK 21
5.3 OUTPUT OF THE TWENTY ONE LEVEL
INVERTER 22
5.4 FFT ANALYSIS OF PROPOSED TOPOLOGY
OUTPUT 23

6 HARDWARE IMPLEMENTATION ON PROPOSED

MODEL
6.1 INTRODUCTION 25
6.2 COMPONENTS USED 25
6.3 POWER SUPPLY UNIT 25
6.3.1 BLOCK DIAGRAM 25
6.3.2 WORKIG PRINCIPLE 26
6.4 DRIVER CIRCUIT 29
6.5 MULTILEVEL INVERTER UNIT 30
6.6 HARDWARE CIRCUIT 31

7 CONCLUSION 33
REFERENCES 35
APPENDIX A 37
APPENDIX B 39

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 LIST OF TABLES
TABLE NO TITLE PAGE NO

4.1 SWITCHING TABLE FOR TWENTY ONE LEVEL INVERTER 20

8.1 COMPARISON OF NUMBER OF PARAMETERS AMONG
VARIOUS TOPOLOGIES OF TWENTY ONE LEVEL
INVERTER 34

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 LIST OF FIGURES
FIGURE NO TITLE PAGE NO
2.1 MULTILEVEL INVERTER TOPOLOGIES 7
2.2 DIODE CLAMPE (a) THREE LEVEL
(b) FIVE LEVEL INVERTER 8
2.3 ONE LEG OF FLYING STRUCTURE
(a) Three-level; and (b) Five-level capacitor 9
2.4 Cascaded H-bridge structure for multilevel inverters 10
3.1 Circuit diagram 11
3.2 Mode 1 12
3.3 Mode 2 13
3.4 Mode 3 14
3.5 Mode 4 14
3.6 Mode 5 15
3.7 Mode 6 16
3.8 Mode 7 16
3.9 Mode 8 17
3.10 Mode 9 17
3.11 Mode 10 18
5.1 Circuit diagram in MATLAB 21
5.2 Output voltage waveform of 21 level inverter (without filter) 22
5.3 Output voltage waveform of 21 level inverter (with filter) 22
5.4 FFT Analysis of proposed twenty one level inverter
(with filter). 23
6.1 Block diagram (Power supply) 26
6.2 Circuit diagram (Power supply) 28
6.3 Direct Gate Driving Circuit 29
6.4 Hardware model of proposed model. 31
6.5 Twenty one level output (without filter) 31
6.6 Output of the Inverter (with filter) 32
6.7 Output of the inverter for positive half cycle 32

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 LIST OF ABBREVIATIONS

ACMLI - Asymmetrical Cascaded Multi Level Inverter

ADCMLI - Asymmetrical Diode Clamped Multi Level Inverter

ANN - Artificial Neural Network

CMLI - Cascaded Multi Level Inverter

DCMLI - Diode Clamped Multi Level Inverter

EMI - Electro Magnetic Interference

FCMLI - Flying Capacitor Multi Level Inverter

MLI - Multi Level Inverter

MI - Modulation Index

MHMLI - Modified H-bridge Multi Level Inverter

MVA - Mega Volt Ampere

NPC - Neutral Point Clamped

PQ - Power Quality

PCC - Point of Common Coupling

SCMLI - Symmetrical Cascaded Multi Level Inverter

TSC - Thyristor Switched Capacitor

TCR - Thyristor Controlled Reactor

VSI - Voltage Source Inverter

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