ELE 3230

Microprocessors and Computer

Systems

Chapter 5
8088 Pin Assignment

(*Brey:ch9; Hall:ch7; Triebel:ch7)

ELE 3230 - Chapter 5 1

 Pin Layout of the 8088
Microprocessor
• Nine pins have functions which depend
Min Mode (Max Mode)
on the state of MN/MX :
GND 1 40 Vcc
A14
A13
2
3
39
38
A15
A16/S3
MN/MX =high - 8088 operates
A12
A11
4
5
37
36
A17/S4
A18/S5
in MINIMUM MODE
A10 6 35 A19/S6
A9 7 34 SS0 (High)
MN/MX =low - 8088 operates
A8
AD7
8
9
33
32
MN/MX in MAXIMUM MODE
RD
AD6
AD5
10
11
8088
CPU
31
30
HOLD
HLDA
( RQ /GT0 )
(RQ / GT1)
• minimum mode: - 8088 directly
AD4
AD3
12
13
29
28
WR ( LOCK ) generates the control signals necessary
IO/M (S2)
AD2 14 27 DT/R (S1 ) for accessing memory and IO ports.
AD1 15 26 DEN (S0 )
AD0
NMI
16
17
25
24
ALE (QS0)
• maximum mode:- external support
INTA (QS1)
INTR 18 23 TEST chips are needed to generate control
CLK 19 22 READY
GND 20 21 RESET signals; the processor can work in a
40 LEAD system containing other processors

2
Signals Common to Both Minimum and
Maximum Modes
Common signals
Name Function Type
Bidirectional, 3-
AD7 – AD0 Address/data bus state
Output,
A15 – A8 Address bus 3-state
Output,
A19/S6 – A16/S3 Address/status
3-state
Minimum/maximum
MN/MX Mode control Input
Output,
Read control
RD 3-state

TEST Wait on test control Input

READY Wait state control Input
RESET System reset Input
Nomaskable
NMI Input
Interrupt request
INTR Interrupt request Input
CLK System clock Input
VCC +5V Input
GND Ground Input
ELE 3230 - Chapter 5 3
Unique Minimum-mode Signals
Minimum mode signals (MN/MX= VCC )
Name Function Type
HOLD Hold request Input
HLDA Hold acknowledge Output
Write control Output,
WR 3-state
IO/memory control Output,
IO/M
3-state
DT/R Data Output,
transmit/receive 3-state
DEN Data enable Output,
3-state
SSO Status line Output,
3-state
ALE Address latch Output
enable
INTA Interrupt Output
acknowledge
ELE 3230 - Chapter 5 4
Unique Maximum-mode Signals

Maximum mode signals (MN/ MX

= GND)
Name Function Type
RQ/GT1, 0 Request/grant bus Bidirectional
access control
LOCK Bus priority lock Output,
control 3-state
S2 - S0 Bus cycle status Output,
3-state
QS1, QS2 Instruction queue Output
status

ELE 3230 - Chapter 5 5

 Maximum-Mode of 8088
❚ 8288 Bus Controller
❙ In maximum-mode, the signal to control memory, I/O, and
interrupt interface is produced by 8288.
❙ WR, IO/M, DT/R, DEN, ALE, and INTA are no longer produced
by 8088, instead 8288 generates

MRDC -- memory read command

MWTC -- memory write command
AMWC -- advanced memory write command
IORC -- I/O read command
IOWC -- I/O write command
AIOWC -- advanced I/O write command
INTA -- interrupt acknowledge command
ELE 3230 - Chapter 5 7
 Bus Status Codes

❚ 8288 produces the commands according to the

output bits S2 S1S0 from 8088.

Status Inputs 8288 Command

CPU Cycle
S2 S1 S0
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read I/O Port IORC
0 1 0 Write I/O Port IOWC, AIOWC
0 1 1 Halt None
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC , AMWC
1 1 1 Passive None

ELE 3230 - Chapter 5 8

 Queue Status Codes
❚Two new signals are produced by 8088 in maximum-mode : QS0
and QS1. The two-bit code tells the external circuitry what type of
information was removed from the queue in the previous cycle.
QS1 QS0 Queue Status
0 (low) 0 No Operation. During the last
clock cycle, nothing was taken
from the queue.
0 1 First Byte. The byte taken
from the queue was the first
byte of the instruction.
1 (high) 0 Queue Empty. The queue has
been reinitialized as a result of
the execution of a transfer
instruction.
1 1 Subsequent Byte. The byte
taken from the queue was a
subsequent byte of the
instruction.
ELE 3230 - Chapter 5 9
 8088 Pin Functions
The 8088 pins may be grouped into the following nine categories:

1. Power Supply and Clock (VCC, GND and CLK)

❚ VCC=5 volts (5 or 10% tolerance)
❚ Maximum current needed is 340mA (10 mA for CMOS version)
❚ BOTH ground (GND) pins must be connected to 0V.
❚ CLK input needs a periodic rectangular waveform with rise and fall times
of less than 10ns. Clock frequency must be between 2 and 5 MHz. (see
ch06, clock chip 8284).

2. Minimum/Maximum Mode pin

❚ Minimum mode selected when(MN/MX) is connected to +5V

ELE 3230 - Chapter 5 11

 8088 Pin Functions
3. Status Pins ( S0, S1, and S2 ) - in maximum mode only
The status pins are outputs which are used by the 8288 bus controller to generate
control signals according to the following table:

S2 S1 S0 Meaning
0 0 0 Interrupt acknowledge (INTA)
0 0 1 I/O read
0 1 0 I/O write
0 1 1 HALT
1 0 0 Code access (fetching instruction)
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive state (not used)

ELE 3230 - Chapter 5 12

 8088 Pin Functions
4. Bus Master (HOLD, HLDA, RQ/GT0, RQ/GT1 and LOCK)
Control of the local bus is transferred to other devices with aid of the following
signals:
Minimum Mode - HOLD and HLDA (hold acknowledge)
Maximum Mode - request/grant (RQ/GT0, RQ/GT1) and LOCK
❚ HOLD is an input (in minimum mode only) which tells the processor to
suspend operations and allow other devices to access the system bus.
Program execution only resumes when HOLD=0.
❚ HLDA (hold acknowledge) is an output which informs other devices in the
system that the 8088 is in a HOLD state. When another device wants to
access the bus, it waits for HLDA=1.

ELE 3230 - Chapter 5 13

 8088 Pin Functions

4. Bus Master (cont.) (HOLD, HLDA, RQ/GT0, RQ/GT1 and LOCK)

❚ Request and Grant pins (RQ/GT0 and RQ/GT1) are used only in
maximum mode and function both as inputs (to accept requests) and
outputs (to grant requests). When another device wants to become the
BUS MASTER (i.e. take control of the local bus) it issues a request by
pulling one of the request pins to a low logic state for one clock cycle.
After a request is received, the 8088 enters a HOLD state and sends a
grant signal on the same pin. RQ/GT0 has a higher priority over RQ/GT1.

❚ LOCK is an output pin in maximum mode and informs other devices that
they cannot takeover the local bus

ELE 3230 - Chapter 5 14

 8088 Pin Functions

5. Interrupt pins (NMI, INTR and INTA)

Interrupt acknowledge pin (INTA) is available only in minimum mode. NMI
(non-maskable interrupt) and INTR (interrupt request) are present in both
modes.
❚ The NMI (non-maskable interrupt) is an input which accepts a rising edge
to trigger the interrupt. It cannot be disabled by software. Interrupt number
2 is generated by an NMI.
❚ INTR is an input which accepts a high logic level as an interrupt request.
Provided the interrupt flag in the FLAGS register is enabled, the processor
will respond to the interrupt request in the same way as it processes an
software INT instruction.
❚ INTA acknowledges an interrupt request and indicates to the interrupting
device that it should place an 8-bit interrupt number on the data bus

ELE 3230 - Chapter 5 15

 8088 Pin Functions
6. RESET is an input which resets and initializes the processor. After a
RESET the processor reads memory location FFFF0h for an instruction.

7. Bus control pins

A group of 7 pins generate the control signals for data transfer to and from
the data and address bus in minimum mode. In maximum mode only two
(RD and READY) of these 7 functions are available directly (the other bus
protocol signals are generated from the status pins).
The seven pins in this group include:
❚ READY - an input to tell the processor that the selected memory or I/O
port is ready to complete a read or write operation. If READY is not
asserted, wait states are added (eg. For slow memory).

ELE 3230 - Chapter 5 16

 8088 Pin Functions

7. Bus control pins (cont.)

❚ RD (read) - an output indicating when the processor is performing read
operation from memory or an I/O port.
❚ ALE (addressing latch enable) - an output to demultiplex the address/data
pins. When ALE is high, address information is being sent.
❚ DEN(data enable) - an output used with an external tristate buffer to disconnect
the processor data pins from the data bus. (When DEN is low the processor
data pins should be connected to the data bus)
❚ DT/R (data transmit/receive) - an output indicates direction of data flow
❚ WR (write) - an output to indicate when the processor is putting data into
memory or I/O port
❚ IO/M - an output indicates whether access is to memory or I/O ports
❚ The logic is different between 8086 & 8088.

ELE 3230 - Chapter 5 17

 8088 Pin Functions

8. Address, data pins and address status pins

❚ AD0-AD7 (address/data bus pins) - these pins output both address and data
information and input data at different times of the bus cycle. Usually an
external latch stores the address information form these pins before the pins
are switched to carry data. Both the low and high order bytes of a 16-bit data
word must be transferred via these pins.
❚ A8-A15 (address bus pins) - used solely for specifying the address of a
memory location or IO port.
❚ A16/S3-A19/S6 (address bus or status pins) - these either carry memory
addressing information or status information. S6 is always at logic 0. S5
describes the state of the interrupt flag in the FLAGS register. S4 and S3
describe the segment register being used to generate the physical address
that was output on the address during the current bus cycle.

ELE 3230 - Chapter 5 18

 8088 Pin Functions
8. Address, data pins and address status pins (cont.)

S4 S3 Segment register
0 0 ES
0 1 SS
1 0 CS or no segment
1 1 DS

❚ The address pins A0-A15 specify either a 16-bit I/O port number or the
first 16 bits of a 20-bit address of a memory location.

9. Coprocessor interaction pins

Three pins (TEST, QS0 and QS1) are used for interactions between the
8088 and 8087 arithmetic co-processor to synchronize MPU with
external hardware.

ELE 3230 - Chapter 5 19

 8088 Pin Functions
9. Coprocessor interaction pins (cont.)
❚ TEST is an input pin that is tested by the WAIT instruction. If TEST is low the
WAIT instruction functions as a NOP. If TEST is at logic 1 then the WAIT
instruction waits until it goes to logic 0 (MPU enters “idel state”). The TEST pin
is often connected directly to a 8087 coprocessor (it must be connect to logic 0
if the 8087 is not present)
❚ QS0 and QS1 (queue status) pins provide information on the 8088 internal
instruction queue. The information is used by the 8087 coprocessor. The
queue status bits indicate the contents of the internal instruction queue
according to the following table:
QS1 QS0 instruction queue contents
0 0 No operation (queue is idle)
0 1 First byte of an opcode
1 0 Queue is empty
1 1 Subsequent byte of an opcode

ELE 3230 - Chapter 5 20