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Introduction to Vivado Design

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Flows
 VIVADO DESIGN SUITE TOOL FLOW

Common data model

throughout the flow
— Cross-probing support

Save checkpoint
designs at any stage
— Netlist, constraints,
place and route
results

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Introduction to Vivado Design Flows - 1-7 © Copyright 2017 Xilinx 108166

 ISE VS. VIVADO DESIGN SUITE

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Introduction to Vivado Design Flows - 1-8 © Copyright 2017 Xilinx 108166

 DIFFERENT USERS – DIFFERENT NEEDS

FPGAs are used in different applications

— Small designs for glue
— Small designs for low to mid-volume consumer applications
— Medium designs for specialty consumer applications
— Large designs for industrial applications
— Very large designs for high-end infrastructure
— Extremely large designs for ASIC prototyping

Each of these applications has differing needs

— Different size teams
— Different levels of FPGA architectural skill
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— Different levels of project infrastructure management

Need different flows to support all users

— Simpler pushbutton flow
— Low overhead, completely automated, and supporting large teams / projects
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 VIVADO DESIGN SUITE USE MODELS

The Vivado tool supports two use models

— Project Mode
— Non-project Mode
The Vivado IDE can be used both in Project mode
and Non-project mode
Project Mode
— Creates project structure on disk
— The Vivado tool manages design runs, status, and data
— Can use GUI and/or Tcl scripts
— Reports are generated automatically
— Robust interactive design environment
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Non-project Mode
— Project is compiled in memory
— Tcl-based, batch processing
— Manual design source file management
— Can use GUI for visualization via start_gui
command
— Must manually create reports and checkpoints
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 PROJECT MODE VS. NON-PROJECT MODE

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Introduction to Vivado Design Flows - 1-11 © Copyright 2017 Xilinx 108166

 PROJECT MODE VS. NON-PROJECT MODE TCL
COMMANDS

Tcl commands correspond to project mode and non-project mode

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 LAUNCHING THE VIVADO IDE

The Vivado IDE can be launched two ways

— From the desktop or Start menu
— From the command line

When launching from the command line, there are three modes
— GUI: launches the IDE (LOG / JOU file stored in launching directory)
— Tcl: launches into interactive Tcl console
— Batch: launches and executes commands in sourced Tcl script

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Introduction to Vivado Design Flows - 1-13 © Copyright 2017 Xilinx 108166

 INTEGRATED DESIGN ENVIRONMENT (IDE)
A: Flow Navigator D: Workspace (IP integrator shown here)
B: Sources E: Console
C: Block Properties / Attributes

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Introduction to Vivado Design Flows - 1-14 © Copyright 2017 Xilinx 108166

 JOURNAL AND LOG FILES

Journal file (vivado.jou)

— Contains just the Tcl commands executed by the Vivado IDE

Log file (vivado.log)

— Contains all messages produced by the Vivado tool, including Tcl commands
and results, info/warning/error messages, etc.

Location
— Linux: directory where the Vivado IDE is invoked
— Windows via icon: %APPDATA%\Xilinx\Vivado or
C:\Users\<user_name>\AppData\Roaming\Xilinx\Vivado
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Windows via command line: directory where the Vivado IDE is invoked
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— From the GUI you can access via

 Select File > Open Log File
 Select File > Open Journal File

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 SUMMARY

The Vivado tool replaces all the ISE point tools like CORE Generator,
Chipscope, Project Navigator
— All these capabilities of ISE are integrated in the Vivado Design Suite

The Vivado tool uses a common data model throughout the FPGA
design process, unlike the ISE tools
— This yields runtime and memory resource benefits to the user

The Vivado Design Suite supports two use model - Project mode and
Non-project mode
— The Vivado tool supports the use of Tcl commands for all processes
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