//2 leds decoder counter

/*
module led(clk,rst,c,a,up,down);
input clk,rst;
output [9:0]up,down;
output reg[3:0]c,a;
always @(posedge clk)
begin
if(rst) begin c=0;a=9;end
else
begin
c=c+1;a=a-1;
if(c==9)
c=0;
if(a==0)
a=9;
end
end
decoder d1(c,up);
decoder d2(a,down);
endmodule
module decoder(in,out);
input [3:0]in;
output reg[15:0]out;
always @(*)
begin
out=0;
out[in]=1;
end
endmodule
*/
//3 Given Counters
//a
/*
module count(clk,rst);
input clk,rst;
reg[2:0]state;
parameter
s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100,s5=3'b101,s6=3'b1
10,s7=3'b111;
always @(posedge clk)
begin
if(rst) state=s0;
else
case(state)
s0:state=s1;
s1:state=s2;
s2:state=s3;
s3:state=s4;
s4:state=s5;
 s5:state=s2;
s6:state=s2;
s7:state=s2;
default state=s0;
endcase
end
endmodule
*/
//b
/*
module count(clk,rst);
input clk,rst;
reg[2:0]state;
parameter
s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100,s5=3'b101,s6=3'b1
10,s7=3'b111;
always @(posedge clk)
begin
if(rst) state=s0;
else
case(state)
s0:state=s2;
s1:state=s2;
s2:state=s4;
s3:state=s4;
s4:state=s5;
s5:state=s7;
s6:state=s7;
s7:state=s0;
default state=s0;
endcase
end
endmodule
*/
//c
/*
module count(clk,rst);
input clk,rst;
reg[2:0]state;
parameter
s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100,s5=3'b101,s6=3'b1
10,s7=3'b111;
always @(posedge clk)
begin
if(rst) state=s0;
else
case(state)
s0:state=s1;
s1:state=s2;
s2:state=s3;
 s3:state=s4;
s4:state=s0;
s5:state=s0;
s6:state=s0;
s7:state=s0;
default state=s7;
endcase
end
endmodule
*/
//4
/*
//a
module regi(clk,out,c);
input clk;
output [5:0]out;
output reg [3:0]c=0;
wire [5:0]w1;
always @(posedge clk)
begin
c=c+1;
if(c==10)
c=0;
end
assign w1[5]=1;
assign w1[4:1]=c;
assign w1[0]=1;
pipo p1(clk,w1,out);
endmodule
module pipo(clk,in,out);
input clk;
input [5:0]in;
output reg[5:0]out;
always @(posedge clk)
begin
out<=in;
end
endmodule
*/
//5.Digital Clock
/*
module digi(clk,rst,seconds,minutes,hours);
input clk,rst;
output reg[5:0]seconds,minutes;
output reg[4:0]hours;
always @(posedge clk)
begin
if(rst)
begin
seconds=0;
 minutes=0;
hours=0;
end
else
begin
seconds=seconds+1;
if(seconds==60)
begin
seconds=0;
minutes=minutes+1;
if(minutes==60)
begin
minutes=0;
hours=hours+1;
if(hours==24)
begin
hours=0;
end
end
end
end
$display("%d:%d::%d",hours,minutes,seconds);
end
endmodule
*/
//6
/*
module vending_machine(candy,cake,drink,clk,coin,rst);
output reg candy,cake,drink;
input [1:0]coin;
input clk,rst;
reg[1:0]state;
reg[1:0]next_state;
parameter [1:0] s0=2'b00;
parameter [1:0] s5=2'b01;
parameter [1:0] s10=2'b10;
parameter [1:0] s15=2'b11;
always @(posedge clk)
begin
if (rst)
state=s0;
else
state=next_state;
end
always @(state,coin)
begin
case (state)
s0:
begin
if (coin==2'b00)
 next_state=s0;
else
if (coin==2'b01)
next_state=s5;
else
if (coin==2'b10)
next_state=s10;
end
s5:
begin
if (coin==2'b00)
next_state=s5;
else
if (coin==2'b01)
next_state=s10;
else
if (coin==2'b10)
next_state=s15;
end
s10:
begin
if (coin==2'b00)
next_state=s10;
else
if (coin==2'b01)
next_state=s15;
else
if (coin==2'b10)
next_state=s15;
end
s15:
begin
next_state=s0;
end
default : next_state=s0;
endcase
end
always @(state)
begin
case (state)
s0 :begin candy<=1'b0; cake<=1'b0; drink<=1'b0;end
s5 :begin candy<=1'b1; cake<=1'b0; drink<=1'b0;end
s10:begin candy<=1'b0; cake<=1'b1; drink<=1'b0;end
s15:begin candy<=1'b0; cake<=1'b0; drink<=1'b1;end
default: begin candy<=1'b0; cake<=1'b0; drink<=1'b0;end
endcase
end
endmodule
*/
//8 Sequence Detector
//a.1001
/*
module SequenceDetectorMealy(din,clk,reset,y);
input din,clk,reset;
output reg y;
parameter S0=3'b000, S1=3'b001, S2=3'b010, S3=3'b011;
reg [2:0]nextState=0;
always @(posedge clk)
begin
if(reset)
begin
y=0; nextState=S0;
end
else
case(nextState)
S0:
begin
if(din==0)
begin
nextState=S0; y=0;
end
else
begin
nextState=S1; y=0;
end
end
S1:
begin
if(din==0)
begin
nextState=S2; y=0;
end
else
begin
nextState=S1; y=0;
end
end
S2:
begin
if(din==0)
begin
nextState=S3; y=0;
end
else
begin
nextState=S1; y=0;
end
end
S3:
begin
 if(din==0)
begin
nextState=S0; y=0;
end
else
begin
nextState=S1; y=1;
end
end
default begin nextState=S0; y=0; end
endcase
end
endmodule
*/
//b.010
/*
module SequenceDetectorMealy(din,clk,reset,y);
input din,clk,reset;
output reg y;
parameter S0=3'b000, S1=3'b001, S2=3'b010;
reg [2:0]nextState=0;
always @(posedge clk)
begin
if(reset)
begin
y=0; nextState=S0;
end
else
case(nextState)
S0:
begin
if(din==0)
begin
nextState=S1; y=0;
end
else
begin
nextState=S0; y=0;
end
end
S1:
begin
if(din==0)
begin
nextState=S1; y=0;
end
else
begin
nextState=S2; y=0;
end
 end
S2:
begin
if(din==0)
begin
nextState=S1; y=1;
end
else
begin
nextState=S0; y=0;
end
end
default begin nextState=S0; y=0; end
endcase
end
endmodule
*/
//c.101
/*
module SequenceDetectorMealy(din,clk,reset,y);
input din,clk,reset;
output reg y;
parameter S0=3'b000, S1=3'b001, S2=3'b010;
reg [2:0]nextState=0;
always @(posedge clk)
begin
if(reset)
begin
y=0; nextState=S0;
end
else
case(nextState)
S0:
begin
if(din==0)
begin
nextState=S0; y=0;
end
else
begin
nextState=S1; y=0;
end
end
S1:
begin
if(din==0)
begin
nextState=S2; y=0;
end
else
 begin
nextState=S1; y=0;
end
end
S2:
begin
if(din==0)
begin
nextState=S0; y=0;
end
else
begin
nextState=S1; y=1;
end
end
default begin nextState=S0; y=0; end
endcase
end
endmodule
*/
//9 Flip-Flop Conversions
//a.JK-FF to D-FF
/*
module convert(clk,rst,d,q);
input clk,rst,d;
output q;
wire w;
assign w=~d;
jkflipflop sa(clk,rst,d,w,q);
endmodule
module jkflipflop(clk,rst,j,k,q);
input clk,rst,j,k;
output reg q;
always @(posedge clk)
begin
if(rst) q=0;
else
begin
case({j,k})
{1'b0,1'b0}:q=q;
{1'b0,1'b1}:q=0;
{1'b1,1'b0}:q=1;
{1'b1,1'b1}:q=~q;
endcase
end
end
endmodule
*/
//b.D-FF to T-FF
/*
module tflipflop(clk,rst,t,q);
input clk,rst,t;
output q;
wire w;
assign w=t^q;
dflipflop dff(clk,rst,w,q);
endmodule
module dflipflop(clk,rst,d,q);
input clk,rst,d;
output reg q;
always @(posedge clk)
begin
if(rst) q=0;
else q=d;
end
endmodule
*/
//11 FB LOGIN
/*
module fb(clk,rst,din,nextState,out);
input clk,rst;
input [1:0]din;
parameter login=3'b000, createprofile=3'b001, selectavatar=3'b010,
facebookprofile=3'b011, termsandconditions=3'b100, finished=3'b101;
output reg [2:0]nextState=0;
output reg out;
always @(posedge clk)
begin
if(rst)
begin
nextState=login; out=0;
end
else
case(nextState)
login:
begin
if(din==0)
nextState=finished;
else if(din==1)
nextState=createprofile;
else nextState=login;
out=0;
end
createprofile:
begin
if(din==0)

nextState=termsandconditions;
else if(din==1)
 nextState=facebookprofile;
else
nextState=selectavatar;
out=0;
end
selectavatar:
begin
if(din==0)
nextState=createprofile;
else
nextState=termsandconditions;
out=0;
end
facebookprofile:
begin
if(din==0)

nextState=termsandconditions;
else
nextState=selectavatar;
out=0;
end
termsandconditions:
begin
nextState=finished;
out=0;
end
finished:
begin
out=1;
nextState=finished;
end
default nextState=login;
endcase
end
endmodule
*/
//14.Fibonacci Series
/*
module fibo(clk,rst,out);
input clk,rst;
output [7:0]out;
reg [7:0]present,previous;
always @(posedge clk)
begin
if(rst) begin present=3'd0; previous=3'd1;end
else
begin
present=present+previous;
previous=present-previous;
 end
$display("%d",present);
end
assign out=present;
endmodule
*/
//16
//Circuit
/*
module noise(clk,rst,a,b,c);
input clk,rst;
output a,b,c;
wire w1,w2;
assign w1=~c;
assign w2=a&b;
jkflipflop j1(clk,rst,w1,1,a);
jkflipflop j2(clk,rst,a,c,b);
jkflipflop j3(clk,rst,w2,1,c);
endmodule
module jkflipflop(clk,rst,j,k,q);
input clk,rst,j,k;
output reg q=0;
always @(posedge clk)
begin
if(rst) q<=0;
else
begin
case({j,k})
{1'b0,1'b0}:q<=q;
{1'b0,1'b1}:q<=0;
{1'b1,1'b0}:q<=1;
{1'b1,1'b1}:q<=~q;
default q<=1'bx;
endcase
end
end
endmodule
*/
/*
//17 LFSR
//a
module lfsr (out, clk, rst);
output reg [5:0] out;
input clk, rst;
wire feedback;
assign feedback = ~(out[5] ^ out[2]);
always @(posedge clk)
begin
if (rst)
out = 4'b0;
 else
out = {out[4:0],feedback};
end
endmodule
*/
//19
//4-10 line decoder
/*
module decoder(in,out);
input [3:0]in;
output reg [9:0]out;
wire w1,w2;
always @(in)
begin
out=0;
out[in]=1;
end
assign w1=~(out[0]&out[2]&out[5]);
assign w2=~(out[5]&out[7]&out[9]);
endmodule
*/
//21
/*
module pro(data,sel,out);
input [15:0]data;
input [3:0]sel;
output reg [15:0]out=0;
wire w1;
wire [3:0]se;
assign se[0]=~(sel[1]&sel[3]);
assign se[1]=~sel[0];
assign se[2]=sel[2]&sel[0];
assign se[3]=sel[3]^sel[2];
Mux m1(data,sel,w1);
Demux m2(w1,se,out);
endmodule

module Mux(data,select,out);
input [15:0]data;
input[3:0]select;
output out;
assign out=data[select];
endmodule

module Demux(in,sel,out);
input in;
input [3:0]sel;
output reg [15:0]out=0;
always @(*)
begin
 out=0;
out[sel]=in;
end
endmodule
*/
//22
/*
module BCD_Addition(cin,x,y,sum,cout);
input cin;
input [3:0]x,y;
output reg[3:0]sum;
output reg cout;
reg [3:0]r;
always @(*)
begin
{cout,r}=x+y+cin;
if(cout==1|r>9)
begin
sum=r+6;
cout=1'b1;
end
else sum=r;
end
endmodule
*/
//25 Circuit
/*
module impl(clk,rst,x,y,z);
input clk,rst,x,y;
output reg z=0;
wire w1,w2,w3;
assign w1=~(z&~x);
assign w2=~(~z&y);
assign w3=~(w1&w2);
dflipflop sai(clk,rst,w3,z);
endmodule
module dflipflop(clk,rst,d,q);
input clk,rst,d;
output reg q;
always @(posedge clk)
begin
if(rst) q=0;
else q<=d;
end
endmodule
*/
//26.b
/*
module top(d,s,z);
input d;
 input [2:0] s;
output z;
wire w1;
wire [7:0]a;
assign w1=~d;
assign a={0,d,0,w1,w1,d,d,d};
mux m1(a,s,z);
endmodule
module mux(d,s,z);
input [7:0] d;
input [2:0] s;
output reg z;
always@(*)
begin
z=d[s];
end
endmodule
*/
//27
/*
module raj(d,q,clk,rst);
input d,clk,rst;
output [1:0] q;
integer q=2'b00;
wire w1,w2,w3,w4,w5;
d_ff d1(w5,clk,rst,w1);
d_ff d2(w2,clk,rst,q[1]);
d_ff d3(w4,clk,rst,q[0]);
assign w2=~w1;
assign w5=~q[0];
assign w4=w1&w3;
assign w3=~q[1];
endmodule

module d_ff(din,clk,rst,q);
input din,clk,rst;
output reg q;
reg q1=1;
always@(posedge clk)
begin
q<=din;
q1=~q;
end
endmodule
*/
//28
/*
module counter(clk,q);
input clk;
output reg [3:0]q=0;
 wire w1;
always@(posedge clk)
begin
if(w1==0)
q=0;
else
q=q+1;
end
assign w1=~(q[2]^q[3]);
endmodule
*/
/*
//29
//a conditional operator
module condition(a,b,sel,y);
input [7:0]a,b;
input [2:0]sel;
output [7:0]y;
assign y=(sel[2]==0)?((sel[1]==0)?((sel[0]==0)?8'b0:a&b):((sel[0]==0)?a|
b:a^b)):((sel[1]==0)?((sel[0]==0)?~a:a-b):((sel[0]==0)?a+b:8'hFF));
endmodule
*/
//29b
/*//a
module random(clk,rst,num);
input clk,rst;
output reg [3:0]num;
reg [3:0]nextstate;
parameter s0=0;
parameter s2=1;
parameter s4=2;
parameter s14=3;
parameter s15=4;
always@(posedge clk)
begin
if (rst)
begin
nextstate=s0; num=0;end
else
case(nextstate)
s0:begin
nextstate=s2;num=0; end
s2:begin
nextstate=s4; num=2;end
s4:begin
nextstate=s14;num=4; end
s14:begin
nextstate=s15; num=14;end
s15:begin
nextstate=s0; num=15;end
 default:begin
nextstate=s0; num=0;end
endcase
end
endmodule
*/
//33
/*
module count(clk,rst,a,b,c,d,out);
input clk,rst;
output reg[4:0]out=0;
output reg[4:0]a=0,c=0;
output reg b=0,d=0;
always @(posedge clk)
begin
if(rst) a=0;
else
begin
a=a+1;
if(a==6)
a=0;
end
b=a[2]&a[0];
end
always @(posedge b)
begin
c=c+1;
if(c==10)
c=0;
d=c[3]&c[0];
end
always @(posedge d)
begin
out=out+1;
if(out==25)
out=0;
end
endmodule
*/