49e90 Compal LA-6973P PDF

A B C D E
1 1
Compal Confidential
2 2
P5WS5 Schematics Document

AMD Sabine
APU Llano / Hudson M3 / Vancouver Whistler_Seymour
DIS only / UMA only / PX Muxless with BACO
3 3
2011-04-20
LA-6973P REV: 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P5WS5 LA-6973P
Date: Wednesday, April 20, 2011 Sheet 1 of 50
A B C D E
A B C D E
ZZZ1 ZZZ2
Compal Confidential PCB 46@

Part Number = DAZ0JU00100
PCB P5WS5 LA-6973P LS-6902P/6905P/6973P HDMI+HDCP LOGO
Model Name : P5WS5 RO0000003HM
1
VRAM 512M/1G/2G
64M16/128M16 x 8
page 18, 19
Sabine 1
DDR3
Thermal Sensor ATI Vancuver Whistler/ Seymour GFX x 16 Gen2
ADM1032 Mahattan Granville
page 14
uFCBGA-962 GFX x 4 (Group 1~4)
AMD FS1 APU Memory BUS(DDR3)
Page 13~17 204pin DDRIII-SO-DIMM X2
APU HDMI Dual Channel
VGA VGA VGA
(UMA / Muxless) Llano BANK 0, 1, 2, 3 Page 11,12
1.5V DDRIII 800~1600MHz
HDMI LVDS(eDP) CRT DP x1 (DP0 TXP/N0)
uPGA-722 Package
HDMI Conn.
page 23
DP x2 Page 6~10
Travis LVDS (DP0 TXP/N 0~1)
LVDS
2 LVDS Conn. Translator DP x 4 2
page 21 P_GPP x 3
Reserve eDP GEN2 (DP1 TXP/N 0~4) UMI
page 22 USB20 USB20/B USB30/B CMOS Bluetooth Mini Mini
UAM eDP
M/B*1 *2 *1 Camera Conn.
Card 1 Card 2
page 34 page 35 page 35 page 22 page 35 page 33 page 33
CRT Conn. FCH CRT (VGA DAC) Port 0 Port 1 Port 3 Port5 FSD0 Port 8 Port 9
page 24 FCH USB
Port 2
3.3V 48MHz
GPP1 GPP0
Hudson-M2/M3
HD Audio 3.3V 24.576MHz/48Mhz Port 6
uFCBGA-656 Port 7
MINI Card 1 LAN(GbE) S-ATA Gen2
WLAN BCM57785 Page 25~29 3G/B
page 33 page 31
GPP x 2 port 0 port 1 port 2 *2
3
LPC BUS 3
GEN2 page 35
SATA HDD1 SATA HDD2 ODD HDA Codec
RJ45
page 32 Conn. Conn. Conn. ALC271X page
page 30 page page 30 38
LED
page 37 ENE KB930
page 36
RTC CKT. USB30 USB30
page 25
On SUB/B On M/B Touch Pad Int.KBD
page 35 page 34 page 37 page 37
Power On/Off CKT. External board
page 37
LID SW - Power/B EC I/O Buffer
page 37
Fan Control
4
page 30 4
USB20/B
BIOS ROM
DC/DC -USB20 x2 page 35
Interface CKT.page SYS BIOS (2M)
39 page 27 Security Classification Compal Secret Data Compal Electronics, Inc.
USB30/B Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
-USB20 x1+ USB30 x1 Block Diagrams

Power Circuit EC BIOS (128K) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 40~48 page 35 page 37 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
P5WS5 LA-6973P 1.0
Date: Thursday, April 21, 2011 Sheet 2 of 50
A B C D E
5 4 3 2 1
CLOCK DISTRIBUTION DISPLAY DISTRIBUTION

: LVDS PATH
, : eDP PATH
: APU HDMI PATH
LVDS CONN
B_SODIMM
D A_SODIMM D
: VGA HDMI PATH
TXOUT[0:2]+/- TXOUT[1:2]+/-
TXCLK+/- I2CC_SCL/DA
TZOUT[0:2]+/-
TZCLK+/-
I2CC_SCL/DA TXOUT[1:2]+/-
AMD R
I2CC_SCL/DA
TXOUT[0:2]+/- TZOUT[0:2]+/-
ATI VGA TXCLK+/- TZCLK+/-
I2CC_SCL/DA
MEM_MB_CLK7_P/N
MEM_MB_CLK1_P/N
MEM_MA_CLK7_P/N
MEM_MA_CLK1_P/N
1066~1600MHz
1066~1600MHz
Whistler/Seymour/Granville
APU_TXOUT[0:2]+/-
C
APU_TXOUT[1:2]+/- R R
APU_TXOUT_CLK+/-
APU_TZOUT[0:2]+/- APU_LVDS_CLK/DATA
CLK_PEG_VGAP/N
APU_TZOUT_CLK+/-
100MHz APU_LVDS_CLK/DATA
Place near
the pin
C
APU_DISP_CLKP/N
C
AMD 100MHz AMD LVDS_OUT C
RTD2132 DP0_TXP/N[0:1]_R VGA_TXOUT[1:2]+/-
CPU FS1 SOCKET

FCH DP_IN
DP0_AUXP/N_R VGA_LCD_CLK/DATA
APU_CLKP/N Hudson-M2/M3 VGA_TXOUT[0:2]+/- VGA_TZOUT[0:2]+/-
VGA_TXCLK+/- VGA_TZCLK+/-
100MHz Internal CLK GEN R
VGA_LCD_CLK/DATA
Place near
the pin
DP0_AUX GPP_CLK
100MHz
LVDS Transtator 32.768KHz 25MHz

R
C
DP0_TXP/N[0:1]
DP0_AUXP/N
B B
GPP4 GPP3 GPP2 GPP1 GPP0 DP0 DPE DPF
PCIE_GFX[0:11] C
USB30 M/B USB30 SUS/B WLAN WLAN GbE LAN APU VGA
OPT PCI Socket Mini PCI Socket PCIE_GFX[12:15] C PCIE_GFX[0:15]
DP1 R DAC1 DPA
25MHz
FCH
R R
R R
A A
CRT CONN HDMI CONN
Security Classification Compal Secret Data

CLOCK / DISPLAY DISTRIBUTION
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom P5WS5 LA-6973P 1.0
Date: W ednesday, April 20, 2011 Sheet 3 of 50
5 4 3 2 1
A B C D E
Voltage Rails
SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for CPU ON OFF OFF
1
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 1
+CPU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.0VSG 1.0V switched power rail for VGA ON OFF OFF
+1.1ALW 1.1V switched power rail for FCH ON ON ON* Board ID / SKU ID Table for AD channel
+1.1VS 1.1V switched power rail for FCH ON OFF OFF Vcc 3.3V +/- 5%
+1.2VS 1.2V switched power rail for APU ON OFF OFF Ra/Rc/Re 100K +/- 5% BOARD ID Table
+1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max Board ID PCB Revision
+1.5VS 1.5V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V 0 NA
+1.8VSG 1.8V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 1 P5WS5
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V 2 P5WH5
+3VALW 3.3V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V 3 P7YE5
+3V_LAN 3.3V power rail for LAN ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V 4 P7YS5
+3VS 3.3V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V 5 NA
+5VALW 5V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V 6 NA
2
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V 7 NA 2
+VSB VSB always on power rail ON ON ON*

+RTCVCC RTC power ON ON ON
BTO Option Table WHIS@ U8 M3@ U25 M2@ U25
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOM Structure BTO Item
UMA@ Display output from APU (UMA only or Mux)
UMAO@ UMA only VGA FCH M3 A13 FCH M2 A13
Part Number = SA00004C720 Part Number = SA000043IB0 Part Number = SA000042C60
APULVDS@ APU output LVDS (UMA only or Mux)
TL@ Translator (UMA only or Mux) BOM Config
APUEDP@ APU output eDP
VGA@ Use VGA (Mux or DIS only)
DISO@ Display output from VGA (DIS only)
x = 1 is read cmd, x= 0 is writee cmd. VAN@ Use Vancouver VGA
MAN@ Use Manhattan VGA
External PCI Devices
GRAN@ Use Granville VGA
Device IDSEL# REQ#/GNT# Interrupts SEYM@ WHIS@ VGA P/N
PX@ WOPX@ With & Without PX function
3 3
BACO@ BACO function (Mux)
WOBACO@ Without BACO function (Mux)
VGALVDS@ VGA output LVDS (DIS only)
VGAEDP@ VGA output eDP (DIS only)
128@ Use VRAM channel A&B
X76@ VRAM ID Table
EC SM Bus1 address EC SM Bus2 address
M2@ Use Hudson-M2
Device Address HEX Device Address HEX M3@ Use Hudson-M3
Smart Battery 0001 011X b 16H ADI ADM1032 (VGA) 1001 101X b 9AH EDP@ Use eDP display (Shared components)
USB30@ USB30 on M/B
USB20@ USB20 on M/B
3G@ With 3G function
930@ Use EC 930
9012@ Use EC 9012
ZERO@ ZERO Power ODD function
FCH FCH
HDT@ HDT debug port
4 SM Bus 0 address SM Bus 1 address 4
Device Address HEX Device Address HEX

DDR DIMM1 1101 000X b D0
DDR DIMM2 1101 001X b D2
Notes List
B 1.0
P5WS5 LA-6973P
A B C D E
5 4 3 2 1
AMD APU FS1

BATTERY BATT+ PU3 PU19 +CPU_CORE
12.6V CHARGER ISL6267HRZ-T 0.7~1.475V VDD CORE 54A
+CPU_CORE
ISL6251AHAZ-T 0.7~1.475V VDDNB 27.5A
+CPU_CORE_NB +CPU_CORE_NB
+2.5VS +2.5VS VDDA 500mA
+2.5VS
+1.5V VDDIO 4.6A
PU13 +1.5V +1.5V
D AC ADAPTOR VIN RT8209MGQW +1.2VS VDDR 6.7A D
PU15 +1.2VS
19V 90W
APL5508
RAM DDRIII SODIMMX2
PU17 +1.2VS +1.5V VDD_MEM 4A
RT8209MGQW VTT_MEM 0.5A
B+ +0.75VS
PU4
+0.75VS
APL5336KAI +0.75VS
VGA ATI
+VGA_CORE Whistler/Seymour/Granville
PU10
+VGA_CORE 0.85~1.1V VDDC 47A
TPS51218DSCR
+VDDCI
0.9~1.0V VDDCI 4.6A
+VDDCI
DPLL_VDDC: 125 mA
PU14 +1.0VSG SPV10: 120 mA
+1.0VSG +1.0VSG
G9731G11U PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
VRAM 512/1GB/2GB
U41 +1.5VSG
+1.5VSG +1.5VSG VDDR1: 3400 mA 64M / 128Mx16 * 4 / 8
AO4430L
PU5 +1.1VALW
RT8209MGQW PLL_PVDD: 75 mA +1.5VSG 2.4 A
TSVDD: 20 mA
AVDD: 70 mA
C VDD1DI: 100 mA C
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
PU2 +3VALW
U40 PU7 VDD_CT: 110 mA
RT8205EGQW +1.8VSG +1.8VSG VDDR4: 170 mA
+5VALW SI4800 SY8033BDBC +1.8VSG PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
+3VS
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
+INVPWR_B+
+3VS
JUMP +3VSG A2VDD: 130 mA
U38 +3VSG +3VSG VDDR3: 60 mA
SI4800
LCD panel +5VS FCH AMD Hudson M2/M3

15.6"
VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
B+ 300mA U39 VDDCR_11: 1007 mA
AO4430L +1.1VS +1.1VS
+3.3 350mA +1.1VS VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA
+5VS VDDAN_11_USB_S: 140 mA

FAN Control VDDCR_11_USB_S: 197 mA
B
APL5607 +1.1VALW VDDAN_11_SSUSB_S: 282 mA B
+1.1VALW
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
+5VS 500mA VDDPL_11_SYS: 70 mA
Q63
SI2301
U54 +5VALW VDDIO_33_PCIGP: 131 mA
TPA2301DRG4 VDDPL_33_SYS: 47 mA
+USB_VCCA VDDPL_33_DAC: 20 mA
+3VS VDDPL_33_ML: 20 mA
+3VS +3VS VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
USB X3 VDDPL_33_SATA: 93 mA
+1.5VS
VDDIO_AZ_S: 26 mA
+5V
Dual+1
2.5A +3VALW VDDPL_33_SSUSB_S: 20 mA
+3VALW VDDPL_33_USB_S: 17 mA
+3VALW VDDAN_33_USB_S: 658 mA
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
SATA Audio Codec EC LAN VDDAN_33_HWM_S: 12 mA
HDD*1 ALC271X ENE KB930 BCM57785 Mini Card*2
ODD*1
VDDIO_33_GBE_S
+5V 3A +5V 45mA +3.3VALW 30mA +3.3VALW 201mA +1.5VS 500mA VDDCR_11_GBE_S
+3.3VS 3mA +3.3VS 1A GND VDDIO_GBE_S
+3.3V +3.3VS 25mA +3.3VALW 330mA
RTC
A RTC BAT VDDBT_RTC_G A
Bettary

POWER DELIVERY CHART
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom P5WS5 LA-6973P 1.0
5 4 3 2 1
A B C D E
<13> PCIE_GTX_C_FRX_P[0..15] PCIE_FTX_C_GRX_P[0..15] <13> APU To HDMI

<13> PCIE_GTX_C_FRX_N[0..15] PCIE_FTX_C_GRX_N[0..15] <13>
PCIE_FTX_GRX_P[12..15] <23>
JCPU1A CONN@
PCI EXPRESS PCIE_FTX_GRX_N[12..15] <23>

PCIE_GTX_C_FRX_P0 AA8 AA2 PCIE_FTX_GRX_P0 C917VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P0
P_GFX_RXP0 P_GFX_TXP0
PCIE_GTX_C_FRX_N0 AA9 AA3 PCIE_FTX_GRX_N0 C918VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N0
P_GFX_RXN0 P_GFX_TXN0
PCIE_GTX_C_FRX_P1 Y7 Y2 PCIE_FTX_GRX_P1 C919VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P1
1 PCIE_GTX_C_FRX_N1 PCIE_FTX_GRX_N1 C920VGA@ PCIE_FTX_C_GRX_N1 1
Y8
Y1 1 2 0.1U_0402_16V7K
PCIE_GTX_C_FRX_P2 W5 Y4 PCIE_FTX_GRX_P2 C921VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P2
PCIE_GTX_C_FRX_N2 W6 Y5 PCIE_FTX_GRX_N2 C922VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N2
PCIE_GTX_C_FRX_P3 W8 W2 PCIE_FTX_GRX_P3 C923VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P3
For UMA Mux.
PCIE_GTX_C_FRX_N3 W9 W3 PCIE_FTX_GRX_N3 C924VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N3
PCIE_GTX_C_FRX_P4 V7 V2 PCIE_FTX_GRX_P4 C925VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P4
PCIE_GTX_C_FRX_N4 V8 V1 PCIE_FTX_GRX_N4 C926VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N4
PCIE_GTX_C_FRX_P5 U5 V4 PCIE_FTX_GRX_P5 C927VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P5
PCIE_GTX_C_FRX_N5 U6 V5 PCIE_FTX_GRX_N5 C928VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N5
PCIE_GTX_C_FRX_P6 U8 U2 PCIE_FTX_GRX_P6 C929VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P6
GRAPHICS
PCIE_GTX_C_FRX_N6 U9 U3 PCIE_FTX_GRX_N6 C930VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N6
PCIE_GTX_C_FRX_P7 T7 T2 PCIE_FTX_GRX_P7 C931VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P7
PCIE_GTX_C_FRX_N7 T8 T1 PCIE_FTX_GRX_N7 C932VGA@ 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N7
PCIE_GTX_C_FRX_P8 R5 T4 PCIE_FTX_GRX_P8 C933 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P8
PCIE_GTX_C_FRX_N8 R6 T5 PCIE_FTX_GRX_N8 C934 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N8
CPU TSI interface level shift
PCIE_GTX_C_FRX_P9 R8 R2 PCIE_FTX_GRX_P9 C936 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P9 BSH111, the Vgs is:
2 PCIE_GTX_C_FRX_N9 PCIE_FTX_GRX_N9 PCIE_FTX_C_GRX_N9
min = 0.4V 2
R9 R3 C937 DISO@1 2 0.1U_0402_16V7K C935 1 2 0.1U_0402_16V4Z
P_GFX_RXN9 P_GFX_TXN9 Max = 1.3V
PCIE_GTX_C_FRX_P10 P7 P2 PCIE_FTX_GRX_P10 C938 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P10
+3VS 1 R535 2 1 R536 2
PCIE_GTX_C_FRX_N10 P8 P1 PCIE_FTX_GRX_N10 C939 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N10
P_GFX_RXN10 P_GFX_TXN10 31.6K_0402_1% 30K_0402_1%
PCIE_GTX_C_FRX_P11 N5 P4 PCIE_FTX_GRX_P11 C940 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P11
PCIE_GTX_C_FRX_N11 N6 P5 PCIE_FTX_GRX_N11 C941 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N11
2
G
Q9
PCIE_GTX_C_FRX_P12 N8 N2 PCIE_FTX_GRX_P12 C942 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P12
P_GFX_RXP12 P_GFX_TXP12 APU_SID 3 EC_SMB_DA 1
PCIE_GTX_C_FRX_N12 PCIE_FTX_GRX_N12 PCIE_FTX_C_GRX_N12
2 <8,26> APU_SID 1 2 EC_SMB_DA2 <14,21,36>
C943 DISO@1 2 0.1U_0402_16V7K @ R537 0_0402_5%
D
N9 N3
PCIE_GTX_C_FRX_P13 M7 M2 PCIE_FTX_GRX_P13 C944 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P13 BSH111 1N_SOT23-3
1
PCIE_GTX_C_FRX_N13 M8
M1 PCIE_FTX_GRX_N13 C945 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N13 To EC
To HDMI
2
G
PCIE_GTX_C_FRX_P14 L5 M4 PCIE_FTX_GRX_P14 C946 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P14 Q10
PCIE_GTX_C_FRX_N14 PCIE_FTX_GRX_N14 C947 DISO@1 PCIE_FTX_C_GRX_N14
0 APU_SIC 3 EC_SMB_CK 1
L6
M5 2 0.1U_0402_16V7K <8,26> APU_SIC 1 2 EC_SMB_CK2 <14,21,36>
@ R538 0_0402_5%
D
PCIE_GTX_C_FRX_P15 L8 L2 PCIE_FTX_GRX_P15 C948 DISO@1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P15
P_GFX_RXP15 P_GFX_TXP15 BSH111 1N_SOT23-3
PCIE_GTX_C_FRX_N15 PCIE_FTX_GRX_N15 PCIE_FTX_C_GRX_N15
CK
L9 L3 C949 DISO@1 2 0.1U_0402_16V7K
AC5 AD4 PCIE_FTX_DRX_P0 C950 1 2 0.1U_0402_16V7K

<31> PCIE_DTX_C_FRX_P0 P_GPP_RXP0 P_GPP_TXP0 PCIE_FTX_C_DRX_P0 <31>
GLAN
AC6 AD5 PCIE_FTX_DRX_N0 C951 1 2 0.1U_0402_16V7K
<31> PCIE_DTX_C_FRX_N0 P_GPP_RXN0 P_GPP_TXN0 PCIE_FTX_C_DRX_N0 <31>
3 PCIE_FTX_DRX_P1 C952 1 3
<33> PCIE_DTX_C_FRX_P1 AC8
P_GPP_RXP1 P_GPP_TXP1
AC2 2 0.1U_0402_16V7K PCIE_FTX_C_DRX_P1 <33>
WLAN
PCIE_FTX_DRX_N1 C953 1 2 0.1U_0402_16V7K
GPP
<33> PCIE_DTX_C_FRX_N1 AC9 AC3 PCIE_FTX_C_DRX_N1 <33>

P_GPP_RXN1 P_GPP_TXN1
AB7 AB2
Remove MINI2 P_GPP_RXP2 P_GPP_TXP2 Remove MINI2
AB8 AB1
P_GPP_RXN2 P_GPP_TXN2
AA5 AB4
P_GPP_RXP3 P_GPP_TXP3
AA6 AB5
P_GPP_RXN3 P_GPP_TXN3 Power Sequence of APU
AF8 AF1 UMI_FTX_MRX_P0 C956 1 2 0.1U_0402_16V7K
+1.5V
<25> UMI_MTX_C_FRX_P0 P_UMI_RXP0 P_UMI_TXP0 UMI_FTX_C_MRX_P0 <25>
AF7 AF2 UMI_FTX_MRX_N0 C957 1 2 0.1U_0402_16V7K
<25> UMI_MTX_C_FRX_N0 P_UMI_RXN0 P_UMI_TXN0 UMI_FTX_C_MRX_N0 <25>
+2.5VS Group A
UMI-LINK
AE6 AF5 UMI_FTX_MRX_P1 C958 1 2 0.1U_0402_16V7K

AE5 AF4 UMI_FTX_MRX_N1 C959 1 2 0.1U_0402_16V7K
AE9 AE3 UMI_FTX_MRX_P2 C960 1 2 0.1U_0402_16V7K
+1.5VS
AE8 AE2 UMI_FTX_MRX_N2 C961 1 2 0.1U_0402_16V7K
AD8 AD1 UMI_FTX_MRX_P3 C962 1 2 0.1U_0402_16V7K
+CPU_CORE
AD7 AD2 UMI_FTX_MRX_N3 C963 1 2 0.1U_0402_16V7K
Group B
+1.2VS 1 2 P_ZVDDP K5 K4 P_ZVSS 1 2
+CPU_CORE_NB
4 R539 196_0402_1% P_ZVDDP P_ZVSS R540 196_0402_1% 4
AMD_TOPEDO_FS-1
+1.2VS

AMD FS1 PCIE / UMI / TSI
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
1 1
JCPU1B CONN@ JCPU1C CONN@
<11> DDRA_SMA[15..0] MEMORY CHANNEL A DDRA_SDQ[63..0] <11> <12> DDRB_SMA[15..0] MEMORY CHANNEL B DDRB_SDQ[63..0] <12>
DDRA_SMA0 U20 E13 DDRA_SDQ0 DDRB_SMA0 T27 A14 DDRB_SDQ0
DDRA_SMA1 MA_ADD0 MA_DATA0 DDRA_SDQ1 DDRB_SMA1 MB_ADD0 MB_DATA0 DDRB_SDQ1
R20 J13 P24 B14
R21 H15 P25 D16
P22 J15 N27 E16
P21 H13 N26 B13
N24 F13 M28 C13
N23 MA_ADD6 MA_DATA6 F15 M27 MB_ADD6 MB_DATA6 B16
DDRA_SMA7 N20 E15 DDRA_SDQ7 DDRB_SMA7 M24 A16 DDRB_SDQ7
DDRA_SMA8 MA_ADD7 MA_DATA7 DDRB_SMA8 MB_ADD7 MB_DATA7
N21 MA_ADD8 M25 MB_ADD8
DDRA_SMA9 M21 H17 DDRA_SDQ8 DDRB_SMA9 L26 C17 DDRB_SDQ8
U23 MA_ADD10 MA_DATA9 F17 U26 MB_ADD10 MB_DATA9 B18
DDRA_SMA11 M22 E19 DDRA_SDQ10 DDRB_SMA11 L27 B20 DDRB_SDQ10
L24 MA_ADD12 MA_DATA11 J19 K27 MB_ADD12 MB_DATA11 A20
DDRA_SMA13 AA25 G16 DDRA_SDQ12 DDRB_SMA13 W26 E17 DDRB_SDQ12
L21 MA_ADD14 MA_DATA13 H16 K25 MB_ADD14 MB_DATA13 B17
DDRA_SMA15 L20 H19 DDRA_SDQ14 DDRB_SMA15 K24 B19 DDRB_SDQ14
MA_ADD15 MA_DATA14 DDRA_SDQ15 MB_ADD15 MB_DATA14 DDRB_SDQ15
MA_DATA15 F19 MB_DATA15 C19
DDRA_SBS0# U24 DDRB_SBS0# U27
<11> DDRA_SBS0# DDRA_SBS1# MA_BANK0 DDRA_SDQ16 <12> DDRB_SBS0# DDRB_SBS1# MB_BANK0 DDRB_SDQ16
<11> DDRA_SBS1# U21 MA_BANK1 MA_DATA16 H20 <12> DDRB_SBS1# T28 MB_BANK1 MB_DATA16 C21
DDRA_SBS2# L23 F21 DDRA_SDQ17 DDRB_SBS2# K28 B22 DDRB_SDQ17
<11> DDRA_SBS2# MA_BANK2 MA_DATA17 <12> DDRB_SBS2# MB_BANK2 MB_DATA17
J23 DDRA_SDQ18 C23 DDRB_SDQ18
<11> DDRA_SDM[7..0] DDRA_SDM0 MA_DATA18 DDRA_SDQ19 <12> DDRB_SDM[7..0] DDRB_SDM0 MB_DATA18 DDRB_SDQ19
E14 MA_DM0 MA_DATA19 H23 D14 MB_DM0 MB_DATA19 A24
DDRA_SDM1 J17 G20 DDRA_SDQ20 DDRB_SDM1 A18 D20 DDRB_SDQ20
DDRA_SDM2 MA_DM1 MA_DATA20 DDRA_SDQ21 DDRB_SDM2 MB_DM1 MB_DATA20 DDRB_SDQ21
E21 MA_DM2 MA_DATA21 E20 A22 MB_DM2 MB_DATA21 B21
DDRA_SDM3 F25 G22 DDRA_SDQ22 DDRB_SDM3 C25 E23 DDRB_SDQ22
DDRA_SDM4 MA_DM3 MA_DATA22 DDRA_SDQ23 DDRB_SDM4 MB_DM3 MB_DATA22 DDRB_SDQ23
AD27 MA_DM4 MA_DATA23 H22 AF25 MB_DM4 MB_DATA23 B23
DDRA_SDM5 AC23 DDRB_SDM5 AG22
2 DDRA_SDM6 MA_DM5 DDRA_SDQ24 DDRB_SDM6 MB_DM5 DDRB_SDQ24 2
AD19 MA_DM6 MA_DATA24 G24 AH18 MB_DM6 MB_DATA24 E24
DDRA_SDM7 AC15 E25 DDRA_SDQ25 DDRB_SDM7 AD14 B25 DDRB_SDQ25
MA_DM7 MA_DATA25 DDRA_SDQ26 MB_DM7 MB_DATA25 DDRB_SDQ26
MA_DATA26 G27 MB_DATA26 B27
DDRA_SDQS0 G14 G26 DDRA_SDQ27 DDRB_SDQS0 C15 D28 DDRB_SDQ27
<11> DDRA_SDQS0 DDRA_SDQS0# MA_DQS_H0 MA_DATA27 DDRA_SDQ28 <12> DDRB_SDQS0 DDRB_SDQS0# MB_DQS_H0 MB_DATA27 DDRB_SDQ28
<11> DDRA_SDQS0# H14 MA_DQS_L0 MA_DATA28 F23 <12> DDRB_SDQS0# B15 MB_DQS_L0 MB_DATA28 B24
DDRA_SDQS1 G18 H24 DDRA_SDQ29 DDRB_SDQS1 E18 D24 DDRB_SDQ29
<11> DDRA_SDQS1 DDRA_SDQS1# MA_DQS_H1 MA_DATA29 DDRA_SDQ30 <12> DDRB_SDQS1 DDRB_SDQS1# MB_DQS_H1 MB_DATA29 DDRB_SDQ30
<11> DDRA_SDQS1# H18 MA_DQS_L1 MA_DATA30 E28 <12> DDRB_SDQS1# D18 MB_DQS_L1 MB_DATA30 D26
DDRA_SDQS2 J21 F27 DDRA_SDQ31 DDRB_SDQS2 E22 C27 DDRB_SDQ31
<11> DDRA_SDQS2 DDRA_SDQS2# MA_DQS_H2 MA_DATA31 <12> DDRB_SDQS2 DDRB_SDQS2# MB_DQS_H2 MB_DATA31
<11> DDRA_SDQS2# H21 <12> DDRB_SDQS2# D22
DDRA_SDQS3 MA_DQS_L2 DDRA_SDQ32 DDRB_SDQS3 MB_DQS_L2 DDRB_SDQ32
<11> DDRA_SDQS3 E27 AB28 <12> DDRB_SDQS3 B26 AG26
DDRA_SDQS3# MA_DQS_H3 MA_DATA32 DDRA_SDQ33 DDRB_SDQS3# MB_DQS_H3 MB_DATA32 DDRB_SDQ33
<11> DDRA_SDQS3# E26 AC27 <12> DDRB_SDQS3# A26 AH26
DDRA_SDQS4 MA_DQS_L3 MA_DATA33 DDRA_SDQ34 DDRB_SDQS4 MB_DQS_L3 MB_DATA33 DDRB_SDQ34
<11> DDRA_SDQS4 AE26 AD25 <12> DDRB_SDQS4 AG24 AF23
<11> DDRA_SDQS4# AD26 AA24 <12> DDRB_SDQS4# AG25 AG23
<11> DDRA_SDQS5 AB22 AE28 <12> DDRB_SDQS5 AG21 AG27
<11> DDRA_SDQS5# AA22 AD28 <12> DDRB_SDQS5# AF21 AF27
<11> DDRA_SDQS6 AB18 AB26 <12> DDRB_SDQS6 AG17 AH24
<11> DDRA_SDQS6# AA18 AC25 <12> DDRB_SDQS6# AG18 AE24
DDRA_SDQS7 MA_DQS_L6 MA_DATA39 DDRB_SDQS7 MB_DQS_L6 MB_DATA39
<11> DDRA_SDQS7 AA14 <12> DDRB_SDQS7 AH14
DDRA_SDQS7# MA_DQS_H7 DDRA_SDQ40 DDRB_SDQS7# MB_DQS_H7 DDRB_SDQ40
<11> DDRA_SDQS7# AA15 Y23 <12> DDRB_SDQS7# AG14 AE22
MA_DQS_L7 MA_DATA40 DDRA_SDQ41 MB_DQS_L7 MB_DATA40 DDRB_SDQ41
AA23 AH22
DDRA_CLK0 MA_DATA41 DDRA_SDQ42 DDRB_CLK0 MB_DATA41 DDRB_SDQ42
<11> DDRA_CLK0 T21 Y21 <12> DDRB_CLK0 R26 AE20
DDRA_CLK0# MA_CLK_H0 MA_DATA42 DDRA_SDQ43 DDRB_CLK0# MB_CLK_H0 MB_DATA42 DDRB_SDQ43
<11> DDRA_CLK0# T22 AA20 <12> DDRB_CLK0# R27 AH20
DDRA_CLK1 MA_CLK_L0 MA_DATA43 DDRA_SDQ44 DDRB_CLK1 MB_CLK_L0 MB_DATA43 DDRB_SDQ44
<11> DDRA_CLK1 R23 AB24 <12> DDRB_CLK1 P27 AD23
DDRA_CLK1# MA_CLK_H1 MA_DATA44 DDRA_SDQ45 DDRB_CLK1# MB_CLK_H1 MB_DATA44 DDRB_SDQ45
<11> DDRA_CLK1# R24 AD24 <12> DDRB_CLK1# P28 AD22
MA_CLK_L1 MA_DATA45 DDRA_SDQ46 MB_CLK_L1 MB_DATA45 DDRB_SDQ46
AA21 AD21
DDRA_CKE0 MA_DATA46 DDRA_SDQ47 DDRB_CKE0 MB_DATA46 DDRB_SDQ47
<11> DDRA_CKE0 H28 AC21 <12> DDRB_CKE0 J26 AD20
DDRA_CKE1 MA_CKE0 MA_DATA47 DDRB_CKE1 MB_CKE0 MB_DATA47
<11> DDRA_CKE1 H27 <12> DDRB_CKE1 J27
MA_CKE1 DDRA_SDQ48 MB_CKE1 DDRB_SDQ48
AA19 AF19
DDRA_ODT0 MA_DATA48 DDRA_SDQ49 DDRB_ODT0 MB_DATA48 DDRB_SDQ49
<11> DDRA_ODT0 Y25 AC19 <12> DDRB_ODT0 W27 AE18
DDRA_ODT1 MA_ODT0 MA_DATA49 DDRA_SDQ50 DDRB_ODT1 MB_ODT0 MB_DATA49 DDRB_SDQ50
<11> DDRA_ODT1 AA27 AC17 <12> DDRB_ODT1 Y28 AE16
MA_ODT1 MA_DATA50 DDRA_SDQ51 MB_ODT1 MB_DATA50 DDRB_SDQ51
AA17 AH16
DDRA_SCS0# MA_DATA51 DDRA_SDQ52 DDRB_SCS0# MB_DATA51 DDRB_SDQ52
<11> DDRA_SCS0# V22 AB20 <12> DDRB_SCS0# V25 AG20
3 DDRA_SCS1# MA_CS_L0 MA_DATA52 DDRA_SDQ53 DDRB_SCS1# MB_CS_L0 MB_DATA52 DDRB_SDQ53 3
<11> DDRA_SCS1# AA26 Y19 <12> DDRB_SCS1# Y27 AG19
MA_CS_L1 MA_DATA53 DDRA_SDQ54 MB_CS_L1 MB_DATA53 DDRB_SDQ54
AD18 AF17
DDRA_SRAS# MA_DATA54 DDRA_SDQ55 DDRB_SRAS# MB_DATA54 DDRB_SDQ55
<11> DDRA_SRAS# V21 AD17 <12> DDRB_SRAS# V24 AD16
DDRA_SCAS# MA_RAS_L MA_DATA55 DDRB_SCAS# MB_RAS_L MB_DATA55
<11> DDRA_SCAS# W24 <12> DDRB_SCAS# V27
DDRA_SWE# MA_CAS_L DDRA_SDQ56 DDRB_SWE# MB_CAS_L DDRB_SDQ56
<11> DDRA_SWE# W23 AA16 <12> DDRB_SWE# V28 AG15
MA_WE_L MA_DATA56 DDRA_SDQ57 MB_WE_L MB_DATA56 DDRB_SDQ57
Y15 AD15
MEM_MA_RST# MA_DATA57 DDRA_SDQ58 MEM_MB_RST# MB_DATA57 DDRB_SDQ58
<11> MEM_MA_RST# H25 AA13 <12> MEM_MB_RST# J25 AG13
MEM_MA_EVENT# MA_RESET_L MA_DATA58 DDRA_SDQ59 MEM_MB_EVENT# MB_RESET_L MB_DATA58 DDRB_SDQ59
<11> MEM_MA_EVENT# T24 AC13 <12> MEM_MB_EVENT# T25 AD13
MA_EVENT_L MA_DATA59 DDRA_SDQ60 MB_EVENT_L MB_DATA59 DDRB_SDQ60
Y17 AG16
MA_DATA60 DDRA_SDQ61 MB_DATA60 DDRB_SDQ61
15mil MA_DATA61
AB16
DDRA_SDQ62 MB_DATA61
AF15
DDRB_SDQ62
+MEM_VREF W20 AB14 AE14
M_VREF MA_DATA62 DDRA_SDQ63 MB_DATA62 DDRB_SDQ63
Y13 AF13
MA_DATA63 MB_DATA63
1 2 M_ZVDDIO W21
+1.5V M_ZVDDIO
R541 39.2_0402_1%
AMD_TOPEDO_FS-1
Place them close to APU within 1"
AMD_TOPEDO_FS-1
EVENT# pull high 0.75V reference voltage +1.5V
+1.5V
2
4 R542 4
1K_0402_1%
R544 1 2 1K_0402_5% MEM_MA_EVENT# 15mil
1
R545 1 2 1K_0402_5% MEM_MB_EVENT# +MEM_VREF

2
1 2
R543 C964
1K_0402_1% C965 Security Classification Compal Secret Data Compal Electronics, Inc.
1000P_0402_50V7K 0.1U_0402_16V7K Issued Date 2010/08/04 2010/08/04 Title
2 1 Deciphered Date
AMD FS1 DDRIII I/F
1
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
Place near APU JCPU1D CONN@ Place near APU If not used, pins are left unconnected (DG ref.)
20101111
C971 1 2 0.1U_0402_16V7K DP0_TXP0 F2 D4 DP0_AUXP C972 1 2 0.1U_0402_16V7K To LVDS
<21> DP0_TXP0_C DP0_TXP0 DP0_AUXP DP0_AUXP_C <21> DP0_AUXP
UMA@ UMA@ R554 2 1 1.8K_0402_5%
To LVDS <21> DP0_TXN0_C
C973 1 2 0.1U_0402_16V7K DP0_TXN0 F1 D5 DP0_AUXN C974 1 2 0.1U_0402_16V7K DP0_AUXN_C <21>
Translator UMA@
UMA@ DP0_TXN0 DP0_AUXN UMA@ DP0_AUXN R555
eDP 2 1 1.8K_0402_5%
Translator UMA@
C966 1 2 0.1U_0402_16V7K DP0_TXP1 E3 E5 ML_VGA_AUXP C975 1 2 0.1U_0402_16V7K ML_VGA_AUXP R547 2 1 1.8K_0402_5%
<21> DP0_TXP1_C DP0_TXP1 DP1_AUXP ML_VGA_AUXP_C <27>
APUEDP@ UMA@ To FCH UMA@
DISPLAY PORT 0
C967 1 2 0.1U_0402_16V7K DP0_TXN1 E2 E6 ML_VGA_AUXN C976 1 2 0.1U_0402_16V7K ML_VGA_AUXN R556 2 1 1.8K_0402_5%
<21> DP0_TXN1_C DP0_TXN1 DP1_AUXN ML_VGA_AUXN_C <27>
APUEDP@ UMA@ UMA@
D2 J5
DP0_TXP2 DP2_AUXP
AUX 2~5 are for GFX interface
DISPLAY PORT MISC.

D1 J6 +1.2VS
1 DP0_TXN2 DP2_AUXN use, they could be selected to I2C 1
or AUX logic TEST25_L R548 1 2 510_0402_1%
C2 H4
DP0_TXP3 DP3_AUXP TEST25_H R557 1
VDDIO level 2 510_0402_1%
C3 H5 Need Level shift
DP0_TXN3 DP3_AUXN
+1.5V
Place near APU
G5
C977 1 DP1_TXP0 DP4_AUXP TEST35
<27> ML_VGA_TXP0 2 0.1U_0402_16V7K K2
DP1_TXP0
R558 1 2 300_0402_5%
UMA@ G6
C968 1 DP1_TXN0 DP4_AUXN
<27> ML_VGA_TXN0 2 0.1U_0402_16V7K K1
DP1_TXN0
R559 1 @ 2 300_0402_5%
UMA@ TEST35 change to PU for HDMI can not output
F4 APU_HDMI_CLK 20110126
DP1_TXP1 DP5_AUXP APU_HDMI_CLK <23> +1.5V
C969 1 2 0.1U_0402_16V7K J3
<27> ML_VGA_TXP1 DP1_TXP1 APU_HDMI_DATA
UMA@ F5
DISPLAY PORT 1
DP1_TXN1 DP5_AUXN APU_HDMI_DATA <23> M_TEST
C970 1 2 0.1U_0402_16V7K J2 R564 1 @ 2 39.2_0402_1%
<27> ML_VGA_TXN1 DP1_TXN1
UMA@
To FCH VGA ML D7 DP0_HPD LVDS/eDP VDDIO level R567 1 2 39.2_0402_1%
DP0_HPD DP0_HPD <10>
C978 1 2 0.1U_0402_16V7K DP1_TXP2 H2
<27> ML_VGA_TXP2 DP1_TXP2 DP1_HPD
Need Level shift
UMA@ E7 CRT FS1R1 : Control S5 Dual PWR plane
DP1_TXN2 DP1_HPD DP1_HPD <10> +3VALW
C979 1 2 0.1U_0402_16V7K H1 In laptop, seems no use
<27> ML_VGA_TXN2 DP1_TXN2
UMA@ J7
DP2_HPD FS1R1 R571 1
System DP 2 10K_0402_5%
C980 1 2 0.1U_0402_16V7K DP1_TXP3 G2 H7
<27> ML_VGA_TXP3 DP1_TXP3 DP3_HPD
UMA@
C981 1 2 0.1U_0402_16V7K DP1_TXN3 G3 G7 Del T4 / T5
<27> ML_VGA_TXN3 DP1_TXN3 DP4_HPD +1.5V
UMA@ Allow_STOP change to PU +1.5V for+1.5VS leakage current
F7 DP5_HPD Change to Port 5 for AMD req. 20110208
DP5_HPD DP5_HPD <23> +1.5VS
201012031500 HDMI R604 1 2 1K_0402_5%
APU_CLKP AH7
<25> APU_CLKP CLKIN_H
100MHz C6 DP_ENBKL VDDIO level ALLOW_STOP R577 1 @ 2 1K_0402_5%
APU_CLKN DP_BLON DP_ENBKL <10>
<25> APU_CLKN AH6 CLKIN_L Need Level shift
2 DP_ENVDD APU_RST# R578 1 2
DP_DIGON C5 DP_ENVDD <10> MISC 2 300_0402_5%
CLK
APU_DISP_CLKP AH4 C7 DP_INT_PWM APU_PWRGD R580 1 2 300_0402_5%
<25> APU_DISP_CLKP DISP_CLKIN_H DP_VARY_BL DP_INT_PWM <10>
100MHz_NSS APU_DISP_CLKN
<25> APU_DISP_CLKN AH3 DISP_CLKIN_L
D8 DP_AUX_ZVSS R569 1 2 150_0402_1%
DP_AUX_ZVSS +1.5V +3VS
Asserted as an input to force the
APU_SVC B8 Chang to unpop (DG ref.) processor into the HTC-active state
<48> APU_SVC SVC
AA10 20101111
TEST6
1
APU_SVD A8
<48> APU_SVD SVD
2
R573 1 @ 2 0_0402_5% R587 R588
SER.
G10
TEST9 R586 10K_0402_5% 10K_0402_5%
APU_SIC AH11 H10 1K_0402_5%
<6,26> APU_SIC SIC TEST10
TSI
2 2
2
APU_SID AG11 H12 R574 1 2 1K_0402_5%
<6,26> APU_SID
1
SID TEST12
B
D9 T6 Q11
TEST14 APU_PROCHOT#
E
1 2 1 3 EC_THERM# <25,36,48>
APU_RST# R598 1 2 0_0402_5% APU_RST#_APU @ R591 0_0402_5%
C
<25> APU_RST# AF10 E9 T7
RESET_L TEST15 MMBT3904_NL_SOT23-3
APU_PWRGD R615 1 2 0_0402_5% APU_PWRGD_APU AE10 G9 +1.5V
<25> APU_PWRGD PWROK TEST16 T8
H9 T9
APU_PROCHOT# TEST17 THERMTRIP shutdown Indicates to the FCH that a thermal trip
AD10
PROCHOT_L
1
Add C35 / C36 / C38 / C40 for ESD 20110313 H11 APU_TEST18 R582 1 2 1K_0402_5% temperature: 125 degree has occurred. Its assertion will cause the FCH to
CTRL
APU_THERMTRIP# TEST18
Change C38,C40 from 10P to 33P for ESD 20110416 AG12 transition the system to S5 immediately
THERMTRIP_L
2
APU_RST# G11 APU_TEST19 R583 1 2 1K_0402_5%
C40 33P_0402_50V8J ALERT_L TEST19 R610
AH12
APU_PWRGD ALERT_L APU_TEST20 R584 1
F12 2 1K_0402_5% R609
2 2
C38 33P_0402_50V8J TEST20 1K_0402_5% 10K_0402_5%
B
2 1 APU_PROCHOT# E11 APU_TEST21 R585 1 2 1K_0402_5%
1
3 C36 22P_0402_50V8J T21 TDI TEST21 Q12 3
Delete for ESD
TEST
C12
TDI
E
2 1 APU_THERMTRIP# D11 APU_TEST22 R589 1 2 1K_0402_5% APU_THERMTRIP# 3 1 1 2
20110416 TEST22 H_THERMTRIP# <26>
C
C35 22P_0402_50V8J T22 TDO A12 R611 0_0402_5%
TDO MMBT3904_NL_SOT23-3
Chang to PU +1.5V (AMD req.)
Add Test point T25 TCK TEST23
F10 T10 1
R612 @
2
0_0402_5%
MAINPWON <36,42,43>
A11
+1.5V 20110419 TCK APU_TEST24 R590 1 Q11 / Q12 change to SB000006A00
20110127
TEST24
G12 2 1K_0402_5%
T26 TMS D12 20101228
JTAG
TMS TEST25_H
AH10
R575 1 APU_SVC TRST# TEST25_H
2 1K_0402_5% T32 B12
TRST_L TEST25_L
Serial VID TEST25_L
AH9
HDT Debug conn
R576 1 2 1K_0402_5% APU_SVD T33 DBRDY B11
DBRDY
T34 DBREQ# C11 TEST28_H
K7 Delete for ESD 20110416
+1.5V DBREQ_L
K8
TEST28_L
R579 1 2 1K_0402_5% APU_SIC AA12
TEST30_H T11
E8
R581 1 APU_SID RSVD_1
2 1K_0402_5% AB12 T12
TEST30_L
K21
RSVD
R791 1 ALERT_L RSVD_2 M_TEST

2 1K_0402_5% K22
TEST31
AC11
RSVD_3
AB11 T13
R597 1 TEST32_H
<48> APU_VDDNB_RUN_FB_L 2 0_0402_5%
Route as differential TEST32_L
AA11 T14
with VSS_SENSE R600 1 2 0_0402_5% B9
<48> APU_VDD_RUN_FB_L VSS_SENSE TEST35
D10
TEST35
C8
VDDP_SENSE
APU_VDDNB_SEN A9
<48> APU_VDDNB_SEN VDDNB_SENSE
Y11 FS1R1
SENSE
FS1R1
B10
VDDIO_SENSE ALLOW_STOP
DMAACTIVE_L AB10 ALLOW_STOP <25>
4 APU_VDD_SEN 4
<48> APU_VDD_SEN C9 VDD_SENSE
Close to Header A10 VDDR_SENSE THERMDA AE12 T15
Delete for ESD 20110416 AD12 T16
THERMDC
Llano do not support this thermal die
AMD_TOPEDO_FS-1
AMD FS1 Display / MISC / HDT
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
Power Name Consumption

VDD
+CPU_CORE 54A CPU BOTTOM SIDE DECOUPLING
VDDNB JCPU1F CONN@
+CPU_CORE
+CPU_CORE_NB 27.5A 22U Change to SE000000I10
VDDIO A7 VSS VSS T11
+1.5V 4.6A A13 VSS VSS T19
C982
22U_0805_6.3V6M
C996
22U_0805_6.3V6M
C983
22U_0805_6.3V6M
C984
22U_0805_6.3V6M
C997
22U_0805_6.3V6M
C985
22U_0805_6.3V6M
C986
22U_0805_6.3V6M
C987
0.22U_0603_16V4Z
C988
0.22U_0603_16V4Z
C989
0.01U_0402_16V7K
C998
0.01U_0402_16V7K
C990
0.01U_0402_16V7K
C991
180P_0402_50V8J
C992
180P_0402_50V8J
C993
330U_D2_2VY_R7M
C994
330U_D2_2VY_R7M
C999
330U_D2_2VY_R7M
C995
330U_D2_2VY_R7M
2160mil 2160mil 1 1 1 1 A15 VSS VSS U4
VDDP / VDDR JCPU1E CONN@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A17 U7
+CPU_CORE +CPU_CORE + + + + VSS VSS
+1.2VS 3A / 3.7A A19
A21
VSS VSS
U10
U18
VSS VSS
VDDA C1
VDD VDD
T6
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A23
VSS VSS
V9
1 1
+2.5VS 0.5A D3
D6
VDD VDD
T10
T18
A25
B7
VSS VSS
V11
V19
VDD VDD VSS VSS
E1 U1 C4 W4
VDD VDD VSS VSS
CORE_NB CPU_CORE F3
VDD VDD
U11 C10
VSS VSS
W7
F6 U19 C14 W10
330uF X 2 330uF X 4 F8
VDD VDD
V3 C16
VSS VSS
W12
VDD VDD +CPU_CORE_NB +CPU_CORE VSS VSS
22uF X 4 22uF X 11 G1
VDD VDD
V6
For there phase
C18
VSS VSS
W14
H3 V10 C20 W16
VDD VDD VSS VSS
H6 V18 20101225 C22 W18
VDD VDD VSS VSS
H8 W1 Delete 3 phase SKU C24 Y9
VDD VDD VSS VSS
C1000
22U_0805_6.3V6M
C1001
22U_0805_6.3V6M
C1002
22U_0805_6.3V6M
C1003
22U_0805_6.3V6M
C1004
0.22U_0603_16V4Z
C1005
0.22U_0603_16V4Z
C1006
180P_0402_50V8J
C1007
180P_0402_50V8J
C1008
180P_0402_50V8J
C1009
330U_D2_2VY_R7M
C1010
330U_D2_2VY_R7M
C29
330U_D2_2VY_R7M
C30
330U_D2_2VY_R7M
J1 W11 1 1 1 1 20110419 C26 Y22
VDD VDD VSS VSS
K3 VDD VDD W13 1 1 1 1 1 1 1 1 1 C28 VSS VSS AA4
K6 W15 + + + + D13 AA7
VDD VDD VSS VSS
L1 VDD VDD W17 D15 VSS VSS AB9
L11 W19 @ @ D17 AB13
VDD VDD 2 2 2 2 2 2 2 2 2 2 2 2 2 VSS VSS
L19 VDD VDD Y3 D19 VSS VSS AB15
M3 VDD VDD Y6 D21 VSS VSS AB17
M6 Y10 Delete C1011 D23 AB19
VDD VDD 20101101 VSS VSS
N1 VDD VDD Y16 E4 VSS VSS AB25
N11 Y18 +1.5V E10 AB27
VDD VDD VSS VSS
N19 VDD VDD Y20 E12 VSS VSS AC4
P3 VDD VDD AA1 F9 VSS VSS AC7
P6 VDD VDD AB3 F11 VSS VSS AC10
C1012
22U_0805_6.3V6M
C1013
22U_0805_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C1018
0.22U_0603_16V4Z
C1019
0.22U_0603_16V4Z
C1020
0.22U_0603_16V4Z
C1021
0.22U_0603_16V4Z
C1022
0.22U_0603_16V4Z
C1023
0.22U_0603_16V4Z
C1024
180P_0402_50V8J
C1025
180P_0402_50V8J
330U_D2_2VY_R7M
P10 VDD VDD AB6 1 F14 VSS VSS AC12
C14
C15
C16
C17
C5
P18 VDD VDD AC1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F16 VSS VSS AC14
R1 AD3 + F18 AC16
VDD VDD VSS VSS
R11 VDD VDD AD6 F20 VSS VSS AC18
R19 VDD VDD AE1 F22 VSS VSS AC20
T3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 F24 AC22
VDD VSS VSS
F26 VSS VSS AC24
2 C5 change to D2 type 2
1120mil 1120mil 201011241030
F28 VSS VSS AC26
+CPU_CORE_NB J9 VDDNB VDDNB K11 +CPU_CORE_NB G4 VSS VSS AC28
J10 VDDNB VDDNB K12 G8 VSS VSS AD9
J11 VDDNB VDDNB K13 G13 VSS VSS AD11
J12 VDDNB VDDNB K14 G15 VSS VSS AE4
K9 K18 G21 AE15
VDDNB VDDNB +1.5V VSS VSS
K10 L18 G23 AE17
VDDNB VDDNB VSS VSS
G25 AE19
VSS VSS
200mil 200mil J4
VSS VSS
AE21
+1.5V G28 R22 +1.5V J8 AE23
VDDIO VDDIO VSS VSS
C1027
0.22U_0603_16V4Z
C1028
0.22U_0603_16V4Z
C1029
180P_0402_50V8J
C1030
180P_0402_50V8J
H26 R25 J18 AE25
VDDIO VDDIO VSS VSS
J28 R28 1 1 1 1 J20 AE27
VDDIO VDDIO VSS VSS
K20 T20 J22 AF3
VDDIO VDDIO VSS VSS
K23 T23 J24 AF6
VDDIO VDDIO VSS VSS
K26 T26 K19 AF9
VDDIO VDDIO 2 2 2 2 VSS VSS
L22 U22 L4 AF12
VDDIO VDDIO VSS VSS
L25 U25 L7 AF14
VDDIO VDDIO VSS VSS
L28 U28 L10 AF16
VDDIO VDDIO VSS VSS
M20
VDDIO VDDIO
V20 Decoupling between CPU and DIMMs M9
VSS VSS
AF18
M23 V23 across VDDIO and VSS split M11 AF20
VDDIO VDDIO VSS VSS
M26 V26 M19 AF22
VDDIO VDDIO VSS VSS
N22 W22 N4 AF24
VDDIO VDDIO VSS VSS
N25 W25 N7 AF26
VDDIO VDDIO VSS VSS
N28 W28 N10 AF28
VDDIO VDDIO VSS VSS
P20 Y24 N18 AG10
VDDIO VDDIO VSS VSS
P23
VDDIO VDDIO
Y26 VDDP decoupling P9
VSS VSS
AH5
P26 AA28 P11 AH8
VDDIO VDDIO +1.2VS VSS VSS
P19 AH13
+1.2VS VSS VSS
120mil 120mil R4
VSS VSS
AH15
+1.2VS AG2 A3 R7 AH17
VDDP_A_1 VDDP_B_1 VSS VSS
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
180P_0402_50V8J
180P_0402_50V8J
0.22U_0603_16V4Z
0.22U_0603_16V4Z
3 3
AG3 A4 R10 AH19
C1034
C1035
C1036
C1037
AG4 B3 1 R18 AH21
C8
C7
C6
AG5 B4 1 1 1 1 1 1 1 T9 AH23
VDDP_A_4 VDDP_B_4 + C1038 VSS VSS
AH25
220U_6.3V_M VSS
160mil 160mil
+1.2VS AG6 A5
VDDR VDDR 2 2 2 2 2 2 2 2
AG7 A6
VDDR VDDR AMD_TOPEDO_FS-1
AG8 B5
VDDR VDDR
AG9 B6
+2.5VS VDDR VDDR C1038 change to SF000002Y00
L1 20101228
40mil
FBMA-L11-201209-221LMA30T_0805 AE11
VDDA VDDA
2 1 AF11
VDDA VDDR decoupling
+1.2VS
C1040
3300P_0402_50V7K
C1041
0.22U_0603_16V4Z
C18
47U_0805_4V6
C1043
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
C1044
C1045
C1046
C1047
C1048
C1049
C1050
C1051
1 1 1
1
AMD_TOPEDO_FS-1 1 1 1 1 1 1 1 1
Keep trace from resistor to APU
within 0.6"
2
2 2 2
Keep trace from Caps to APU 2 2 2 2 2 2 2 2
within 1.2"
Del C1039
201012061900
Demo Board Capacitor (include PWM side)
C18 Change to 47U CPU_CORE CORE_NB VDDIO_SUS VDDIO_SUS VDDP/R_PWM VDDP VDDR
20110124
470uF x 6 470uF x 4 (CPU side) (DIMM x2) 470uF x 2 10uF x 3 4.7uF x 4
C1052
0.22U_0603_16V4Z
C1053
0.22U_0603_16V4Z
C1054
0.22U_0603_16V4Z
C1055
0.22U_0603_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C10
C11
C12
1 1 1 1 1 1 1 2 22uF x 9 22uF x 6 680uF x 1 100uF x 4 10uF x 1 0.22uF x 2 0.22uF x 4

0.22uF x 2 0.22uF x 2 330uF x 1 0.1uF 180pF x 2 1nF x 4
C13
4 2 2 2 2 2 2 2 1 180uF x 2 180uF x 3 22uF x 3 180pF x 4 4

10nF x 3 4.7uF x 4
0.22uF x 6
180pF x 4

AMD FS1 PWR / GND
Custom 1.0
P5WS5 LA-6973P
A B C D E
5 4 3 2 1
HPD +5VS +1.5VS

Panel ENBKL +3VS
1
UMA@ UMA@ UMA@
2
R68 R53 R614
4.7K_0402_5% 1K_0402_5% UMA@ 4.7K_0402_5%
R617
2
D DP0_HPD 100K_0402_5% APU_ENBKL D
DP0_HPD <8>
Translator and eDP HPD
1
6
3
From Translator or Conn.
1
D @ D16
2 UMA@ 2 1 PLT_RST# <25,36>
LVDS_HPD 2 UMA@ 5 UMA@ G Q14
<21,22> LVDS_HPD
MMBT3904_NL_SOT23-3
Q92A Q92B UMA@ S 2N7002_SOT23
3
CH751H-40PT_SOD323-2
1
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 UMA@ Q15 C
4
<8> DP_ENBKL 1 2 2
R619 2.2K_0402_5% B
2
E
3
UMA@
R620
+5VS +1.5VS 100K_0402_5%
1
1
2
UMA@ UMA@
R71 R69
4.7K_0402_5% 1K_0402_5%
2
1
CRT HPD DP1_HPD
DP1_HPD <8> APU_ENBKL
From FCH R624 1 UMA@ 2 0_0402_5% ENBKL <36>
6
3
R625 1 DISO@ 2 0_0402_5%
<14> VGA_ENBKL
FCH_CRT_HPD 2 UMA@ 5 UMA@
<27> FCH_CRT_HPD
Q94A Q94B
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
1
4 Panel ENVDD
C +3VS C
HDMI HPD
1
Page 23
2
@
@ R632
R631 4.7K_0402_5%
100K_0402_5%
2
APU_ENVDD <22>
1
D
2 @
G Q18
MMBT3904_NL_SOT23-3
@ S 2N7002_SOT23
3
1
Q19 C
1 @ 2 2
<8> DP_ENVDD
R633 2.2K_0402_5% B
E
3
2
@
R634
100K_0402_5%
1
Panel PWM
B B
+3VS
1
UMA@ UMA@
R635 R636
47K_0402_5% 4.7K_0402_5%
2
APU_INVT_PWM <21,22>
1
D
2 UMA@
G Q20
MMBT3904_NL_SOT23-3
UMA@ S 2N7002_SOT23
3
1
UMA@ Q21 C
<8> DP_INT_PWM 1 2 2
R637 2.2K_0402_5% B
E
3
1
UMA@
R638
4.7K_0402_5%
Q15 / Q19 / Q21 change to SB000006A00
2
20101228
A A

AMD FS1 Singal Level Shifter
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
A B C D E
+VREF_DQ +1.5V +1.5V
15mil JDIMM1
1 VREF_DQ VSS1 2
3 4 DDRA_SDQ4 DDRA_SDQ[0..63]
DDRA_SDQ0 VSS2 DQ4 DDRA_SDQ5 DDRA_SDQ[0..63] <7>
5 DQ0 DQ5 6
DDRA_SDQ1 7 8 DDRA_SDM[0..7]
DQ1 VSS3 DDRA_SDM[0..7] <7>
9 10 DDRA_SDQS0#
DDRA_SDM0 VSS4 DQS#0 DDRA_SDQS0 DDRA_SDQS0# <7> DDRA_SMA[0..15]
11 DM0 DQS0 12 DDRA_SDQS0 <7> DDRA_SMA[0..15] <7>
13 VSS5 VSS6 14
DDRA_SDQ2 15 16 DDRA_SDQ6
DDRA_SDQ3 DQ2 DQ6 DDRA_SDQ7
17 18
DQ3 DQ7
19 20
1 DDRA_SDQ8 VSS7 VSS8 DDRA_SDQ12 1
21 22
23 24
DQ9 DQ13
25 26
DDRA_SDQS1# VSS9 VSS10 DDRA_SDM1
<7> DDRA_SDQS1# 27 28
DDRA_SDQS1 DQS#1 DM1 MEM_MA_RST#
<7> DDRA_SDQS1 29
DQS1 RESET#
30 MEM_MA_RST# <7> Place near DIMM1
31 32
DDRA_SDQ10 VSS11 VSS12 DDRA_SDQ14
33 34
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15 +1.5V
35 36
DQ11 DQ15
37 38
DDRA_SDQ16 VSS13 VSS14 DDRA_SDQ20 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
39 40
41 42 2 2 2 2 2 2 2 2 2 2
DQ17 DQ21
43 VSS15 VSS16 44
DDRA_SDQS2# 45 46 DDRA_SDM2 C1067 C1068 C1069 C1070 C1071 C1072 C1073 C1074 C1075 C1076
<7> DDRA_SDQS2# DDRA_SDQS2 DQS#2 DM2
<7> DDRA_SDQS2 47 DQS2 VSS17 48
49 50 DDRA_SDQ22 1 1 1 1 1 1 1 1 1 1
DDRA_SDQ18 VSS18 DQ22 DDRA_SDQ23 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
51 DQ18 DQ23 52
DDRA_SDQ19 53 54
DQ19 VSS19 DDRA_SDQ28
55 VSS20 DQ28 56
DDRA_SDQ24 57 58 DDRA_SDQ29
DDRA_SDQ25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDRA_SDQS3#
DDRA_SDM3 VSS22 DQS#3 DDRA_SDQS3 DDRA_SDQS3# <7>
63 64 +0.75VS +1.5V
DM3 DQS3 DDRA_SDQS3 <7>
65 VSS23 VSS24 66
DDRA_SDQ26 67 68 DDRA_SDQ30 0.1U_0402_16V4Z 1 2
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31 C1106 0.1U_0402_16V4Z
69 DQ27 DQ31 70 2 2 1
71 VSS25 VSS26 72
C1077 C1078 C1079 Add C1106
20101101
1 1 2
DDRA_CKE0 73 74 DDRA_CKE1 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
<7> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <7>
75 VDD1 VDD2 76
77 78 DDRA_SMA15
2 DDRA_SBS2# NC1 A15 DDRA_SMA14 2
<7> DDRA_SBS2# 79 BA2 A14 80
81 VDD3 VDD4 82
DDRA_SMA12 83 84 DDRA_SMA11
DDRA_SMA9 A12/BC# A11 DDRA_SMA7
85 A9 A7 86
87 VDD5 VDD6 88
DDRA_SMA8 89 90 DDRA_SMA6
DDRA_SMA5 A8 A6 DDRA_SMA4
91 A5 A4 92
93 94
DDRA_SMA3 VDD7 VDD8 DDRA_SMA2 +VREF_CA +1.5V
95 96
DDRA_SMA1 A3 A2 DDRA_SMA0 +VREF_DQ +1.5V
97 98
A1 A0
99 100
VDD9 VDD10
2
DDRA_CLK0 101 102 DDRA_CLK1
<7> DDRA_CLK0 CK0 CK1 DDRA_CLK1 <7>
2
DDRA_CLK0# 103 104 DDRA_CLK1# R640
<7> DDRA_CLK0# CK0# CK1# DDRA_CLK1# <7>
105 106 R639 1K_0402_1%
DDRA_SMA10 VDD11 VDD12 DDRA_SBS1# 1K_0402_1%
107 108 DDRA_SBS1# <7>
DDRA_SBS0# A10/AP BA1 DDRA_SRAS#
<7> DDRA_SBS0# 109 110 DDRA_SRAS# <7> 15mil
1
BA0 RAS# +VREF_CA
111 112 15mil
1
DDRA_SWE# VDD13 VDD14 DDRA_SCS0# +VREF_DQ
113 114 DDRA_SCS0# <7>
<7> DDRA_SWE# WE# S0#
1000P_0402_50V7K
0.1U_0402_16V4Z
DDRA_SCAS# 115 116 DDRA_ODT0
<7> DDRA_SCAS# CAS# ODT0 DDRA_ODT0 <7>
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
117 118
VDD15 VDD16
1000P_0402_50V7K
4.7U_0603_6.3V6K
DDRA_SMA13 119 120 DDRA_ODT1 1 1 1
A13 ODT1 DDRA_ODT1 <7>
2
DDRA_SCS1# 121 122 1 1 1 @ C1064 C1065
<7> DDRA_SCS1# S1# NC2
C1063
123 124 15mil @ C1061 C1062 R642
VDD17 VDD18
C1060
125 126 +VREF_CA R641 1K_0402_1%
NCTEST VREF_CA 1K_0402_1% 2 2 2
127 128
DDRA_SDQ32 VSS27 VSS28 DDRA_SDQ36 2 2 2
129 130
1
131 132 1
1
DQ33 DQ37 C1066
133 134
<7> DDRA_SDQS4# 135 136
DDRA_SDQS4 DQS#4 DM4 1000P_0402_50V7K
<7> DDRA_SDQS4 137 138
DQS4 VSS31 DDRA_SDQ38 2
139 140
DDRA_SDQ34 VSS32 DQ38 DDRA_SDQ39
141 142
3 DDRA_SDQ35 DQ34 DQ39 3
143 144
145 146
147 148
149 150
DQ41 VSS35 DDRA_SDQS5#
151 152 DDRA_SDQS5# <7>
DDRA_SDM5 VSS36 DQS#5 DDRA_SDQS5
153 154 DDRA_SDQS5 <7>
DM5 DQS5
155 156
157 158
159 160
DQ43 DQ47
161 162
163 164
165 166
DQ49 DQ53
167 168
<7> DDRA_SDQS6# 169 170
DDRA_SDQS6 DQS#6 DM6
<7> DDRA_SDQS6 171 172
DQS6 VSS43 DDRA_SDQ54
173 174
175 176
177 178
179 180
181 182
183 184
DQ57 VSS47 DDRA_SDQS7#
185 186 DDRA_SDQS7# <7>
DDRA_SDM7 VSS48 DQS#7 DDRA_SDQS7
187 188 DDRA_SDQS7 <7>
DM7 DQS7
189 190
191 192
193 194
R643 10K_0402_5% DQ59 DQ63
195 196
VSS51 VSS52 MEM_MA_EVENT#
1 2 197 198 MEM_MA_EVENT# <7>
+3VS SA0 EVENT#
+3VS 199 200 FCH_SDATA0 <12,26,33>
VDDSPD SDA
201 202 FCH_SCLK0 <12,26,33>
SA1 SCL
203 204 +0.75VS
VTT1 VTT2
1
4 R645 4
1 1 205 G1 G2 206
C1080 C1081
10K_0402_5% CONN@
2.2U_0603_6.3V4Z 0.1U_0402_16V4Z SUYIN_600023HB204G256ZL
2
2 2

2010/08/04 2010/08/04 Title
DIMM_A STD H:8mm Change to SUYIN Issued Date Deciphered Date
DDRIII SO-DIMM 1
<Address: 00> SP07000N500 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
+VREF_DQ +1.5V +1.5V
15mil JDIMM2
1 VREF_DQ VSS1 2
3 4 DDRB_SDQ4 DDRB_SDQ[0..63]
DDRB_SDQ0 VSS2 DQ4 DDRB_SDQ5 DDRB_SDQ[0..63] <7>
5 DQ0 DQ5 6
DDRB_SDQ1 7 8 DDRB_SDM[0..7]
DQ1 VSS3 DDRB_SDM[0..7] <7>
9 10 DDRB_SDQS0#
DDRB_SDM0 VSS4 DQS#0 DDRB_SDQS0 DDRB_SDQS0# <7> DDRB_SMA[0..15]
11 DM0 DQS0 12 DDRB_SDQS0 <7> DDRB_SMA[0..15] <7>
13 VSS5 VSS6 14
DDRB_SDQ2 15 16 DDRB_SDQ6
DDRB_SDQ3 DQ2 DQ6 DDRB_SDQ7
17 18
DQ3 DQ7
19 20
1 DDRB_SDQ8 VSS7 VSS8 DDRB_SDQ12 1
21 22
23 24
DQ9 DQ13
25 26
DDRB_SDQS1# VSS9 VSS10 DDRB_SDM1
<7> DDRB_SDQS1# 27 28
DDRB_SDQS1 DQS#1 DM1 MEM_MB_RST#
<7> DDRB_SDQS1 29 30 MEM_MB_RST# <7>
DQS1 RESET#
31 32
DDRB_SDQ10 VSS11 VSS12 DDRB_SDQ14
33 34
35 36
DQ11 DQ15
37 38
39 40
41 42
DQ17 DQ21
DDRB_SDQS2#
43 VSS15 VSS16 44
DDRB_SDM2
Place near DIMM2
<7> DDRB_SDQS2# 45 DQS#2 DM2 46
DDRB_SDQS2 47 48
<7> DDRB_SDQS2 DQS2 VSS17 DDRB_SDQ22
49 50 +1.5V
DDRB_SDQ18 VSS18 DQ22 DDRB_SDQ23
51 DQ18 DQ23 52
DDRB_SDQ19 53 54 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DQ19 VSS19 DDRB_SDQ28
55 VSS20 DQ28 56 2 2 2 2 2 2 2 2 2 2
DDRB_SDQ25 DQ24 DQ29 C1089 C1090 C1091 C1092 C1093 C1094 C1095 C1096 C1097 C1098
59 DQ25 VSS21 60
61 62 DDRB_SDQS3#
DDRB_SDM3 VSS22 DQS#3 DDRB_SDQS3 DDRB_SDQS3# <7> 1 1 1 1 1 1 1 1 1 1
63 DM3 DQS3 64 DDRB_SDQS3 <7>
65 66 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
67 DQ26 DQ30 68
DQ27 DQ31
71 VSS25 VSS26 72
+0.75VS +1.5V +1.5V

DDRB_CKE0 73 74 DDRB_CKE1
<7> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <7>
75 76 0.1U_0402_16V4Z 1 2
VDD1 VDD2 DDRB_SMA15 C1107 0.1U_0402_16V4Z
77 NC1 A15 78 2 2 1
1
2 DDRB_SBS2# DDRB_SMA14 2
<7> DDRB_SBS2# 79 BA2 A14 80
81 82 C1099 C1100 C1101 Add C1107 +@
DDRB_SMA12 VDD3 VDD4 DDRB_SMA11 20101101 C9
83 A12/BC# A11 84
DDRB_SMA9 DDRB_SMA7 1 1 2 330U_2.5V_M_R15
85 86
2
A9 A7 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
87 VDD5 VDD6 88
DDRB_SMA8 89 90 DDRB_SMA6 C1102 change to OSCON
DDRB_SMA5 A8 A6 DDRB_SMA4 20101101
91 A5 A4 92
93 94
DDRB_SMA3 VDD7 VDD8 DDRB_SMA2
95 96
DDRB_SMA1 A3 A2 DDRB_SMA0
97 98
A1 A0
99 100
DDRB_CLK0 VDD9 VDD10 DDRB_CLK1
101 102 DDRB_CLK1 <7>
<7> DDRB_CLK0 DDRB_CLK0# CK0 CK1 DDRB_CLK1#
103 104 DDRB_CLK1# <7>
<7> DDRB_CLK0# CK0# CK1#
105 106
DDRB_SMA10 VDD11 VDD12 DDRB_SBS1#
107 108 DDRB_SBS1# <7>
DDRB_SBS0# A10/AP BA1 DDRB_SRAS#
<7> DDRB_SBS0# 109 110 DDRB_SRAS# <7>
BA0 RAS#
111 112
DDRB_SWE# VDD13 VDD14 DDRB_SCS0#
113 114 DDRB_SCS0# <7>
<7> DDRB_SWE# DDRB_SCAS# WE# S0# DDRB_ODT0
<7> DDRB_SCAS# 115 116 DDRB_ODT0 <7>
CAS# ODT0
117 118
DDRB_SMA13 VDD15 VDD16 DDRB_ODT1
119 120 DDRB_ODT1 <7>
DDRB_SCS1# A13 ODT1 +VREF_DQ +VREF_CA
121 122
<7> DDRB_SCS1# S1# NC2
123
VDD17 VDD18
124 15mil
125
NCTEST VREF_CA
126 +VREF_CA 15mil +VREF_DQ
15mil +VREF_CA
127 128
129 130
DQ32 DQ36
1000P_0402_50V7K
1000P_0402_50V7K
DDRB_SDQ33 131 132 DDRB_SDQ37 1
DQ33 DQ37
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
133 134 C1088
DDRB_SDQS4# VSS29 VSS30 DDRB_SDM4 1000P_0402_50V7K
<7> DDRB_SDQS4# 135 136 1 1 1 1 1 1
DDRB_SDQS4 DQS#4 DM4 C1083 C1084 C1086 C1087
<7> DDRB_SDQS4 137 138
DQS4 VSS31 2
C1082
C1085
139 140 DDRB_SDQ38
141 142
3 DDRB_SDQ35 DQ34 DQ39 2 2 2 2 2 2 3
143 144
145 146
147 148
DDRB_SDQ41 DQ40 DQ45
149 150
DQ41 VSS35 DDRB_SDQS5#
151 152 DDRB_SDQS5# <7>
DDRB_SDM5 VSS36 DQS#5 DDRB_SDQS5
153 154 DDRB_SDQS5 <7>
DM5 DQS5
155 156
157 158
159 160
DQ43 DQ47
161 162
163 164
165 166
DQ49 DQ53
167 168
DDRB_SDQS6# VSS41 VSS42 DDRB_SDM6
<7> DDRB_SDQS6# 169 170
DDRB_SDQS6 DQS#6 DM6
<7> DDRB_SDQS6 171 172
DQS6 VSS43 DDRB_SDQ54
173 174
175 176
177 178
179 180
181 182
183 184
DQ57 VSS47 DDRB_SDQS7#
185 186 DDRB_SDQS7# <7>
DDRB_SDM7 VSS48 DQS#7 DDRB_SDQS7
187 188 DDRB_SDQS7 <7>
DM7 DQS7
189 190
191 192
193 194
R646 10K_0402_5% DQ59 DQ63
195 196
VSS51 VSS52 MEM_MB_EVENT#
1 2 197 198 MEM_MB_EVENT# <7>
SA0 EVENT#
+3VS 199 200 FCH_SDATA0 <11,26,33>
VDDSPD SDA
201 202 FCH_SCLK0 <11,26,33>
SA1 SCL
203 204 +0.75VS
VTT1 VTT2
1
4 R648 4
205 G1 G2 206
10K_0402_5% FOX_AS0A626-U4SN-7F
CONN@
2

2010/08/04 2010/08/04 Title
DIMM_B STD H:4mm Issued Date Deciphered Date
DDRIII SO-DIMM 2
P/N: SP07000H800 Size Document Number Rev
<Address: 01> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
F/P: FOX_AS0A626-U4SN-7F_204P DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
P5WS5 LA-6973P
A B C D E
A B C D E
<DIGON> <VARY_BL>
Controls panel digital power on/off. LCD PWM (pulse width modulated)
GFX PCIE LANE REVERSAL Active High ,external PD need output to adjust LCD brightness
Active High ,external PD need
PCIE_FTX_C_GRX_P[0..15] U8A U8G
<6> PCIE_FTX_C_GRX_P[0..15] PCIE_GTX_C_FRX_P[0..15]
PCIE_FTX_C_GRX_N[0..15] PCIE_GTX_C_FRX_P[0..15] <6> R386 1 DISO@ 2 10K_0402_5%
<6> PCIE_FTX_C_GRX_N[0..15] PCIE_GTX_C_FRX_N[0..15]
PCIE_GTX_C_FRX_N[0..15] <6> LVDS CONTROL
VARY_BL AK27 VGA_INVT_PWM <22>
DIGON AJ27 VGA_ENVDD <22>
PCIE_FTX_C_GRX_P0 AA38 Y33 PCIE_GTX_FRX_P0 C580 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P0 R387 1 DISO@ 2 10K_0402_5%
1
PCIE_FTX_C_GRX_N0 PCIE_RX0P PCIE_TX0P PCIE_GTX_FRX_N0 C291 0.1U_0402_16V7K PCIE_GTX_C_FRX_N0 1
Y37 PCIE_RX0N PCIE_TX0N Y32 1 2
VGA@
VGA@ AK35
PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1
Y35 PCIE_RX1P PCIE_TX1P W 33 PCIE_GTX_FRX_P1
PCIE_GTX_FRX_N1
C247 1
C473
2 0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N AL36 Display Port F config
W 36 PCIE_RX1N PCIE_TX1N W 32 1 2
VGA@ TXOUT_U0P_DPF2P AJ38
VGA@ TXOUT_U0N_DPF2N AK37
PCIE_FTX_C_GRX_P2 W 38 U33 PCIE_GTX_FRX_P2 C572 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P2
PCIE_FTX_C_GRX_N2 PCIE_RX2P PCIE_TX2P PCIE_GTX_FRX_N2 C288 0.1U_0402_16V7K PCIE_GTX_C_FRX_N2
V37 PCIE_RX2N PCIE_TX2N U32 1 2 TXOUT_U1P_DPF1P AH35
VGA@ TXOUT_U1N_DPF1N AJ36
VGA@
PCIE_FTX_C_GRX_P3 V35 U30 PCIE_GTX_FRX_P3 C579 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P3 For UMA Mux. AG38
PCIE_FTX_C_GRX_N3 PCIE_RX3P PCIE_TX3P PCIE_GTX_FRX_N3 C316 0.1U_0402_16V7K PCIE_GTX_C_FRX_N3 TXOUT_U2P_DPF0P
U36 PCIE_RX3N PCIE_TX3N U29 1 2 TXOUT_U2N_DPF0N AH37
VGA@
VGA@ TXOUT_U3P AF35
PCIE_FTX_C_GRX_P4 U38 T33 PCIE_GTX_FRX_P4 C287 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P4 AG36
PCIE_FTX_C_GRX_N4 PCIE_RX4P PCIE_TX4P PCIE_GTX_FRX_N4 C228 0.1U_0402_16V7K PCIE_GTX_C_FRX_N4 TXOUT_U3N
T37 PCIE_RX4N PCIE_TX4N T32 1 2
PCI EXPRESS INTERFACE

VGA@
PCIE_FTX_C_GRX_P5 PCIE_GTX_FRX_P5 C224 1

VGA@
0.1U_0402_16V7K PCIE_GTX_C_FRX_P5
LVTMDP Display Port E config eDP
T35 PCIE_RX5P PCIE_TX5P T30 2
PCIE_FTX_C_GRX_N5 R36 T29 PCIE_GTX_FRX_N5 C576 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_N5 AP34 VGA_TXCLK+
PCIE_RX5N PCIE_TX5N TXCLK_LP_DPE3P VGA_TXCLK+ <22>
VGA@ AR34 VGA_TXCLK-
VGA_TXCLK- <22>
DP3
TXCLK_LN_DPE3N
VGA@
PCIE_FTX_C_GRX_P6 R38 P33 PCIE_GTX_FRX_P6 C295 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P6 AW 37 VGA_TXOUT0+
PCIE_RX6P PCIE_TX6P TXOUT_L0P_DPE2P VGA_TXOUT0+ <22>
PCIE_FTX_C_GRX_N6 P37 P32 PCIE_GTX_FRX_N6 C472 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_N6 AU35 VGA_TXOUT0-
VGA_TXOUT0- <22>
DP2
PCIE_RX6N PCIE_TX6N TXOUT_L0N_DPE2N
VGA@
VGA@ AR37 VGA_TXOUT1+
TXOUT_L1P_DPE1P VGA_TXOUT1+ <22>
PCIE_FTX_C_GRX_P7 P35 P30 PCIE_GTX_FRX_P7 C242 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P7 AU39 VGA_TXOUT1- DP1
PCIE_RX7P PCIE_TX7P TXOUT_L1N_DPE1N VGA_TXOUT1- <22>
PCIE_FTX_C_GRX_N7 N36 P29 PCIE_GTX_FRX_N7 C468 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_N7
PCIE_RX7N PCIE_TX7N VGA_TXOUT2+
2 VGA@ TXOUT_L2P_DPE0P AP35 VGA_TXOUT2+ <22> 2
VGA@ AR35 VGA_TXOUT2-
VGA_TXOUT2- <22>
DP0
PCIE_FTX_C_GRX_P8 PCIE_GTX_FRX_P8 C581 1 0.1U_0402_16V7K PCIE_GTX_C_FRX_P8 TXOUT_L2N_DPE0N
N38 PCIE_RX8P PCIE_TX8P N33 2
PCIE_FTX_C_GRX_N8 M37 N32 PCIE_GTX_FRX_N8 C286 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_N8 AN36
PCIE_RX8N PCIE_TX8N TXOUT_L3P
DISO@ TXOUT_L3N AP37
DISO@
PCIE_FTX_C_GRX_P9 M35 N30 PCIE_GTX_FRX_P9 C574 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P9
L36 PCIE_RX9N PCIE_TX9N N29 1 2
DISO@
DISO@ 2160809000A11SEYMOU_FCBGA962
PCIE_FTX_C_GRX_P10 L38 L33 PCIE_GTX_FRX_P10 C474 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P10 SEYM@
K37 PCIE_RX10N PCIE_TX10N L32 1 2
DISO@
DISO@
PCIE_FTX_C_GRX_P11 K35 L30 PCIE_GTX_FRX_P11 C337 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P11
J36 PCIE_RX11N PCIE_TX11N L29 1 2
DISO@
DISO@
PCIE_FTX_C_GRX_P12 J38 K33 PCIE_GTX_FRX_P12 C582 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P12
PCIE_FTX_C_GRX_N12 PCIE_RX12P PCIE_TX12P PCIE_GTX_FRX_N12 C578 0.1U_0402_16V7K PCIE_GTX_C_FRX_N12 +3VSG
H37 PCIE_RX12N PCIE_TX12N K32 1 2
DISO@
DISO@
PCIE_FTX_C_GRX_P13 H35 J33 PCIE_GTX_FRX_P13 C577 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P13
G36 PCIE_RX13N PCIE_TX13N J32 1 2
1
DISO@ @
DISO@ R394
PCIE_FTX_C_GRX_P14 G38 K30 PCIE_GTX_FRX_P14 C570 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P14 2.2K_0402_5% PX@
PCIE_FTX_C_GRX_N14 PCIE_RX14P PCIE_TX14P PCIE_GTX_FRX_N14 C571 0.1U_0402_16V7K PCIE_GTX_C_FRX_N14 U21
F37 PCIE_RX14N PCIE_TX14N K29 1 2
5
DISO@
2
DISO@ 2
P
3 <25> PE_GPIO0 B 3
PCIE_FTX_C_GRX_P15 F35 H33 PCIE_GTX_FRX_P15 C336 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P15 4 VGA_RST#
PCIE_FTX_C_GRX_N15 PCIE_RX15P PCIE_TX15P PCIE_GTX_FRX_N15 C197 0.1U_0402_16V7K PCIE_GTX_C_FRX_N15 Y
E37 PCIE_RX15N PCIE_TX15N H32 1 2 <25,31,33> APU_PCIE_RST# 1 A
G
DISO@
DISO@ Change to APU_PCIE_RST# (SCH ref.)
3
20101111 NC7SZ08P5X_NL_SC70-5
CLOCK
<25> CLK_PEG_VGA AB35 PCIE_REFCLKP
<25> CLK_PEG_VGA# AA36 PCIE_REFCLKN 1 DISO@ 2
R159 0_0402_5%
CALIBRATION
Y30 VGA_PCIE_CALRP R388 1 2 1.27K_0402_1%
PCIE_CALRP VGA@
2 1 AH16 Y29 VGA_PCIE_CALRN R390 1 2 2K_0402_1% +1.0VSG
R389 VGA@ 10K_0402_5% PW RGOOD PCIE_CALRN VGA@
VGA_RST# AA30 PERSTB
2160809000A11SEYMOU_FCBGA962
SEYM@
4 4

Vancouver_ PCIE / LVDS
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
U8B
Strap Name Pin Straps description <all internal PD> Setting +3VSG External VGA Thermal Sensor
VIP Device Strap Enable indicates to the software driver (Internal PD) Don't have this strap on U9 VGA@
VIP_DEVICE_EN V2SYNC 0: Driver would ignore the value sampled on VHAD_0 during reset 0 AU24 1 8 VGA_SMB_CK2
Whistler and Seymour TXCAP_DPA3P VGA_HDMI_TXC+ <23> VDD SCLK
(GENLK_VSYNC) 1: VHAD_0 to determine whether or not a VIP slave device TXCAM_DPA3N AV23 VGA_HDMI_TXC- <23> 1 VGA@
0.1U_0402_16V4Z
C324
GPU_THERM_D+ 2 7 VGA_SMB_DA2
2200P_0402_50V7K D+ SDATA
VGA Disable determines (Internal PD) TX0P_DPA2P AT25 VGA_HDMI_TXD0+ <23>
VGA_DIS GPIO9 0: VGA Controller capacity enabled 0 MUTI GFX AR24 1 2 3 6 THM_ALERT#
DPA TX0M_DPA2N VGA_HDMI_TXD0- <23> 2 D- ALERT#
1: The device will not be recognized as the system’s VGA controller C325 VGA@
AU26 GPU_THERM_D- 4 5 1 2
TX1P_DPA1P VGA_HDMI_TXD1+ <23> THERM# GND +3VSG
Transmitter Power Saving Enable (Internal PD) AV25 R391 VGA@ 4.7K_0402_5%
TX1M_DPA1N VGA_HDMI_TXD1- <23>
TX_PWRS_ENB GPIO0 0: 50% Tx output swing 1
1: full Tx output swing AR8 AT27 ADM1032ARMZ-2REEL_MSOP8
NC_DVPCNTL_MVP_0 TX2P_DPA0P VGA_HDMI_TXD2+ <23>
NC on Park, AU8 NC_DVPCNTL_MVP_1 TX2M_DPA0N AR26 VGA_HDMI_TXD2- <23>
PCI Express Transmitter De-emphasis Enable (Internal PD) AP8
TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled 1 Robson and Seymour AW8
NC_DVPCNTL_0
AR30 +3VSG
NC_DVPCNTL_1 TXCBP_DPB3P
1: Tx de-emphasis enabled NC on Park, Robson AR3
NC_DVPCNTL_2 TXCBM_DPB3N
AT29
AR1 +3VSG
1
VRAM_ID0 NC_DVPCLK 1
GPIO13,12,11 (config 2,1,0) : (Internal PD) memory apertures AU1
DVPDATA_0 TX3P_DPB2P
AV31
2
CONFIG[2] GPIO13 a) If BIOS_ROM_EN = 1, then Config[2:0] defines VRAM_ID1 AU3 AU30
CONFIG[3:0] VRAM_ID2 DVPDATA_1 DPB TX3M_DPB2N
AW3 R392 R393
the ROM type. 128 MB 000 VRAM_ID3 DVPDATA_2
CONFIG[1] GPIO12 001 AP6 AR32 4.7K_0402_5% 4.7K_0402_5%
2
b) If BIOS_ROM_EN = 0, then Config[2:0] defines 256 MB 001 * AW5 AT31 VGA@ VGA@ VGA@
DVPDATA_4 TX4M_DPB1N
CONFIG[0] GPIO11 the primary memory aperture size. 64 MB 010 AU5
1
DVPDATA_5 VGA_SMB_CK2 EC_SMB_CK2
AR6 AT33 1 6 EC_SMB_CK2 <6,21,36>
BIOS_ROM_EN GPIO22 Enable external BIOS ROM device (Internal PD) AW6
DVPDATA_7 TX5M_DPB0N
AU32
0: Diable, 1: Enable 0 AU6 Q8A DMN66D0LDW-7_SOT363-6
DVPDATA_8
5
AT7 AU14
DVPDATA_9 TXCCP_DPC3P VGA@
AUD[1] HSYNC 00: No audio function; 10: Audio for DisplayPort only; AV7
DVPDATA_10 TXCCM_DPC3N
AV13
11 AN7 VGA_SMB_DA2 4 3 EC_SMB_DA2
01: Audio for DisplayPort and HDMI if adapter is detected; DVPDATA_11 EC_SMB_DA2 <6,21,36>
AUD(0) VSYNC 11: Audio for both DisplayPort and HDMI
AV9
DVPDATA_12 TX0P_DPC2P
AT15
AT9 AR14 Q8B DMN66D0LDW-7_SOT363-6
DVPDATA_13 TX0M_DPC2N
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on AR10
DVPDATA_14
BIF_GEN2_EN GPIO2 1= Advertises the PCI-E device as 5.0 GT/s capable at power-on 0 AW10 DPC AU16
DVPDATA_15 TX1P_DPC1P
5.0 GT/s capability will be controlled by software AU10
DVPDATA_16 TX1M_DPC1N
AV15
AP10
NC_DVPDATA_17
H2SYNC Internal use only. THIS PAD HAS AN INTERNAL AV11
NC_DVPDATA_18 TX2P_DPC0P
AT17
RESERVED (GENLK_CLK) NC on Park, AT11 AR16
PULL-DOWN AND MUST BE 0 V AT RESET. The NC_DVPDATA_19 TX2M_DPC0N
GPIO8 Robson and Seymour
AR12
NC_DVPDATA_20
pad may be left unconnected DNI AW12
NC_DVPDATA_21 NC_TXCDP_DPD3P
AU20
GPIO21 AU12
NC_DVPDATA_22 NC_TXCDM_DPD3N
AT19
AP12
NC_DVPDATA_23
AT21
NC_TX3P_DPD2P
Global Swap Lock on AJ21
SWAPLOCKA NC_TX3M_DPD2N
AR20
Multiple GPUs
AK21
SWAPLOCKB NC on Park,
VRAM ID
DPD AU22
+1.8VSG NC_TX4P_DPD1P
AV21 Robson and Seymour
NC_TX4M_DPD1N
GPIO5 fast-power reduction: I2C AT23
X76@ X76@ X76@ X76@ NC_TX5P_DPD0P
HW control will casue display disturb Move to NC_TX5M_DPD0N
AR22
1
1
10K_0402_5%
R426
10K_0402_5%
R427
10K_0402_5%
R428
10K_0402_5%
R429
AK26
should use SW method control DDCCLK_AUX3P,DDCDATA_AUX3N, SCL
AJ26
SDA Not share via for other GND
GPIO6 voltage control signal ,No use can NC
AD39 VGA_CRT_R <24>
GENERAL PURPOSE I/O R
AD37
2
VRAM_ID0 VGA_GPIO0 RB
DISCRETE ONLY AH20
GPIO_0
VRAM_ID1 VGA_GPIO1 AH18 AE36
GPIO_1 G VGA_CRT_G <24>
2 VRAM_ID2 VGA_GPIO2 AN16 AD35 2
VRAM_ID3 PD 100K at EC side VGA_GPIO3 GPIO_2 GB VGA_CRT_R R423 1 DISO@ 2 150_0402_1%
AH23
X76@ X76@ X76@ X76@ VGA_GPIO4 GPIO_3_SMBDATA VGA_CRT_G R424 1 DISO@ 2 150_0402_1%
<10> VGA_ENBKL AJ23 AF37 VGA_CRT_B <24>
GPIO_4_SMBCLK B
1
1
10K_0402_5%
R432
10K_0402_5%
R433
10K_0402_5%
R434
10K_0402_5%
R435
AH17 AE38 VGA_CRT_B R425 1 DISO@ 2 150_0402_1%

GPIO_5_AC_BATT DAC1 BB
AJ17
VGA_ENBKL GPIO_6
GPIO7 Controls backlight on/off. 2 DISO@ 1 AK17 AC36 VGA_CRT_HSYNC <24>
R413 10K_0402_5% GPIO_7_BLON HSYNC
Active High ,need external PD AJ13 AC38 VGA_CRT_VSYNC <24>
GPIO_8_ROMSO VSYNC
ROM AH15 HSYNC:VSYNC
2
GPIO_9_ROMSI
if GPIO22 High ,GPIO 11-13->CFG[0:2] AJ16
Config ROM type ,GPU has internal PD VGA_GPIO11 AK16
GPIO_10_ROMSCK
AB34 R414 1 2 499_0402_1% L8 11: Audio for both DisplayPort and HDMI
VGA_GPIO12 GPIO_11 RSET VGA@ BLM18AG121SN1D_0603 +3VSG
AL16
GPIO_12 10mil
GPIO6,15,16,20 VGA_GPIO13 AM16 70mA AVDD AD34 +AVDD 2 1 +1.8VSG
GPIO_13 VGA@ VGA@ VGA@ VGA@ VGA_CRT_VSYNC R417 1 DISO@ 2 10K_0402_5%
Voltage control signal AM14
GPIO_14_HPD2 AVSSQ
AE34 AUD Strap
22U_0805_6.3V6M
C331
GPU_VID0 AM13 10mil 1 1 1 VGA_CRT_HSYNC R418 1 DISO@ 2 10K_0402_5%
GPIO6,15 no use can NC <47> GPU_VID0 GPIO_15_PWRCNTL_0
1U_0402_6.3V6K
C329
0.1U_0402_16V4Z
C330
AK14 100mA VDD1DI AC33 +VDD1DI AMD ref:120ohm/0.3A
THM_ALERT# GPIO_16 VGA_HDMI_SDATA R419 1 DISO@ 2 10K_0402_5%
Thermal monitor interrupt AG30
GPIO_17_THERMAL_INT VSS1DI
AC34
<22> VGA_EDP_HPD VGA_EDP_HPD AN14 CRT,HDMI VGA_HDMI_SCLK R420 1 DISO@ 2 10K_0402_5%
+3VSG GPIO_18_HPD3 2 2 2
Critical temperature fault AM17
GPU_VID1 AL13
GPIO_19_CTF
AC30 L9 DDC VGA_CRT_CLK R421 1 DISO@ 2 10K_0402_5%
VGA_GPIO0 <47> GPU_VID1 GPIO_20_PWRCNTL_1 R2/NC VGA_CRT_DATA
R395 1 VGA@ 2 10K_0402_5% Reserved AJ14 AC31 NC on Whistler R422 1 DISO@ 2 10K_0402_5%
R396 VGA_GPIO1 GPIO_22_ROMCSB GPIO_21_BB_EN R2B/NC
1 VGA@ 2 10K_0402_5% AK13 2 1 +1.8VSG
R397 1 @ 2 10K_0402_5% VGA_GPIO2 External BIOS device AN13
GPIO_22_ROMCSB
AD30 VGA@ and Seymour
R398 @ 10K_0402_5% VGA_GPIO3 JTAG_TRSTB GPIO_23_CLKREQB G2/NC VGA@ 1 VGA@ 1 VGA@ 1 BLM18AG121SN1D_0603
1 2 ON(1)/OFF(0) inter PD AM23 AD31
JTAG_TRSTB G2B/NC
1U_0402_6.3V6K
C332
0.1U_0402_16V4Z
C333
10U_0603_6.3V6M
C334
R401 1 @ 2 10K_0402_5% VGA_GPIO4 T18 AN23 AMD ref:120ohm/0.3A
VGA_OPT_27M_R JTAG_TDI
Internal Debug AK23
JTAG_TCK B2/NC
AF30 SM010030010
JTAG_TMS AL24 AF31
VGA_GPIO11
no use can floating JTAG_TMS B2B/NC 2 2 2 200ma 120ohm@100mhz DCR 0.2
R405 1 VGA@ 2 10K_0402_5% T17 AM24
R406 @ 10K_0402_5% VGA_GPIO12 ON(1)/OFF(0) JTAG_TDO
1 2 AJ19
R408 @ 10K_0402_5% VGA_GPIO13 GENERICA
1 2 Stereo Sync AK19
GENERICB C/NC
AC32
R409 1 @ 2 3K_0402_5% GPIO_22_ROMCSB AJ20 AD32
no use can NC GENERICC Y/NC
AK20 AF32
HPD GENERICD COMP/NC
For ATI Cross fire AJ24
GENERICE_HPD4
AH26 DAC2
no use can NC NC_GENERICF_HPD5
Park NC pins AH24
NC_GENERICG_HPD6 H2SYNC/GENLK_CLK
AD29 T2
V2SYNC/GENLK_VSYNC
AC29 T3 Back compatibility(Manhattan)
VGA_HDMI_DET HPD AK24 10mil
<23> VGA_HDMI_DET HPD1
1 GRAN@ 2 JTAG_TRSTB AG31 +VDD2DI R77 1 GRAN@ 2 0_0402_5% +VDD1DI
R437 10K_0402_5% VDD2DI/NC VSS2DI R209 1 GRAN@ 2 0_0402_5%
100mA VSS2DI/NC
AG32 Whistler and Seymour
3
+3VSG 1 GRAN@ 2 JTAG_TMS
+1.8VSG R430 1 VGA@ 2 499_0402_1% 10mil Except A2VSSQ change to TSVSSQ, 3
R438 10K_0402_5% 20mil 100mA AG33 +A2VDD R70 1 GRAN@ 2 0_0402_5% +3VSG others are NC
R431 1 VGA@ A2VDD/NC
2 249_0402_1% 10mil
+3VSG 1 GRAN@ 2 2mA AD33 +A2VDDQ R256 1 GRAN@ 2 0_0402_5% +1.8VSG
R441 10K_0402_5% TESTEN <15> C335 +VGA_VREF AH13 A2VDDQ/NC
SM010030010 1 2 0.1U_0402_16V4Z 1 GRAN@1 GRAN@1 GRAN@
VREFG
1U_0402_6.3V6K
C342
0.1U_0402_16V4Z
C343
10U_0603_6.3V6M
C344
200ma 120ohm@100mhz DCR 0.2 AF33
VGA_OPT_27M_R A2VSSQ/TSVSSQ
<36> VGA_DBCLK 1 GRAN@ 2 VGA@
R442 0_0402_5% +1.8VSG
20mil 2 2 2
1 VGA@ L10 AA29 1 2
C349 +DPLL_PVDD R2SET/NC R436 VGA@ 715_0402_1%
2 1 AM32
12P_0402_50V8J BLM18AG121SN1D_0603 DPLL_PVDD
1 1 VGA@ 1 VGA@ AN32
DPLL_PVSS 75mA
0.1U_0402_16V4Z
C340
1U_0402_6.3V6K
C341
@ AMD ref:470ohm/1A VGA@

2 C339 DDC/AUX VGA_HDMI_SCLK
20mil PLL/CLOCK DDC1CLK
AM26
VGA_HDMI_SDATA
VGA_HDMI_SCLK <23>
10U_0603_6.3V6M AN31 AN26 HDMI
2 2 2 DPLL_VDDC DDC1DATA VGA_HDMI_SDATA <23>
External 500KHz 3.3V CLK 125mA
AM27
+1.0VSG 27MCLK AUX1P
AV33 AL27
VGA@ L11 XTALOUT AU34 XTALIN AUX1N
VGA@ +DPLL_VDDC XTALOUT
2 1 AM19
XTALOUT 27MCLK BLM18AG121SN1D_0603 DDC2CLK +3VSG
2 1 1 VGA@ 1 VGA@ 1 VGA@ DDC2DATA
AL19 GPIO8 Serial-ROM output from ROM. if GPIO22 High ,GPIO 11-13->CFG[0:2]
10U_0603_6.3V6M
C345
0.1U_0402_16V4Z
C346
1U_0402_6.3V6K
C347
R445 1M_0402_5% AMD ref:470ohm/1A XO_IN AW34

XO_IN
AN20 4.7K_0402_5% 2 DISO@ 1 R399 GPIO9 Serial-ROM input to ROM. Config ROM type ,GPU has internal PD
AUX2P
VGA@ Y3
2 2 2
XO_IN2 AW35
XO_IN2 AUX2N
AM20 4.7K_0402_5% 2 DISO@ 1 R400 GPIO10 Serial-ROM clock to ROM. if GPIO22 Low ,GPIO 11-13->CFG[0:2]
2 1
GPIO22 erternal BIOS-ROM enable Config Primary memory-aperture size
1
AL30 VGA_LCD_CLK
DDCCLK_AUX3P VGA_LCD_CLK <22>
27MHZ_16PF_X5H027000FG1H R443 R444
DDCDATA_AUX3N
AM30 VGA_LCD_DAT
VGA_LCD_DAT <22> LVDS CFG[3:0]
VGA@ VGA@ @ @ GPIO8,GPIO9,GPIO10 no use can NC
C353 C354 0_0402_5% 0_0402_5% 128MB 000
NC_DDCCLK_AUX4P
AL29 NC on Park, GPIO22
18P_0402_50V8J 18P_0402_50V8J AF29 AM29 256MB 001 *
2
AG29
DPLUS THERMAL NC_DDCDATA_AUX4N Robson and Seymour Enable need 3K PH ,no use must NC 64MB 010
DMINUS VGA_CRT_CLK
AN21 VGA_CRT_CLK <24>
DDCCLK_AUX5P VGA_CRT_DATA
GPU_THERM_D+ DDCDATA_AUX5N
AM21 VGA_CRT_DATA <24> CRT
AK32
GPU_THERM_D- TS_FDO
AJ30
DDC6CLK
AL31 AJ31
TS_A/NC DDC6DATA
Future ASIC call MLPS NC_DDCCLK_AUX7P
AK30 NC on Park,
AJ32 AK29
OLD ASIC is Fan PWM AJ33
TSVDD
20mA
NC_DDCDATA_AUX7N Robson and Seymour
4
TSVSS 4
+1.8VSG L12
BLM18AG121SN1D_0603 10mil 2160809000A11SEYMOU_FCBGA962
2 1 +TSVDD SEYM@
VGA@ 1 1 1
VGA@ VGA@ VGA@
10U_0603_6.3V6M
C350
1U_0402_6.3V6K
C351
0.1U_0402_16V4Z
C352
120ohm/0.3A
2 2 2

Vancouver_Strape/DP/HDMI//CRT
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
U8C U8D
DDR2 DDR2 DDR2 DDR2
GDDR3/GDDR5 GDDR5/GDDR3 MAA[0..12] GDDR3/GDDR5 GDDR5/GDDR3 MAB[0..12]
MDA[0..63] DDR3 DDR3 MAA[0..12] <18> MDB[0..63] DDR3 DDR3 MAB[0..12] <19>
<18> MDA[0..63] <19> MDB[0..63]
MDA0 C37 G24 MAA0 MDB0 C5 P8 MAB0
MDA1 NC_DQA0_0/DQA_0 NC_MAA0_0/MAA_0 MAA1 MDB1 DQB0_0/DQB_0 MAB0_0/MAB_0 MAB1
C35 J23 C3 T9
A35 H24 E3 P9
E34 J24 E1 N7
NC_DQA0_3/DQA_3 NC_MAA0_3/MAA_3 DQB0_3/DQB_3 MAB0_3/MAB_3
MEMORY INTERFACE A
MDA4 G32 H26 MAA4 MDB4 F1 N8 MAB4
NC_DQA0_4/DQA_4 NC_MAA0_4/MAA_4 DQB0_4/DQB_4 MAB0_4/MAB_4
MEMORY INTERFACE B
MDA5 D33 J26 MAA5 MDB5 F3 N9 MAB5
F32 H21 F5 U9
E32 G21 G4 U8
D31 H19 H5 Y9
F30 H20 H6 W9
1 MDA10 NC_DQA0_9/DQA_9 NC_MAA1_1/MAA_9 MAA10 MDB10 DQB0_9/DQB_9 MAB1_1/MAB_9 MAB10 1
C30 L13 J4 AC8
A30 G16 K6 AC9
MDA12 NC_DQA0_11/DQA_11 NC_MAA1_3/MAA_11 MAA12 A_BA[0..2] MDB12 DQB0_11/DQB_11 MAB1_3/MAB_11 MAB12 B_BA[0..2]
F28 J16 A_BA[0..2] <18> K5 AA7 B_BA[0..2] <19>
MDA13 NC_DQA0_12/DQA_12 NC_MAA1_4/MAA_12 A_BA2 MDB13 DQB0_12/DQB_12 MAB1_4/MAB_12 B_BA2
C28 H16 L4 AA8
+1.5VSG MDA14 NC_DQA0_13/DQA_13 NC_MAA1_5/MAA_13_BA2 A_BA0 MDB14 DQB0_13/DQB_13 MAB1_5/BA2 B_BA0
A28 J17 M6 Y8
MDA15 NC_DQA0_14/DQA_14 NC_MAA1_6/MAA_14_BA0 A_BA1 +1.5VSG MDB15 DQB0_14/DQB_14 MAB1_6/BA0 B_BA1
E28 H17 M1 AA9
MDA16 NC_DQA0_15/DQA_15 NC_MAA1_7/MAA_A15_BA1 DQMA#[0..7] MDB16 DQB0_15/DQB_15 MAB1_7/BA1 DQMB#[0..7]
D27 DQMA#[0..7] <18> M3 DQMB#[0..7] <19>
MDA17 NC_DQA0_16/DQA_16 DQMA#0 MDB17 DQB0_16/DQB_16 DQMB#0
F26 A32 M5 H3
NC_DQA0_17/DQA_17 NC_WCKA0_0/DQMA_0 DQB0_17/DQB_17 WCKB0_0/DQMB_0
1
MDA18 C26 C32 DQMA#1 MDB18 N4 H1 DQMB#1

NC_DQA0_18/DQA_18 NC_WCKA0B_0/DQMA_1 DQB0_18/DQB_18 WCKB0B_0/DQMB_1
1
R446 MDA19 A26 D23 DQMA#2 MDB19 P6 T3 DQMB#2
VGA@ MDA20 NC_DQA0_19/DQA_19 NC_WCKA0_1/DQMA_2 DQMA#3 R447 MDB20 DQB0_19/DQB_19 WCKB0_1/DQMB_2 DQMB#3
F24 E22 P5 T5
40.2_0402_1% MDA21 NC_DQA0_20/DQA_20 NC_WCKA0B_1/DQMA_3 DQMA#4 VGA@ MDB21 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 DQMB#4
15mil MDA22
C24
NC_DQA0_21/DQA_21 NC_WCKA1_0/DQMA_4
C14
DQMA#5 40.2_0402_1% MDB22
R4
DQB0_21/DQB_21 WCKB1_0/DQMB_4
AE4
DQMB#5
A24 A14 15mil T6 AF5
2
MVREFDA MDA23 NC_DQA0_22/DQA_22 NC_WCKA1B_0/DQMA_5 DQMA#6 MDB23 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 DQMB#6

E24 E10 T1 AK6
2
MDA24 NC_DQA0_23/DQA_23 NC_WCKA1_1/DQMA_6 DQMA#7 MVREFDB MDB24 DQB0_23/DQB_23 WCKB1_1/DQMB_6 DQMB#7
C22 NC_DQA0_24/DQA_24 NC_WCKA1B_1/DQMA_7 D9 U4 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 AK5
1
1 MDA25 A22 QSA[0..7] MDB25 V6 QSB[0..7]

NC_DQA0_25/DQA_25 QSA[0..7] <18> DQB0_25/DQB_25 QSB[0..7] <19>
1
GDDR5/DDR2/GDDR3 GDDR5/DDR2/GDDR3
0.1U_0402_16V4Z
C355
R448 VGA@ MDA26 F22 C34 QSA0 MDB26 V1 F6 QSB0

MDA27 NC_DQA0_26/DQA_26 NC_EDCA0_0/QSA_0/RDQSA_0 QSA1 MDB27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 QSB1
D21 NC_DQA0_27/DQA_27 NC_EDCA0_1/QSA_1/RDQSA_1 D29 1 V3 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 K3
0.1U_0402_16V4Z
C356
100_0402_1% VGA@ MDA28 A20 D25 QSA2 R449 VGA@ MDB28 Y6 P3 QSB2
2 MDA29 NC_DQA0_28/DQA_28 NC_EDCA0_2/QSA_2/RDQSA_2 QSA3 100_0402_1% MDB29 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 QSB3
F20 E20 Y1 V5
2
MDA30 NC_DQA0_29/DQA_29 NC_EDCA0_3/QSA_3/RDQSA_3 QSA4 VGA@ MDB30 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 QSB4

D19 E16 Y3 AB5
2
MDA31 NC_DQA0_30/DQA_30 NC_EDCA1_0/QSA_4/RDQSA_4 QSA5 2 MDB31 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 QSB5
E18 NC_DQA0_31/DQA_31 NC_EDCA1_1/QSA_5/RDQSA_5 E12 Y5 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AH1
MDA32 C18 J10 QSA6 MDB32 AA4 AJ9 QSB6
MDA33 NC_DQA1_0/DQA_32 NC_EDCA1_2/QSA_6/RDQSA_6 QSA7 MDB33 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 QSB7
A18 NC_DQA1_1/DQA_33 NC_EDCA1_3/QSA_7/RDQSA_7 D7 AB6 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 AM5
MDA34 F18 QSA#[0..7] MDB34 AB1 QSB#[0..7]
+1.5VSG NC_DQA1_2/DQA_34 QSA#[0..7] <18> DQB1_2/DQB_34 QSB#[0..7] <19>
MDA35 D17 A34 QSA#0 MDB35 AB3 G7 QSB#0
MDA36 NC_DQA1_3/DQA_35 NC_DDBIA0_0/QSA_0B/WDQSA_0 QSA#1 +1.5VSG MDB36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 QSB#1
A16 NC_DQA1_4/DQA_36 NC_DDBIA0_1/QSA_1B/WDQSA_1 E30 AD6 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 K1
MDA37 F16 E26 QSA#2 MDB37 AD1 P1 QSB#2
MDA38 NC_DQA1_5/DQA_37 NC_DDBIA0_2/QSA_2B/WDQSA_2 QSA#3 MDB38 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 QSB#3
D15 NC_DQA1_6/DQA_38 NC_DDBIA0_3/QSA_3B/WDQSA_3 C20 AD3 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 W4
1
MDA39 E14 C16 QSA#4 MDB39 AD5 AC4 QSB#4

NC_DQA1_7/DQA_39 NC_DDBIA1_0/QSA_4B/WDQSA_4 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4
1
R450 MDA40 F14 C12 QSA#5 MDB40 AF1 AH3 QSB#5
VGA@ MDA41 NC_DQA1_8/DQA_40 NC_DDBIA1_1/QSA_5B/WDQSA_5 QSA#6 R451 MDB41 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 QSB#6
D13 NC_DQA1_9/DQA_41 NC_DDBIA1_2/QSA_6B/WDQSA_6 J11 AF3 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AJ8
40.2_0402_1% 15mil MDA42 F12 F8 QSA#7 VGA@ MDB42 AF6 AM3 QSB#7
MDA43 NC_DQA1_10/DQA_42NC_DDBIA1_3/QSA_7B/WDQSA_7 40.2_0402_1% MDB43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
A12 15mil AG4
2
MVREFSA MDA44 NC_DQA1_11/DQA_43 ODTA0 MDB44 DQB1_11/DQB_43 ODTB0

2 D11 J21 ODTA0 <18> AH5 T7 ODTB0 <19> 2
2
MDA45 NC_DQA1_12/DQA_44 NC_ADBIA0/ODTA0 ODTA1 MVREFSB MDB45 DQB1_12/DQB_44 ADBIB0/ODTB0 ODTB1
F10 NC_DQA1_13/DQA_45 NC_ADBIA1/ODTA1 G19 ODTA1 <18> AH6 DQB1_13/DQB_45 ADBIB1/ODTB1 W7 ODTB1 <19>
1
1 MDA46 A10 MDB46 AJ4

NC_DQA1_14/DQA_46 DQB1_14/DQB_46
1
0.1U_0402_16V4Z
C357
R452 VGA@ MDA47 C10 H27 CLKA0 1 MDB47 AK3 L9 CLKB0

NC_DQA1_15/DQA_47 NC_CLKA0 CLKA0 <18> DQB1_15/DQB_47 CLKB0 CLKB0 <19>
0.1U_0402_16V4Z
C358
MDA48 G13 G27 CLKA0# R453 MDB48 AF8 L8 CLKB0#
NC_DQA1_16/DQA_48 NC_CLKA0B CLKA0# <18> DQB1_16/DQB_48 CLKB0B CLKB0# <19>
100_0402_1% VGA@ MDA49 H13 VGA@ MDB49 AF9
2 MDA50 NC_DQA1_17/DQA_49 CLKA1 100_0402_1% VGA@ MDB50 DQB1_17/DQB_49 CLKB1
J13 J14 CLKA1 <18> AG8 AD8 CLKB1 <19>
2
MDA51 NC_DQA1_18/DQA_50 NC_CLKA1 CLKA1# 2 MDB51 DQB1_18/DQB_50 CLKB1 CLKB1#

H11 H14 CLKA1# <18> AG7 AD7 CLKB1# <19>
2
MDA52 NC_DQA1_19/DQA_51 NC_CLKA1B MDB52 DQB1_19/DQB_51 CLKB1B
G10 AK9
MDA53 NC_DQA1_20/DQA_52 RASA0# MDB53 DQB1_20/DQB_52 RASB0#
G8 K23 RASA0# <18> AL7 T10 RASB0# <19>
MDA54 NC_DQA1_21/DQA_53 NC_RASA0B RASA1# MDB54 DQB1_21/DQB_53 RASB0B RASB1#
K9 K19 RASA1# <18> AM8 Y10 RASB1# <19>
MDA55 NC_DQA1_22/DQA_54 NC_RASA1B MDB55 DQB1_22/DQB_54 RASB1B
K10 AM7
MDA56 NC_DQA1_23/DQA_55 CASA0# MDB56 DQB1_23/DQB_55 CASB0#
G9 K20 CASA0# <18> AK1 W10 CASB0# <19>
MDA57 NC_DQA1_24/DQA_56 NC_CASA0B CASA1# MDB57 DQB1_24/DQB_56 CASB0B CASB1#
A8 K17 CASA1# <18> AL4 AA10 CASB1# <19>
MDA58 NC_DQA1_25/DQA_57 NC_CASA1B MDB58 DQB1_25/DQB_57 CASB1B
C8 AM6
MDA59 NC_DQA1_26/DQA_58 CSA0#_0 MDB59 DQB1_26/DQB_58 CSB0#_0
E8 K24 CSA0#_0 <18> AM1 P10 CSB0#_0 <19>
MDA60 NC_DQA1_27/DQA_59 NC_CSA0B_0 MDB60 DQB1_27/DQB_59 CSB0B_0
A6 K27 AN4 L10
C6 AP3
MDA62 NC_DQA1_29/DQA_61 CSA1#_0 MDB62 DQB1_29/DQB_61 CSB1#_0
E6 M13 CSA1#_0 <18> AP1 AD10 CSB1#_0 <19>
A5 K16 AP5 AC10
NC_DQA1_31/DQA_63 NC_CSA1B_1 DQB1_31/DQB_63 CSB1B_1
MVREFDA L18 K21 CKEA0 U10 CKEB0
+1.5VSG NC_MVREFDA NC_CKEA0 CKEA0 <18> CKEB0 CKEB0 <19>
MVREFSA L20 J20 CKEA1 MVREFDB Y12 AA11 CKEB1
NC_MVREFSA NC_CKEA1 CKEA1 <18> MVREFDB CKEB1 CKEB1 <19>
MVREFSB AA12
MVREFSB
1 VGA@ 2 L27
NC_MEM_CALRN0 NC_WEA0B
K26 WEA0#
WEA0# <18> WEB0B
N10 WEB0#
WEB0# <19>
R454 1 VGA@ 2 243_0402_1% N12 L15 WEA1# <14> TESTEN AB11 WEB1#
MEM_CALRN1 NC_WEA1B WEA1# <18> WEB1B WEB1# <19>
R455 1 VGA@ 2 243_0402_1% AG12 R459
R456 243_0402_1% NC_MEM_CALRN2 5.11K_0402_1%
1 VGA@ 2 M12 H23 MAA13 <18> 2 VGA@ 1 TESTEN AD28 T8 MAB13 <19>
R457 MEM_CALRP1 NC_MAA0_8 TESTEN MAB0_8
1 VGA@ 2 243_0402_1% M27 NC_MEM_CALRP0 NC_MAA1_8
J19
MAB1_8
W8
R458 1 VGA@ 2 243_0402_1% AH12 TEST_MCLK AK10 R461 10_0402_5%
GDDR5
NC_MEM_CALRP2 CLKTESTA
GDDR5
R460 243_0402_1% TEST_YCLK AL10 AH11 1 2 1 2

CLKTESTB DRAM_RST VRAM_RST# <18,19>
VGA@ R462 VGA@ 51.1_0402_1%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3 2 2 3
2
C360
C361
1
VGA@ VGA@ R463 VGA@ C359
VGA@
1 1 2160809000A11SEYMOU_FCBGA962 5.11K_0402_1% 120P_0402_50V8
2160809000A11SEYMOU_FCBGA962 SEYM@ 2
1
1
1
SEYM@
R464 R465
VGA@ VGA@ Place all these components very close
51.1_0402_1% 51.1_0402_1%
to GPU (Within 25mm) and
2
keep all component close to
each Other (within5mm) except Rser2
Note:
route 50ohms single-ended
and 100ohms diff
and keep short
REF137-03 suggest Park&Seymour is single channel for
memory (channel B only)
4 4

Vancouver_Memory
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
Seymour/Whistler ：
U8E PCIE_VDDR,PCIE_PVDD can combian to PCIE_VDDR
+1.5VSG
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ MEM I/O
1 SM010014520 3000ma 220ohm@100mhz DCR 0.04
1U_0402_6.3V6K
C363
PCIE
1 1 1 1 1 1 1 1 40mil
1U_0402_6.3V6K
C375
1U_0402_6.3V6K
C376
1U_0402_6.3V6K
C362
1U_0402_6.3V6K
C377
1U_0402_6.3V6K
C378
1U_0402_6.3V6K
C379
1U_0402_6.3V6K
C380
VGA@ + AC7 AA31 +PCIE_VDDR 2 1
VDDR1#1 PCIE_VDDR#1 +1.8VSG
C374 AD11 AA32 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ L13 VGA@
330U_2.5V_M VDDR1#2 PCIE_VDDR#2 FBMA-L11-201209-221LMA30T_0805
AF7 VDDR1#3 PCIE_VDDR#3 AA33 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2
0.1U_0402_16V4Z
C381
0.1U_0402_16V4Z
C382
1U_0402_6.3V6K
C364
1U_0402_6.3V6K
C383
1U_0402_6.3V6K
C365
10U_0603_6.3V6M
C384
AG10 VDDR1#4 PCIE_VDDR#4 AA34 220ohm/2A
AJ7 VDDR1#5 440mA PCIE_VDDR#5 V28
AK8 VDDR1#6 PCIE_VDDR#6 W29
C374 change to SF000002Z00 2 2 2 2 2 2
AL9 VDDR1#7 PCIE_VDDR#7 W30
20101228 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ G11 Y31
VDDR1#8 PCIE_VDDR#8
1U_0402_6.3V6K
C390
1 1 1 1 1 1 1 1 G14 VDDR1#9 PCIE_VDDR/PCIE_PVDD AB37
1U_0402_6.3V6K
C385
1U_0402_6.3V6K
C366
1U_0402_6.3V6K
C386
1U_0402_6.3V6K
C387
1U_0402_6.3V6K
C388
1U_0402_6.3V6K
C367
1U_0402_6.3V6K
C389
1 G17 VDDR1#10
1
G20 VDDR1#11 PCIE_VDDC#1 G30 +1.0VSG
G23 G31 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ For UMA only SKU
2 2 2 2 2 2 2 2 VDDR1#12 PCIE_VDDC#2
G26 H29 1 1 1 1 1 1 1 1 20110419
VDDR1#13 PCIE_VDDC#3
1U_0402_6.3V6K
C391
1U_0402_6.3V6K
C392
1U_0402_6.3V6K
C368
1U_0402_6.3V6K
C393
1U_0402_6.3V6K
C369
1U_0402_6.3V6K
C370
1U_0402_6.3V6K
C394
10U_0603_6.3V6M
C395
G29 VDDR1#14 PCIE_VDDC#4 H30
H10 J29
1
VGA@ VDDR1#15 PCIE_VDDC#5 UMAO@ UMAO@ UMAO@
J7 VDDR1#16 3400mA 2A PCIE_VDDC#6 J30
2 2 2 2 2 2 2 2
1U_0402_6.3V6K
C401
1 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 J9 VDDR1#17 PCIE_VDDC#7 L28 C391 C392 C393
10U_0603_6.3V6M
C396
10U_0603_6.3V6M
C371
10U_0603_6.3V6M
C372
10U_0603_6.3V6M
C373
10U_0603_6.3V6M
C397
1U_0402_6.3V6K
C398
1U_0402_6.3V6K
C399
1U_0402_6.3V6K
C400
K11 M28 0_0402_5% 0_0402_5% 0_0402_5%
VGA@ VDDR1#18 PCIE_VDDC#8
K13 N28
2
VDDR1#19 PCIE_VDDC#9
K8 VDDR1#20 PCIE_VDDC#10 R28
2 2 2 2 2 2 2 2 2
L12 VDDR1#21 PCIE_VDDC#11 T28
L16 VDDR1#22 PCIE_VDDC#12 U28
L21 VDDR1#23
L23 VDDR1#24 Granville VDDC:47A
L26 VDDR1#25 VDDC#1 AA15 +VGA_CORE
1U_0402_6.3V6K
C405
1U_0402_6.3V6K
C406
1U_0402_6.3V6K
C407
1U_0402_6.3V6K
C408
1U_0402_6.3V6K
C409
1U_0402_6.3V6K
C410
1U_0402_6.3V6K
C411
1U_0402_6.3V6K
C412
1U_0402_6.3V6K
C413
1U_0402_6.3V6K
C414
CORE
SM010030010 +1.8VSG
L14
2
1 L7 VDDR1#26 VDDC#2 AA17 1 1 1 1 1 1 1 1 1 1
1 1 1 M11 VDDR1#27 VDDC#3 AA20
300ma 120ohm@100mhz DCR 0.3
0.1U_0402_16V4Z
C404
120ohm/0.3A BLM18AG121SN1D_0603 VGA@ VGA@ N11 AA22
VDDR1#28 VDDC#4
10U_0603_6.3V6M
C402
1U_0402_6.3V6K
C403
VGA@ VGA@ P7 AA24 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ Granville PRO VDDC:47A
VDDR1#29 VDDC#5 2 2 2 2 2 2 2 2 2 2
R11 VDDR1#30 VDDC#6 AA27
2 2 2
U11 VDDR1#31 VDDC#7 AB16 Madison PRO VDDC+VDDCI=31.3A
U7 VDDR1#32 VDDC#8 AB18 Whistler PRO VDDC+VDDCI=24A
Y11 VDDR1#33 VDDC#9 AB21
Ref137-12~ remove Bead Y7 VDDR1#34 VDDC#10 AB23 SeymourXT VDDC+VDDCI=14.2A
1U_0402_6.3V6K
C416
1U_0402_6.3V6K
C417
1U_0402_6.3V6K
C418
1U_0402_6.3V6K
C419
1U_0402_6.3V6K
C420
1U_0402_6.3V6K
C421
1U_0402_6.3V6K
C422
1U_0402_6.3V6K
C423
1U_0402_6.3V6K
C424
1U_0402_6.3V6K
C425
AB26 1 1 1 1 1 1 1 1 1 1
VDDC#11
AB28
RobsonXT VDDC+VDDCI=12.9A
+3VSG VDDC#12
1 1 1 VDDC#13 AC17
0.1U_0402_16V4Z
C427
VGA@ VGA@ AC20 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
VDDC#14 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
C415
1U_0402_6.3V6K
C426
LEVEL
VGA@
20mil TRANSLATION VDDC#15 AC22
VDDC#16 AC24
2 2 2
POWER
+VDD_CT AF26 AC27
VDD_CT#1 VDDC#17
AF27 VDD_CT#2 VDDC#18 AD18
10U_0603_6.3V6M
C428
10U_0603_6.3V6M
C429
10U_0603_6.3V6M
C430
10U_0603_6.3V6M
C431
10U_0603_6.3V6M
C432
10U_0603_6.3V6M
C433
10U_0603_6.3V6M
C434
AG26 VDD_CT#3 219mA VDDC#19 AD21 1 1 1 1 1 1 1 1
VGA@
1
VGA@
2
AG27 VDD_CT#4 VDDC#20 AD23 2
AD26 + C435 + C436
VDDC#21 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 330U_2.5V_M 330U_2.5V_M
SM010030010 +1.8VSG
L16
2 1
VGA@ VGA@ VGA@ I/O VDDC#22 AF17
2 2 2 2 2 2 2
VDDC#23 AF20
300ma 120ohm@100mhz DCR 0.3 120ohm/0.3ABLM18AG121SN1D_0603 1 1 1 +VDDR3 AF23 AF22
2 2 Change to OS-CON
VDDR3#1 VDDC#24
10U_0603_6.3V6M
C437
1U_0402_6.3V6K
C438
0.1U_0402_16V4Z
C439
VGA@ 10mil AF24 AG16 20101115
VDDR3#2 VDDC#25 C435 / C436 change to SF000002Z00
AG23 VDDR3#3 60mA VDDC#26 AG18
AG24 AG21 20101228
2 2 2 VDDR3#4 VDDC#27
20mil 47A VDDC#28 AH22
VDDC#29 AH27
+VDDR4_5 AF13 AH28
VDDR4#4 VDDC#30
AF15 VDDR4#5 VDDC#31 M26 BIF_VDDC
AG13 VDDR4#7 VDDC#32 N24 Park/Madison:Connect to VDDC
AG15 N27 +BIF_VDDC +BIF_VDDC
VDDR4#8 VDDC/BIF_VDDC#33 Seymour/Whisler:
170mA VDDC#34 R18
VDDC#35 R21 dGPU operating:VDDC
AD12 VDDR4#1 VDDC#36 R23 BACO mode:+1.0V
AF11 VDDR4#2 55mA VDDC#37 R26
AF12 VDDR4#3 VDDC#38 T17
AG11 VDDR4#6 VDDC#39 T20 2010/04/27
VDDC#40 T22 non-BACO design,N27,T27
VDDC#41 T24
470ohm/1A T27 connect BIF_VDDC to VDDC
VDDC/BIF_VDDC#42
VDDC#43 U16 For BACO design
SM010030010 M20 NC_VDDRHA VDDC#44 U18
M21 NC_VSSRHA VDDC#45 U21
200ma 120ohm@100mhz DCR 0.2 VDDC#46 U23
VDDC#47 U26
L17 V12 V17
NC_VDDRHB VDDC#48
+1.8VSG 2 1 U12 NC_VSSRHB VDDC#49 V20
BLM18AG121SN1D_0603 VGA@ VGA@ VGA@ VGA@ VGA@ V22
VGA@ VDDC#50
1 1 1 1 1 VDDC#51 V24
10U_0603_6.3V6M
C440
1U_0402_6.3V6K
C441
0.1U_0402_16V4Z
C442
1U_0402_6.3V6K
C443
0.1U_0402_16V4Z
C444
VDDC#52 V27 VDDCI and VDDC should have seperate regulators with a merge option on PCB
VDDC#53 Y16
PLL Y18 For Madison and Park, VDDCI and VDDC can share one common regulator
2 2 2 2 2 VDDC#54
3
VDDC#55 Y21 3
VDDC#56 Y23 (GDDR3/DDR3 1.12V@4A VDDCI)

SM010030010 20mil +MPV_18
H7 MPV18#1 VDDC#57 Y26
(GDDR5 1.12V@16A VDDCI)
200ma 120ohm@100mhz DCR 0.2
H8 MPV18#2 150mA VDDC#58 Y28 SM01000BY00 5000ma 120ohm@100mhz DCR 0.02
L20 10mil Granville VDDCI:4.6A
+1.8VSG 2 1 +SPV_18 AM10 75mA 160mil
BLM18AG121SN1D_0603 VGA@ VGA@ VGA@ L18 SPV18 +VDDCI
VGA@
20mil +SPV10 VDDCI#1 AA13
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2
VAN@
1 +VGA_CORE
1 1 1 +1.0VSG 2 1 AN9 SPV10 120mA VDDCI#2 AB13
10U_0603_6.3V6M
C458
1U_0402_6.3V6K
C459
0.1U_0402_16V4Z
C460
VGA@ VGA@ VGA@ AC12 1 1 1 1 1 1 1 1 1 1 L19 Seymour/Whistler

VDDCI#3
10U_0603_6.3V6M
C445
1U_0402_6.3V6K
C446
0.1U_0402_16V4Z
C447
1U_0402_6.3V6K
C448
1U_0402_6.3V6K
C449
1U_0402_6.3V6K
C450
1U_0402_6.3V6K
C451
1U_0402_6.3V6K
C452
1U_0402_6.3V6K
C453
1U_0402_6.3V6K
C454
1U_0402_6.3V6K
C455
1U_0402_6.3V6K
C456
1U_0402_6.3V6K
C457
BLM18AG121SN1D_0603 1 1 1 AN10 AC15 FBMA-L11-201209-121LMA50T_0805
VGA@ SPVSS VDDCI#4
VDDCI#5 AD13 2 1
2 2 2 VAN@
470ohm/1A VDDCI#6 AD16
2 2 2 2 2 2 2 2 2 2 L21
SM010030010 2 2 2 VDDCI#7 M15
M16 FBMA-L11-201209-121LMA50T_0805
200ma 120ohm@100mhz DCR 0.2 VOLTAGE VDDCI#8
SENESE
5A VDDCI#9 M18
VDDCI#10 M23
GCORE_SEN
10mil VDDCI#11 N13
<47> GCORE_SEN AF28 FB_VDDC VDDCI#12 N15
VDDCI#13 N17
VDDCI#14 N20
AG28 N22 VGA@ VGA@ VGA@ VGA@ VGA@
FB_VDDCI ISOLATED VDDCI#15
1U_0402_6.3V6K
C461
0.1U_0402_16V4Z
C462
10U_0603_6.3V6M
C463
10U_0603_6.3V6M
C464
10U_0603_6.3V6M
C465
NC 20101116 R12
CORE I/O VDDCI#16 R13
VDDCI#17 1 1 1 1 1
FB_GND AH29 R16
FB_GND VDDCI#18
VDDCI#19 T12
1
VDDCI#20 T15
@ 2 2 2 2 2
VDDCI#21 V15
R466 Y13
0_0402_5% VDDCI#22
2
2160809000A11SEYMOU_FCBGA962
SEYM@
4 4

Vancouver_Power/GND
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
U8F
DPA_VDD18,DPA_PVDD,DPB_VDD18,DPB_PVDD Seymour/Whistler ：
can combian to DPAB_VDD18 DPA_VDD10,DPB_VDD10
DPC_VDD18,DPC_PVDD,DPD_VDD18,DPD_PVDD can combian to DPAB_VDD10
AB39 PCIE_VSS#1 GND#1 A3 can combian to DPCD_VDD18 DPC_VDD10,DPD_VDD10
E39 PCIE_VSS#2 GND#2 A37 (DPD_VDD18,DPD_PVDD not applicable on Robson/Park) can combian to DPCD_VDD10
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18 DPE_VDD18,DPE_PVDD,DPF_VDD18,DPF_PVDD DPE_VDD10,DPD_VDD10
G33 PCIE_VSS#5 GND#5 AA2 can combian to DPEF_VDD18 can combian to DPEF_VDD10
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
H34 AA26
H39
PCIE_VSS#8 GND#8
AA28
DPx-VSSR,DPx_PVSS can combian to DP_VSSR
PCIE_VSS#9 GND#9
1
J31
PCIE_VSS#10 GND#10
AA6 (Manhatann should have individual GND) 1
J34 AB12
K31
PCIE_VSS#11 GND#11
AB15 where x is A,B,C,D,E,F
PCIE_VSS#12 GND#12
K34 AB17
PCIE_VSS#13 GND#13 U8H
K39
PCIE_VSS#14 GND#14
AB20 SM01000BL00
L31 AB22 1000ma 470ohm@100mhz DCR 0.2
PCIE_VSS#15 GND#15 DP C/D POWER DP A/B POWER
L34 AB24
PCIE_VSS#16 GND#16 L23
M34
PCIE_VSS#17 GND#17
AB27 Manhatann:300mA 20mil 20mil MBK1608221YZF_2P
M39
PCIE_VSS#18 GND#18
AC11
Seymour:150mA +DPABCD_VDD18
AP20
DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1
AN24
+DPABCD_VDD18
300mA
N31 AC13 AP21 AP24 2 1 +1.8VSG
PCIE_VSS#19 GND#19 DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2 VGA@
N34 AC16
PCIE_VSS#20 GND#20
P31 AC18 1 1 1
PCIE_VSS#21 GND#21 VGA@ VGA@ VGA@
P34 PCIE_VSS#22 GND#22 AC2 20mil 20mil FootPrint
10U_0603_6.3V6M
C469
0.1U_0402_16V4Z
C470
1U_0402_6.3V6K
C471
P39 PCIE_VSS#23 GND#23 AC21 AP13 DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1 AP31
R34 AC23 +DPABCD_VDD10 AT13 AP32 +DPABCD_VDD10
PCIE_VSS#24 GND#24 DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2 2 2 2
T31 PCIE_VSS#25 GND#25 AC26
T34 PCIE_VSS#26 GND#26 AC28
T39 PCIE_VSS#27 GND#27 AC6 AN17 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AN27
U31 PCIE_VSS#28 GND#28 AD15 AP16 DP/DPC_VSSR#2 DP/DPA_VSSR#2 AP27
U34 PCIE_VSS#29 GND#29 AD17 AP17 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AP28
V34 PCIE_VSS#30 GND#30 AD20 AW14 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW24
V39 PCIE_VSS#31 GND#31 AD22 AW16 DP/DPC_VSSR#5 DP/DPA_VSSR#5 AW26
W31 PCIE_VSS#32 GND#32 AD24
W34 PCIE_VSS#33 GND#33 AD27
Y34 PCIE_VSS#34 GND#34 AD9 20mil 20mil
Y39 PCIE_VSS#35 GND#35 AE2 AP22 DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1 AP25
AE6 +DPABCD_VDD18 AP23 AP26 +DPABCD_VDD18 SM01000BL00
GND#36 DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2
GND#37 AF10 1000ma 470ohm@100mhz DCR 0.2
GND#38 AF16 20mil
AF18 20mil L25
GND#39 +DPABCD_VDD10 MBK1608221YZF_2P
AF21 Manhatann:220mA AP14 AN33 220mA
F15 GND#100
GND GND#40
GND#41
GND#42
AG17
AG2 Seymour:110mA
AP15
DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2
DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2 AP33 +DPABCD_VDD10 2
VGA@
1 +1.0VSG
2 2
F17 GND#101 GND#43 AG20
F19 GND#102 GND#44 AG22 1 VGA@ 1 VGA@ 1 VGA@ FootPrint
0.1U_0402_16V4Z
C475
1U_0402_6.3V6K
C476
10U_0603_6.3V6M
C477
F21 GND#103 GND#45 AG6 AN19 DP/DPD_VSSR#1 DP/DPB_VSSR#1 AN29
F23 GND#104 GND#46 AG9 AP18 DP/DPD_VSSR#2 DP/DPB_VSSR#2 AP29
F25 GND#105 GND#47 AH21 AP19 DP/DPD_VSSR#3 DP/DPB_VSSR#3 AP30
F27 AJ10 AW20 AW30 2 2 2
GND#106 GND#48 DP/DPD_VSSR#4 DP/DPB_VSSR#4
F29 GND#107 GND#49 AJ11 AW22 DP/DPD_VSSR#5 DP/DPB_VSSR#5 AW32
F31 AJ2
GND#108 GND#50 R467 R468
F33 AJ28
GND#109 GND#51 150_0402_1% 150_0402_1%
F7
GND#110 GND#52
AJ6 SM01000BL00 DP mode:300mA
F9 AK11 1000ma 470ohm@100mhz DCR 0.2 2 1 AW18 AW28 1 2
GND#111 GND#53 LVDS mode:440mA VGA@ DPCD_CALR DPAB_CALR VGA@
G2 AK31
GND#112 GND#54 L26
G6
GND#113 GND#55
AK7 20mil 20mA
H9 AL11 MBK1608221YZF_2P DP E/F POWER DP PLL POWER 10mil
GND#114 GND#56 +DPEF_VDD18 +DPABCD_VDD18
J2 AL14 +1.8VSG 2 1 AH34 AU28
GND#115 GND#57 VGA@ DPEF/DPE_VDD18#1 DPAB_VDD18/DPA_PVDD
J27 AL17 AJ34 AV27
GND#116 GND#58 DPEF/DPE_VDD18#2 DP_VSSR/DPA_PVSS
J6
GND#117 GND#59
AL2 1 VGA@ 1 VGA@ 1 VGA@
10U_0603_6.3V6M
C478
1U_0402_6.3V6K
C479
0.1U_0402_16V4Z
C480
J8
GND#118 GND#60
AL20 FootPrint 20mil 20mA
K14 AL21 PX_EN 10mil
GND#119 GND/PX_EN#61 PX_EN <20> +DPEF_VDD10 +DPABCD_VDD18
K7 AL23 AL33 AV29
GND#120 GND#62 2 2 2 DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD
L11
GND#121 GND#63
AL26 PX_EN: PU at P.20 AM33
DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS
AR28
L17 AL32
L2
GND#122 GND#64
AL6 SBIOS will control VGA power on/off. 20mA
GND#123 GND#65
L22
GND#124 GND#66
AL8 High :BACO mode enable +DPABCD_VDD18
10mil
L24 AM11 AN34 AU18
GND#125 GND#67 LOW:BACO disable DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD
L6 AM31 AP39 AV17
GND#126 GND#68 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS
M17 AM9 AR39
GND#127 GND#69 DP/DPE_VSSR#3
M22
GND#128 GND#70
AN11 AU37
DP/DPE_VSSR#4 20mA
M24
GND#129 GND#71
AN2
+DPABCD_VDD18
10mil
N16 AN30 AV19
GND#130 GND#72 DPCD_VDD18/DPD_PVDD
N18 AN6 AR18
GND#131 GND#73 DP_VSSR/DPD_PVSS
3
N2
GND#132 GND#74
AN8 20mil 3
N21
GND#133 GND#75
AP11
+DPEF_VDD18
AF34
DPEF/DPF_VDD18#1 20mA
N23
GND#134 GND#76
AP7 SM01000BL00 AG34
DPEF/DPF_VDD18#2 10mil
N26 AP9 AM37 +DPEF_VDD18
GND#135 GND#77 1000ma 470ohm@100mhz DCR 0.2 DPEF_VDD18/DPE_PVDD
N6
GND#136 GND#78
AR5 DP mode:220mA 20mil DP_VSSR/DPE_PVSS
AN38
R15 B11 L27
R17
GND#137 GND#79
B13 MBK1608221YZF_2P LVDS mode:240mA AK33 20mA
GND#138 GND#80 +DPEF_VDD10 DPEF/DPF_VDD10#1
R2
GND#139 GND#81
B15 +1.0VSG 2 1 AK34
DPEF/DPF_VDD10#2 +DPEF_VDD18
10mil
R20 B17 VGA@ AL38
GND#140 GND#82 DPEF_VDD18/DPF_PVDD
R22
GND#141 GND#83
B19 1 VGA@ 1 VGA@ 1 VGA@ DP_VSSR/DPF_PVSS
AM35
10U_0603_6.3V6M
C481
1U_0402_6.3V6K
C482
0.1U_0402_16V4Z
C483
R24
GND#142 GND#84
B21 FootPrint
R27 B23 AF39
GND#143 GND#85 DP/DPF_VSSR#1
R6 B25 AH39
GND#144 GND#86 2 2 2 DP/DPF_VSSR#2
T11 B27 AK39
T13 B29 AL34
T16 B31 AM34
T18 B33
GND#148 GND#90
T21 B7
GND#149 GND#91 R470
T23 B9
GND#150 GND#92
T26 C1 2 1 AM39
GND#151 GND#93 VGA@ DPEF_CALR
U15 C39
GND#153 GND#94 150_0402_1%
U17 E35
GND#154 GND#95 2160809000A11SEYMOU_FCBGA962
U2 E5
GND#155 GND#96 SEYM@
U20 F11
GND#156 GND#97
U22 F13
GND#157 GND#98
U24
GND#158
U27
GND#159
U6
GND#160
V11
GND#161
V16
GND#163 Park/Madison :AL21left NC
V18
GND#164
V21
GND#165
4
V23 GND#166 Seymour/Whistler: 4
V26 GND#167
W2 GND#168
AL21:PX_EN
W6 GND#169 use to control discreate GPU regulators
Y15 GND#170
Y17 GND#171
for power express BACO mode
Y20 GND#172 Support BACO:
Y22 GND#173 VSS_MECH#1 A39
Y24 AW1 output High3.3V:turn off regulators (BACO mode on)
Y27
GND#174 VSS_MECH#2
AW39
U13
GND#175 VSS_MECH#3 output Low0V:turn on regulators (BACO mode off) 2010/07/12 2012/07/12 Title
GND#152 Issued Date Deciphered Date
V13 GND#162 need PD resistor Vancouver_Power/GND
2160809000A11SEYMOU_FCBGA962 No support BACO: THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SEYM@ left NC DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
P5WS5 LA-6973P 1.0
REF137-13 update MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
A B C D E
U11 U12 U13 U14
VREFCA_A1 M8 E3 MDA22 VREFCA_A2 M8 E3 MDA25 VREFCA_A3 M8 E3 MDA35 VREFCA_A4 M8 E3 MDA48

VREFDA_Q1 H1 VREFCA DQL0 MDA19 VREFDA_Q2 VREFCA DQL0 MDA30 VREFDA_Q3 VREFCA DQL0 MDA32 VREFDA_Q4 VREFCA DQL0 MDA51
VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDA21 F2 MDA24 F2 MDA38 F2 MDA55
MAA0 DQL2 MDA18 MAA0 DQL2 MDA29 MAA0 DQL2 MDA34 MAA0 DQL2 MDA54
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAA1 P7 H3 MDA23 MAA1 P7 H3 MDA26 MAA1 P7 H3 MDA37 MAA1 P7 H3 MDA50
MAA2 A1 DQL4 MDA16 MAA2 A1 DQL4 MDA31 MAA2 A1 DQL4 MDA36 MAA2 A1 DQL4 MDA52
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAA3 N2 G2 MDA20 MAA3 N2 G2 MDA27 MAA3 N2 G2 MDA39 MAA3 N2 G2 MDA49
MAA4 A3 DQL6 MDA17 MAA4 A3 DQL6 MDA28 MAA4 A3 DQL6 MDA33 MAA4 A3 DQL6 MDA53
MAA5 P2 MAA5 P2 MAA5 P2 MAA5 P2
MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
R8 A6 R8 A6 R8 A6 R8 A6
MAA7 R2 D7 MDA0 MAA7 R2 D7 MDA15 MAA7 R2 D7 MDA43 MAA7 R2 D7 MDA63
MAA8 A7 DQU0 MDA5 MAA8 A7 DQU0 MDA11 MAA8 A7 DQU0 MDA44 MAA8 A7 DQU0 MDA58
T8 C3 T8 C3 T8 C3 T8 C3
R3 C8 R3 C8 R3 C8 R3 C8
1 MAA10 A9 DQU2 MDA7 MAA10 A9 DQU2 MDA10 MAA10 A9 DQU2 MDA45 MAA10 A9 DQU2 MDA59 1
L7 C2 L7 C2 L7 C2 L7 C2
MAA11 A10/AP DQU3 MDA3 MAA11 A10/AP DQU3 MDA13 MAA11 A10/AP DQU3 MDA42 MAA11 A10/AP DQU3 MDA61
R7 A7 R7 A7 R7 A7 R7 A7
N7 A2 N7 A2 N7 A2 N7 A2
T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 MDA6 A13 DQU6 MDA8 A13 DQU6 MDA47 A13 DQU6 MDA57
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15/BA3 +1.5VSG A15/BA3 +1.5VSG A15/BA3 +1.5VSG A15/BA3 +1.5VSG
M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

<15> A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 A_BA1 N8 D9
<15> A_BA1 BA1 VDD A_BA2 BA1 VDD A_BA2 BA1 VDD A_BA2 BA1 VDD
<15> A_BA2 M3 G7 M3 G7 M3 G7 M3 G7
BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
MDA[0..63] N1 N1 N1 N1
<15> MDA[0..63] CLKA0 VDD CLKA0 VDD CLKA1 VDD CLKA1 VDD
J7 CK VDD N9 J7 CK VDD N9 J7 CK VDD N9 J7 CK VDD N9
CLKA0# K7 R1 CLKA0# K7 R1 CLKA1# K7 R1 CLKA1# K7 R1
CK VDD CKEA0 CK VDD CK VDD CKEA1 CK VDD
<15> CKEA0 K9 CKE/CKE0 VDD R9 K9 CKE/CKE0 VDD R9 <15> CKEA1 K9 CKE/CKE0 VDD R9 K9 CKE/CKE0 VDD R9
+1.5VSG +1.5VSG +1.5VSG +1.5VSG
ODTA0_1 K1 A1 ODTA0_1 K1 A1 ODTA1_1 K1 A1 ODTA1_1 K1 A1

<15> MAA[13..0] ODT/ODT0 VDDQ CSA0#_0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ CSA1#_0 ODT/ODT0 VDDQ
<15> CSA0#_0 L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 <15> CSA1#_0 L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
<15> RASA0# RAS VDDQ CASA0# RAS VDDQ <15> RASA1# RAS VDDQ CASA1# RAS VDDQ
<15> CASA0# K3 C9 K3 C9 <15> CASA1# K3 C9 K3 C9
CAS VDDQ WEA0# CAS VDDQ CAS VDDQ WEA1# CAS VDDQ
<15> WEA0# L3 WE VDDQ D2 L3 WE VDDQ D2 <15> WEA1# L3 WE VDDQ D2 L3 WE VDDQ D2
<15> DQMA#[7..0] VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA2 F3 H2 QSA3 F3 H2 QSA4 F3 H2 QSA6 F3 H2
QSA0 DQSL VDDQ QSA1 DQSL VDDQ QSA5 DQSL VDDQ QSA7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
<15> QSA[7..0]
DQMA#2 E7 A9 DQMA#3 E7 A9 DQMA#4 E7 A9 DQMA#6 E7 A9
DQMA#0 DML VSS DQMA#1 DML VSS DQMA#5 DML VSS DQMA#7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
2 2
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSA#2 G3 J2 QSA#3 G3 J2 QSA#4 G3 J2 QSA#6 G3 J2
<15> QSA#[7..0] QSA#0 DQSL VSS QSA#1 DQSL VSS QSA#5 DQSL VSS QSA#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
VSS P1 VSS P1 VSS P1 VSS P1
VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9
<15,19> VRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
VSS VSS VSS VSS
L8 T9 L8 T9 L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1 J1 B1 J1 B1
R471 NC/ODT1 VSSQ R472 NC/ODT1 VSSQ R473 NC/ODT1 VSSQ R474 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J9 D1 J9 D1 J9 D1 J9 D1
128@ NC/CE1 VSSQ 128@ NC/CE1 VSSQ 128@ NC/CE1 VSSQ 128@ NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2
2
VSSQ VSSQ VSSQ VSSQ
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
G1 G1 G1 G1
VSSQ VSSQ VSSQ VSSQ
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
+1.5VSG X76@ X76@ X76@ X76@
+1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG
Pull high for Madison and Park...
ODTA0_1
1
1
R484 R475 R476 R477 R478 R479 R480 R481 R482
128@ 56_0402_1% 4.99K_0402_1% 128@ 4.99K_0402_1% 128@ 4.99K_0402_1% 128@ 4.99K_0402_1% 128@ 4.99K_0402_1% 128@ 4.99K_0402_1%
128@ 4.99K_0402_1% 128@ 4.99K_0402_1% 128@
3 ODTA0 2 3
<15> ODTA0 1 1 2
R483 0_0402_5% 128@ 15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil
2
2
R486 VREFCA_A1 VREFDA_Q1 VREFCA_A2 VREFDA_Q2 VREFCA_A3 VREFDA_Q3 VREFCA_A4 VREFDA_Q4
R485 0_0402_5% 56_0402_1%
1
1
ODTA1 2 1 1 2 1 1 1 1 1 1 1 1
<15> ODTA1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
128@ 128@ R487 C484 R488 R489 C486 R490 C487 R491 C488 R492 C489 R493 C490 R494 C491
4.99K_0402_1% 4.99K_0402_1% C485 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 128@ 4.99K_0402_1% 4.99K_0402_1% 128@
ODTA1_1 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@
2 2 2 2 2 2 2 2
2
2
+1.5VSG +1.5VSG +1.5VSG
+1.5VSG
128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 128@ 128@ 128@ 128@ 128@
1U_0402_6.3V6K
C492
1U_0402_6.3V6K
C493
1U_0402_6.3V6K
C494
1U_0402_6.3V6K
C495
1U_0402_6.3V6K
C496
1U_0402_6.3V6K
C497
1U_0402_6.3V6K
C498
1U_0402_6.3V6K
C499
1U_0402_6.3V6K
C500
1U_0402_6.3V6K
C501
1U_0402_6.3V6K
C502
1U_0402_6.3V6K
C503
1U_0402_6.3V6K
C504
1U_0402_6.3V6K
C505
1U_0402_6.3V6K
C506
128@ 1 1 1 1 1
1U_0402_6.3V6K
C507
1U_0402_6.3V6K
C508
1U_0402_6.3V6K
C509
1U_0402_6.3V6K
C510
1U_0402_6.3V6K
C511
<15> CLKA0 1 2
R495 56_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
128@ 2 2 2 2 2
<15> CLKA0# 1 2
R496 56_0402_1%
+1.5VSG
1
+1.5VSG
128@ C512
0.01U_0402_16V7K 128@ 128@ 128@ 128@
2 128@ 128@ 128@ 128@ 1 10U_0603_6.3V6M 1 1 1
C519
10U_0603_6.3V6M
C520
10U_0603_6.3V6M
C517
10U_0603_6.3V6M
C518
4
1 1 1 1 4
128@
10U_0603_6.3V6M
C513
10U_0603_6.3V6M
C514
10U_0603_6.3V6M
C515
10U_0603_6.3V6M
C516
<15> CLKA1 1 2
R497 56_0402_1% 2 2 2 2
2 2 2 2
128@
<15> CLKA1# 1 2
R498 56_0402_1%
1
C521 Security Classification Compal Secret Data Compal Electronics, Inc.
128@ 0.01U_0402_16V7K Issued Date 2010/07/12 2012/07/12 Title
Deciphered Date
2
VRAM_DDR3 / Channel A
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
U15 U16 U17 U18
VREFCB_A1 M8 E3 MDB26 VREFCB_A2 M8 E3 MDB22 VREFCB_A3 M8 E3 MDB35 VREFCB_A4 M8 E3 MDB55

VREFDB_Q1 H1 VREFCA DQL0 MDB28 VREFDB_Q2 H1 VREFCA DQL0 MDB20 VREFDB_Q3 H1 VREFCA DQL0 MDB37 VREFDB_Q4 H1 VREFCA DQL0 MDB49
VREFDQ DQL1 F7 VREFDQ DQL1 F7 VREFDQ DQL1 F7 VREFDQ DQL1 F7
F2 MDB27 F2 MDB21 F2 MDB34 F2 MDB52
MAB0 DQL2 MDB31 MAB0 DQL2 MDB18 MAB0 DQL2 MDB39 MAB0 DQL2 MDB50
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAB1 P7 H3 MDB25 MAB1 P7 H3 MDB19 MAB1 P7 H3 MDB33 MAB1 P7 H3 MDB53
MAB2 A1 DQL4 MDB30 MAB2 A1 DQL4 MDB17 MAB2 A1 DQL4 MDB38 MAB2 A1 DQL4 MDB48
MAB3 N2 G2 MDB24 MAB3 N2 G2 MDB23 MAB3 N2 G2 MDB32 MAB3 N2 G2 MDB54
MAB4 A3 DQL6 MDB29 MAB4 A3 DQL6 MDB16 MAB4 A3 DQL6 MDB36 MAB4 A3 DQL6 MDB51
MAB5 P2 MAB5 P2 MAB5 P2 MAB5 P2
MAB6 A5 MAB6 A5 MAB6 A5 MAB6 A5
R8 A6 R8 A6 R8 A6 R8 A6
MAB7 R2 D7 MDB15 MAB7 R2 D7 MDB1 MAB7 R2 D7 MDB44 MAB7 R2 D7 MDB56
MAB8 A7 DQU0 MDB10 MAB8 A7 DQU0 MDB6 MAB8 A7 DQU0 MDB43 MAB8 A7 DQU0 MDB59
T8 C3 T8 C3 T8 C3 T8 C3
R3 C8 R3 C8 R3 C8 R3 C8
1 MAB10 A9 DQU2 MDB11 MAB10 A9 DQU2 MDB4 MAB10 A9 DQU2 MDB41 MAB10 A9 DQU2 MDB62 1
L7 C2 L7 C2 L7 C2 L7 C2
MAB11 A10/AP DQU3 MDB13 MAB11 A10/AP DQU3 MDB3 MAB11 A10/AP DQU3 MDB45 MAB11 A10/AP DQU3 MDB57
R7 A7 R7 A7 R7 A7 R7 A7
N7 A2 N7 A2 N7 A2 N7 A2
T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 MDB8 A13 DQU6 MDB5 A13 DQU6 MDB42 A13 DQU6 MDB60
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15/BA3 +1.5VSG A15/BA3 +1.5VSG A15/BA3 +1.5VSG A15/BA3 +1.5VSG
M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2

<15> B_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
<15> B_BA1 BA1 VDD B_BA2 BA1 VDD B_BA2 BA1 VDD B_BA2 BA1 VDD
<15> B_BA2 M3 G7 M3 G7 M3 G7 M3 G7
BA2 VDD BA2 VDD BA2 VDD BA2 VDD
MDB[0..63] K8 K8 K8 K8
<15> MDB[0..63] VDD VDD VDD VDD
VDD N1 VDD N1 VDD N1 VDD N1
CLKB0 J7 N9 CLKB0 J7 N9 CLKB1 J7 N9 CLKB1 J7 N9
CLKB0# CK VDD CLKB0# CK VDD CLKB1# CK VDD CLKB1# CK VDD
K7 CK VDD R1 K7 CK VDD R1 K7 CK VDD R1 K7 CK VDD R1
K9 R9 CKEB0 K9 R9 K9 R9 CKEB1 K9 R9
<15> CKEB0 CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG <15> CKEB1 CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG
<15> MAB[13..0] ODTB0_1 ODTB0_1 ODTB1_1 ODTB1_1
K1 ODT/ODT0 VDDQ A1 K1 ODT/ODT0 VDDQ A1 K1 ODT/ODT0 VDDQ A1 K1 ODT/ODT0 VDDQ A1
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
<15> CSB0#_0 CS/CS0 VDDQ RASB0# CS/CS0 VDDQ <15> CSB1#_0 CS/CS0 VDDQ RASB1# CS/CS0 VDDQ
<15> RASB0# J3 RAS VDDQ C1 J3 RAS VDDQ C1 <15> RASB1# J3 RAS VDDQ C1 J3 RAS VDDQ C1
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
<15> CASB0# CAS VDDQ WEB0# CAS VDDQ <15> CASB1# CAS VDDQ WEB1# CAS VDDQ
<15> DQMB#[7..0] <15> WEB0# L3 WE VDDQ D2 L3 WE VDDQ D2 <15> WEB1# L3 WE VDDQ D2 L3 WE VDDQ D2
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB3 F3 H2 QSB2 F3 H2 QSB4 F3 H2 QSB6 F3 H2
QSB1 DQSL VDDQ QSB0 DQSL VDDQ QSB5 DQSL VDDQ QSB7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
<15> QSB[7..0]
DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9
DQMB#1 DML VSS DQMB#0 DML VSS DQMB#5 DML VSS DQMB#7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
2 2
VSS E1 VSS E1 VSS E1 VSS E1
<15> QSB#[7..0] VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 J2 QSB#2 G3 J2 QSB#4 G3 J2 QSB#6 G3 J2
QSB#1 DQSL VSS QSB#0 DQSL VSS QSB#5 DQSL VSS QSB#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS P1 VSS P1 VSS P1 VSS P1
VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9
<15,18> VRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
VSS VSS VSS VSS
L8 T9 L8 T9 L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1 J1 B1 J1 B1
R499 NC/ODT1 VSSQ R500 NC/ODT1 VSSQ R501 NC/ODT1 VSSQ R502 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
VGA@ NC/CS1 VSSQ VGA@ NC/CS1 VSSQ NC/CS1 VSSQ VGA@ NC/CS1 VSSQ
243_0402_1% J9 D1 243_0402_1% J9 D1 243_0402_1% J9 D1 243_0402_1% J9 D1
NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2
2
VSSQ VSSQ VSSQ VSSQ
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VGA@ VSSQ VSSQ
G1 G1 G1 G1
VSSQ VSSQ VSSQ VSSQ
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
Pull high for Madison and Park... K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
X76@ X76@ X76@ X76@
+1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG
+1.5VSG +1.5VSG +1.5VSG +1.5VSG
1
1
ODTB0_1
1
R503 R504 R505 R506
R512 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ R507 R508 R509 R510
3 VGA@ 56_0402_1% 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ 3
ODTB0 R511 1 2
<15> ODTB0
2
2
VGA@
2
0_0402_5% VREFCB_A1 VREFDB_Q1 VREFCB_A2 VREFDB_Q2
R514 VREFCB_A3 VREFDB_Q3 VREFCB_A4 VREFDB_Q4
1
1
VGA@ 56_0402_1% 1 1 1 1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ODTB1 R513 1 2 R515 C522 R516 C523 R517 C524 R518 C525 1 1 1 1
<15> ODTB1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ R519 C526 R520 C527 R521 C528 R522 C529
0_0402_5% VGA@ VGA@ VGA@ VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@
ODTB1_1 2 2 2 2 VGA@ VGA@ VGA@ VGA@
2
2
2 2 2 2
2
R523 56_0402_1%
1 2 +1.5VSG +1.5VSG
<15> CLKB0
VGA@ +1.5VSG +1.5VSG
R524 56_0402_1% VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1 2 1 1 1 1 1 1 1 1 1 1 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
<15> CLKB0#
1U_0402_6.3V6K
C531
1U_0402_6.3V6K
C532
1U_0402_6.3V6K
C533
1U_0402_6.3V6K
C534
1U_0402_6.3V6K
C535
1U_0402_6.3V6K
C536
1U_0402_6.3V6K
C537
1U_0402_6.3V6K
C538
1U_0402_6.3V6K
C539
1U_0402_6.3V6K
C540
VGA@ 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
C541
1U_0402_6.3V6K
C542
1U_0402_6.3V6K
C543
1U_0402_6.3V6K
C544
1U_0402_6.3V6K
C545
1U_0402_6.3V6K
C546
1U_0402_6.3V6K
C547
1U_0402_6.3V6K
C548
1U_0402_6.3V6K
C549
1U_0402_6.3V6K
C550
1
VGA@ C530 2 2 2 2 2 2 2 2 2 2
+1.5VSG 2 2 2 2 2 2 2 2 2 2
0.01U_0402_16V7K
2 +1.5VSG
R525
56_0402_1%
<15> CLKB1 1 2 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
10U_0603_6.3V6M
C551
10U_0603_6.3V6M
C552
10U_0603_6.3V6M
C554
10U_0603_6.3V6M
C553
VGA@ 1 1 1 1
R526 VGA@ VGA@ VGA@ VGA@
10U_0603_6.3V6M
C555
10U_0603_6.3V6M
C556
10U_0603_6.3V6M
C557
10U_0603_6.3V6M
C558
56_0402_1%
2 2 2 2
<15> CLKB1# 1 2
4 VGA@ 2 2 2 2 4
1
VGA@ C559
0.01U_0402_16V7K
2

VRAM_DDR3 / Channel B
Custom 1.0
P5WS5 LA-6973P
A B C D E
5 4 3 2 1
VGA Muxless and Dis only Status Mapping table

Power Sequence of Granville Power Sequence of Whistler and Seymour Dis only Muxless High performance GPU Muxless Power-saving GPU
FCH_PWRGD VGA_PWR_ON 1 1 0
38ms SUSP#
1.5_VDDC_PWREN 1 1 0
Ref CLK +3VSG
+3.3VSG ON ON OFF
(JUMP form +3VS)
INT_VGAPWR_ON +1.8VSG ON ON OFF
50ms VGA_ON 10ms
+1.0VSG ON ON OFF
VGA_PWR_ON
D VGA_PWR_ON +VGA_CORE ON ON OFF D
+3VSG +1.5VSG ON ON OFF

1.5_VDDC_PWREN
+BIF_VDDC +VGA_CORE +VGA_CORE OFF
+VGA_CORE
+VGA_CORE
VGA Muxless with BACO Status Mapping table VGA Power Enable Signal Mapping table
VDDCI
+1.5VSG Normal mode BACO mode Graville Whistler and Seymour
+1.5VSG PX_EN 0 1 VGA_PWR_ON source signal INT_VGAPWR_ON VGA_ON
+1.0VSG
1.5_VDDC_PWREN 1 0 +3.3VSG VGA_PWR_ON SUSP#
+1.0VSG
+1.8VSG VDDC_EN 1 0 +1.8VSG VGA_PWR_ON VGA_PWR_ON
20ms
+1.8VSG 1.0_EN 0 1 +1.0VSG VGA_PWR_ON VGA_PWR_ON
20ms
+3.3VSG ON ON +VDDCI VGA_PWR_ON Combine with +VGA_CORE
+1.8VSG ON ON +VGA_CORE VGA_PWR_ON 1.5_VDDC_PWREN
+5VALW For PX sequence, >2mS delay is required between
PE_GPIO1 and VGA_PWR_ON +1.0VSG ON ON +1.5VSG VGA_PWR_ON 1.5_VDDC_PWREN
+VGA_CORE ON OFF
2
@ +1.5VSG ON OFF WOBACO@

R1113 R649 1 2 0_0402_5%
100K_0402_5% +BIF_VDDC +VGA_CORE +1.0VSG +3VS C1103 BACO@
PE_GPIO1
1
PE_GPIO1# 0.1U_0402_16V4Z
1 2
C C
VGA_PWR_ON >2ms
1
D BACO@
5
<25> PE_GPIO1 2 @ U19
G Q62 VGA_PWR_ON 2
P
B
1
S 2N7002_SOT23 4 1.5_VDDC_PWREN
1.5_VDDC_PWREN <39,46,47>
3
@ R650 1 Y
+3VS 2 10K_0402_5% 1 A
G
R1115
100K_0402_5% NC7SZ08P5X_NL_SC70-5
3
2
1
D
<17> PX_EN 1 BACO@ 2 2

R651 0_0402_5% G BACO@
1
+3VALW +3VALW S Q22
3
BACO@ 2N7002_SOT23
VGA Power ON Circuit VGA@
U44A
VGA@
U44B
R652
5.11K_0402_1% +5VS +5VS
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14
14
2
Delay SUSP# 10ms
P
2
<36> VGA_ON 1 VAN@ 2 1
I O
2 3
I O
4 1 VAN@ 2
R111 0_0402_5% 2 R170 0_0402_5% BACO@ BACO@
G
R653 R654
VGA@ 1K_0402_5% 1K_0402_5%
7
C208
1
0.1U_0402_16V4Z 1 VAN_GPIO1_DELAY VDDC_EN
BACO@ C1104 +3VS
0.1U_0402_16V4Z 1.0_EN
2 1
3
DMN66D0LDW-7_SOT363-6
Q23A
Q23B
BACO@
5
+3VALW +3VALW U20
B 1.5_VDDC_PWREN B
1 BACO@ 2 2
P
R655 0_0402_5% B
4 2 5
Y
BACO@
BACO@
VGA@ VGA@ 1
<25,47> VGA_PWRGD A
G
U44C U44D
14
14
4
Delay EC_PWROK 50ms SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 From +VGA_CORE regulator NC7SZ08P5X_NL_SC70-5
3
P
<36> INT_VGAPWR_ON 1 MAN@ 2 5 6 9 8 1 MAN@ 2

R115 0_0402_5% I O I O R172 0_0402_5%
2
G
C210
MAN@
7
0.1U_0402_16V4Z
1 MAN_GPIO1_DELAY
+BIF_VDDC +VGA_CORE
2
DISO@ +1.0VSG BACO@ Q24 BACO@ Q25

R116 20mil 30mil WOBACO@
+3VS
D
+3VALW +3VALW 0_0402_5% 3 1 1 3 1 2
S
VGA@ R656 0_0805_5%
C211 AO3416_SOT23-3 AO3416_SOT23-3 1
1
1
@ 1 2 0.1U_0402_16V4Z
G
2
2
Change to 30K 1% R118 BACO@
20110124 31.6K_0402_1% VGA@ VGA@ 1.0_EN C1105
14
14
U44E U44F 2 22U_0805_6.3V6M

PX@ SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
For VGA Power on control
P
P
2
1 R119 2 11 C1105 Change to SE00000I10

O 10
13 I
O 12
<25> PE_GPIO1 1 2 VGA_PWR_ON <39,45>
30K_0402_1% I PX@R120
PX@ R120 VDDC_EN
20101228
G
G
6
2 0_0402_5% 2
C213 @
7
2
G
@ VGA@ C214
G
PE_GPIO1# 1 2 2 Q89A 0.1U_0402_16V4Z 0.1U_0402_16V4Z 30mil AO3416 NMOS
R121 @ 0_0402_5% 1 1
3 1 1 3 Vgs(th)(Max)= 1V
BACO@ BACO@
S
1
A DMN66D0LDW-7_SOT363-6 Q26 Q27 Rds(on)(Max)= 22m ohm @Vgs=4.5V A

+VGA_CORE AO3416_SOT23-3 AO3416_SOT23-3
@
VAN_GPIO1_DELAY 1 @ 2 5 Q89B Q24 / Q25 / Q26 / Q27 change to SB00000FG10
R122 0_0402_5% DMN66D0LDW-7_SOT363-6 20101228
MAN_GPIO1_DELAY 1 @ 2
4
R123 0_0402_5%
VGA power sequence and BACO
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
5 4 3 2 1
EEROM
+3VS +3VS_PS
SWR_VDD
30mil 30mil
TL@
R1160 0_0603_5%
TL@U2
TL@ U2
+3VS_PS 8 1
TL@ U46 VCC A0
Close to Pin3 7 WP A1 2
19 APU_TXOUT_CLK+ MIIC_SCL 6 3
TXEC+ APU_TXOUT_CLK+ <22> SCL A2
DP_V33 TL@L76
TL@ L76 2 1 DP_V33 40mil 3 20 APU_TXOUT_CLK- MIIC_SDA 5 4
DP_V33 TXEC- APU_TXOUT_CLK- <22> SDA GND
FBMA-L11-201209-221LMA30T_0805
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z 60mil 13 21 APU_TXOUT2+ CAT24C64WI-GT3_SO8

SWR_VDD TXE2+ APU_TXOUT2+ <22>
TL@C20
TL@
TL@C1482
TL@
TL@C1483
TL@
Power
D D
1 1 1 TL@L78
TL@ L78 2 1 SWR_VDD 18 22 APU_TXOUT2-
LVDS
PVCC TXE2- APU_TXOUT2- <22>
FBMA-L11-201209-221LMA30T_0805
C20
C1482
C1483
SWR_V12 TL@L77
TL@ L77 1 2 SWR_LX 60mil 12 23 APU_TXOUT1+
SWR_LX TXE1+ APU_TXOUT1+ <22>
4.7UH_PG031B-4R7MS_1.1A_20% 60mil 11 24 APU_TXOUT1- APU_TXOUT1- <22>
2 2 2 SWR_VCCK TXE1-
27
VCCK APU_TXOUT0+
7 25 APU_TXOUT0+ <22>
DP_V12 TXE0+ APU_TXOUT0-
26 APU_TXOUT0- <22>
TXE0- +3VS_PS
APU_LVDS_DAT 1 TL@
RTD2132S R1163
2
4.7K_0402_5%
DP0_AUXP_C 2 APU_LVDS_CLK 1 TL@ 2
<8> DP0_AUXP_C AUX_P
DP-IN
DP0_AUXN_C 1 14 1 2 R1164 4.7K_0402_5%
GPIO
<8> DP0_AUXN_C AUX_N GPIO(PWM OUT) TL_INVT_PWM <22>
Close to L2 Close to P18 15 @ R1161 0_0402_5% MIIC_SCL 1 TL@ 2
DP0_TXP0_C GPIO(Panel_VCC) TL_ENVDD <22>
5 16 1 TL@ 2 R1165 4.7K_0402_5%
SWR_VDD <8> DP0_TXP0_C DP0_TXN0_C LANE0P GPIO(PWM IN) APU_INVT_PWM <10,22> MIIC_SDA
6 17 R1162 0_0402_5% 1 TL@ 2
<8> DP0_TXN0_C LANE0N GPIO(BL_EN) TL_BKOFF# <22>
R1166 4.7K_0402_5%
10U_0603_6.3V6M
0.1U_0402_16V4Z
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CSCL 1 TL@ 2
TL@ C21
TL@C21
TL@C1485
TL@
TL@C1486
TL@
TL@C1487
TL@
TL@C1488
TL@
1 1 1 1 1 Reserved for EC programming ROM CSCL 9 LVDS 29 APU_LVDS_CLK APU_LVDS_CLK <22> R1167 4.7K_0402_5%
CSDA CIICSCL1 MIICSCL1 APU_LVDS_DAT CSDA
10 EDID 28 APU_LVDS_DAT <22> 1 TL@ 2
Need EC confirm CIICSDA1 MIICDA1
C1485
C1486
C1487
C1488
Other
R1170 4.7K_0402_5%
2 2 2 2 2 32 ROM 31 MIIC_SCL
<10,22> LVDS_HPD HPD MIICSCL0
30 MIIC_SDA
MIICSDA0
8 DP_REXT
1
4 DP_GND GND 33
2
TL@ +3VS_PS Add for EC
Close to Pin13 R1168 TL@ 20101230
100K_0402_5% R30 RTD2132S-GR_QFN32_5X5
12K_0402_1%
2
TL@
2
Close to L3 +1.2VS Q90A
C @ L87 C
SWR_V12 2 1 CSDA 1 6 EC_SMB_DA2
EC_SMB_DA2 <6,14,36>
FBMA-L11-201209-221LMA30T_0805 Change to 12Kohm 1% (DG ref.)
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
20101114 DMN66D0LDW-7_SOT363-6 TL@
5
TL@C1489
TL@
TL@C1490
TL@
TL@C1491
TL@
TL@C1492
TL@
1 1 1 1 20110124 Modify Q90B

C1489
C1490
C1491
C1492
CSCL 4 3 EC_SMB_CK2
EC_SMB_CK2 <6,14,36>
2 2 2 2 DMN66D0LDW-7_SOT363-6
APU Co-lay eDP function Use common via

Close to
Pin27 DP0_TXP0_C APU_TXOUT2+
Close to Pin7 R1171 1 2 APUEDP@ 0_0402_5%
DP0_TXN0_C R1172 1 2 APUEDP@ 0_0402_5% APU_TXOUT2-
DP0_TXP1_C R1173 1 2 APUEDP@ 0_0402_5% APU_TXOUT1+
<8> DP0_TXP1_C DP0_TXN1_C APU_TXOUT1-
R1174 1 2 APUEDP@ 0_0402_5%
<8> DP0_TXN1_C
DP0_AUXP_C R1175 1 2 APUEDP@ 0_0402_5% APU_LVDS_CLK
DP0_AUXN_C R1176 1 2 APUEDP@ 0_0402_5% APU_LVDS_DAT
B B
A A

LVDS Translator - RTD2132S
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
5 4 3 2 1
+LCDVDD UMA/DIS LVDS/eDP Mapping table

Panel LCDVDD Control +3VS UMA DIS Panel
1
R707 +3VALW
60mils LVDS eDP LVDS eDP Conn.
300_0603_5% 1 APU_TXOUT0+ VGA_TXOUT0+ TXOUT0+
C1153 APU_TXOUT0- VGA_TXOUT0- TXOUT0-
1
4.7U_0603_6.3V6K
6 2
R708 APU_TXOUT1+ DP0_TXP1_R VGA_TXOUT1+ eDP_TX1P TXOUT1+
100K_0402_5% 2 APU_TXOUT1- DP0_TXN1_R VGA_TXOUT1- TXOUT1-
eDP_TX1N
3
Q28A APU_TXOUT2+ DP0_TXP0_R VGA_TXOUT2+ eDP_TX0P TXOUT2+
2
DMN66D0LDW-7_SOT363-6 2 2 1 2 Q29 APU_TXOUT2- DP0_TXN0_R VGA_TXOUT2- eDP_TX0N TXOUT2-
R709 1K_0402_5% AP2301GN-HF_SOT23-3
D APU_TXOUT_CLK+ VGA_TXCLK+ TXCLK+ D
1
3
+LCDVDD APU_TXOUT_CLK- VGA_TXCLK- TXCLK-
Q28B
R712 1 TL@ 2 0_0402_5% C1152 60mils
<21> TL_ENVDD
1
0.047U_0402_16V7K APU_TZOUT0+ VGA_TZOUT0+ TZOUT0+
2
4.7U_0603_6.3V6K
<10> APU_ENVDD
R710 1 @ 2 0_0402_5% 5 APU_TZOUT0- VGA_TZOUT0- TZOUT0-
1 1
C1149
<13> VGA_ENVDD
R711 1 DISO@ 2 0_0402_5% C1154 APU_TZOUT1+ VGA_TZOUT1+ TZOUT1+
4
UMA@ 0.1U_0402_16V4Z APU_TZOUT1- VGA_TZOUT1- TZOUT1-
VGA_ENVDD PD at VGA side R713
100K_0402_5% 2 2 APU_TZOUT2+ VGA_TZOUT2+ TZOUT2+
APU_TZOUT2- VGA_TZOUT2- TZOUT2-
1
APU_TZOUT_CLK+ VGA_TZCLK+ TZCLK+
APU_TZOUT_CLK- VGA_TZCLK- TZCLK-
+3VS EDP@
TL@ R714 0_0402_5% APU_LVDS_CLK DP0_AUXP_R VGA_LCD_CLK eDP_AUXP I2CC_SCL
Panel Backlight Control U22 APU_LVDS_DAT DP0_AUXN_R VGA_LCD_DATA eDP_AUXN I2CC_SDA
5
NC7SZ08P5X_NL_SC70-5
TL_BKOFF# R718 1 TL@ 2 0_0402_5% 2
P
<21> TL_BKOFF# B DISPOFF#
Y 4
BKOFF# 1
<36> BKOFF# A
1
1 TL@ 2
3
R715 10K_0402_5% R730
1 @ 2 10K_0402_5%
R722 10K_0402_5%
2
1 DISO@ 2 Mosify for Fn+F5 function issue +INVPWR_B+
R714 0_0402_5% B+ C1155
20110315 40mils
L36 680P_0402_50V7K
Panel PWM Control JLVDS1 W=60mils 1 2 2 1
EC_INVT_PWM 1 DISO@ 2 INVT_PWM +INVPWR_B+ FBMA-L11-201209-221LMA30T_0805
<36> EC_INVT_PWM 1
R716 0_0402_5% 2 1
2
2
C VGA_INVT_PWM @ Remove C
<13> VGA_INVT_PWM 1 2 3
R717 0_0402_5% R719 20110315 C1156
APU_INVT_PWM @ 100K_0402_5% 4 EDP_HPD 68P_0402_50V8J
<10,21> APU_INVT_PWM 1 2
R720 0_0402_5% 5 DISPOFF#
TL_INVT_PWM TL@ 6 INVT_PWM
<21> TL_INVT_PWM 1 2
1
R721 0_0402_5% 7
8 TXCLK+
9 TXCLK-
10
eDP HDP for APU and VGA 11
12
TXOUT2+ DISPOFF# 1 2
13
TXOUT2- eDP_TX0 C1163 220P_0402_50V7K
+3VSG +3VS +3VS INVT_PWM 1 2
14 TXOUT1+ C1164 220P_0402_50V7K
15
16
TXOUT1- eDP_TX1
1
VGAEDP@
R729 APUEDP@ EDP@ 17 TXOUT0+
10K_0402_5% R723 R724 18 TXOUT0-
10K_0402_5% 10K_0402_5% 19
VGAEDP@ 20 I2CC_SDA
2
21
<14> VGA_EDP_HPD 2 1
22
I2CC_SCL eDP_AUX @ D6
R725 0_0402_5% EDP@ EDP@ +3VS 6 1

23 I/O4 I/O1
3
APUEDP@ Q31B Q31A +LCDVDD

24
<10,21> LVDS_HPD 2 1 +3VS 5 2
R726 0_0402_5% 25 DAC_BRIG REF2 REF1
EDP_HPD 26 DAC_BRIG <36> USB20_P5 USB20_N5
5 2 2 EDP@ 1 +3VS 4 3
R727 200K_0402_5% 27 USB20_P5 I/O3 I/O2
28 USB20_P5 <26>
1
USB20_N5 PJUSB208H_SOT23-6
USB20_N5 <26>
4
29
R728 30
200K_0402_5% ACES_88341-3000B001
CONN@
2
B B
DG ref. Need close to eDP Conn.

Place near LVDS Conn 2 3 TXCLK+ 201011251400
<21> APU_TXOUT_CLK+ TXCLK-
<21> APU_TXOUT_CLK- 1 4
UMA@ RP1 0_0404_4P2R_5%
eDP_TX0P 2 3 TXOUT2+ +3VS
<21> APU_TXOUT2+ TXOUT2-
eDP_TX0N 1 4
Translator <21> APU_TXOUT2-
UMA@ RP2 0_0404_4P2R_5%
2
eDP_TX1P 2 3 TXOUT1+
LVDS Output eDP_TX1N
<21> APU_TXOUT1+
<21> APU_TXOUT1- 1 4 TXOUT1- APUEDP@
UMA@ RP4 0_0404_4P2R_5% R34
2 3 TXOUT0+ 100K_0402_5%
<21> APU_TXOUT0+
1 4 TXOUT0-
<21> APU_TXOUT0-
1
UMA@ RP5 0_0404_4P2R_5% I2CC_SDA

eDP_AUXP <21> APU_LVDS_CLK 1 4 I2CC_SCL
eDP_AUXN <21> APU_LVDS_DAT 2 3 I2CC_SDA I2CC_SCL 1 2
UMA@ RP6 0_0404_4P2R_5% APUEDP@ R33 100K_0402_5%
VGALVDS@ RP3 1 4 0_0404_4P2R_5% TXCLK+

<13> VGA_TXCLK+ TXCLK-
<13> VGA_TXCLK- 2 3 VGA Co-lay eDP function
eDP_TX0P VGALVDS@ R731 1 2 0_0402_5% TXOUT2+ VGAEDP@ R731 0.1U_0402_16V7K
<13> VGA_TXOUT2+
2
eDP_TX0N VGALVDS@ R733 1 2 0_0402_5% TXOUT2-

VGA <13> VGA_TXOUT2-
VGAEDP@ R733 0.1U_0402_16V7K
2
eDP_TX1P VGALVDS@ R734 1 2 0_0402_5% TXOUT1+

LVDS Output eDP_TX1N
<13> VGA_TXOUT1+
<13> VGA_TXOUT1-
VGALVDS@ R736 1 2 0_0402_5% TXOUT1- VGAEDP@ R734 0.1U_0402_16V7K
2
VGALVDS@ RP7 1 4 0_0404_4P2R_5% TXOUT0+ VGAEDP@ R736 0.1U_0402_16V7K

<13> VGA_TXOUT0+
2
2 3 TXOUT0-
A <13> VGA_TXOUT0- A
VGAEDP@ R741 0.1U_0402_16V7K
2
eDP_AUXP VGALVDS@ R741 1 2 0_0402_5% I2CC_SCL

<14> VGA_LCD_CLK
eDP_AUXN VGALVDS@ R742 1 2 0_0402_5% I2CC_SDA VGAEDP@ R742 0.1U_0402_16V7K
<14> VGA_LCD_DAT
2

LVDS/eDP Connector
B 1.0
P5WS5 LA-6973P
5 4 3 2 1
5 4 3 2 1
+HDMI_5V_OUT
+1.5VS +3VSG +1.5VS +HDMI_5V_OUT
W=40mils F1 W=40mils
+5VS 1 2
1
2
4.7K_0402_5%
UMA@
4.7K_0402_5%
UMA@
1.1A_6VDC_FUSE C1165
DISO@ UMA@ 0.1U_0402_16V4Z
R747 R748
1
2
2K_0402_1%
2K_0402_1%
0_0402_5% 0_0402_5%
R745
R746
R749
R750
2
1
D D
2
UMA@
2
G
Q32
1 DISO@ 2 3 1 HDMI_SCLK
<14> VGA_HDMI_SCLK R751 0_0402_5% JHDMI1
D
1 UMA@ 2 HDMI_HPD 19
HP_DET
2
<8> APU_HDMI_CLK
G
R752 0_0402_5% BSH111 1N_SOT23-3 +HDMI_5V_OUT 18
+5V
17
HDMI_SDATA HDMI_SDATA DDC/CEC_GND
1 DISO@ 2 3 1 16 SDA
<14> VGA_HDMI_SDATA R753 0_0402_5% HDMI_SCLK
D
15 SCL
1 UMA@ 2 UMA@ Q33 14
<8> APU_HDMI_DATA R754 0_0402_5% BSH111 1N_SOT23-3 Reserved
13 CEC
HDMI_R_CK- 12 20
CK- GND
G
11 CK_shield GND 21
DISO@ HDMI_R_CK+ 10 22
HDMI_R_D0- CK+ GND
Q32 9 D0- GND 23
2N7002_SOT23
D
8 D0_shield
HDMI_R_D0+ 7 D0+
G
HDMI_R_D1- 6
DISO@ D1-
5 D1_shield
+1.5VS +3VSG +5VS Q33 HDMI_R_D1+ 4
2N7002_SOT23 HDMI_R_D2- D1+
D
3 D2-
4.7K_0402_5%
2 2 D2_shield
1
BOM Option 20101117 HDMI_R_D2+ 1 D2+
R74
UMA@ DISO@
R73 R72 ACON_HMR2E-AK120D
1K_0402_5% 4.7K_0402_5% CONN@
1
2
<14> VGA_HDMI_DET 2 DISO@ 1
C R767 0_0402_5% C
3
6
<8> DP5_HPD 2 UMA@ 1
R771 0_0402_5%
For APU_HDMI_HPD
5 2 HDMI_HPD
Q96B Q96A
2
4
1
R75
100K_0402_5%
1
HDMI_C_CLK- R756 1 2 0_0402_5% HDMI_R_CK-
1 1 2
@ L38 2
WCM2012F2SF-900T04_0805
Place near C917~C924 and use common via 4 4
3
3
HDMI_C_CLK+ 1 2 HDMI_R_CK+
DISO@R757
DISO@R757 1 2 0_0402_5% HDMI_C_TX2-_R R765 0_0402_5%
<14> VGA_HDMI_TXD2- HDMI_C_TX2+_R
DISO@R758
DISO@R758 1 2 0_0402_5%
<14> VGA_HDMI_TXD2+ HDMI_C_TX1-_R HDMI_C_TX0- HDMI_R_D0-
DISO@R759
DISO@R759 1 2 0_0402_5% R769 1 2 0_0402_5%
<14> VGA_HDMI_TXD1- HDMI_C_TX1+_R
DISO@R760
DISO@R760 1 2 0_0402_5%
<14> VGA_HDMI_TXD1+ HDMI_C_TX0-_R
DISO@R761
DISO@R761 0_0402_5%
From VGA <14> VGA_HDMI_TXD0-
DISO@R763
DISO@R763
1
1
2
2 0_0402_5% HDMI_C_TX0+_R @ L39
1
1 2
2
<14> VGA_HDMI_TXD0+ HDMI_C_CLK-_R
DISO@R764
DISO@R764 1 2 0_0402_5% WCM2012F2SF-900T04_0805
<14> VGA_HDMI_TXC- HDMI_C_CLK+_R
DISO@R766
DISO@R766 1 2 0_0402_5% 4 4 3
<14> VGA_HDMI_TXC+ 3
HDMI_C_TX0+ 1 2 HDMI_R_D0+
B UMA@ R770
UMA@R770 0_0402_5% HDMI_C_TX2-_R R779 0_0402_5% B
<6> PCIE_FTX_GRX_N12 1 2
UMA@R772
UMA@ R772 1 2 0_0402_5% HDMI_C_TX2+_R
<6> PCIE_FTX_GRX_P12 HDMI_C_TX1-_R HDMI_C_TX1- HDMI_R_D1-
UMA@R773
UMA@ R773 1 2 0_0402_5% R781 1 2 0_0402_5%
<6> PCIE_FTX_GRX_N13 HDMI_C_TX1+_R
UMA@R774
UMA@ R774 1 2 0_0402_5%
<6> PCIE_FTX_GRX_P13
UMA@R776
UMA@ R776 0_0402_5% HDMI_C_TX0-_R
From APU <6> PCIE_FTX_GRX_N14
UMA@R777
UMA@ R777
1
1
2
2 0_0402_5% HDMI_C_TX0+_R @ L40
1 1
2
2
<6> PCIE_FTX_GRX_P14
Change to 12~15 for AMD req. UMA@R778
UMA@ R778 1 2 0_0402_5% HDMI_C_CLK-_R WCM2012F2SF-900T04_0805
<6> PCIE_FTX_GRX_N15 HDMI_C_CLK+_R
201012031500 UMA@R780
UMA@ R780 1 2 0_0402_5% 4 4 3
<6> PCIE_FTX_GRX_P15 3
HDMI_C_TX1+ 1 2 HDMI_R_D1+
R782 0_0402_5%
Near the connector HDMI_C_TX2- R783 1 2 0_0402_5% HDMI_R_D2-
HDMI_C_TX2-_R C1166 2 1 0.1U_0402_16V7K HDMI_C_TX2- R784 1 2DISO@499_0402_1% UMA use 604 ohm 1 1 2
HDMI_C_TX2+_R 2
C1167 2 1 0.1U_0402_16V7K HDMI_C_TX2+ R786 1 2DISO@499_0402_1% @ L41
VGA use 499 ohm WCM2012F2SF-900T04_0805
HDMI_C_TX1-_R C1168 2 1 0.1U_0402_16V7K HDMI_C_TX1- R788 1 2DISO@499_0402_1% 4 4 3
HDMI_C_TX1+_R 3
C1169 2 1 0.1U_0402_16V7K HDMI_C_TX1+ R790 1 2DISO@499_0402_1% For UMA HDMI HDMI_C_TX2+ 1 2 HDMI_R_D2+
HDMI_C_TX0-_R C1170 2 1 0.1U_0402_16V7K HDMI_C_TX0- R792 1 2DISO@499_0402_1% termination BOM option R794 0_0402_5%
HDMI_C_TX0+_R C1171 2 1 0.1U_0402_16V7K HDMI_C_TX0+ R795 1 2DISO@499_0402_1%
HDMI_C_CLK-_R C1172 2 1 0.1U_0402_16V7K HDMI_C_CLK- R797 1 2DISO@499_0402_1% R784 2 UMA@1 604_0402_1%
HDMI_C_CLK+_R C1173 2 1 0.1U_0402_16V7K HDMI_C_CLK+ R799 1 2DISO@499_0402_1% R786 2 UMA@1 604_0402_1%
1
D R788 2 UMA@1 604_0402_1%

+HDMI_5V_OUT 2 Q35 R790 2 UMA@1 604_0402_1%
G 2N7002_SOT23
1
S R792 2 UMA@1 604_0402_1%

3
R801 R795 2 UMA@1 604_0402_1%

A 100K_0402_5% R797 2 UMA@1 604_0402_1% A
R799 2 UMA@1 604_0402_1%
2

HDMI Connector
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
A B C D E
W=40mils
+5VS +R_CRT_VCC +CRT_VCC
2
D22 F2 W=40mils
2 1 1 2
RB491D_SC59-3 1.1A_6VDC_FUSE
@ @ 1
D20 D21
PJDLC05C_SOT23-3 PJDLC05C_SOT23-3 C1174
0.1U_0402_16V4Z
1 2 1
1
T19
CRT_R L42 1 2 FCM2012CF-800T06_2P CRT_R_2 JCRT1
CRT_G L43 1 CRT_G_2

6
11 CRT Connector
2 FCM2012CF-800T06_2P 1
CRT_B L44 1 CRT_B_2

7
12 Follow P5WE0
2 FCM2012CF-800T06_2P 2
8
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
13
1
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1 3
C1175
C1176
C1177
C1178
C1179
C1180
9
R805
R806
R807
14 G 16
4 G 17
2 2 2 2 2 2 10
2
15
1 5
C1181
100P_0402_50V8J CONN@
2 T20 C-H_13-12201513CP
+CRT_VCC
L45 1 2 CRT_HSYNC_2
C1182 1 2 0.1U_0402_16V4Z R808 2 1 10K_0402_5% FCM2012CF-800T06_2P DSUB_12
L46 1 2 CRT_VSYNC_2 1
5
FCM2012CF-800T06_2P 1 1
OE#
P
2 CRT_HSYNC CRT_HSYNC_1 C1183 C1184 DSUB_15 2

2 A Y 4
10P_0402_50V8J 10P_0402_50V8J C1185 2
G
U23 2 2 68P_0402_50V8J 1
74AHCT1G125GW_SOT353-5
3
C1186
+CRT_VCC 68P_0402_50V8J
2
C1187 1 2 0.1U_0402_16V4Z
5
1
OE#
P
CRT_VSYNC 2 4 CRT_VSYNC_1
A Y
G
U24
74AHCT1G125GW_SOT353-5
3
Use common via Close to Conn side

FCH_CRT_R R809 2 UMA@ 1 0_0402_5% CRT_R +3VSG +CRT_VCC
<27> FCH_CRT_R
FCH_CRT_G R810 2 UMA@ 1 0_0402_5% CRT_G
<27> FCH_CRT_G
FCH_CRT_B R811 2 UMA@ 1 0_0402_5% CRT_B
<27> FCH_CRT_B
1
3 FCH_CRT_HSYNC R814 2 UMA@ 1 0_0402_5% CRT_HSYNC R812 R813 3
From FCH <27> FCH_CRT_HSYNC
DISO@ 4.7K_0402_5% 4.7K_0402_5%
2
FCH_CRT_VSYNC R815 2 UMA@ 1 0_0402_5% CRT_VSYNC Q5A
<27> FCH_CRT_VSYNC
2
FCH_CRT_DDC_SDA R816 2 UMA@ 1 0_0402_5% DSUB_12 VGA_CRT_DATA 1 6 DSUB_12
<27> FCH_CRT_DDC_SDA
FCH_CRT_DDC_SCL R817 2 UMA@ 1 0_0402_5% DSUB_15 DMN66D0LDW-7_SOT363-6 DISO@
<27> FCH_CRT_DDC_SCL
5
Q5B
VGA_CRT_CLK 4 3 DSUB_15
VGA_CRT_R R818 2 DISO@ 1 0_0402_5% CRT_R
<14> VGA_CRT_R
Change to 2N7002DW
VGA_CRT_G R819 2 DISO@ 1 0_0402_5% CRT_G 20101111
<14> VGA_CRT_G
VGA_CRT_B R820 2 DISO@ 1 0_0402_5% CRT_B
<14> VGA_CRT_B
From VGA VGA_CRT_HSYNC R821 2 DISO@ 1 0_0402_5% CRT_HSYNC
<14> VGA_CRT_HSYNC
VGA_CRT_VSYNC R822 2 DISO@ 1 0_0402_5% CRT_VSYNC
<14> VGA_CRT_VSYNC
VGA_CRT_DATA
<14> VGA_CRT_DATA
<14> VGA_CRT_CLK VGA_CRT_CLK
4 4

CRT Connector
B 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
U25A
C1188 1 2 150P_0402_50V8J
HUDSON-2
PCI Host Bus Reset (To EC) APU_PCIE_RST#_C AE2 AF3
R825 1 PCIE_RST# PCICLK0
2 33_0402_5% AD5 AF1
PCI CLKS
<10,36> PLT_RST# A_RST# PCICLK1/GPO36 PCI_CLK1 <28>
PCICLK2/GPO37 AF5
C1189 1 2 0.1U_0402_16V7K UMI_MTX_FRX_P0 AE30 AG2
<6> UMI_MTX_C_FRX_P0 UMI_MTX_FRX_N0 UMI_TX0P PCICLK3/GPO38 PCI_CLK3 <28>
C1190 1 2 0.1U_0402_16V7K AE32 AF6
<6> UMI_MTX_C_FRX_N0 UMI_MTX_FRX_P1 UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 <28> +3VALW
C1191 1 2 0.1U_0402_16V7K AD33
<6> UMI_MTX_C_FRX_P1 UMI_MTX_FRX_N1 UMI_TX1P
C1192 1 2 0.1U_0402_16V7K AD31 AB5 For PCIE device reset on FS1 C1193
<6> UMI_MTX_C_FRX_N1 UMI_MTX_FRX_P2 UMI_TX1N PCIRST#
C1196 1 2 0.1U_0402_16V7K AD28 (GFX,GLAN,WLAN,LVDS Travis) 1 2
<6> UMI_MTX_C_FRX_P2 UMI_MTX_FRX_N2 UMI_TX2P
C1197 1 2 0.1U_0402_16V7K AD29
<6> UMI_MTX_C_FRX_N2 UMI_MTX_FRX_P3 UMI_TX2N
C1198 1 2 0.1U_0402_16V7K AC30 AJ3 0.1U_0402_16V4Z
<6> UMI_MTX_C_FRX_P3 UMI_TX3P AD0/GPIO0
5
C1194 1 2 0.1U_0402_16V7K UMI_MTX_FRX_N3 AC32 AL5
<6> UMI_MTX_C_FRX_N3 UMI_TX3N AD1/GPIO1
AG4 2
P
1 UMI_FTX_C_MRX_P0 AD2/GPIO2 APU_PCIE_RST#_C R829 1 B 1
<6> UMI_FTX_C_MRX_P0 AB33
UMI_RX0P AD3/GPIO3
AL6 2 33_0402_5% Y
4 APU_PCIE_RST# <13,31,33>
UMI_FTX_C_MRX_N0 AB31 AH3 1
<6> UMI_FTX_C_MRX_N0
PCI EXPRESS INTERFACES

UMI_RX0N AD4/GPIO4 A
G
2
UMI_FTX_C_MRX_P1 AB28 AJ5 1 U26
<6> UMI_FTX_C_MRX_P1 UMI_RX1P AD5/GPIO5
UMI_FTX_C_MRX_N1 AB29 AL1 R826 NC7SZ08P5X_NL_SC70-5
<6> UMI_FTX_C_MRX_N1
3
UMI_FTX_C_MRX_P2 UMI_RX1N AD6/GPIO6 C1195 @ 8.2K_0402_5%
<6> UMI_FTX_C_MRX_P2 Y33 AN5
UMI_FTX_C_MRX_N2 UMI_RX2P AD7/GPIO7 150P_0402_50V8J
<6> UMI_FTX_C_MRX_N2 Y31 AN6
UMI_FTX_C_MRX_P3 UMI_RX2N AD8/GPIO8 2
<6> UMI_FTX_C_MRX_P3 Y28 AJ1
1
UMI_FTX_C_MRX_N3 UMI_RX3P AD9/GPIO9
<6> UMI_FTX_C_MRX_N3 Y29 AL8
UMI_RX3N AD10/GPIO10
AL3
AD11/GPIO11 +3VALW
R827 1 2 590_0402_1% PCIE_CALRP AF29 AM7
PCIE_CALRP AD12/GPIO12
+PCIE_VDDR_FCH R828 1 2 2K_0402_1% PCIE_CALRN AF31
PCIE_CALRN AD13/GPIO13
AJ6 @ C1199
AD14/GPIO14 AK7 1 2
V33 GPP_TX0P AD15/GPIO15 AN8
V31 AG9 0.1U_0402_16V4Z
GPP_TX0N AD16/GPIO16
5
W30 AM11 @U27
@ U27
GPP_TX1P AD17/GPIO17
W32 AJ10 2 B
P
GPP_TX1N AD18/GPIO18 VGA_PWRGD VGA_PWRGD_R
AB26 GPP_TX2P AD19/GPIO19 AL12 <20,47> VGA_PWRGD Y 4 1 2
AB27 AK11 1 http://ISPDPRD/Windchill/servlet/WindchillAuthGW/wt.enterprise.URLProcessor/UR
R830INS60031349http://ISPDPRD/Windchill/servlet/WindchillAuthGW/wt.enterprise.URLProce
GPP_TX2N AD20/GPIO20 A
G
AA24 GPP_TX3P AD21/GPIO21 AN12
AA23 AG12 NC7SZ08P5X_NL_SC70-5
3
GPP_TX3N AD22/GPIO22
AD23/GPIO23 AE12 PCI_AD23 <28> 1 2
AA27 AC12 R831 @ 100K_0402_5%
GPP_RX0P AD24/GPIO24 PCI_AD24 <28>
AA26 GPP_RX0N AD25/GPIO25 AE13 PCI_AD25 <28>
W27 AF13 1 2
PCI INTERFACE
GPP_RX1P AD26/GPIO26 PCI_AD26 <28>
V27 AH13 R832 0_0402_5%
GPP_RX1N AD27/GPIO27 PCI_AD27 <28>
V26 AH14 VGA_PWRGD_R
GPP Port0 For USB30 on SUS/B W26
GPP_RX2P AD28/GPIO28
AD15
GPP Port1 For USB30 on M/B 20101103 W24
GPP_RX2N AD29/GPIO29
AC15
W23
GPP_RX3P
GPP_RX3N
AD30/GPIO30
AD31/GPIO31 AE16
AN3
Level shift to ISL6267
CBE0#
CBE1# AJ8
AN10 +1.5VS +3VS
2 CBE2# 2
+1.1VS_CKVDD R833 1 2 2K_0402_1% CLK_CALRN F27 CLK_CALRN CBE3# AD12
FRAME# AG10
1
DEVSEL# AK9
AL10 Q38 change to SB000006A00
IRDY# R834
G30 AF10 20101228
PCIE_RCLKP TRDY#
2
For "EXT" CLK mode, input to PCIE, 10K_0402_5%
SS G28 PCIE_RCLKN PAR AE10
AH1 R836
2 2
APU_DISP_CLKP STOP#
<8> APU_DISP_CLKP R26 AM9 4.7K_0402_5%
DISP_CLKP PERR#
B
APU_DISP_CLKN
APU DISP <8> APU_DISP_CLKN T26
DISP_CLKN SERR#
AH8
AG15
1
REQ0#
E
APU_PWRGD
NSS H33
DISP2_CLKP REQ1#/GPIO40
AG13 3 1 APU_PWRGD_L <48>
C
H31 AF15 Q38
DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41 MMBT3904_NL_SOT23-3
AM17 T23
APU_CLKP REQ3#/CLK_REQ5#/GPIO42
<8> APU_CLKP T24 AD16
APU_CLKN APU_CLKP GNT0#
T23 AD13 1 PX@ 2
APU <8> APU_CLKN APU_CLKN GNT1#/GPO44
AD21 R842 1 2 0_0402_5%
PE_GPIO0 <13>
RTC BATT Conn.

CLK_PEG_VGA GNT2#/SD_LED/GPO45 PE_GPIO1 <20>
<13> CLK_PEG_VGA J30
SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46
AK17 T24 R843 PX@ 0_0402_5%
VGA CLK_PEG_VGA# K29 AD19
<13> CLK_PEG_VGA# SLT_GFX_CLKN CLKRUN#
AH9 +RTCBATT
LOCK#
H27
GPP_CLK0P
1
H28 AF18 CONN@
GPP_CLK0N INTE#/GPIO32 JBATT1
AE18
+
INTF#/GPIO33
J27 AC16
GPP_CLK1P INTG#/GPIO34
K26 AD18
GPP_CLK1N INTH#/GPIO35
CLK_PCIE_MINI1 F33
CLOCK GENERATOR
<33> CLK_PCIE_MINI1 CLK_PCIE_MINI1# GPP_CLK2P

MINI1-WLAN <33> CLK_PCIE_MINI1# F31
GPP_CLK2N LPC_CLK0_EC
SS CLK_PCIE_LAN E33
LPCCLK0
B25 LPC_CLK0_EC <28,36>
<31> CLK_PCIE_LAN CLK_PCIE_LAN# GPP_CLK3P LPC_CLK1
GLAN <31> CLK_PCIE_LAN# E31
GPP_CLK3N LPCCLK1
D25 LPC_CLK1 <28>
D27 LPC_LAD0
LAD0 LPC_AD0 <36>
M23 C28 LPC_LAD1
3 GPP_CLK4P LAD1 LPC_AD1 <36> 3
MINI2-OPT Remove MINI2 LPC_LAD2
-
M24
GPP_CLK4N LAD2
A26
LPC_LAD3
LPC_AD2 <36> P/N: SP07000OU00
SUYIN_060003HA002G202ZL
LPC
A29 LPC_AD3 <36>
2
M27
LAD3
A31 LPC_FRAME# <36>
F/P: SUYIN_060003HA002G202ZL_2P
GPP_CLK5P LFRAME#
M26 B27
GPP_CLK5N LDRQ0#
AE27
LDRQ1#/CLK_REQ6#/GPIO49
N25 AE19 SERIRQ <36>
GPP_CLK6P SERIRQ/GPIO48
N26
GPP_CLK6N APU_PWRGD
R23 C41 33P_0402_50V8J
GPP_CLK7P APU_RST#
R24 G25 ALLOW_STOP <8>
GPP_CLK7N DMA_ACTIVE# R853 1 @
E28 2 0_0402_5% EC_THERM# <8,36,48>
C42 33P_0402_50V8J
PROCHOT# APU_PWRGD Add C41 / C42 for ESD 20110313
N27 E26 APU_PWRGD <8>
GPP_CLK8P APU_PG
Change C41,C42 from 10p to 33p for ESD 20110416
APU
R27 G26
GPP_CLK8N LDT_STP# APU_RST#
F26 APU_RST# <8>
APU_RST#
APU_PG/APU_RST#/LDT_STP# : OD pin
J26
14M_25M_48M_OSC DMA_ACTIVE# : IN/OD, 0.8V threshold
H7 PROCHOT# : IN, 0.8V threshold +RTCBATT
S5_CORE_EN R855 1
F1 2 22_0402_5% RTC_CLK <28,36> LDT_STP : No use, NC
RTCCLK
INTRUDER_ALERT#
F3 DMA active. The FCH drives the DMA_ACTIVE# to
1
1 2 1 2 25M_X1 C31 E6
25M_X1 VDDBT_RTC_G APU to notify DMA activity. This will cause the APU
C1200 R856 0_0402_5% R857
S5 PLUS
to reestablish the UMI link quicker.

1
27P_0402_50V8J G2 32K_X1 1K_0402_5%

R858 32K_X1
X1 1M_0402_5% 25M_X2 C33 D23
2
25M_X2 +RTCVCC
25MHZ_20PF_7A25000012
2
G4 32K_X2 2
32K_X2 RTCVCC_R
1 2 1 2 1
C1201 R859 510_0402_5% 3 +CHGRTC
0.1U_0402_16V4Z
27P_0402_50V8J C1202 1 1 C1203 W=20mils
2
0.1U_0402_16V4Z
1U_0402_6.3V4Z
HUDSON-M2_FCBGA656 1
@ R860 C1204 DAN202UT106_SC70-3
@
4 2 2 4
for Clear CMOS 0_0603_5%
2
C1205 1 2 32K_X1
1
15P_0402_50V8J Y4
1
4 OSC NC 3
For RTC issue
Change C1205,C1206 from 22pF to 15pF R861 1 2
20M_0402_5% OSC NC
20110420
32.768KHZ_12.5PF_Q13MC14610002 Security Classification Compal Secret Data Compal Electronics, Inc.
2

C1206 1 32K_X2
2
Hudson-M2/M3-UMI/PCI/CLOCK/LPC/RTC
15P_0402_50V8J Close to HUDSON-M2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
PCIE_RST2 : Reset PCIE device on Hudson2

U25D
HUDSON-2
AB6 G8
USB MISC
PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
<36> EC_LID_OUT# R2 RI#/GEVENT22#
W7 B9 USB_RCOMP R863 1 2 11.8K_0402_1%
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
<36> SLP_S3# T3 SLP_S3#
<36> SLP_S5# W2 SLP_S5# USB_FSD1P/GPIO186 H1
<36> PBTN_OUT# J4 PWR_BTN# USB_FSD1N H3 Hudson-M2/M3
<36> FCH_PWRGD N7 PWR_GOOD OHCI CTL
USB 1.1
H6 USBFS_P0 DEV 20, Fn 5
USB_FSD0P/GPIO185 USBFS_P0 <35>
ACPI / WAKE UP EVENTS

TEST0 T9 H5 USBFS_N0 BT <Disable CTL>
TEST0 USB_FSD0N USBFS_N0 <35>
TEST1 T10
1 TEST2 TEST1/TMS 1
V9 H10
TEST2 USB_HSD13P
G10
USB_HSD13N
<36> EC_GA20 AE22
GA20IN/GEVENT0# USB30_P12
USB_HSD12P
K10 USB30_P12 <34> Hudson-M2 Hudson-M3
AG19 J12 USB30_N12 30 Pin Sub board USB3.0 Conn EHCI CTL xHCI CTL
<36> EC_KBRST# KBRST#/GEVENT1# USB_HSD12N USB30_N12 <34>
<36> EC_SCI# R9
LPC_PME#/GEVENT3# DEV 22, Fn 2 DEV 16, Fn 1
C26 G12 USB30_P11 <Disable CTL of M2> xHCI CTL
<36> EC_SMI# LPC_SMI#/GEVENT23# USB_HSD11P USB30_N11 USB30_P11 <34>
T5
LPC_PD#/GEVENT5# USB_HSD11N
F12 USB30_N11 <34> 30 Pin Sub board USB3.0 Conn DEV 16, Fn 0
+3VALW 1 @ 2 SYS_RESET# U4
SYS_RESET#/GEVENT19#
R18 10K_0402_5% K1 K12 USB30_P10
<31,33> FCH_PCIE_WAKE# WAKE#/GEVENT8# USB_HSD10P USB30_N10 USB30_P10 <34>
V7
IR_RX1/GEVENT20# USB_HSD10N
K13 USB30_N10 <34> On board USB Conn
THERMTRIP: <8> H_THERMTRIP# R10 THRMTRIP#/SMBALERT#/GEVENT2#
Need level shift from +3VALW to +1.5V +3VS 1 2 AF19 WD_PWRGD USB_HSD9P B11
R862 10K_0402_5% D11 Hudson-M2/M3
USB_HSD9N
<36> EC_RSMRST# U2 RSMRST# EHCI CTL
E10 USB20_P8 DEV 19, Fn 2
USB_HSD8P USB20_N8 USB20_P8 <33>
Remove MINI2 AG24 F10 Mini1-WLAN
LAN_CLKREQ#_1 CLK_REQ4#/SATA_IS0#/GPIO64 USB_HSD8N USB20_N8 <33>
<31> LAN_CLKREQ# 1 2 AE24 CLK_REQ3#/SATA_IS1#/GPIO63
@ D17 CH751H-40PT_SOD323-2 AE26 C10 USB20_P7
SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD7P USB20_N7 USB20_P7 <35>
R81 1 2 0_0402_5% AF22 A10 3G
USB 2.0
CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N USB20_N7 <35>
AH17 SATA_IS4#/FANOUT3/GPIO55
AG18 H9 USB20_P6
SATA_IS5#/FANIN3/GPIO59 USB_HSD6P USB20_N6 USB20_P6 <35>
<38> FCH_SPKR AF24 SPKR/GPIO66 USB_HSD6N G9 USB20_N6 <35> 3G
FCH_SCLK0
GPIO
<11,12,33> FCH_SCLK0 AD26 SCL0/GPIO43
SM bus 0-->S0 PWR domain FCH_SDATA0 AD25 A8 USB20_P5
<11,12,33> FCH_SDATA0 SDA0/GPIO47 USB_HSD5P USB20_P5 <22>
FCH_SCLK1 T7 C8 USB20_N5 Camera
SM bus 1-->S5 PWR domain FCH_SDATA1 SCL1/GPIO227 USB_HSD5N USB20_N5 <22>
R7 SDA1/GPIO228
VGA_PD: Support MLDAC power MINI1_CLKREQ# AG25 F8
<33> MINI1_CLKREQ# CLK_REQ2#/FANIN4/GPIO62 USB_HSD4P
save if connect AG22 CLK_REQ1#/FANOUT4/GPIO61 USB_HSD4N E8 Hudson-M2/M3
0: MLDAC power on
J2 IR_LED#/LLB#/GPIO184 EHCI CTL
AG26 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD3P C6 DEV 18, Fn 2
1: MLDAC power off VGA_PD V8 A6 <Support Wakeup>
2 +3VS <28> VGA_PD DDR3_RST#/GEVENT7#/VGA_PD USB_HSD3N 2
W8 GBE_LED0/GPIO183
+3VS Y6 C5
SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD2P
V10 GBE_LED2/GEVENT10# USB_HSD2N A5
2
ZERO@ AA8 USB20_P0

GBE_STAT0/GEVENT11#
2
R954 AF25 C1
10K_0402_5% CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P For SW debug @
USB_HSD1N C3
2
G
20110315 R82
M7 E1 USB20_P0 0_0402_5%
1
ODD_DA#_1 BLINK/USB_OC7#/GEVENT18# USB_HSD0P USB20_N0 Remove MINI2 USB20_N0

<30> ODD_DA# 3 1 R8 E3 Mini2-Option
1
R78 USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N
2 0_0402_5%
S
1 T1
USB OC
<30> ODD_PLUG# ODD_DA#_1 USB_OC5#/IR_TX0/GEVENT17# USBSS_CALRP
Q84 ZERO@ ZERO@ P6 C16 R864 1 M3@ 2 1K_0402_1%
2N7002_SOT23 USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP USBSS_CALRN R865 1
F5 A16 2 1K_0402_1% +FCH_VDD_11_SSUSB_S
T28 USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN M3@
P5
USB_OC1# USB_OC2#/TCK/GEVENT14# USB30_MTX_DRX_P3 C25 1
<34> USB_OC1# J7 A14 2 0.1U_0402_16V7K USB30_MTX_C_DRX_P3 <35>
USB_OC0# USB_OC1#/TDI/GEVENT13# USB_SS_TX3P USB30_MTX_DRX_N3 C26 1
<34> USB_OC0# T8
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N
C14 2 0.1U_0402_16V7K USB30_MTX_C_DRX_N3 <35> Hudson-M3
M3@ M3@ HD Camera xHCI CTL
C12 USB30_MRX_DTX_P3 DEV 16, Fn 1
USB_SS_RX3P USB30_MRX_DTX_N3 USB30_MRX_DTX_P3 <35>
USB_SS_RX3N
A12 USB30_MRX_DTX_N3 <35> xHCI CTL
DEV 16, Fn 0
R866 1 2 33_0402_5% HDA_BITCLK AB3 D15 USB30_MTX_DRX_P2
<38> HDA_BITCLK_AUDIO HDA_SDOUT AZ_BITCLK USB_SS_TX2P USB30_MTX_DRX_N2 USB30_MTX_DRX_P2 <34>
R867 1 2 33_0402_5% AB1 B15
<38> HDA_SDOUT_AUDIO AZ_SDOUT USB_SS_TX2N USB30_MTX_DRX_N2 <34>
HDA_SDIN0 AA2 30 Pin Sub board
HD AUDIO
<38> HDA_SDIN0 AZ_SDIN0/GPIO167
HDA_SDIN1 Y5 E14 USB30_MRX_DTX_P2
USB3.0 Conn
USB 3.0
AZ_SDIN1/GPIO168 USB_SS_RX2P USB30_MRX_DTX_N2 USB30_MRX_DTX_P2 <34>
Y3 F14 USB30_MRX_DTX_N2 <34>
AZ_SDIN2/GPIO169 USB_SS_RX2N
Y1
R868 1 HDA_SYNC AZ_SDIN3/GPIO170 USB30_MTX_DRX_P1
<38> HDA_SYNC_AUDIO 2 33_0402_5% AD6 F15 USB30_MTX_DRX_P1 <34>
R869 1 HDA_RST# AZ_SYNC USB_SS_TX1P USB30_MTX_DRX_N1
<38> HDA_RST_AUDIO# 2 33_0402_5% AE4 G15 USB30_MTX_DRX_N1 <34>
AZ_RST# USB_SS_TX1N
30 Pin Sub board
H13 USB30_MRX_DTX_P1
+3VALW USB_SS_RX1P USB30_MRX_DTX_N1 USB30_MRX_DTX_P1 <34> USB3.0 Conn
G13 USB30_MRX_DTX_N1 <34>
+3VALW USB_SS_RX1N
K19 J16 USB30_MTX_DRX_P0 C39 1 2 0.1U_0402_16V7K
3 PS2_DAT/SDA4/GPIO187 USB_SS_TX0P USB30_MTX_C_DRX_P0 <34> 3
T27 J19 H16 USB30_MTX_DRX_N0 C37 1 2 0.1U_0402_16V7K On board
PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N USB30_MTX_C_DRX_N0 <34>
8.2K_0402_5%
8.2K_0402_5%
PX@ R45
8.2K_0402_5%
VGA@ R43
1 2 USB_OC1# @ J21 M3@ M3@

SPI_CS2#/GBE_STAT2/GPIO166 USB Conn
1
R54 100K_0402_5% J15 USB30_MRX_DTX_P0

H_THERMTRIP# USB_SS_RX0P USB30_MRX_DTX_N0 USB30_MRX_DTX_P0 <34>
1 2 K15 USB30_MRX_DTX_N0 <34>
USB_SS_RX0N
R47
R871 10K_0402_5%
1 2 FCH_SCLK1 FCH_GPIO189 D21
R874 2.2K_0402_5% FCH_GPIO190 PS2KB_DAT/GPIO189 R870 1
C20 H19 2 10K_0402_5%
2
FCH_SDATA1 FCH_GPIO189 FCH_GPIO191 PS2KB_CLK/GPIO190 SCL2/GPIO193 R872 1

1 2 D23
PS2M_DAT/GPIO191 SDA2/GPIO194
G19 2 10K_0402_5%
R876 2.2K_0402_5% FCH_GPIO190 C22 EMBEDDED CTRL G22 APU_SIC
PS2M_CLK/GPIO192 SCL3_LV/GPIO195 APU_SIC <6,8>
1 @ 2 EC_LID_OUT# FCH_GPIO191 G21 APU_SID
SDA3_LV/GPIO196 APU_SID <6,8>
R877 100K_0402_5% E22
EC_PWM0/EC_TIMER0/GPIO197
1
1
8.2K_0402_5%
R48
8.2K_0402_5%
WOPX@ R46
8.2K_0402_5%
UMAO@ R44
1 2 FCH_PCIE_WAKE# H22
R878 10K_0402_5% EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2
Project SKU ID F21
KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
J22 EC_PWM2 <28>
E20 H21
GPIO189 (use VGA) L(NO) H(YES) KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200
F20
KSO_2/GPIO211
R44 R43 A22 K21
2
GPIO190 (use PX) L(NO) H(YES) KSO_3/GPIO212 KSI_0/GPIO201

E18
KSO_4/GPIO213 KSI_1/GPIO202
K22 For PCIE device reset on FS1
R46 R45 A20 F22 (GFX,GLAN,WLAN,LVDS Travis)
+3VS GPIO191 L(15") H(17") KSO_5/GPIO214 KSI_2/GPIO203
J18 F24
KSO_6/GPIO215 KSI_3/GPIO204
R48 R47 H18 E24
FCH_SCLK0 Add Project ID Table KSO_7/GPIO216 KSI_4/GPIO205
1 2 G18 B23
R880 2.2K_0402_5% KSO_8/GPIO217 KSI_5/GPIO206
201011301600 B21 C24
FCH_SDATA0 KSO_9/GPIO218 KSI_6/GPIO207
1 2 K18 F18
R881 2.2K_0402_5% KSO_10/GPIO219 KSI_7/GPIO208
D19
MINI1_CLKREQ# KSO_11/GPIO220
1 2 A18
R882 8.2K_0402_5% KSO_12/GPIO221
C18
KSO_13/GPIO222
B19
KSO_14/GPIO223
B17
KSO_15/GPIO224
A24
KSO_16/GPIO225
D17
KSO_17/GPIO226
4 LAN_CLKREQ#_1 HUDSON-M2_FCBGA656 4
1 2
R940 8.2K_0402_5% @
Modify 20101111
1 2 EC_RSMRST# +3VALW For FCH internal debug use

R884 2.2K_0402_5%
1 @ 2 HDA_BITCLK 1 @ 2 TEST0
R885 10K_0402_5% R887 2.2K_0402_5%
1 @ 2 HDA_SDIN0 1 @ 2 TEST1 Security Classification Compal Secret Data Compal Electronics, Inc.
R886 10K_0402_5% R889 2.2K_0402_5% Issued Date 2010/08/04 2010/08/04 Title
@ HDA_SDIN1 @ TEST2 Deciphered Date
1
R888
2
10K_0402_5% R890
1 2
2.2K_0402_5%
Hudson-M2/M3-ACPI/USB/EC
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
U25B SYS BIOS ROM 0.1U_0402_16V4Z C466

+3VALW
HUDSON-2 2 1
AK19 AL14 +3VALW
<30> SATA_STX_DRX_P0 SATA_TX0P SD_CLK/SCLK_2/GPIO73
AM19 AN14 U28
<30> SATA_STX_DRX_N0 SATA_TX0N SD_CMD/SLOAD_2/GPIO74 FCH_SPI_CS1#
HDD1 SD_CD/GPIO75 AJ12 1
R626 1
2
FCH_SPI_WP#
1 CS# VCC 8
FCH_SPI_CLK
<30> SATA_DTX_C_SRX_N0 AL20 SATA_RX0N SD_WP/GPIO76 AH12 2 1K_0402_5% 3 WP# SCLK 6
SD CARD
AN20 AK13 R934 1 2 10K_0402_5% FCH_SPI_HOLD# 7 5 FCH_SPI_MOSI
<30> SATA_DTX_C_SRX_P0 SATA_RX0P SD_DATA0/SDATI_2/GPIO77 HOLD# SI FCH_SPI_MISO
AM13 R935 10K_0402_5% 4 2
SD_DATA1/SDATO_2/GPIO78 GND SO
<30> SATA_STX_DRX_P1 AN22 SATA_TX1P SD_DATA2/GPIO79 AH15
AL22 AJ14 MX25L1606EM2I-12G SOP 8P
<30> SATA_STX_DRX_N1 SATA_TX1N SD_DATA3/GPIO80
ODD SA000041N00
AH20 AC4 GBE_COL
<30> SATA_DTX_C_SRX_N1 SATA_RX1N GBE_COL
AJ20 AD3 GBE_CRS @ R36 @ C23
1 <30> SATA_DTX_C_SRX_P1 SATA_RX1P GBE_CRS FCH_SPI_CLK 1
AD9 1 2 1 2
GBE_MDCK GBE_MDIO 10_0402_5%
AJ22 W10
SATA_TX2P GBE_MDIO 10P_0402_50V8J
AH22 AB8
SATA_TX2N GBE_RXCLK Add for EMI 201011291330
HDD2 GBE_RXD3
AH7
AM23 AF7
SATA_RX2N GBE_RXD2
AK23 AE7
SATA_RX2P GBE_RXD1 +3VALW
AD7
GBE_RXD0
AH24 AG8
SATA_TX3P GBE_RXCTL/RXDV GBE_RXERR GBE_MDIO
AJ24 AD1 1 2
SATA_TX3N GBE_RXERR R891 10K_0402_5%
AB7
GBE LAN
GBE_TXCLK
AN24 AF9
SATA_RX3N GBE_TXD3 Change to PD 20101112
AL24 SATA_RX3P GBE_TXD2 AG6
GBE_TXD1 AE8
AL26 AD8 GBE_PHY_INTR 1 2
SATA_TX4P GBE_TXD0 R892 10K_0402_5%
AN26 SATA_TX4N GBE_TXCTL/TXEN AB9
AC2 GBE_COL 1 2
SERIAL ATA
GBE_PHY_PD R893 10K_0402_5%
AJ26 SATA_RX4N GBE_PHY_RST# AA7
AH26 W9 GBE_PHY_INTR GBE_CRS 1 2
SATA_RX4P GBE_PHY_INTR R894 10K_0402_5%
AN29 GBE_RXERR 1 2
SATA_TX5P FCH_SPI_MISO R895 10K_0402_5%
AL28 SATA_TX5N SPI_DI/GPIO164 V6
V5 FCH_SPI_MOSI
SPI_DO/GPIO163
SPI ROM
AK27 V3 FCH_SPI_CLK_R R35 1 2 0_0402_5% FCH_SPI_CLK
SATA_RX5N SPI_CLK/GPIO162 FCH_SPI_CS1#
AM27 SATA_RX5P SPI_CS1#/GPIO165 T6 Add SYS BIOS ROM
V1 FCH_SPI_WP#
ROM_RST#/SPI_WP#/GPIO161 20101111
AL29 NC6
AN31 NC7
VGA_RED L30 FCH_CRT_R <24>
AL31 R896 1 2 150_0402_1%
NC8
AL33 NC9
VGA_GREEN L32 FCH_CRT_G <24>
AH33 R897 1 2 150_0402_1%
2 NC10 2
AH31 NC11
VGA_BLUE M29 FCH_CRT_B <24>
AJ33 R898 1 2 150_0402_1%
VGA DAC
NC12
AJ31 NC13
VGA_HSYNC/GPO68 M28 FCH_CRT_HSYNC <24>
VGA_VSYNC/GPO69 N30 FCH_CRT_VSYNC <24>
M33 FCH_CRT_DDC_SDA <24>
1K_0402_1% 2 SATA_CALRP VGA_DDC_SDA/GPO70
1 R899 AF28 N32 FCH_CRT_DDC_SCL <24>
SATA_CALRP VGA_DDC_SCL/GPO71
1K_0402_1% 2 1 R900 SATA_CALRN AF27
+AVDD_SATA SATA_CALRN
K31 R901 1 2 715_0402_1%
VGA_DAC_RSET
SATA_LED# AD22
<37> SATA_LED# SATA_ACT#/GPIO67
V28 ML_VGA_AUXP_C <8>
R902 1 AUX_VGA_CH_P
+3VS 2 10K_0402_5% V29 ML_VGA_AUXN_C <8>
AUX_VGA_CH_N
AF21
VGA MAINLINK
SATA_X1
U28 AUXCAL 1 2 +VDDAN_11_ML
AUXCAL R903 100_0402_1%
T31 ML_VGA_TXP0 <8>
ML_VGA_L0P
T33 ML_VGA_TXN0 <8>
ML_VGA_L0N
AG21 T29 ML_VGA_TXP1 <8>
SATA_X2 ML_VGA_L1P
T28 ML_VGA_TXN1 <8>
ML_VGA_L1N
R32 ML_VGA_TXP2 <8>
ML_VGA_L2P
R30 ML_VGA_TXN2 <8>
ML_VGA_L2N
P29 ML_VGA_TXP3 <8>
ML_VGA_L3P
P28 ML_VGA_TXN3 <8>
ML_VGA_L3N +FCH_VDDAN_33_DAC_R
C29 FCH_CRT_HPD FCH_CRT_HPD 2 1

ML_VGA_HPD/GPIO229 FCH_CRT_HPD <10>
10K_0402_5% R904
3 Remove MINI2 T29 3
AH16 N2 1 2
ODD_PWR FANOUT0/GPIO52 VIN0/GPIO175 R5 10K_0402_5%
<30> ODD_PWR AM15
BT_ON# FANOUT1/GPIO53 HW MONITOR
<35> BT_ON# AJ16 M3 1 2
FANOUT2/GPIO54 VIN1/GPIO176 R6 10K_0402_5%
W_DISABLE#_2 AK15 L2 1 2
<33> W_DISABLE#_2 WL_OFF# FANIN0/GPIO56 VIN2/SDATI_1/GPIO177
AN16 R7 10K_0402_5%
<33> WL_OFF# FANIN1/GPIO57
WWAN_OFF# AL16 N4 1 2
<35> WWAN_OFF# FANIN2/GPIO58 VIN3/SDATO_1/GPIO178 R8 10K_0402_5%
P1 1 2
VIN4/SLOAD_1/GPIO179 R9 10K_0402_5%
1 2 K6
TEMPIN0/GPIO171
R13 10K_0402_5% P3 1 2
VIN5/SCLK_1/GPIO180 R10 10K_0402_5%
1 2 K5 M1 1 2
R14 10K_0402_5% TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181 R11 @ 10K_0402_5%
M5 1 2
VIN7/GBE_LED3/GPIO182 R12 10K_0402_5%
1 2 K3
R15 10K_0402_5% TEMPIN2/GPIO173
AG16
NC1
1 2 M6 AH10
R16 10K_0402_5% TEMPIN3/TALERT#/GPIO174 NC2
A28
NC3
G27
NC4
L4
NC5
HUDSON-M2_FCBGA656
@
4 4

Hudson-M2/M3-SATA/GBE/HWM
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
STRAP PINS
PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 RTC_CLK
1 1
PULL ALLOW USE NON_FUSION EC CLKGEN LPC ROM S5 PLUS If support ML DAC power down when no VGA plug
HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED MODE
STRAPS DISABLED
DEFAULT DEFAULT DEFAULT
L47 30mil
1 2
PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS FBMA-L11-201209-221LMA30T_0805
LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE 220 ohm
STRAP MODE ENABLED +3VS +FCH_VDDAN_33_DAC +FCH_VDDAN_33_DAC_R
DEFAULT DEFAULT DEFAULT DEFAULT
@ L48
@ Q39 3
@Q39 1 1 2
2.2U_0603_6.3V4Z
AP2301GN-HF_SOT23-3 FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z
C1209
C1210
220 ohm
1 1
2
+3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW
2 2
R905
R906 10K_0402_5%
R907 10K_0402_5%
R908 10K_0402_5%
R909 10K_0402_5%
R910 10K_0402_5%
R911 10K_0402_5%
VGA_PD# AO3413 Vgs(max)=1V
1
1
1 2
10K_0402_5%
@ @ @ @ R912 0_0402_5%
+1.1VS +FCH_VDDAN_11_MLDAC
2
2
30mil
@ Q40 3 1 1 @ 2
<25> PCI_CLK1
AP2301GN-HF_SOT23-3 R913 0_0402_5%
2 <25> PCI_CLK3 2
<25> PCI_CLK4
2
<25,36> LPC_CLK0_EC VGA_PD#
+3VS
<25> LPC_CLK1
<26> EC_PWM2
<25,36> RTC_CLK
1
100K_0402_5%
R916
100K_0402_5%
R914
1
R915 10K_0402_5%
R917 10K_0402_5%
R918 10K_0402_5%
R919 10K_0402_5%
R920 10K_0402_5%
R921 2.2K_0402_5%
R922 2.2K_0402_5%
1
2
@ @ @
2
VGA_PD#
2
6
1K_0402_5%
R923
0_0402_5%
Q41A
VGA_PD: Support MLDAC power
R924
save if not connect
@ @
0: MLDAC power on 2
1: MLDAC power off
3
Q41B
1U_0402_6.3V4Z
1
1
C1211
@
Check VGA_PD states
DEBUG STRAPS <26> VGA_PD
1
5
2
4
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23] R925 C1212
2.2K_0402_5%
2
3 1U_0402_6.3V4Z 3
1
PCI_AD26 PCI_AD27 PCI_AD25 PCI_AD24 PCI_AD23
USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI

PULL PLL ILA PLL PCIE STRAPS MEM BOOT
HIGH AUTORUN
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI

LOW PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT
AUTORUN
<25> PCI_AD27
<25> PCI_AD26
<25> PCI_AD25
<25> PCI_AD24
<25> PCI_AD23
R926 2.2K_0402_5%
R927 2.2K_0402_5%
R928 2.2K_0402_5%
R929 2.2K_0402_5%
R930 2.2K_0402_5%
4 4
1
@ @ @ @ @
2

Hudson-M2/M3-STRAP
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E
C1218 / C1219 / C1247 Change to SE00000I10

20101228 +VCC_FCH_R +1.1VS
U25C 1007mA
131mA 10mils 1 2
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
2.2U_0603_6.3V4Z
22U_0805_6.3V6M
HUDSON-2 50mils R937 0_0805_5%
C1213
C1214
C1215
C1216
C1217
C1219
+3VS 1 2 +VDDIO_33_PCIGP AB17 T14
+3VS VDDIO_33_PCIGP_1 VDDCR_11_1
22U_0805_6.3V6M
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
R20 0_0603_5% AB18 T17 1 1 1 1 1 1
VDDIO_33_PCIGP_2 VDDCR_11_2
C1218
C1228
C1220
C1221
L3 AE9 T20 U25E
PCI/GPIO I/O
+VDDPL_3.3V VDDIO_33_PCIGP_3 VDDCR_11_3
1 2 1 1 1 1 AD10
U16
2.2U_0603_6.3V4Z
MBK1608221YZF_2P AG7 U18 HUDSON-2
.1U_0402_16V7K
VDDIO_33_PCIGP_5 VDDCR_11_5 2 2 2 2 2 2
C1222
C1229
CORE S0
220 ohm AC13
V14 A3
VSS VSS
T25
1 1
1 1 AB12 V17 A33 T27
2 2 2 2 VDDIO_33_PCIGP_7 VDDCR_11_7 VSS VSS
AB13 V20 B7 U6
VDDIO_33_PCIGP_8 VDDCR_11_8 VSS VSS
AB14 Y17 B13 U14
VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1VS_CKVDD +1.1VS VSS VSS
AB16 D9 U17
2 2 VDDIO_33_PCIGP_10 VSS VSS
47mA 10mils 20mils 340mA D13
VSS VSS
U20
+VDDPL_3.3V H24 H26 +1.1VS_CKVDD 1 2 E5 U21
VDDPL_33_SYS VDDAN_11_CLK_1 VSS VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
2.2U_0603_6.3V4Z
20mA 10mils J25 R25 0_0603_5% E12 U30
+FCH_VDDAN_33_DAC_R VDDAN_11_CLK_2 VSS VSS
C1223
C1224
C1225
C1226
C1230
2 +VDDPL_33_DAC
1 V22 K24 E16 U32
CLKGEN I/O
+FCH_VDDPL_33_MLDAC VDDPL_33_DAC VDDAN_11_CLK_3 VSS VSS
20mA R22 0_0402_5% 10mils VDDAN_11_CLK_4
L22 1 1 1 1 1 E29
VSS VSS
V11
1 2 +FCH_VDDPL_33_MLDAC 2 +VDDPL_33_ML
1 U22 M22 F7 V16
R19 0_0603_5% VDDPL_33_ML VDDAN_11_CLK_5 VSS VSS
200mA R23 0_0402_5% 10mils VDDAN_11_CLK_6
N21 F9
VSS VSS
V18
+3VS
2.2U_0603_6.3V4Z
+FCH_VDDAN_33_DAC_R T22 N22 F11 W4

.1U_0402_16V7K
VDDAN_33_DAC VDDAN_11_CLK_7 2 2 2 2 2 VSS VSS

C1227
C1231
@ L4 VDDPL_33_SSUSB_S 20mA 10mils P22 F13 W6

R936 2 M2@ 10_0402_5% +FCH_VDDPL_33_SSUSB_S VDDAN_11_CLK_8 VSS VSS
1 2 1 1 For Hudson3 USB3.0 only L18 F16 W25
MBK1608221YZF_2P VDDPL_33_SSUSB_S VSS VSS
For Hudson2, connect to GND 17mA 10mils F17 VSS VSS W28
220 ohm +FCH_VDDPL_33_USB_S +PCIE_VDDR_FCH +1.1VS
D7 VDDPL_33_USB_S 50mils F19 VSS VSS Y14
2 2
43mA 10mils VDDAN_11_PCIE_1 AB24 1088mA F23 VSS VSS Y16
+VDDPL_33_PCIE AH29 Y21 +PCIE_VDDR_FCH 1 2 F25 Y18
VDDPL_33_PCIE VDDAN_11_PCIE_2 VSS VSS
PCI EXPRESS
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
2.2U_0603_6.3V4Z
93mA 10mils AE25 R938 0_0805_5% F29 AA6
VDDAN_11_PCIE_3 VSS VSS
C1233
C1234
C1235
C1236
C1237
LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA AG28 VDDPL_33_SATA VDDAN_11_PCIE_4 AD24 G6 VSS VSS AA12
supply for the RGB outputs VDDAN_11_PCIE_5 AB23 1 1 1 1 1 G16 VSS VSS AA13
For A11: Cap = 1nF @ AA22 G32 AA14
+3VALW VDDAN_11_PCIE_6 VSS VSS
For A12, Cap = DNI 1 2 M31 AF26 H12 AA16
M3@L6
M3@L6 +FCH_VDDAN_11_MLDAC C1232 2.2U_0603_6.3V4Z LDO_CAP VDDAN_11_PCIE_7 VSS VSS
VDDAN_11_PCIE_8 AG27 H15 VSS VSS AA17
2 +FCH_VDDPL_33_SSUSB_S L24 2 2 2 2 2
1 7mA 10mils H29 AA25
GROUND
VSS VSS
2.2U_0603_6.3V4Z
.1U_0402_16V7K
MBK1608221YZF_2P 1 2 1 2 +VDDPL_11_DAC V21 J6 AA28

VDDPL_11_DAC +1.1VS VSS VSS
C1238
C1239
MBK1608221YZF_2P R24 0_0402_5% 60mils J9 AA30

+VDDAN_11_ML VSS VSS
220 ohm 1 1 220 ohm/2A 226mA VDDAN_11_SATA_1 AA21 1337mA+AVDD_SATA J10 VSS VSS AA32
1 2 20mils Y20 +AVDD_SATA 1 2 J13 AB25
VDDAN_11_SATA_4 VSS VSS
.1U_0402_16V7K
.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
22U_0805_6.3V6M
M3@ M3@ R1148 0_0603_5% Y22 AB21 R941 0_0805_5% J28 AC6
VDDAN_11_ML_1 VDDAN_11_SATA_2 VSS VSS
MAIN LINK
C1240
4.7U_0603_6.3V6K
C1241
C1242
C1243
C1244
C1245
C1246
C1247
V23 AB22 J32 AC18
SERIAL ATA
2 2 VDDAN_11_ML_2 VDDAN_11_SATA_3 VSS VSS
1 1 1 V24 VDDAN_11_ML_3 VDDAN_11_SATA_5 AC22 1 1 1 1 1 K7 VSS VSS AC28
2 2
V25 VDDAN_11_ML_4 VDDAN_11_SATA_6 AC21 K16 VSS VSS AD27
VDDAN_11_SATA_7 AA20 K27 VSS VSS AE6
VDDAN_11_SATA_8 AA18 K28 VSS VSS AE15
+VDDAN_33_USB 2 2 2 2 2 2 2 2
VDDAN_11_SATA_9 AB20 L6 VSS VSS AE21
L7 AC19 L12 AE28
VDDAN_11_SATA_10 +3VALW VSS VSS
1 2 +FCH_VDDPL_33_USB_S AB10 VDDIO_33_GBE_S L13 VSS VSS AF8
2.2U_0603_6.3V4Z
.1U_0402_16V7K
MBK1608221YZF_2P 10mils 59mA L15 AF12

VSS VSS
C1248
C1249
220 ohm AB11 N18 +VDDIO_33_S 1 2 L16 AF16

VDDCR_11_GBE_S_1 VDDIO_33_S_1 VSS VSS
GBE LAN
.1U_0402_16V7K
.1U_0402_16V7K
2.2U_0603_6.3V4Z
1 1 AA11 L19 R26 0_0402_5% L21 AF33
VDDCR_11_GBE_S_2 VDDIO_33_S_2 VSS VSS
C1250
C1251
C1252
M18 M13 AG30
VDDIO_33_S_3 VSS VSS
3.3V_S5 I/O
1 2 AA9 V12 1 1 1 M16 AG32
R945 0_0402_5% VDDIO_GBE_S_1 VDDIO_33_S_4 VSS VSS
AA10 V13 M21 AH5
2 2 +3VALW VDDIO_GBE_S_2 VDDIO_33_S_5 VSS VSS
Y12 M25 AH11
L54 VDDIO_33_S_6 VSS VSS
658mA 30mils VDDIO_33_S_7
Y13
2 2 2
N6
VSS VSS
AH18
1 2 +VDDAN_33_USB G7 W11 N11 AH19
VDDAN_33_USB_S_1 VDDIO_33_S_8 VSS VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
.1U_0402_16V7K
FBMA-L11-201209-221LMA30T_0805 H8 N13 AH21
+3VS VDDAN_33_USB_S_2 +3VALW VSS VSS
C1253
C1254
C1255
C1256
C1257
220 ohm/2A J8
VDDAN_33_USB_S_3
N23
VSS VSS
AH23
L15 1 1 1 1 1 K8 10mils 5mA M3@ L28 N24 AH25
+VDDPL_33_PCIE VDDAN_33_USB_S_4 +VDDXL_3.3V VSS VSS
1 2 K9
VDDAN_33_USB_S_5 VDDXL_33_S
G24 1 2 P12
VSS VSS
AH27
2.2U_0603_6.3V4Z
.1U_0402_16V7K
.1U_0402_16V7K
2.2U_0603_6.3V4Z
MBK1608221YZF_2P M9 MBK1608221YZF_2P P18 AJ18
VDDAN_33_USB_S_6 +3VS VSS VSS
C1258
C1259
C1260
C1261
220 ohm 2 2 2 2 2
M10
VDDAN_33_USB_S_7
P20
VSS VSS
AJ28
1 1 N9 1 1 M2@ L30 P21 AJ29
VDDAN_33_USB_S_8 VSS VSS
N10 1 2 P31 AK21
VDDAN_33_USB_S_9 MBK1608221YZF_2P VSS VSS
M12 P33 AK25
2 2
N12
VDDAN_33_USB_S_11 2 2
220 ohm R4
VSS VSS
AL18
M11 R11 AM21
+1.1VALW VDDAN_33_USB_S_12 VSS VSS
R25 AM25
L57 +1.1VALW VSS VSS
140mA 10mils R28
VSS VSS
AN1
USB
1 2 +VDDAN_11_USB_S U12 10mils 187mA T11 AN18
2.2U_0603_6.3V4Z
.1U_0402_16V7K
MBK1608221YZF_2P U13 N20 +VDDCR_1.1V 1 2 T16 AN28

+3VS VDDAN_11_USB_S_2 VDDCR_11_S_1 VSS VSS
C1262
C1263
1U_0402_6.3V6K
1U_0402_6.3V6K
220 ohm M20 R1145 0_0603_5% T18 AN33
VDDCR_11_S_2 VSS VSS
C1264
C1265
L22 1 1
3 +VDDPL_33_SATA 3
1 2 1 1 SYSON <36,39,44> N8
VSSAN_HWM VSSPL_DAC
T21
2.2U_0603_6.3V4Z
.1U_0402_16V7K
MBK1608221YZF_2P L28
VSSAN_DAC
C1266
C1267
220 ohm @ Q13 K25 K33

VSSXL VSSANQ_DAC
2
2 2
G
1 1 BSH111 1N_SOT23-3 N28
2 2 VSSIO_DAC
H25
VSSPL_SYS
3 1 EFUSE
R6
+1.1VALW
D
2 2 L59 +1.1VALW
197mA 10mils
1 2 +VDDCR_1.1V_USB T12 10mils 70mA L29
VDDCR_11_USB_S_1
2.2U_0603_6.3V4Z
.1U_0402_16V7K
.1U_0402_16V7K
MBK1608221YZF_2P T13 J24 +VDDPL_1.1V 1 2 HUDSON-M2_FCBGA656

VDDCR_11_USB_S_2 VDDPL_11_SYS_S
C1268
C1269
C1270
2.2U_0603_6.3V4Z
220 ohm MBK1608221YZF_2P @
.1U_0402_16V7K
+1.1VS
C1271
C1272
1 1 1 Connected to VSS through a dedicated via.
1 1 @ L31
1 2
MBK1608221YZF_2P
2 2 2 Q13 change to SB00000FG10 AOS3416
2 2
220 ohm
20110322
+3VALW
+FCH_VDD_11_SSUSB_S 12mA
20mils 10mils +VDDAN_33_HWM
282mA P16
VDDAN_11_SSUSB_S_1 VDDAN_33_HWM_S
M8 1 2
2.2U_0603_6.3V4Z
M3@ 2 +VDDAN_SSUSB R27 0_0402_5% AMD reply:
.1U_0402_16V7K
1 M14
VDDAN_11_SSUSB_S_2
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
C1472
C1473
R1149 0_0603_5% N14 VDDAN_33_HWM_S: Please connect
VDDAN_11_SSUSB_S_3
C1273
C1274
C1275
For FCH M2 - BOM option 40mils P13 1 1 it to +3.3V_S5 directly if HWM is not used.
+FCH_VDD_11_SSUSB_S
VDDAN_11_SSUSB_S_4
VDDAN_11_SSUSB_S / VDDAN_11_SSUSB_S 1 1 1 P14
VDDAN_11_SSUSB_S_5
Connected to VSS.
USB SS
M3@ M3@ M3@ 2 2

2 2 2 30mils
N16
1
M2@ M2@ VDDCR_11_SSUSB_S_1 +3VS

N17
C1275 C1281 VDDCR_11_SSUSB_S_2
P17
VDDCR_11_SSUSB_S_3 10mils 26mA
0_0402_5% 0_0402_5% M17 AA4 +VDDIO_AZ 1 2
4 VDDCR_11_SSUSB_S_4 VDDIO_AZ_S R28 0_0402_5% VDDIO_AZ_S should be tied to 4
2
POWER 1 2 +3.3/1.5V_S5 rail if Wake on Ring

424mA C1276 2.2U_0603_6.3V4Z is supported
+1.1VALW 2 L61 M3@ 1 1 M3@ 2 +VDDCR_11_SSUSB HUDSON-M2_FCBGA656 1 2
10U_0603_6.3V6M
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
R1150 0_0603_5% @ C1277 .1U_0402_16V7K

C1278
C1279
C1280
C1281
FBMA-L11-201209-221LMA30T_0805
42 ohm/4A 1 1 1 1
M3@ M3@ M3@ M3@ Issued Date 2010/08/04 2010/08/04 Title
2 2 2 2 Deciphered Date
Hudson-M2/M3-POWER/GND
Custom 1.0
P5WS5 LA-6973P
A B C D E
A B C D E F G H
SATA HDD1 Conn. Fllow P5WE0 SATA ODD Conn. Fllow P5WE0
JHDD1
1 JODD1
C1283 1 SATA_STX_C_DRX_P0 GND
<27> SATA_STX_DRX_P0 2 0.01U_0402_16V7K 2 RX+
C1285 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_N0 3 1
<27> SATA_STX_DRX_N0 RX- SATA_STX_C_DRX_P1 GND
4 <27> SATA_STX_DRX_P1 C1301 1 2 0.01U_0402_16V7K 2
C1287 1 SATA_DTX_SRX_N0 GND SATA_STX_C_DRX_N1 A+
<27> SATA_DTX_C_SRX_N0 2 0.01U_0402_16V7K 5 <27> SATA_STX_DRX_N1 C1300 1 2 0.01U_0402_16V7K 3
C1289 1 SATA_DTX_SRX_P0 TX- A-
<27> SATA_DTX_C_SRX_P0 2 0.01U_0402_16V7K 6
TX+
4
GND
7 C1302 1 2 0.01U_0402_16V7K SATA_DTX_SRX_N1 5
GND <27> SATA_DTX_C_SRX_N1 B-
C1303 1 2 0.01U_0402_16V7K SATA_DTX_SRX_P1 6
1 <27> SATA_DTX_C_SRX_P1 B+ 1
7
+3VS GND
+3VS 8
3.3V
9
3.3V R79
1 10 <26> ODD_PLUG# 1 2 0_0402_5% 8
C1290 3.3V ZERO@ DP
11
GND +5VS_ODD
100mils 9
+5V
12 10 17
0.1U_0402_16V4Z GND R80 +5V GND
13 <26> ODD_DA# 1 2 0_0402_5% 11 16
2 GND ZERO@ MD GND
14 12 15
5V GND GND
+5VS_HDD1
80mils 15
5V
13
GND GND
14
2 @ 1 16
+5VS 5V
R953 0_0805_5% 17 10U_0805_10V4Z 0.1U_0402_16V4Z
GND CONN@
18 Rsv
10U_0805_10V4Z 0.1U_0402_16V4Z 19 1 1 1 OCTEK_SLS-13SB1G_RV
GND
1
20 C1304 C1305 C1306 C1307
12V
1 1 1 21 12V
1
C1292 C1293 C1294 C1295 22
2
12V 2 2 2
23 GND
24
2
2 2 2 GND 1U_0603_10V6K 1000P_0402_50V7K
CONN@
1U_0603_10V6K 1000P_0402_50V7K OCTEK_SAT-22DD1G
+5VS +5VS_ODD +5VS_ODD

100mils 100mils
2
2 @ 1
R793 0_0805_5% ZERO@
+5VS +VSB R1129
D
1U_0603_10V6K
6 470_0603_5%
S
Change to +5VS 5 4
1
1
1
470K_0402_5%
C812
ZERO@
2 2
20110208 2
ZERO@ ZERO@ 1 ZERO@
1
R21 R789 Q86 D
G
2
10K_0402_5% SI3456BDV-T1-E3 1N TSOP6 2 ODD_EN#
3
G
1
S ZERO@
3
ODD_EN# ODD_EN Q75
2N7002_SOT23
2
1.5M_0402_5%
1 ZERO@
C811
R785
ZERO@
ZERO@ 0.1U_0603_25V7K
2 Q91A 5 ZERO@
<27> ODD_PWR 2
Q91B
1
4
FAN Screw Hole Follow P5WE0
FAN Stand-Off JUSB3 Stand-Off
H1 H2 H3 H4 H5 H6 H7
H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4
@ @ @ @ @ @ @
1
+5VS
3 C1404 10U_0805_10V4Z 3
1 2
H8 H9 H10 H11 H13 H14 H15 H16 H17 H18

H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
U35
1 8
EN GND @ @ @ @ @ @ @ @ @ @
2 7
1
1
+VCC_FAN1 VIN GND
3 6
VOUT GND
<36> EN_DFAN1 1 2 4 5
R1065 0_0402_5% 1 VSET GND
@ APL5607KI-TRG_SO8 H19 H20 H21 H22 H23 H24
C1405 H_4P0 H_4P0 H_4P2 H_4P2 H_4P2 H_4P2
0.1U_0402_16V4Z
2
@ @ @ @ @ @
1
1
C1406
10U_0805_10V4Z For Layout request H26 H27
1 2 Delete H25 H_3P0N H_3P5X3P0N
20110419
+3VS C1407
1000P_0402_50V7K @ @
1
1 2
1
R1066 FD1 FD3 FD2 FD4

10K_0402_5%
40mil
JFAN1 @ @ @ @
2
+VCC_FAN1 1 1 1
4 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 4
<36> FAN_SPEED1 2 2
3 3
1
C1408 4
1000P_0402_50V7K GND
5 GND
2 CONN@
ACES_85205-03001
HDD/ODD/FAN/SCREW
B 1.0
P5WS5 LA-6973P
A B C D E F G H
5 4 3 2 1
+1.2V_LAN +3V_LAN +3VALW +3V_LAN

60mil @PJ36
@ PJ36 JUMP_43X39
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z U48 1 1 2 L79
+3V_LAN +LAN_BIASVDDH 2 +LAN_XTALVDDH
BIASVDDH 37 20mil 1 2
4.7U_0603_6.3V6K
1 1 1 1 1 1 1 20 1 BLM18AG601SN1D_2P
VDDO_CR
C1493
C1500 C1494 C1501 C1502 C1503 C1495 1 1

+1.2V_LAN 35 17 +LAN_XTALVDDH C1504 C1505 C1506
VDDC XTALVDDH 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
61 VDDC
2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 48 +LAN_AVDDH 2 2
AVDDH L80
AVDDH 42
+3V_LAN +LAN_BIASVDDH
20mil 1 2
7 1 BLM18AG601SN1D_2P
+3V_LAN VDDO
56
D VDDO C1507 D
62
0.1U_0402_16V4Z VDDO LAN_MIDI3- 0.1U_0402_16V4Z
49 LAN_MIDI3- <32>
TRD3_N LAN_MIDI3+ 2
50 LAN_MIDI3+ <32>
TRD3_P
4.7U_0603_6.3V6K
1 1 1 1
C1496
C1497 C1498 C1499 47 LAN_MIDI2- L81

TRD2_N LAN_MIDI2- <32>
46 LAN_MIDI2+ 20mil +LAN_AVDDH 1 2
TRD2_P LAN_MIDI2+ <32>
2 2 2 2 +LAN_AVDDL 39 43 LAN_MIDI1- C1509 C1510
AVDDL TRD1_N LAN_MIDI1+ LAN_MIDI1- <32>
45 44 LAN_MIDI1+ <32>
0.1U_0402_16V4Z 0.1U_0402_16V4Z AVDDL TRD1_P 0.1U_0402_16V4Z 0.1U_0402_16V4Z
51
AVDDL LAN_MIDI0- 2 2
41 LAN_MIDI0- <32>
+LAN_GPHYPLLVDDL TRD0_N LAN_MIDI0+
36 GPHY_PLLVDDL TRD0_P 40 LAN_MIDI0+ <32>
+LAN_PCIEPLLVDD 32 PCIE_PLLVDDL
29 SPROM_CLK (EECLK) SPROM_DOUT (EEDATA)
PCIE_PLLVDDL On chip 1 0
SO_LINKLED# 65
LAN_LINK# <32> AT24C02 1 1
SCLK_SPD1000LED# 66
2 +3V_LAN
SPD100LED#_SERIALDO
SPROM_CLK 2 1
<6> PCIE_DTX_C_FRX_P0
.1U_0402_16V7K 1 2 C1508 PCIE_DTX_FRX_P0 28 PCIE_TXD_P TRAFFICLED#_SERIALDI 67 @ R1178 1 2 0_0402_5% R1210 4.7K_0402_5%
LAN_ACTIVITY# <32>
<6> PCIE_DTX_C_FRX_N0
.1U_0402_16V7K 1 2 C1511 PCIE_DTX_FRX_N0 27 PCIE_TXD_N
SPROM_DOUT 2 1
33 R1211 4.7K_0402_5%
<6> PCIE_FTX_C_DRX_P0 PCIE_RXD_P +VDDO_CR
<6> PCIE_FTX_C_DRX_N0 34 PCIE_RXD_N GPIO1_LR_OUT 8
5 5IN1_LED#_R @ R1180 1 2 0_0402_5% 5IN1_LED#

<36> EC_PME# R1181 1 2 0_0402_5%
GPIO_0 5IN1_LED# <37> R232 (+VDDO_CR) Change to 0_0603
R1182 1 SPROM_DOUT
For B0 version 20101228
+3V_LAN 2 4.7K_0402_5% 64
C SI_EEDATA SPROM_CLK +VDDO_CR +XDPWR_SDPWR_MSPWR C
CS#_EECLK 63
R1183 1 @ 2 0_0402_5% LAN_PME# 3
<26,33> FCH_PCIE_WAKE# WAKE# @ Add for HW 20110416 @ R1185
R1184 1 @ 2 0_0402_5% 11 CR_XD_CE#_MS_INS#_R C1465 1 2 100P_0402_50V8J 1 2
<13,25,33> APU_PCIE_RST# PREST#
<25> CLK_PCIE_LAN 31 PCIE_REFCLK_P 1 1 1
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
C1512
C1513
0.1U_0402_16V4Z
30 C1514 0_0603_5%
<25> CLK_PCIE_LAN# PCIE_REFCLK_N CR_XD_WE#_SD_DETECT_R CR_XD_WE#_SD_DETECT
1 R1186 2 1 0_0402_5%
SD_DETECT/XD_WE# CR_XD_WE#_SD_DETECT <32>
CR_XD_DETECT#_R R1187 CR_XD_DETECT# 2 2 2
68 2 1 0_0402_5%
CR_DATA0 R1188 1 47_0402_5% CR_DATA0_R SR_DISABLE/XD_DETECT# CR_XD_DETECT# <32>
2 25
<32> CR_DATA0 CR_DATA1 CR_DATA1_R CR_DATA0 CR_XD_CE#_MS_INS#_R
R1189 1 2 47_0402_5% 24 59 R1190 1 2 47_0402_5% CR_XD_CE#_MS_INS#
<32> CR_DATA1 CR_DATA2 R1191 1 47_0402_5% CR_DATA2_R CR_DATA1 MS_INS#/XD_CE# CR_XD_CE#_MS_INS# <32>
2 23
<32> CR_DATA2 CR_DATA3 R1192 1 47_0402_5% CR_DATA3_R CR_DATA2 CR_XD_RE#_R R1193 CR_XD_RE#
2 22
CR_DATA3 GPIO2_MEDIA_SENSE/XD_RE#
9 2 1 0_0402_5%
<32> CR_DATA3 CR_DATA4 R1194 1 47_0402_5% CR_DATA4_R CR_XD_RE# <32>
2 52
<32> CR_DATA4 CR_DATA5 R1195 1 47_0402_5% CR_DATA5_R CR_DATA4 CR_WP#_XD_WP#_R R1196 CR_WP#_XD_WP#
2 53
CR_DATA5 CR_WP#/XD_WP#
57 2 1 0_0402_5%
<32> CR_DATA5 CR_DATA6 R1197 1 47_0402_5% CR_DATA6_R CR_WP#_XD_WP# <32>
2 54
<32> CR_DATA6 CR_DATA7 R1198 1 47_0402_5% CR_DATA7_R CR_DATA6 CR_PWR_XD_ALE_R R1199 @ CR_PWR_XD_ALE
2 55 60 2 1 0_0402_5%
<32> CR_DATA7 CR_DATA7 CR_LED_CR_BUS_PWR/XD_ALE CR_PWR_XD_ALE <32>
R04 modify 21 CR_CLK_XD_RY_BY#_R R1200 1 2 47_0402_5% CR_CLK_XD_RY_BY#
+3VS CR_CLK/XD_RY_BY# CR_CLK_XD_RY_BY# <32>
26 CR_CMD_XD_CLE_R R1201 1 2 47_0402_5% CR_CMD_XD_CLE
CR_CMD_XD_CLE CR_CMD_XD_CLE <32> R1203 C1515
1 2 58
VMAIN_PRSNT
+3V_LAN R1202 1K_0402_5% R1190 / R1200 change to 47 ohm for Vender req. 1 2 2 1
201111291530
1 2 6 22_0402_5% 22P_0402_50V8J
TEST1
R1204 4.7K_0402_5%
L82 For EMI request
1 2 10
TEST2 40mil +1.2V_LAN_OUT 1
40mil
R1205 4.7K_0402_5% 16 2 +1.2V_LAN
SR_LX 4.7UH_PG031B-4R7MS_1.1A_20%
CR_PWR_XD_ALE 2 1 4 13 1 1
R1206 0_0402_5% LOW_PWR SR_VFB C1516 C1517 EMI Request...2010/07/27
10U_0603_6.3V6M
B LAN_XTALO_R 0.1U_0402_16V4Z B
19
XTALO 2 2
SM010005500
LAN_XTALI 18
XTALI 500ma 600ohm@100mhz DCR 0.38
+3V_LAN 20mil L83
40mil +LAN_PCIEPLLVDD
GND PLANE
15 +3V_LAN 1 2 +1.2V_LAN
@ LAN_CLKREQ# SR_VDDP BLM18AG601SN1D_2P
1 2 15mil SR_VDD
14
R17 10K_0402_5% 1 2 LAN_RDAC 38 1 1 1 1
R1208 1.24K_0402_1% RDAC C1518 C1519 C1520 C1521
Add PU 20101111 <26> LAN_CLKREQ# 12
CLK_REQ# 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
BCM57785XA0KMLG_QFN68_8X8 2 2 2 2
69
Close to P14 20mil

L84
+LAN_GPHYPLLVDDL 1 2 +1.2V_LAN
BLM18AG601SN1D_2P
1 1
C1524 C1525
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
LAN_XTALI
20mil
L85
+LAN_AVDDL 1 2 +1.2V_LAN
LAN_XTALO_R BLM18AG601SN1D_2P
1 1
1
C1527 C1528
R1207
200_0402_1% 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
A 2 2 A
2
Y5
1 2LAN_XTALO
25MHZ_20PF_7A25000012
C1522 C1523
33P_0402_50V8J 33P_0402_50V8J
C1522 / C1523 change to 33P for TXC test result
20110208 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Broadcom BCM57785
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
5 4 3 2 1
Timag only (Height)

T30
<31> LAN_MIDI0+ LAN_MIDI0+ 1 16 RJ45_MIDI0+

LAN_MIDI0- TD+ TX+ RJ45_MIDI0-
D <31> LAN_MIDI0- 2 TD- TX- 15 D
3 CT CT 14
4 NC NC 13
5 NC NC 12
6 CT CT 11
LAN_MIDI1- RD+ RX+ RJ45_MIDI1-
<31> LAN_MIDI1- 8 RD- RX- 9
TAIMAG_HD-024A
T31

TD+ TX+
LAN_MIDI2- 2 15 RJ45_MIDI2- R03 modify
<31> LAN_MIDI2-
3
TD-
CT
TX-
CT 14 LAN Connector
4
5
NC NC 13
12
C474,C475 and D14
NC NC
LAN_MIDI3+
6 CT CT 11
RJ45_MIDI3+
ME interefer,do not pop!!
<31> LAN_MIDI3+ 7 RD+ RX+ 10 +3V_LAN 2 1
<31> LAN_MIDI3- LAN_MIDI3- 8 9 RJ45_MIDI3- R1215 1K_0402_5% 1
RD- RX-
220P_0402_50V7K
TAIMAG_HD-024A C1533
1
2 C1534 68P_0402_50V8J
1 1 1 1 @ JRJ45
C1 C2 C3 C4 R1 R3 2 1 9
75_0402_1% 75_0402_1% Green LED+
0.1U_0402_16V4Z 0.1U_0402_16V4Z LAN_LINK# 10
2
<31> LAN_LINK# Green LED-
1
C 2 2 2 2 C
RJ45_MIDI0+ 1 14
0.1U_0402_16V4Z 0.1U_0402_16V4Z R2 R4 PR1+ SHLD1
SHLD2 13
75_0402_1% 75_0402_1% RJ45_MIDI0- 2 PR1-
2
Place close to TCT pin RJ45_MIDI1+ 3
RJ45_GND PR2+
RJ45_MIDI2+ 4 PR3+
40mil RJ45_MIDI2- 5 PR3-
RJ45_MIDI1- 6 PR2-
RJ45_MIDI3+ 7
Card Reader Connector RJ45_MIDI3- 8

PR4+
PR4-
+3V_LAN 2 1 11 Yellow LED+

R1218 1K_0402_5% 1
JREAD1 LAN_ACTIVITY# 12
220P_0402_50V7K <31> LAN_ACTIVITY# Yellow LED-
11 31 CR_DATA0 C1535 68P_0402_50V8J CONN@
+XDPW R_SDPW R_MSPW R SD_VCC XD_D0 CR_DATA0 <31> 2
18 32 CR_DATA1 2 1 SANTA_130451-K
MS_VCC XD_D1 CR_DATA2 CR_DATA1 <31> @
39 XD_VCC XD_D2 33
34 CR_DATA3 CR_DATA2 <31> C1536
XD_D3 CR_DATA4 CR_DATA3 <31>
XD_D4 35
CR_CLK_XD_RY_BY# 8 36 CR_DATA5 CR_DATA4 <31>
CR_CMD_XD_CLE SD_CLK XD_D5 CR_DATA6 CR_DATA5 <31>
CR_XD_W E#_SD_DETECT
16 SD_CMD XD_D6 37
CR_DATA7 CR_DATA6 <31> 40mil
1 SD_CD XD_D7 38
B CR_W P#_XD_W P# CR_DATA7 <31> B
2 SD_WP
CR_DATA0 4 22 CR_XD_DETECT#
CR_DATA1 SD/MMC_DAT0 XD_CD CR_CLK_XD_RY_BY# CR_XD_DETECT# <31>
3 SD/MMC_DAT1 XD_R/B 23
CR_DATA2 21 24 CR_XD_RE# CR_CLK_XD_RY_BY# <31> C1537
CR_DATA3 SD/MMC_DAT2 XD_RE CR_XD_CE#_MS_INS# CR_XD_RE# <31> RJ45_GND LANGND
19 SD/MMC_DAT3 XD_CE 25 1 2
26 CR_CMD_XD_CLE CR_XD_CE#_MS_INS# <31>
XD_CLE CR_CMD_XD_CLE <31>
100UH_SSC0301101MCF_0.18A_20%
B88069X9231T203_4P5X3P2-2
27 CR_PW R_XD_ALE 1000P_1206_2KV7K
XD_ALE
3
28 CR_XD_W E#_SD_DETECT CR_PW R_XD_ALE <31>
XD_WE CR_W P#_XD_W P# CR_XD_W E#_SD_DETECT <31>
XD_WP-IN 29 2 1
CR_W P#_XD_W P# <31>
10U_0603_6.3V6M
0.1U_0402_16V4Z
2
1
6 @ JP4 @ 1 @
CR_DATA0_MS SD_GND B88069X9231T203_4P5X3P2-2
10 MS_DATA0 SD_GND 13 1
C43
L86
JP5
C24
CR_DATA1_MS 9 5
CR_DATA2_MS MS_DATA1 MS_GND
12 MS_DATA2 MS_GND 20 2 1
CR_DATA3_MS 2
15 MS_DATA3 XD_GND 30
CR_CLK_XD_RY_BY#_MS @ JP3 2 @
17 40
1
CR_XD_CE#_MS_INS# MS_SCLK XD_GND B88069X9231T203_4P5X3P2-2 D42
14 MS_INS GND 41
CR_CMD_XD_CLE_MS 7 42 PJDLC05C_SOT23-3
MS_BS GND
TAITW _R013-P17-HM_NR
CONN@ For EMI request
+3VS 20110210 +5VS EMI Request
For Vender req. 201011291530
2 1
CR_DATA0 2 1 CR_DATA0_MS C33 680P_0402_50V7K
R37 0_0402_5% 2 1
R38 0_0402_5% +3VS
A
CR_DATA2 2 1 CR_DATA2_MS A
R39 0_0402_5% 2 1
R40 0_0402_5%
CR_CLK_XD_RY_BY# 2 1 CR_CLK_XD_RY_BY#_MS
R41 0_0402_5%
CR_CMD_XD_CLE CR_CMD_XD_CLE_MS
R42
2 1
0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
LAN Magnetic & RJ45
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
A B C D E
Mini-Express Card for WLAN Follow P5WE0

Mini Card Power Rating
Power Primary Power (mA) Auxiliary Power (mA)
Peak Normal Normal
+3VS 1000 750
1 1
+3V 330 250 250 (wake enable)
+1.5VS 500 375 5 (Not wake enable)
TOP View - Right
JMINI1 +1.5VS
FCH_PCIE_WAKE# R984 1 @ 2 0_0402_5% 1 2 +3VS
<26,31> FCH_PCIE_WAKE# 1 2
3 3 4 4
5 5 6 6 +1.5VS 1 1 1
<26> MINI1_CLKREQ# 7 8 C1342 C1343 C1344
7 8
9 9 10 10
11 12 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<25> CLK_PCIE_MINI1# 11 12 2 2 2
<25> CLK_PCIE_MINI1 13 13 14 14
15 15 16 16
17 17 18 18
19 19 20 20 @ R985 1 2 0_0402_5% WL_OFF# WL_OFF# <27>
21 22 APU_PCIE_RST#
21 22 +3VS_MINI1 APU_PCIE_RST# <13,25,31>
<6> PCIE_DTX_C_FRX_N1 23 23 24 24 1 2 +3VS
25 26 R986 1 2 0_0603_5% +3VS
<6> PCIE_DTX_C_FRX_P1 25 26 +3VALW
27 28 R987 @ 0_0603_5%
27 28 MINI1_SMBCLK @ R988 1 FCH_SCLK0
29 29 30 30 2 0_0402_5% FCH_SCLK0 <11,12,26>
<6> PCIE_FTX_C_DRX_N1 31 32 MINI1_SMBDAT @ R989 1 2 0_0402_5% FCH_SDATA0 1 1 1
31 32 FCH_SDATA0 <11,12,26>
<6> PCIE_FTX_C_DRX_P1 33 34 C1339 C1340 C1341
33 34 USB20_N8
35 35 36 36 USB20_N8 <26>
37 38 USB20_P8 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z
37 38 USB20_P8 <26> 2 2 2
+3VS 39 39 40 40
R993 41 42 WIMAX_LED1# R992 2 1 0_0402_5%
100K_0402_5% 41 42 MINI1_LED#_R
43 44 2 1 0_0402_5% MINI1_LED# <36>
2 43 44 R50 2
2 1 45 45 46 46
47 48 2 1 +3VS For BCM WLAN lost issue:
R995 1 @ E51TXD_P80DATA_R 47 48
<36> E51TXD_P80DATA 2 0_0402_5% 49 50 R994 100K_0402_5% Change C1339 from 4.7uF to 10uF
R996 1 @ E51RXD_P80CLK_R 49 50
<36> E51RXD_P80CLK 2 0_0402_5% 51 51 52 52 (9~16mA) Change C1340,C1341 from 0.1uF to 1uF
20110419
<27> W_DISABLE#_2 1 2 53 GNDGND 54
R997 @ 1K_0402_5%
CONN@
ACES_51711-0520W-001
Remove MINI2
3 3
4 4

MINI1 CARD (WLAN) / MINI2 CARD (Option)
B 1.0
P5WS5 LA-6973P
A B C D E
5 4 3 2 1
30 Pin USB30/B Conn JUSB3

Change to Zif Conn. (SP010015Z00) CONN@
1 R1224 1 @ 2 0_0402_5% For ESD request
20101229 2
1
2 USB30_MTX_C_DRX_N0 U3TXDN0 @ D43
+5VALW 3 3 <26> USB30_MTX_C_DRX_N0 4 4 3 3
4 U3TXDP0 1 10 U3TXDP0
4 M3@ OCE2012120YZF, 0805-12ohm-RDC
5 5
6 USB30_MTX_C_DRX_P0 L88 1 U3TXDP0 U3TXDN0 U3TXDN0
2 2
<26> USB30_MTX_C_DRX_P0 2 9
6 1
7 7
8 R1225 1 @ 2 0_0402_5% U3RXDP0 4 7 U3RXDP0
8
9
SYSON# 9 R1226 @ 0_0402_5% U3RXDN0 U3RXDN0
10 1 2 5 6
10
11
D <26> USB_OC1# 11 USB30_MRX_DTX_N0 U3RXDN0 D
12 <26> USB30_MRX_DTX_N0 4 3 3
12 4 3
13
<26> USB30_MRX_DTX_N2 13 M3@ OCE2012120YZF, 0805-12ohm-RDC 8
14
<26> USB30_MRX_DTX_P2 14 USB30_MRX_DTX_P0 L89 1 U3RXDP0
15
15 <26> USB30_MRX_DTX_P0 1 2 2 RCLAMP0524P.TCT~D
<26> USB30_MTX_DRX_N2 16
16 R1228 @ 0_0402_5%
<26> USB30_MTX_DRX_P2 17 1 2
17
18
USB30_P12_R 18
19
USB30_N12_R 19 R971 @ 0_0402_5%
20 1 2
20 D4
21
USB30_P11_R 21 USB30_P10 USB30_P10_R USB30_P10_R USB30_N10_R
22 <26> USB30_P10 1 2 6 1
USB30_N11_R 22 1 2 I/O4 I/O1
23 23
24 L64 OCE2012120YZF, 0805-12ohm-RDC +USB3_VCCA 5 2
24 USB30_N10 USB30_N10_R REF2 REF1
25 25 <26> USB30_N10 4 4 3 3
<26> USB30_MRX_DTX_N1 26 4 3
<26> USB30_MRX_DTX_P1 26 R974 @ 0_0402_5% I/O3 I/O2
27 27 1 2
28 32 PJUSB208H_SOT23-6
<26> USB30_MTX_DRX_N1 28 GND2
<26> USB30_MTX_DRX_P1 29 29
30 30 GND1 31
+5VALW +USB3_VCCA +3VALW

ACES_87152-30051
W=60mils W=60mils
1
C22 U54 R965
10U_0805_10V4Z 1 8 100K_0402_5%
12 Pin USB20/B Conn
GND VOUT
1 2 2 VIN VOUT 7
USB30_N11 R29 1 @ 2 0_0402_5% USB30_N11_R 3 6
2
VIN VOUT
EPAD
USB30_P11 R31 1 @ 2 0_0402_5% USB30_P11_R
(Port 11 , 12) <39> SYSON# 4
EN FLG
5 1
R969
2
10K_0402_5%
USB_OC0# <26>
USB30_N12 R32 1 @ 2 0_0402_5% USB30_N12_R 1
C USB30_P12 R51 USB30_P12_R C
1 @ 2 0_0402_5% AP2301MPG-13_MSOP8 C1320
9
JUSB1 0.1U_0402_16V4Z
CONN@ Close to JUSB1 2
1 1
<26> USB30_N11 2 2
<26> USB30_P11 3 3
4 4
<26> USB30_N12 5
5
<26> USB30_P12 6
6 +USB3_VCCA
7
SYSON# 7
8
8
9
9 +USB3_VCCA
10
10 JUSB5
11 13 1
11 GND
470P_0402_50V7K
12 14 1 U3TXDP0 9
+5VALW 12 GND SSTX+
C1571
C1572 + 1
220U_6.3V_M U3TXDN0
<BOM Structure> VBUS
8
ACES_85201-1205N USB30_P10_R SSTX-
3
2 2 D+
7
USB30_N10_R GND
2 10
U3RXDP0 D- GND
6 11
SSRX+ GND
4 12
U3RXDN0 GND GND
5 13
C1572 change to SF000002Y00 SSRX- GND
20101228 ACON_TARA4-9K1311
CONN@
B B
A A

USB2.0 / USB3.0
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
A B C D E
For HD Camrea
JCAM1
USB30_MTX_C_DRX_P3 1
<26> USB30_MTX_C_DRX_P3 USB30_MTX_C_DRX_N3 1
<26> USB30_MTX_C_DRX_N3 2
2
3
USB30_MRX_DTX_P3 3
<26> USB30_MRX_DTX_P3 4
1 USB30_MRX_DTX_N3 4 1
<26> USB30_MRX_DTX_N3 5
5
6
6
7
7
+3VS 8
8
9
9
10
10
11
GND
12
GND
ACES_87036-1001-CP
CONN@
For 3G / GPS
J3G1
22 GND 20 20
+3VALW +3VS +3VALW
19 19 Peak: 2.75A
18 18
2
17 1 Normal: 1.1A 2
17
2
16 3G@
16 3G@ C562
15 15
14 R407 0.1U_0402_16V4Z
14 2
13 13 100K_0402_5%
12
1
12 WWAN_OFF#
11 11 WWAN_OFF# <27>
10 3G_LED#
10 3G_LED# <36>
9
9 USB20_N6
8 USB20_N6 <26>
8 USB20_P6
7 USB20_P6 <26>
7
6
6 USB20_N7
5 USB20_N7 <26>
5 USB20_P7
4 USB20_P7 <26>
4
3
3
2
2 3G_GATE
21 1
GND 1
ACES_87213-2000G
CONN@
20mil
3G@R796
3G@ R796
+VSB 2 1
47K_0402_5%
1
D
1 3G@
SUSP 2 3G@ C820
<39,45> SUSP
G Q82 0.1U_0603_25V7K
S
3
3 2N7002_SOT23 2 3
Bluetooth Conn. Follow P5WE0

+3VALW +3VS
+BT_VCC
1
C1326 C1327 JBT1
10 8
0.1U_0402_16V4Z 1U_0402_6.3V4Z GND 8
7
7
3
2 6
6 USBFS_P0 <26>
<27> BT_ON# 1 2 2 5 USBFS_N0 <26>
R982 10K_0402_5% AP2301GN-HF_SOT23-3 5
4
Q42 4
3
3
2
C1330 2
W=40mils 9 1
1
GND 1
+BT_VCC
4.7U_0603_6.3V6K
0.1U_0402_16V4Z ACES_87213-0800G
C1331
4 CONN@ 4
1
1
C1332
R983 <NAL00 use>
300_0603_5%
2 0.1U_0402_16V4Z
2

1
D
2 Q43 Issued Date 2010/08/04 2010/08/04 Title
G 2N7002_SOT23
Deciphered Date
S USB2.0/3.0 CONN/USB/B CONN/LAN CONN
3
B 1.0
P5WS5 LA-6973P
A B C D E
5 4 3 2 1
+3VALW Analog Board ID definition

+3VLP +3VALW
L65
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2+EC_VCCA 1 9012@ 2 +3VALW
2
1 1 C1346 1 1 2 2 BLM18AG601SN1D_2P R66 0_0402_5%
C1345 1 +EC_VCC_VL 1 930@ 2 R1024
1000P_0402_50V7K
C1350
C1347 C1348 C1349 R67 0_0402_5% Ra
+EC_VCC_VL
1000P_0402_50V7K C1351 100K_0402_5%
2 2 2 2 1 1
1
2
ECAGND
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AD_BID0
1
1
D R1026 C1356 D
Rb
111
125
8.2K_0402_5% 0.1U_0402_16V4Z
22
33
96
67
9
U31 2
2
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
EC_GA20 1 21 3G_LED# VGA_DBCLK
<26> EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F 3G_LED# <35> +3VALW
EC_KBRST# 2 23 BEEP#
<26> EC_KBRST#
SERIRQ KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <38> EC must program to 500KHZ output
Change to pop for EMI 3 26
<25> SERIRQ SERIRQ# FANPWM1/GPIO12 VGA_DBCLK <14> Start and stop follow SUP high/Low
20110313 LPC_FRAME# 4 27 ACOFF 65W /90W # 2 1
<25> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <40,41>
C1352 R1014 LPC_AD3 5 2 1 ECAGND R1010 100K_0402_5%
<25> LPC_AD3 LAD3
22P_0402_50V8J 22_0402_5% LPC_AD2 7 PWM Output C1354 0.01U_0402_16V7K VR_ON 2 1
<25> LPC_AD2 LAD2
2 1 2 1 LPC_AD1 8 63 BATT_TEMP R1012 100K_0402_5%
<25> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <43>
LPC_AD0 3S/4S#
<25> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I R1013
1 2
4.7K_0402_5%
ADP_I/AD2/GPIO3A 65 ADP_I <41>
LPC_CLK0_EC 12 AD Input 66 AD_BID0
<25,28> LPC_CLK0_EC PCICLK AD3/GPIO3B
PLT_RST# 13 75
<10,25> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
+3VALW 2 1 37 76 C1360 100P_0402_50V8J
R1011 47K_0402_5% EC_SCI# ECRST# SELIO2#/AD5/GPIO43 BATT_TEMP
<26> EC_SCI# 20 SCI#/GPIO0E 2 1
2 1 1 2 38 C1363 100P_0402_50V8J
C1353 0.1U_0402_16V4Z @ R1015 10K_0402_5% CLKRUN#/GPIO1D DAC_BRIG ACIN
DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG <22> 2 1
70 EN_DFAN1
EN_DFAN1/DA1/GPIO3D EN_DFAN1 <30>
DA Output 71 IREF
IREF/DA2/GPIO3E IREF <41>
KSI0 55 72 CALIBRATE#
KSO[0..17] KSI0/GPIO30 DA3/GPIO3F CALIBRATE# <41>
KSI1 56
KSO[0..17] <37> KSI1/GPIO31
KSI2 57
KSI[0..7] KSI3 KSI2/GPIO32 EC_MUTE# EC_SPICLK <37>
KSI[0..7] <37> 58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# <38>
C KSI4 59 84 EC_SPICLK_L 1 2 1 2 C
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B W W AN_LED# R1033 10_0402_5% C1357 10P_0402_50V8J
60 KSI5/GPIO35 PSCLK2/GPIO4C 85 W W AN_LED# <37>
KSI6 61 PS2 Interface 86 EC_THERM#
KSI6/GPIO36 PSDAT2/GPIO4D EC_THERM# <8,25,48>
+5VS KSI7 62 87 TP_CLK Reserve for EMI, close to EC
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <37>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <37>
1 2 TP_CLK KSO1 40
R1018 4.7K_0402_5% KSO2 KSO1/GPIO21 GPXO05
41 KSO2/GPIO22 1 930@ 2 EC_ON
1 2 TP_DATA KSO3 42 97 GPXOA00 R57 1 9012@ 2 0_0402_5% VGATE R1047 0_0402_5%
R1019 4.7K_0402_5% KSO4 KSO3/GPIO23 SDICS#/GPXOA00 65W /90W #
43 KSO4/GPIO24 SDICLK/GPXOA01 98 65W /90W # <41> 1 @ 2 9012_PH2 9012_PH2 <43>
KSO5 VLDT_EN R61 0_0402_5%
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
GPXID0
VLDT_EN <39,46>
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109
KSO7 46 SPI Device Interface GPXO06 1 930@ 2 3S/4S#
KSO7/GPIO27 3S/4S# <41>
+3VALW 1 2 KSO8 47 R62 0_0402_5%
R1020 2.2K_0402_5% KSO9 KSO8/GPIO28
48 KSO9/GPIO29 SPIDI/RD# 119 EC_SI_SPI_SO <37> 1 2 MAINPW ON
+3VS 1 2 EC_SMB_CK2 KSO10 49 120 R63 @ 0_0402_5%
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <37>
R1021 @ 2.2K_0402_5% KSO11 50 SPI Flash ROM 126 EC_SPICLK_L
EC_SMB_DA2 KSO12 KSO11/GPIO2B SPICLK/GPIO58 GPXO07
1 2 51 KSO12/GPIO2C SPICS# 128 EC_SPICS#/FSEL# <37> 1 930@ 2 FCH_PW RGD FCH_PW RGD <26>
R1022 @ 2.2K_0402_5% KSO13 52 R64 0_0402_5%
KSO14 KSO13/GPIO2D
+3VALW 1 2 53 KSO14/GPIO2E 1 2 MAINPW ON MAINPW ON <8,42,43>
R1023 2.2K_0402_5% KSO15 INT_VGAPW R_ON R65 9012@ 0_0402_5%
KSO16
54 KSO15/GPIO2F CIR_RX/GPIO40 73 INT_VGAPW R_ON <20> Delay EC_PWROK 50ms
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 for VGA criterial
KSO17 82 89
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <41>
90 BATT_BLUE_LED# GPXO09 1 9012@ 2 ENBKL
+3VALW BATT_CHGI_LED#/GPIO52 BATT_BLUE_LED# <37>
91 R1061 0_0402_5%
EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_AMB_LED# GPXO10
<43> EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BATT_AMB_LED# <37> 1 9012@ 2 FCH_PW RGD
1 2 EC_SMB_CK1 EC_SMB_DA1 78 93 PW R_LED PW R_LED <37> R60 0_0402_5%
<43> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
R1027 2.2K_0402_5% EC_SMB_CK2 79 SM Bus 95 SYSON
<6,14,21> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <29,39,44>
1 2 EC_SMB_DA1 EC_SMB_DA2 80 121 VR_ON
<6,14,21> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <48>
R1028 2.2K_0402_5% 127 GPIO59
B KSO1 AC_IN/GPIO59 930@ ACIN B
1 2 1 2
R1029 47K_0402_5% R1044 0_0402_5%
1 2 KSO2 SLP_S3# 6 100 EC_RSMRST#
<26> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <26>
R1030 47K_0402_5% SLP_S5# 14 101 EC_LID_OUT#
<26> SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <26>
2 1 LID_SW # EC_SMI# 15 102 GPXO05 GPXID0 1 930@ 2 LID_SW #
<26> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05
R1031 100K_0402_5% EC_PME# 16 103 GPXO06 R58 0_0402_5%
<31> EC_PME# LID_SW#/GPIO0A EC_SWI#/GPXO06
1 @ 2 EC_PME# MINI1_LED# 17 104 GPXO07 Delay SUSP# 10ms 1 2
<33> MINI1_LED# SUSP#/GPIO0B ICH_PWROK/GPXO06 9012_PH1 <43>
R1032 10K_0402_5% 18 GPO 105 BKOFF# R59 9012@ 0_0402_5%
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <22>
2 1 ENBKL 19 GPIO 106 GPXO09
R1034 100K_0402_5% EC_INVT_PW M EC_PME#/GPIO0D WL_OFF#/GPXO09 GPXO10 GPXID1
<22> EC_INVT_PW M 25 EC_THERM#/GPIO11 GPXO10 107 1 930@ 2 VGATE VGATE <48>
FAN_SPEED1 28 108 VGA_ON <20> R1042 0_0402_5%
<30> FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
29 FANFB2/GPIO15 1 9012@ 2 ACIN ACIN <39,41>
E51TXD_P80DATA 30 R1041 0_0402_5%
<33> E51TXD_P80DATA EC_TX/GPIO16
E51RXD_P80CLK 31 110 GPXID1
<33> E51RXD_P80CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1
ON/OFF 1 930@ 2 GPIO18 32 112 GPXID2 GPXID2 1 930@ 2 ENBKL
ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <10>
R1059 0_0402_5% <37> PW R_SUSP_LED# PW R_SUSP_LED# 34 114 GPXID3 R1046 0_0402_5%
EAPD PWR_LED#/GPIO19 GPXID3
1 9012@ 2 <37> W LAN_LED#
W LAN_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 GPXID4 1 9012@ 2 LID_SW # LID_SW # <37> 1 9012@ 2 EC_ON EC_ON <37,42>
R1058 0_0402_5% 116 SUSP# R1038 0_0402_5% R1045 0_0402_5%
GPXID5 SUSP# <39>
117 PBTN_OUT#
GPXID6 GPXID7 PBTN_OUT# <26> GPXID3
GPXID7 118 1 930@ 2 EAPD EAPD <38>
EC_CRY1 122 R1057 0_0402_5%
XCLK1
<25,28> RTC_CLK 1 2 EC_CRY2 123 XCLK0 V18R 124 1 9012@ 2 ON/OFF ON/OFF <37>
R1036 0_0402_5% 1 R1048 0_0402_5%
1
AGND
2 C1359
GND
GND
GND
GND
GND
EC_CRY1 EC_CRY2 R1037 @ C1358 GPXID7 1 9012@ 2 3S/4S#

100K_0402_5% 22P_0402_50V8J 4.7U_0603_6.3V6K R55 0_0402_5%
KB930QF A1 LQFP 128P 2
2 2
11
24
35
94
113
69
@ @ 1
20mil
2
1
A
C1361 @ C1362 A
15P_0402_50V8J X2 15P_0402_50V8J ECAGND 2 L66 1
OSC
OSC
NC
NC
32.768KHZ_12.5PF_Q13MC14610002
2
EC ENE KB930
B 1.0
P5WS5 LA-6973P
5 4 3 2 1
+3VLP +3VALW
Power Button POWER/B Fllow P5WE0 TP Conn. Fllow P5WE0
2
2
930@
9012@ R1040 JPWR1
R56 100K_0402_5% +5VS +5VS
100K_0402_5% 1 1
LID_SW#
+3VALW
JTP1
P/N: SP01000LB00
2 LID_SW# <36>
1
2 F/P: ACES_85201-0605N_6P
3 1 1 C1371
1
3 1 TP_CLK 0.1U_0402_16V4Z
2 1 4 4 2 2 TP_CLK <36>
9012@R1056
9012@ R1056 0_0402_5% 5 +3VS 3 TP_DATA
D26 5 PWR_LED# 3 LEFT_BTN# TP_DATA <36>
Remove Power Button SW1. 6 4
6 ON/OFFBTN# 4 RIGHT_BTN# 2
20110418 2 ON/OFF <36> 7 5
ON/OFFBTN# 7 5
1 8
8
6
6
3 51ON# <40> 9 7 1 1
GND GND C1376 C1377
10 8
DAN202UT106_SC70-3 GND GND
930@ ACES_85201-0805N ACES_85201-0605N 220P_0402_50V7K 220P_0402_50V7K
CONN@ CONN@ 2 2
2
930@
C1365 RIGHT_BTN# TP_CLK
1000P_0402_50V7K
1 LEFT_BTN# TP_DATA
2
SW3 SW4
1
D SMT1-05-A_4P SMT1-05-A_4P
EC_ON 2 930@ LEFT_BTN# 3 1 RIGHT_BTN# 3 1
<36,42> EC_ON
G Q44
2
S 2N7002_SOT23 4 2 4 2
3
930@
R1043 D29 D27
5
6
5
6
10K_0402_5%
PJDLC05C_SOT23-3 PJDLC05C_SOT23-3
1
KB Conn. Fllow P5WE0 LED Fllow P5WE0
Power/SUS Battery 3G/WLAN BlueTooth ACIN
JKB1 LED Status
KSO0 KSI[0..7]
ON SUS Full Charge 3G WLAN
1 1 KSI[0..7] <36>
KSO1 2
KSO2 2 KSO[0..17]
KSO3
3 3 KSO[0..17] <36> NEW70/80/90 Blue Amber Blue Amber Blue Amber
4 4
KSO4 5
KSO5 5
6 6
KSO6 7 KSO16 C1378 1 2 100P_0402_50V8J
KSO7 7 @
8 8
KSO8 KSO17 C1379 1 100P_0402_50V8J PWR_LED#
KSO9
9
10
9 @
2 EC Request LED5
KSO10 10 KSO7 C1381 1 100P_0402_50V8J
11 11 2
KSO11 12 @ +3VALW 1 2 2 1 PWR_LED#
12
1
KSO12 KSO6 C1382 1 100P_0402_50V8J R374 390_0402_5% B D
13 2
KSO13 13 @
14 <36> PWR_LED 2
KSO14 14 KSO5 C1385 1 100P_0402_50V8J HT-191NB5_BLUE G Q48
15 2
15
2
KSO15 16 @ LED1 S 2N7002_SOT23
3
KSO16 16 KSO4 C1387 1 100P_0402_50V8J R1063
17 2
KSO17 17 @ PWR_SUSP_LED# 100K_0402_5%
18 +3VALW 1 2 2 1 PWR_SUSP_LED# <36>
KSI0 18 R378 820_0402_5% A <BOM Structure>
19
KSI1 19
20
1
KSI2 20 KSO0 C1397 1 100P_0402_50V8J HT-191UD5_AMBER
21 2
KSI3 21 @
22
KSI4 22 KSI5 C1399 1 100P_0402_50V8J LED6
23 2
KSI5 23 @
24
KSI6 24 KSI6 C1401 1 100P_0402_50V8J BATT_BLUE_LED#
25 27 2 +3VALW 1 2 2 1 BATT_BLUE_LED# <36>
25 G1
KSI7 26
26 G2
28 @ R379 390_0402_5% B
KSI7 C1403 1 2 100P_0402_50V8J +3VS
@ HT-191NB5_BLUE R05 modify
CONN@
ACES_85201-26051 LED2 +3VS
2
1 2 2 1 BATT_AMB_LED# R1060
BATT_AMB_LED# <36>
KSO15 C1380 1 2 100P_0402_50V8J KSI2 C1396 1 2 100P_0402_50V8J R376 820_0402_5% A 10K_0402_5%
@ @
KSO14 C1383 1 2 100P_0402_50V8J KSO9 C1398 1 2 100P_0402_50V8J HT-191UD5_AMBER
1
5
@ @ U34
KSO13 C1384 1 2 100P_0402_50V8J KSI3 C1400 1 2 100P_0402_50V8J 3G@LED8 2
P
B 5IN1_LED# <31>
@ @ HT-191NB5_BLUE MEDIA_LED# 4
KSO12 C1386 1 100P_0402_50V8J KSO8 C1402 1 100P_0402_50V8J Y
2 2 1 SATA_LED# <27>
A
G
@ @ 1 2 2 1 WWAN_LED#
+3VS WWAN_LED# <36>
3G@R381
3G@R381 390_0402_5% B NC7SZ08P5X_NL_SC70-5
3
KSI0 C1388 1 2 100P_0402_50V8J KSO3 C1389 1 2 100P_0402_50V8J
@ @ U34 change to SA007080B90
KSO11 C1390 1 2 100P_0402_50V8J KSI4 C1391 1 2 100P_0402_50V8J 20101228
@ @ LED4
KSO10 C1392 1 2 100P_0402_50V8J KSO2 C1393 1 2 100P_0402_50V8J LED7
@ @ 1 2 2 1 WLAN_LED# HT-191NB5_BLUE
+3VS WLAN_LED# <36>
KSI1 C1394 1 2 100P_0402_50V8J KSO1 C1395 1 2 100P_0402_50V8J R377 931_0402_1% A
@ @ 1 2 2 1 MEDIA_LED#
+3VS
HT-191UD5_AMBER R380 B
499_0402_1%
LED3
HT-191NB5_BLUE
2 1
B
EC BIOS ROM
+3VALW 1 @ 2 C1370 1 2 0.1U_0402_16V4Z
R1049 0_0603_5% Pop R1055 / C1374 for EMI
20110313
+SPI_VCC C1374 22P_0402_50V8J
2 1 2 1
U42 R1055 10_0402_5%
EC_SPICS#/FSEL# 1 8
<36> EC_SPICS#/FSEL# CE# VDD
R1050 1 2 4.7K_0402_5% EC_SPI_WP# 3 6 EC_SPICLK_R R1051 1 2 0_0402_5%
WP# SCK EC_SPICLK <36>
R1052 1 2 4.7K_0402_5% EC_SPI_HOLD#7 5 EC_SO_SPI_SI_R R1053 1 2 0_0402_5%
+3VALW HOLD# SI EC_SO_SPI_SI <36>
4 2 EC_SI_SPI_SO_R R1054 1 2 0_0402_5%
VSS SO EC_SI_SPI_SO <36>
MX25L1005AMC-12G_SOP8

BIOS, I/O Port & K/B CONN/TP CONN/PBTN
B 1.0
P5WS5 LA-6973P
5 4 3 2 1
+VDDA JSPK2
+5VS 2 @ 1 1
R1067 0_0805_5% Int. Speaker Conn. 2
1
2
1
@ U36 R1068
60mil 1 40mil +3VS 10K_0402_5% SPKL+ R1069 1 2 0_0603_5% SPK_L+ 3
IN SPKL- R1070 1 0_0603_5% SPK_L- G1
1 OUT 5 +VDDA 2 4 G2
C1409 2 SPKR+ R1071 1 2 0_0603_5% SPK_R+
2
GND SPKR- SPK_R-
4.75V 1 2 R1072 1 2 0_0603_5% ACES_88266-02001
1
0.1U_0402_16V4Z 3 C1410 1U_0402_6.3V4Z 20mil
BYP 4
1 2 CONN@
SHDN
3
2 C1411 R1073
G9191-475T1U_SOT23-5 0.01U_0402_16V7K R1074 JSPK1
@ 10K_0402_5% 10K_0402_5% 1
1
2
2
C1412 2
(output = 300 mA)
2
D MONO_IN D
1 2
1U_0402_6.3V4Z D33 D34 3
G1
1
C PJDLC05C_SOT23-3 PJDLC05C_SOT23-3 4
C1413 1 R1075 G2
<36> BEEP# 2 1 2 2 1 2
1
SM010014520 3000ma 220ohm@100mhz DCR 0.04 +PVDD_HDA B Q49 R1076 2.4K_0402_1% ACES_88266-02001
1U_0402_6.3V4Z 560_0402_5% E CONN@
3
+5VS L67 2 1 0.1U_0402_16V4Z 2SC2411K_SOT23-3
FBMA-L11-201209-221LMA30T_0805 C1414 1 R1077
@
1
C1416
1 40mil <26> FCH_SPKR
2 1 2
1
C1415 1U_0402_6.3V4Z 560_0402_5%
10U_0805_10V4Z D35
Int. MIC Conn.
2
@ 2 2 RB751V-40_SOD323-2 +INTMIC_VREFO
@ SM010004010 300ma 70ohm@100mhz DCR 0.3
R1078 D35 change to SCS00000Z00
1
Place near Pin46 0_0603_5% 20101228 INT_MIC_L P/N: SP020008Y00 For EMI
R1079
F/P: ACES_88266-02001_2P
1
SM010014520 3000ma 220ohm@100mhz DCR 0.04 10K_0402_5%
3
15mil 15mil
D36 JMIC2
2
L68 2 1 0.1U_0402_16V4Z +PVDD1_HDA 1 INT_MIC_L 1 2 INT_MIC_R
+5VS
FBMA-L11-201209-221LMA30T_0805 1
C1418
1 40mil HD Audio Codec @
1
2 2 L69 FBMA-L11-160808-700LMT_2P
1
C1417 C1419
10U_0805_10V4Z PJDLC05C_SOT23-3 3
2 2 G1 220P_0402_50V7K
G2 4
2
1
SM010030010 200ma 120ohm@100mhz DCR 0.2 ACES_88266-02001
Place near Pin39 CONN@
SM010030010 200ma 120ohm@100mhz DCR 0.2

10mil +3VS_DVDD 10U_0603_6.3V6M L70 2 1
+AVDD_HDA +3VS
BLM18AG121SN1D_0603
C L71 2 1 0.1U_0402_16V4Z 40mil 1
C1420
1
C1421
1
C1425 MIC_PLUG# C
+VDDA +MIC1_VREFO
BLM18AG121SN1D_0603 1 1 1
0.1U_0402_16V4Z HP_PLUG#
C1422 C1423 C1424 2 2 2 D38 / D39 change to SCS00000Z00
2
10U_0805_10V4Z 0.1U_0402_16V4Z 20101228
2 2 2 Place near Pin1, 9 D37
0.1U_0402_16V4Z PJDLC05C_SOT23-3 D38 D39
RB751V-40_SOD323-2 RB751V-40_SOD323-2
25
38
39
46
9
Place near Pin25, 38 U37 P/N: DC230004K00
1 1
1 1
DVDD_IO
AVDD1
AVDD2
PVDD1
PVDD2
DVDD
C1426 1 2 MIC2_C_L 14 F/P: SINGA_2SJ-A960-C01_6P
INT_MIC_R INT_MIC 4.7U_0603_6.3V6K LINE2_L
Internal MIC 2 1
R1080 1K_0402_5% C1427 1 2 MIC2_C_R 15 35mA R1081 R1085 MIC JACK
1
4.7U_0603_6.3V6K LINE2_R SPKL+ 4.7K_0402_5% 4.7K_0402_5%
C1428 1 2 LINE2_C_L 16
68mA 600mA SPK_OUT_L+
40
JMIC1
2
COM_MIC MIC2_L
Combo MIC 2 1 COM_MIC_R 4.7U_0603_6.3V6K 1
R1082 1K_0402_5% C1429 1 2 LINE2_C_R 17 41 SPKL- MIC1_L 1 2 MIC1_L_1 L72 1 2 MIC1_L_R 2
4.7U_0603_6.3V6K MIC2_R SPK_OUT_L- R1084 1K_0603_5% FBMA-L11-160808-700LMT_2P
23 45 SPKR+ MIC1_R 1 2 MIC1_R_1 L73 1 2 MIC1_R_R 3
LINE1_L SPK_OUT_R+ R1083 1K_0603_5% FBMA-L11-160808-700LMT_2P
3
C1432 220P_0402_50V7K
C1433 220P_0402_50V7K
D40 PJDLC05C_SOT23-3
24 4
LINE1_R SPKR-
SPK_OUT_R-
44 SM010004010 300ma 70ohm@100mhz DCR 0.3
MIC1_L C1430 1 2 MIC1_C_L 21 1 1 MIC_PLUG# 5
4.7U_0603_6.3V6K MIC1_L HP_LEFT
External MIC HPOUT_L
32
MIC1_R C1431 1 2 MIC1_C_R 22
4.7U_0603_6.3V6K MIC1_R HP_RIGHT
33
CBN HPOUT_R 2 2
1 35 6
CBN
SDATA_IN
8 1 R1086 2 HDA_SDIN0 <26>
C1434 33_0402_5% CONN@
1
2.2U_0603_6.3V4Z CBP 36 5 SINGA_2SJ-A960-C01
2 CBP SDATA_OUT HDA_SDOUT_AUDIO <26>
Combo MIC +MIC2_VREFO 29
MIC2_VREFO 10mil SYNC
10 HDA_SYNC_AUDIO <26>
B B
11 HDA_RST_AUDIO# <26>
RESET#
30
MIC1_VREFO_R +MIC2_VREFO
6 HDA_BITCLK_AUDIO <26>
BCLK COM_MIC
External MIC +MIC1_VREFO 31
MIC1_VREFO_L 10mil
@
3
1 @ 2 1 2 C1435
PJDLC05C_SOT23-3
D41
R1087 0_0402_5% 22P_0402_50V8J MIC2JD R1088
Internal MIC +INTMIC_VREFO 28
LDD_CAP 10mil 2.2K_0402_5%
1 2 GPIO0/DMIC_DATA
2 For EMI
1
C1436 10U_0805_10V4Z D R1089
2
R1090 3 2 1 2 COM_MIC
GPIO1/DMIC_CLK Q50 G 22K_0402_5%
2 1 19
JDREF P/N: DC021007151
1
20K_0402_1% 4 BSS138_NL_SOT23-3S 1
3
PD# EC_MUTE# <36> C1437 R52 F/P: SINGA_2SJ2326-001111_6P-T
1
10U_0805_10V4Z 22K_0402_5%
Singatron 2SJ2326
2
HP_PLUG# 2 1 C1438 1 2 2.2U_0603_6.3V4Z 34 12 MONO_IN DC021007151
2
R1091 39.2K_0402_1% CPVEE PCBEEP
MIC_PLUG# SENSE_A
10mil
2 1 13 20
R1092 20K_0402_1% MIC2JD 1 2 SENSE_B 18
SENSE A
SENSE B
MONO_OUT
AVSS2
37 C1439
2 2
C1440 Headphone Out
R1093
1 2 20K_0402_1% 47 JHP1
<36> EAPD @ R1094 0_0402_5% EAPD CODEC_VREFC1441 1 COM_MIC
27 2 0.1U_0402_16V4Z 330P_0402_50V7K 330P_0402_50V7K 3
VREF @ C1442 1 1 1
48
SPDIFO 10mil 2 10U_0805_10V4Z 6
7 26 Place next pin27 HP_LEFT 1 2 HPOUT_L_1 1 2 HPOUT_L_2 1

DVSS AVSS1 R1095 51.1_0402_1% L74 FBMA-L11-160808-700LMT_2P
43
PVSS2 HP_RIGHT HPOUT_R_1 1 HPOUT_R_2
49 42 1 2 2 2
GND PVSS1 R1096 51.1_0402_1% L75 FBMA-L11-160808-700LMT_2P 4
ALC271X-GR_QFN48_7X7
DGND AGND for FSOV acer spec SM010004010 HP_PLUG# 5
201012062000 300ma 70ohm@100mhz DCR 0.3
A PJ27 PJ28 A
@ JUMP_43X39 @ JUMP_43X39 CONN@
1 1 SINGA_2SJ2326-001111
2 2 1 1 2 2
PJ29 PJ30
@ JUMP_43X39 @ JUMP_43X39
1 1 2 2 1 1 2 2
PJ31 PJ26 Security Classification Compal Secret Data Compal Electronics, Inc.
@ JUMP_43X39 @ JUMP_43X39 Issued Date 2010/08/04 2010/08/04 Title
Deciphered Date
1 1 2 2 1 1 2 2
HD Audio Codec ALC271X
GND GNDA GND GNDA Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
A B C D E
+5VALW TO +5VS (5A) +5VALW +5VS

+1.1VALW TO +1.1VS (1.1A) +5VALW +5VALW
2
U38 +1.1VALW +1.1VS
SI4800BDY-T1-GE3_SO8 U39 R1097 R1098
8 1 AO4430L_SO8 100K_0402_5% 100K_0402_5%
7 2 8 1
2
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1U_0603_10V6K
6 3 1 7 2
1
1
2
C1446
C1444
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1 1 5 6 3 1 1 VLDT_EN#
1
C1443
C1447
C1449
R1099 1 5 SYSON#
<34> SYSON#
C1445
470_0603_5% R1100 R1101
3
2 D
C1448
Q52B
1K_0402_5% 470_0603_5%
3 1
4
2 2 2 2 2 Q51
<36,46> VLDT_EN
3 1
2 G 2N7002_SOT23
1
S <29,36,44> SYSON 5
3
1 1
1
5 SUSP R1102
4
1 2 5VS_GATE 5 VLDT_EN# 10K_0402_5% R1104
+VSB
R1103 100K_0402_5% Q53B +VSB 1 2 1.1VS_GATE 100K_0402_5%
2
1 R1105 47K_0402_5% Q54B
4
6
6
2
300K_0402_5%
C1450 +5VALW
1
1
0.1U_0603_25V7K
2
R1106
SUSP 2 Q53A VLDT_EN# 2 C1451
2
Q54A 0.1U_0603_25V7K
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 2 R1108
1
1
100K_0402_5%
1 2
D
+3VS For Power noise
1
ACIN 2 Q57 20110127 SUSP
+3VALW TO +3VS (3.3A)

<36,41> ACIN <35,45> SUSP
G 2N7002_SOT23 2 1
Q52A
S C19 680P_0402_50V7K
3
+3VALW +3VS Q57 change to SB000008J10 2 1
U40 20101228 C27 680P_0402_50V7K
SI4800BDY-T1-GE3_SO8 2 1 <36> SUSP# 2
8 1 C28 680P_0402_50V7K
1
7 2 2 1
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
6 3 1 1 C31 680P_0402_50V7K
C1455
1 1 5 R1109
C1452
R1110 10K_0402_5%
C1453
C1454
470_0603_5%
4
2
2 2
3 1
2 2
2 1 3VS_GATE 5 SUSP
VGA Power
2 +VSB 2
R1112 200K_0402_5%
6
Q60B
4
1
SUSP 2 Q60A C1456 +1.5V to +1.5VSG (1.5A)
0.1U_0603_25V7K
DMN66D0LDW-7_SOT363-6 2 +1.5V +1.5VSG
1
U41 VGA@
AO4430L_SO8
8 1
7 2
+1.5V TO +1.5VS (1.5A)
2
10U_0603_6.3V6M
VGA@ C1459
10U_0603_6.3V6M
10U_0603_6.3V6M
VGA@ C1457
6 3 1 1
1 1 5 VGA@ VGA@
C1458 R1114
+1.5V +1.5VS
C1460
VGA@
AP2301GN-HF_SOT23-3 1U_0402_6.3V4Z 470_0603_5%
4
Q63 2 2
3 1
2 2
3 1
2
2
10U_0603_6.3V6M
1
C1461
R1116 R1117 5 1.5_VDDC_PWREN#

2
100K_0402_5% 470_0603_5% 1 VGA@ 2 1.5VSG_GATE

2 +VSB
R1118 100K_0402_5% Q64B
1
3 1
4
6
510K_0402_5%
DMN66D0LDW-7_SOT363-6 Q64A 1
6
1
+5VALW
VGA@ R1121
C1462
1.5_VDDC_PWREN# 2 1 2 VGA@
R1122 Q65A 5 SUSP VGA@ R1120 47K_0402_5% 0.1U_0603_25V7K
2
SUSP# 2
2 1 2
1
47K_0402_5% 1 Q65B 1 R1119
4
2
VGA@ 100K_0402_5%
1
C1463 C1464
1
3 0.22U_0603_16V4Z 0.1U_0402_16V7K D 3
1
2 2 ACIN 2 Q69 VGA_PWR_ON#
G VGA@
S 2N7002_SOT23
1
D
2
<20,45> VGA_PWR_ON G Q68
1
S 2N7002_SOT23
3
R1123
100K_0402_5%
+1.0VSG +VGA_CORE +1.8VSG +1.2VS
2
2
R1125 R1126 R1127 R1128

470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
VGA@ VGA@ +3VS to +3VSG (3.3A) +5VALW
1
Change to Jump
2
201012062000
1
D D D D R1131
2 VGA_PWR_ON# 2 1.5_VDDC_PWREN# 2 VGA_PWR_ON# 2 VLDT_EN# @ PJ14 100K_0402_5%
G G G G +3VS 1 2 +3VSG
Q71 Q72 Q73 Q74 1 2
S S S S
3
1
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 JUMP_43X118 1.5_VDDC_PWREN#
VGA@ VGA@
1
D
<20,46,47> 1.5_VDDC_PWREN 2
+1.5V +2.5VS +0.75VS G Q77
1
S 2N7002_SOT23
3
2
4 R1134 4
R1135 R1136 R1137 10K_0402_5%
470_0603_5% 470_0603_5% 470_0603_5%
2
1
1
1
D D D
2 SYSON# 2 SUSP 2 SUSP Security Classification Compal Secret Data Compal Electronics, Inc.
G G G Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
Q78 Q79 2N7002_SOT23
S S S
DC Interface
3
2N7002_SOT23 2N7002_SOT23 Q80 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
B 1.0
P5WS5 LA-6973P
A B C D E
5 4 3 2 1
@ PJP1
ACES_50305-00441-001
PL1
SMB3025500YA_2P
VIN
1 1 2
2
3
4
GND
1
GND PC1 PC2 PC3 PC4
1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K
2
2
D D
PD10 @ PR6
PJSOT24CH_SOT23-3 0_0603_5%
1 2
1
VIN
2
PD1
LL4148_LL34-2
1
PD2
LL4148_LL34-2
2 1
BATT+
1
PR1 PR2
68_1206_5% 68_1206_5%
PQ1 VS
TP0610K-T1-E3_SOT23-3
2
N1 3 1
0.22U_0603_25V7K
1
PJ1 PJ2
1
PR3 1 PC6
+3VALWP 1 1 2 2 +3VALW +1.8VSGP 1 1 2 2 +1.8VSG
PC5
C 100K_0402_5% 0.1U_0603_25V7K C
JUMP_43X118 JUMP_43X118
2
(3.9A,160mils ,Via NO.= 8) (3A,120mils ,Via NO.=6)

2
<37> 51ON# 1 2
PJ3 PJ4
PR4 1 2 1 2
22K_0402_5% +5VALWP 1 2 +5VALW +1.1VALWP 1 2 +1.1VALW
JUMP_43X118 JUMP_43X118
(5A,200mils ,Via NO.= 10) (7A,280mils ,Via NO.=14)
PJ6
PJ5
1 2
+0.75VSP 1 2 +0.75VS
1 2
+VSBP 1 2 +VSB JUMP_43X79
JUMP_43X39 (3A,120mils ,Via NO.=6)
PreCHG (120mA,40mils ,Via NO.= 2)
PQ2
PR5 VIN PR7 LL4148_LL34-2 TP0610K-T1-E3_SOT23-3
0_0603_5% 1K_1206_5% PD3 B+
+CHGRTC 1 2 1 2 2 1 3 1
+3VLP @PJP3
@ PJP3
100K_0402_5%
100K_0402_5%
PR8 JUMP_43X118
1K_1206_5% 1 PJ8
1 2 2
1
1
PR9
1 @ 2 @ PR10 +1.5VSGP 1 2 +1.5VSG

1 2
PR11 @PJP4
@ PJP4 JUMP_43X118
1K_1206_5% JUMP_43X118
2
1 @ 2 +VGA_COREP 1 1
2 2 (8.1A,320mils ,Via NO.=17)
2
+VGA_CORE
B PJ9 B
PR12
@
1
1K_1206_5% +2.5VSP 1 2 +2.5VS
PR13 1 2
1 @ 2
@ @ 100K_0402_5% JUMP_43X39
12
1
@
PD4 @ PJ10
<36,41> ACOFF PJ11
2 +1.2VSP 1
1 2
2 +1.2VS
1 2 2 +1.0VSGP 1
1 2
2 +1.0VSG
3 JUMP_43X118
<42> +5VALWP PQ4 JUMP_43X39
BAS40CW_SOT323-3 PQ3 PDTC115EU_SOT323-3
PDTC115EU_SOT323-3
3
@
@ @ PJ7
+1.5VP 1
1 2
2 +1.5V
JUMP_43X118
PJ13
1 1
2 2
JUMP_43X118
A A

PWR DCIN / Pre-charge
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
A B C D
Iada=0~4.74A(90W/19V=4.736A) @
PC112
10U_0805_25V6K PQ5
CP = 85%*Iada ; CP = 4.07A @ PJ32 2 1 AO4407A_SO8
ADP_I = 19.9*Iadapter*Rsense 2 2 1 1 PC113 1 8
@ 10U_0805_25V6K 2 7
JUMP_43X118 2 1 3 6
P2 P3 B+ CHG_B+ 5
PQ6 PQ7 PR14 0.02_2512_1% PL22
AO4407A_SO8 SI4459ADY-T1-GE3_SO8 PL17 HCB4532KF-800T90_1812
4
VIN 8 1 1 8 1 4 1 2 1 2
7 2 2 7 1.2UH_1231AS-H-1R2N=P3_2.9A_30% PR16
6 3 3 6 2 3 CSIN 200K_0402_1%
5 5 1 2 VIN
CSIP
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_25V7K
0.1U_0603_25V7K
5600P_0402_25V7K
VIN PreCHG
2
1 1
PC8
PC9
2
PC10
PC11
PR15 PD6
PC7
47K_0402_1% 1 2 ACOFF
2
1
1
PR120
1
1
191K_0402_1% PR18 @ @ PC101 1SS355_SOD323-2
1
1
2
191K_0402_1% 2200P_0402_50V7K PR224
0.1U_0603_25V7K
1
2
PR19 PR17 200K_0402_1%
1
PC12
47K_0402_1% 200K_0402_1% 6251VDD 1 2 VIN
1
PD5
2
RB751V-40_SOD323-2 ACSETIN
1000P_0402_25V8J
2.2U_0603_6.3V6K
2
1
PC13
PD9
1 1
3
1
2 1 2
1
PC14
10_1206_5%
47K
PR22
PR23 1SS355_SOD323-2
2 47K 14.3K_0402_1%
2
PR24
0.1U_0603_25V7K
2
1
0_0402_5% PQ9 @ PR119 D <BOM
PQ51Structure>
1
PC107
2 1 PU1 PDTC115EU_SOT323-3 100K_0402_1% 2 PACIN
<36> FSTCHG
1
PC15 2N7002W
G -T/R7_SOT323-3
V1
1
PQ8 DCIN 2 D
1 24 1 S
1
3
V1
VDD DCIN
1
1
PDTA144EU_SOT323-3 PR25 47K_0402_5%
100K_0402_1%
2
6251VDD 1 2 0.1U_0603_25V7K G
PR26
2 PR27 ACSETIN 2 23 ACPRN <42> S
3
ACPRN
ACSET ACPRN
1
150K_0402_1% PR28 PQ30@
PQ13 20_0402_5% 2N7002W -T/R7_SOT323-3
2
2
6
PQ10 PDTC115EU_SOT323-3 6251_EN 3 22 1 2 CSON

EN CSON
2
PDTC115EU_SOT323-3 PC18
3
5
6
7
8
2 0.047U_0402_16V7K
<36> 3S/4S#
2 PQ14A 4 21 1 2 CSOP PQ15
1
CELLS CSOP PR29 AO4466_SO8
3
PC19 6800P_0402_25V7K 20_0402_5%

1
2 2
3 1 2 5 ICOMP CSIN 20 2 1
2
PR30 4
PC20 PR31 PC21 20_0402_5%
DMN66D0LDW -7_SOT363-6
5
1 2 1 2 6 19 0.1U_0603_25V7K
1 2 TCR=50ppm / C
<40,41>
1
PQ14B VCOMP CSIP PR32 PL2
4
0.01U_0402_25V7K 10K_0402_1% 2_0402_5% 10UH_PCMB104T-100MS_6A_20% BATT+
3
2
1
<36> ADP_I 1 2 7 18 LX_CHG 1 2 CHG 1 4 PR34
PR33 100_0402_1% ICM PHASE 0.02_1206_1%
5
6
7
8
4.7_1206_5%
1 2 2 3
PR35
PR38 6251VREF 8 17 DH_CHG
47K_0402_5% PR36 PC22 .1U_0402_16V7K VREF UGATE PR37 PC23
PACIN 80.6K_0402_1% 2.2_0603_1% 0.1U_0603_25V7K PQ16
10U_1206_25V6M
10U_1206_25V6M
1 2
2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1 AO4466_SO8
2
<36> IREF CHLIM BOOT
1
4
0.01U_0402_25V7K
1
1
PC25
PC26
PR40 PD8
1
PC24
PR39 6251VREF 6251aclim 6251VDDP RB751V-40_SOD323-2
680P_0402_50V7K
1 2 10 ACLIM VDDP 15
PC27
100K_0402_1%
2
2
1
26251VDD
20K_0402_1%
12.1K_0402_1%
2.55K_0402_1%
3
2
1
2
1
ACOFF 2 11 14 DL_CHG
<36,40> ACOFF
2
VADJ LGATE
2
PR42
PR43
PR41
4.7_0603_5%
12 13 PC28
1 2
1
PQ17 GND PGND 4.7U_0603_6.3V6M
3
PDTC115EU_SOT323-3 D
2 ISL6251AHAZ-T_QSOP24
<36> 65W/90W# G
PQ18 S
3
2N7002W -T/R7_SOT323-3
CP mode 1 2
3
<36> CALIBRATE# PR44
3
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) 15.4K_0402_1%
2
where Vaclm=1.502V, Iinput=4.07A PR45

31.6K_0402_1%
6251VDD
Charging Voltage
1
BATT Type CV mode CC=0.6~4.48A PR48

(0x15) 10K_0402_1%
1
1 2
IREF=0.7224*Icharge PR46 PR47
ACIN <36,39>
Normal 3S LI-ON Cells 47K_0402_5% 10K_0402_1%

12600mV 12.60V IREF=0.43V~3.24V
2
2
PACIN
1
Ki
1
Vchlim=Iref*(PR374/(PR372+PR374)) PR49
14.3K_0402_1%
=Iref*(100K/(80.6K+100K))
=Iref*0.5537
2
Ichanrge=(165mV/PR369)*(Vchlim/3.3V) ACPRN 2
=(165m/20m)*(1/3.3V)*Iref*0.5537
=1.3842*Iref PQ19
Iref=0.7224*Ichanrge =>Ki=0.7224 PDTC115EU_SOT323-3
3
Kv
4 4
Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K
R=514K//31.6K//(15.4K+3k)=11.372K
r=514K//514K//31.6K=28.14K
Vcell=0.175*Vadj+3.99v
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 Security Classification Compal Secret Data Compal Electronics, Inc.
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title
A=Vref*(R/(R+514K))=0.052
Kv=9.451 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CHARGER
Custom 1.0
P5WS5 LA-6973P
A B C D
5 4 3 2 1
2VREF_8205
1U_0603_10V6K
D D
1
PC29
2
10U_0805_25V6K
10U_0805_25V6K
1
PR50 PR51
PC104
PC110
13.3K_0402_1% 30K_0402_1%
1 2 1 2
2
@ @
PR52 PR53
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
1 2 1 2
PL3
HCB4532KF-800T90_1812
B+ 1 2 Typ: 175mA +3VLP
ENTRIP2
ENTRIP1
PR54 PR55
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0603_25V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
137K_0402_1% 154K_0402_1%
PC31
PC38
1 2 1 2
4.7U_0805_10V6K
1
1
PC32
PC33
PC34
PC35
PC36
PC37
PC200
5
PU2
2
2
PQ20 PQ21
PC39
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
1
C AON7408L_DFN8-5 AON7408L_DFN8-5 C
25 P PAD
2
4 4
7 VO2 VO1 24
SPOK <43,44>
8 23 PR57 PC41
PR56 VREG3 PGOOD 2.2_0603_1% 0.1U_0603_25V7K
1
2
3
3
2
1
1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2
2.2_0603_1%
4.7UH_PCMC063T-4R7MN_5.5A_20% PC40 UG_3V 10
VFB=2.0V 21 UG_5V PL5
PL4 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_PCMC063T-4R7MN_5.5A_20%
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
1
LG_3V LG_5V
4.7_1206_5%
4.7_1206_5%
12 LGATE2 LGATE1 19
3
PR58
PR60
SKIPSEL
PQ22 PR59 @
VREG5
IRFH3707TRPBF_PQFN8-3 0_0402_5%
GND
VIN
MAINPW ON RT8205EGQW _W QFN24_4X4
NC
EN
1 2 1 1
2
2
2
PC42 + 2 PC43 +
13
14
15
16
17
18
1
1
220U_6.3V_M PR61 220U_6.3V_M
680P_0402_50V7K
680P_0402_50V7K
499K_0402_1% PQ23
PC44
PC45
2 IRFH3707TRPBF_PQFN8-3 2
1 2
2
2
B+
1
1
100K_0402_1%
1U_0603_10V6K
VL
1
PC46
1
PR62
PC47
Typ: 175mA
4.7U_0805_10V6K
B B
2
ENTRIP1 ENTRIP2
2
2
RT8205_B+
0.1U_0603_25V7K
D D
3
2VREF_8205
2
PQ24B PQ24A
PC48
5 2
DMN66D0LDW -7_SOT363-6 G G DMN66D0LDW -7_SOT363-6 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
<8,36,43> MAINPWON PR63
0_0402_5% S S
(2)SMPS2=375KHZ(+3VALWP)
4
2 1
PR64
100K_0402_1%
2 1
VL
+3.3VALWP +5VALWP
Ipeak=5.78A ; 1.2Ipeak=6.94A; Imax=4.05A Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
f=375KHz, L=4.7UH f=300KHz, L=4.7UH,Rentrip=154k ohm
1
2N7002W -T/R7_SOT323-3
PQ26 PQ25
Rdson=15~18m ohm Rdson=15~18m ohm
PR65
D
PDTC115EU_SOT323-3 1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.716A 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
1
200K_0402_5% Vlimit=10*10^-6*110Kohm/10=0.14V Vlimit=10*10^-6*154Kohm/10=0.15V

<41> ACPRN 2 1 2 1 2 2
G VS Ilimit=0.11/(18m*1.2)~0.11/(15m)=6.34A~9.13A Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
S PR66 Iocp=7.06A~9.85AA (7.06A>6.94A -> ok) -DVT- Iocp=8.44~11.57A (8.44>8.4 -> OK)
3
A A
1
100K_0402_1%
1
1
2.2U_0603_6.3V6K
3
40.2K_0402_1%
PC49
100K_0402_1%
2
1
PR67
<36,37> EC_ON PQ27

PR121
2
PDTC115EU_SOT323-3 Security Classification Compal Secret Data Compal Electronics, Inc.
@
3VALWP/5VALWP
2
3
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
5 4 3 2 1
PJP2
SUYIN_200275GR008G13GZR
D D
10
GND
9
GND
8
8
7
7 EC_SMDA
6
6
2
5 EC_SMCA
5 TH PR68
4
4 PI 100_0402_1%
3
3
2
2
1 PH1 under CPU botten side :
1
1
2
PR69
CPU thermal protection at 92 degree C
<40,41> 100_0402_1% Recovery at 72 degree C
EC_SMB_DA1 <36>
VL
VMB
1
1
PL6
SMB3025500YA_2P
<40,41> EC_SMB_CK1 <36>
1 2 BATT+ PR70
1
1K_0402_5%
2
PR73 PC50 PR71 PR72
1
6.49K_0402_1% 0.1U_0603_25V7K VL 10K_0402_1% 21K_0402_1%
2
PC51 PC52 2 1
0.01U_0402_25V7K +3VALWP
1000P_0402_50V7K
2
2
2
PU3
@ PR74 1 8 2 1 9012_PH1 <36>
VCC TMSNS1
1
100K_0402_1%
PR75 2 7 2 1 @ PR123
1K_0402_1% GND RHYST1 0_0402_5%
1
3 6 PR76
OT1 TMSNS2
C
<8,36,42> MAINPWON 9.53K_0402_1%
9012_PH2 <36>
C
2
4 OT2 RHYST2 5 2 1 2 1
BATT_TEMP <36> @ PR77
G718TM1U_SOT23-8 @ PR124
47K_0402_1% 0_0402_5%
1
PH2 @ PH1
100K_0402_1%_NCP15WF104F03RC 100K_0402_1%_NCP15WF104F03RC
2
PQ28
TP0610K-T1-E3_SOT23-3
B+ 3 1 +VSBP
100K_0402_1%
0.22U_0603_25V7K
1
1
PR78
PC53
PC54
@ 0.1U_0603_25V7K
2
2
2
PR79
VL 22K_0402_1%
1 2
2
PR80
100K_0402_1%
B B
PR81
1
1K_0402_5% D
1 2 2 PQ29
<42,44> SPOK
G 2N7002W-T/R7_SOT323-3
1U_0402_6.3V6K
S
3
1
PC55
2
A A

PWR-BATTERY CONN/OTP
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
A B C D
PL8
FBMA-L18-453215-900LMA90T_1812
1.1VALW _B+ 2 1 B+
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
1
PC59
PC60
PC116
PC133
PC114
PC111
1.Enable resistor is must under 140KΩ avoid over enable turn-off threshold voltage.
2
2.Input enable need to reserve a pull-down resistor about 30KΩ to GND. @
PR83
255K_0402_1% 4
1 1 2 PQ31 1
PR84 PR85 AON7408L_DFN8-5

0_0402_5% 2.2_0603_5%
1 2 BST_1.1VALW
1 2
3
2
1
<42,43> SPOK DCR= 7.5 mohm
1
@ PR86 PL9
15
14
1
30K_0402_5% @ PC61 PU5 PC62 2.2U_FDV0630-2R2M-P3_7.2A_20%
0.1U_0402_16V7K BST_1.1VALW -11 2 1 2
EN_PSV
TP
VBST
+1.1VALWP
2
2
2 13 DH_1.1VALW 0.1U_0603_25V7K
TON DRVH
1
PR88 3 12 LX_1.1VALW
VOUT LL
3
100_0603_1% PR87 1
+5VALW 1 2 4 11 1 2 +5VALW 4.7_1206_5%
V5FILT TRIP PR89 + PC63
2
5 10 7.32K_0402_1% PQ32 330U_4V_M
VFB V5DRV IRFH3707TRPBF_PQFN8-3
1
DL_1.1VALW 2
6 PGOOD DRVL 9 2
PGND
PC64 PC65
GND
4.7U_0603_6.3V6K 680P_0603_50V7K
2
1
<Vo=1.1V> VFB=0.75V TPS51117RGYR_QFN14_3P5X3P5 PC66
1
4.7U_0805_10V6K
V=0.75*(1+4.7K/10K)=1.1V
2
Fsw=280KHz
PR90
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm. 4.99K_0402_1%
2 1
Ipeak=5.5A, Imax=3.85A, Iocp=8.9A
1
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
2
=>1/2Delta I=1.03A PR91 2
Vtripmax=Iocp*Rdson=8.9*5.6*1.3=0.065V 10K_0402_1%
Rcs=Vtrip/9uA=0.065V/9uA=7.2K
2
choose Rcs=7.32K
Iocpmax=((7.32K*11uA)/0.0045)+1.03A=19A PL10
FBMA-L18-453215-900LMA90T_1812
Iocpmin=((7.32K*9uA)/(0.0056*1.3))+1.03A=10A 1.5V_B+ 2 1 B+
Iocp=10A~19A
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
VGA@ PR98
1
PC117
PC67
PC68
PC103
PC102
PC199
PC187
5
6
7
8
2
8.45K_0402_1%
PR92 PQ33
226K_0402_1% 4 AO4466_SO8
1 2
PR94
PR93 0_0402_5% 2.2_0603_5%
1 2 BST_1.5V 1 2
<29,36,39> SYSON
3
2
1
1
@ PR95 PC70 PL24
15
14
1
30K_0402_5% @PC69
@ PC69 PU13 0.1U_0603_25V7K 1.0UH_PCMC104T-1R0MN_20A_20%
0.1U_0402_16V7K BST_1.5V-1 1 2 1 2
EN_PSV
TP
VBST
+1.5VP
2
2
2 13 DH_1.5V
TON DRVH
1
3 3
PR97 3 12 LX_1.5V PR96

VOUT LL
5
6
7
8
100_0603_1% 4.7_1206_5% 1
1 2 4 11 1 2 +5VALW
D
D
D
D
+5VALW V5FILT TRIP + PC71
6670@ PR98
2
5 10 15.8K_0402_1% PQ65 6670@ 330U_D2E_2VM_R6M
VFB V5DRV FDS6670AS_NL_SO8
1
1
DL_1.5V PC73 2 VGA@ PQ65
6 PGOOD DRVL 9 4 G
PGND
PC72 680P_0603_50V7K
GND
4.7U_0603_6.3V6K
2
2
1
S
S
S
TPS51117RGYR_QFN14_3P5X3P5 PC170
7
3
2
1
4.7U_0805_10V6K
2
AO4456_SO8
<Vo=1.5V> VFB=0.75V PR99

6.04K_0402_1%
Vo=0.75*(1+5.9K/5.76K)=1.5V 2 1
Fsw=335KHz
1
Cout ESR=17 mohm Rdson(max)=18 mohm Rdson(typ)=15 mohm

PR100
Ipeak=27.7A, Imax=19.39A, Iocp=13.2A 5.76K_0402_1%
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=3.9A
2
=>1/2Delta I=1.95A
Vtripmax=Iocp*Rdson=16.2*5.6*1.3=0.118V
choose Rcs=13K
Iocpmax=((13K*11uA)/0.0045)+1.95A=32A
4 Iocpmin=((13K*9uA)/(0.0056*1.3))+1.95A=18A 4
Iocp=9.94A~13.2A

1.1VALWP/1.5VP
Custom 1.0
P5WS5 LA-6973P
A B C D
5 4 3 2 1
D D
Note:Imax=3.3A
VGA@
PU7 VGA@ PL12
PJ21
4
@ 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
+3VALW 1 2 10 2 LX_1.8V 1 2
PG
1 2 PVIN LX +1.8VSGP
JUMP_43X79 9 3
68P_0402_50V8J
PVIN LX
PC76
4.7_1206_5%
1
VGA@ PC75 8 VGA@
22U_0805_6.3VAM
22U_0805_6.3VAM
SVIN
1
22U_0805_6.3VAM VGA@ PR102
PR101
2
10K_0402_1% VGA@
PC77
PC78
6
2
FB VGA@
5
2
VGA@ PR103 EN
NC
NC
TP
200K_0402_1% FB_1.8V VGA@
VGA_PWR_ON 1.8V_EN
1 2 FB=0.6V
11
1
1
680P_0603_50V7K
0.1U_0402_10V7K
SY8033BDBC_DFN10_3X3 VGA@ PR104
PC81
PC79
1
1
4.99K_0402_1%
2
VGA@ PC80
2
0.22U_0603_25V7K @ VGA@
2
+1.5V
C C
1
1
PJ12
JUMP_43X79
2
PU4
2
1 8
VIN NC
+3VALW
2 7
GND NC
1
PC58
1
PC57 3 6 1U_0603_6.3V6M
4.7U_0805_6.3V6K PR139 VREF VCNTL
2
1K_0402_1% 4 5
VOUT NC
9
2
TP
+3VALW APL5336KAI-TRL_SOP8P8
PR82
0.1U_0402_16V7K
+0.75VSP
1
300K_0402_5% PQ11 D
+1.5V PR140
PC56
<35,39> SUSP 1 2 2
1
1
VGA@ PC82 G 1K_0402_1%
2
1
1U_0402_6.3V6K S PC16
3
PC30 2N7002W-T/R7_SOT323-3 22U_0805_6.3V6M
2
2
0.22U_0402_10V4Z
2
1
PJ22 @
1
JUMP_43X79
PU14 VGA@
Note:Imax=3.0A
2
6
VPP
5 3
2
9
VIN
TP
VO
VO
4 +1.0VSGP Ipeak=1A, Imax=0.7A
1
8 FB=0.8V VGA@ PR105

VEN
1
B B
VGA@ PC83 7 2 1.54K_0402_1% VGA@ PC84 VGA@ PC85
GND
4.7U_0603_6.3V6K POK ADJ 0.022U_0402_25V7K 22U_0805_6.3V6M

2
2
2
G9731F11U_SO8
1
VGA@ PR106
6.04K_0402_1%
VGA@ PR107
2
15K_0402_1%
<20,39> VGA_PWR_ON 1 2
1
1
VGA@ PC86 @ PR108

1U_0402_6.3V6K 22K_0402_5% Ien=10uA, Vth=0.3V, notice
2
the res. and pull high

2
voltage from HW PU15

APL5508-25DC-TRL_SOT89-3
+3VS 2 3
IN OUT
+2.5VSP
4.7U_0805_6.3V6K
1
GND
1
PC87
1U_0402_6.3V6K 1 @ PR109
PC88
150_1206_5%
2
A A

+1.8VSGP/+1.0VSGP/+2.5VSP/+0.75V
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
5 4 3 2 1
5 4 3 2 1
PL13
FBMA-L18-453215-900LMA90T_1812
1.2V_B+ 2 1 B+
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
1
PC74
PC89
PC90
PC182
PC138
PC188
5
6
7
8
2.Input enable need to reserve a pull-down resistor about 30KΩ to GND.
2
D D
PR110 PQ36
226K_0402_1% 4 AO4466_SO8
1 2
PR112
PR111 0_0402_5% 2.2_0603_1%
1 2 BST_1.2V 1 2
<36,39> VLDT_EN
3
2
1
1
1
@ PR113 PC92 PL14
15
14
1
30K_0402_5% @PC91
@ PC91 PU17 0.1U_0603_25V7K 2.2U_FDV0630-2R2M-P3_7.2A_20%
0.1U_0402_16V7K BST_1.2V-1 1 2 1 2
EN_PSV
TP
VBST
+1.2VSP
2
2
2 13 DH_1.2V
TON DRVH
1
PR115 3 12 LX_1.2V PR114
VOUT LL
5
6
7
8
100_0603_1% 4.7_1206_5% 1
+5VALW 1 2 4 11 1 2 +5VALW PQ37
V5FILT TRIP PR116 AO4456_SO8 + PC93
2
5 10 13K_0402_1% 330U_4V_M
VFB V5DRV
1
DL_1.2V PC95 2
6 PGOOD DRVL 9 4
PGND
PC94 680P_0603_50V7K
GND
4.7U_0603_6.3V6K
2
1
3
2
1
4.7U_0805_10V6K
2
C PR117 C
6.34K_0402_1%
2 1
1
PR118
10K_0402_1%
2 @PL23
@ PL23
FBMA-L18-453215-900LMA90T_1812
1.5VSG_B+ 2 1 B+
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
1
PC115
PC177
PC173
PC184
C184
PC183
PC189
5
6
7
8
@
@P
2
PR239 PQ66
226K_0402_1% 4 AO4466_SO8
@1 2 @
@ PR230 @ @ @
PR226 0_0402_5% 2.2_0603_1%
B BST_1.5VSG B
<20,39,47> 1.5_VDDC_PW REN 1 2 1 2
3
2
1
1
@ PR245 15 PC174 @ PL25
14
1
30K_0402_5% @PC176
@ PC176 PU16 @ 0.1U_0603_25V7K 2.2U_FDV0630-2R2M-P3_7.2A_20%
0.1U_0402_16V7K BST_1.5VSG-1 1 2 1 2
EN_PSV
TP
VBST
+1.5VSGP
2
2
2 13 DH_1.5VSG
TON DRVH
1
PR242 3 12 LX_1.5VSG @ @
@ PR244
VOUT LL
5
6
7
8
100_0603_1% 4.7_1206_5% 1
+5VALW 1 2 4 11 1 2 +5VALW PQ67
V5FILT TRIP PR241 AO4712_SO8 + PC175
2
5 10 13K_0402_1% 330U_4V_M
VFB V5DRV
@
1
1
DL_1.5VSG @ PC171 2
@ 6 PGOOD DRVL 9 4
PGND
PC178 680P_0603_50V7K
GND
4.7U_0603_6.3V6K @
2
2
1
7
3
2
1
<Vo=1.5V> VFB=0.75V @ 4.7U_0805_10V6K
2
Vo=0.75*(1+10K/10K)=1.5V @
Fsw=335KHz PR240 @
5.9K_0402_1%
Cout ESR=17 mohm Rdson(max)=18 mohm Rdson(typ)=15 mohm 2 1
@
Ipeak=27.7A, Imax=19.39A, Iocp=13.2A
1
A Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=3.9A A
PR243
@
=>1/2Delta I=1.95A 5.76K_0402_1%
Vtripmax=Iocp*Rdson=16.2*5.6*1.3=0.118V
2
choose Rcs=13K @ Security Classification Compal Secret Data Compal Electronics, Inc.
Iocpmax=((13K*11uA)/0.0045)+1.95A=32A Issued Date 2010/04/12 Deciphered Date 2010/10/12 Title
Iocpmin=((13K*9uA)/(0.0056*1.3))+1.95A=18A
+1.2VSP/+1.5VSGP
Iocp=9.94A~13.2A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
5 4 3 2 1
VGA@ PL15
FBMA-L18-453215-900LMA90T_1812
B+ 1 2 B+_CORE
2200P_0402_50V7K
+3VS
PC190
2200P_0402_25V7K
1
0.1U_0603_25V7K
2
10U_0805_25V6K
10U_0805_25V6K
@ VGA@ PR142
1
PC98
D 10K_0402_5% D
5
PC97
PC99
VGA@ PC100
2
2
VGA@
VGA@ VGA@
<20,25> VGA_PWRGD
4
VGA@ PR143 VGA@ PC105 VGA@ PQ42

PU10 VGA@ 2.2_0603_1% 0.1U_0603_25V7K TPCA8065-H_SOP-ADV8-5
VGA@ PR145 1 10 BST_VCORE 1 2 1 2
3
2
1
30K_0402_1% PGOOD VBST
1 2 2 9 DH_VCORE VGA@ PL16
TRIP DRVH 0.36UH_PCMC104T-R36MN1R17_30A_20%
+3VS 3 8 SW_VCORE 1 2
EN SW +VGA_COREP
4 VFB V5IN 7 +5VALW
1 2 5 6 DL_VCORE
RF DRVL
2
VGA@ PQ45
ESR=10mohm
1
@ PR146 VGA@ PR200 11 TPCA8057-H_SOP-ADVANCE8-5 1
TP
1
10K_0402_5% 470K_0402_1% VGA@ PC106 @ PR206 VGA@ PC108
TPS51218DSCR_SON10_3X3 1U_0603_6.3V6M VGA@ PR147 VGA@ 0_0402_5% + 390U_2.5V_M
1
VGA@ PR217 VFB=0.6V VGA@ PQ44 4.7_1206_5% PC201
1
2
10K_0402_1% TPCA8057-H_SOP-ADVANCE8-5 .1U_0402_16V7K
2
1 2 PR212 VGA@ 2
<20,39,46> 1.5_VDDC_PWREN
1 2
4 4 100_0402_1%
2 1
1
VGA@ PC109
2
C VGA@ PC166 680P_0603_50V7K C
2
.1U_0402_16V7K GCORE_SEN
GCORE_SEN <16>
2
3
2
1
3
2
1
PR222 VGA@
1.2K_0402_1%
1 1
Rds=4.5m/5.6mOHM PR202 VGA@
5.9K_0402_1% PC202 VGA@
1000P_0402_50V7K
2
+3VSG
2
1
SEY@ PR218
2
WEI@ PR218
@ PC169 VGA@ PR198 41.2K_0402_1% VGA@ PR211
2200P_0402_25V7K 20.5K_0402_1% 10K_0402_5%
1
2
VGA@ PR199
1
6
27.4K_0402_1% D 40.2K_0402_1%
VGA_CORE 2 1 2
SEY@ PR208 G
F=1/(75*e-12*44.2)=300K
2
Ipeak=25A Imax=17.5A Iocp=30A
1
VGA@ PQ47A S
1
WEI@ PR208 VGA@ PC168 @ PR207
84.5K_0402_1% +3VSG 4700P_0402_25V7K 10K_0402_5%
1
41.2K_0402_1%
2
Follow the project of NEW70 for VGA_CORE circuit
B VGA@ PR203 B
10K_0402_5%
VGA@ PR219
3
D 10K_0402_5%
1
5 1 2 +3VSG
G
2
VGA@ PQ47B S VGA@ PC167
4
DMN66D0LDW-7_SOT363-6 4700P_0402_25V7K @ PR201
2
10K_0402_5%
@ PR165
2
For Whistler 10K_0402_5%
1
VGA@ PR210
1/2Delta I=4.05A
6
D 10K_0402_5%
GPIO 20 GPIO 15 Whistler Seymour Vtrip=36.5K*10uA=0.365V 2 2 1
GPU_VID1 <14>
1
VGA@PQ68A G
Iocpmin=0.365V/(8*1.6m)+1/2Delta I=28.51A+4.05A
GPU_VID1 GPU_VID0 Core Voltage Level Core Voltage Level =32.56A S VGA@ PR197
1
10K_0402_5%
+3VSG
2
1 1 0.9V 0.9V
For Seymour
2
1 0 0.95V 1.0V 1/2Delta I=4.31A @ PR209
Vtrip=40.2K*10uA=0.402V VGA@ PR213 10K_0402_5%
3
D 10K_0402_5%
Iocp=0.402V/(8*3.2m)+1/2Delta I
0 1 1.0V 1.05V 5 2 1
GPU_VID0 <14>
11
=15.70A+4.31A=20.01A VGA@PQ68B G
A DMN66D0LDW-7_SOT363-6 VGA@ PR205 A
0 0 1.05V 1.15V S 10K_0402_5%
2
Security Classification Compal Secret Data AP Compal Electronics, Inc.
+VGA_COREP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. P5WE0
5 4 3 2 1
5 4 3 2 1
CPU_B+ PL18
PLACE NEAR NB choke FBMA-L18-453215-900LMA90T_1812
2 1 B+
PR148
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_50V7K
0.01U_0402_25V7K
5
10_0402_5% PC118
100U_25V_M
1
2200P_0402_50V7K
2200P_0402_50V7K
0.01U_0402_25V7K
0.01U_0402_25V7K
2 1 1000P_0402_50V7K VSUMG+
10U_0805_25V6K
10U_0805_25V6K
1
1
+
PC120
PC121
PC122
PC119
PC186
PC185
1
1
PC165
PC124
PC125
PC126
PC127
2 1
2.61K_0402_1%
2
PR149
0.1U_0402_10V7K
0.047U_0402_16V7K
<8> APU_VDDNB_RUN_FB_L
2
PC123 @ 4 PQ46 2 @ @
2
330P_0402_50V7K TPCA8065-H_PPAK56-8-5
11K_0402_1%
<8> APU_VDDNB_SEN
1
PR150 2 1
2
+CPU_CORE_NB 10_0402_5%
PC129
PC130
PR151
2 1 PL19
3
2
1
1
@ PC128 0.36UH_PCMC104T-R36MN1R17_30A_20%
330P_0402_50V7K PH3 1 4
+CPU_CORE_NB
2
D D
PLACE NEAR NB L-MOS 10K_0402_5%_ERTJ0ER103J 2 3
5
2
1
VSUMG- PR160
PQ48 PR214 3.65K_0402_1%
PC131 PR152 PR153 TPCA8057-H_PPAK56-8-5 4.7_1206_5% VSUMG+ 2 1
470P_0402_50V7K 143K_0402_1% 2.26K_0402_1% PH4
1
2 1 2 1 2 1 470K_0402_5%_TSM0B474J4702RE 4 4 PR161
845_0402_1%
1 2
1 2 PC132 PC181 1_0402_1%
680P_0603_50V7K VSUMG-
PR154
0.1U_0603_50V7K 2 1
2
PR158
1
27.4K_0402_1%
3
2
1
3
2
1
2
@PR156
@PR156 2 1 2 1 2 1 1 2 1 2 PQ49
10_0402_5% PR159 TPCA8057-H_PPAK56-8-5
PC134 PR157 PC135 3.83K_0402_1%
100P_0402_50V8J 332_0402_1% 330P_0402_50V7K
2
PROG2 6.65K_0402_1%
2
PR162 PC136
+5VS 2.2_0603_1% 0.22U_0603_50V7K
PR163
2
2 1 2 1
2
CPU_B+
PR164 PC137
BOOT1_NB
1
8.06K_0402_1% 1000P_0402_50V7K
NTC_NB
1
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_50V7K
0.01U_0402_25V7K
1
QC@ PC192
QC@ PC193
QC@ PC194
QC@ PC195
+5VS
1
48
47
46
45
44
43
42
41
40
39
38
37
PU19 QC@ PR227
1 2 0_0603_5%
PROG2
ISEN1_NB
ISEN2_NB
VSEN_NB
RTN_NB
ISUMP_NB
ISUMN_NB
NTC_NB
BOOT1_NB
UG1_NB
PH1_NB
LG1_NB
2
2 1UGATE3-1 4 PQ53 QC@
QC@ PR225 QC@ PR228 QC@ PC197 TPCA8065-H_PPAK56-8-5
1 36 0_0402_5% QC@ PU11 2.2_0603_1% 0.22U_0603_50V7K
FB2_NB PWM2_NB BOOT3
5 1 2 1 2 1
BOOT2 VCC BOOT
2 35
3
2
1
FB_NB BOOT2 UGATE3 QC@ PL26
6 8
UGATE2 FCCM UGATE 0.36UH_PCMC104T-R36MN1R17_30A_20%
DC@ PR166
2 0_0603_5%
3 34
COMP_NB UG2
1
+3VS PHASE3
0_0603_5%
2 7 1 4
1U_0603_10V6K
PHASE2 PWM PHASE +CPU_CORE
PR167
C 4 33 C
VW_NB PH2 LGATE3 ISEN3 ISEN1
QC@ PC191
3 4 2 1 2 3 1 2
GND LGATE
1
5 32 LGATE2 QC@ PR229
PGOOD_NB LG2
1
PR172 0_0402_5% PR232 10K_0402_1% QC@ PR233
QC@ PR223
0_0603_5%
9
2
PGND
<8> APU_SVD 2 1 SDA 6 31 4.7_1206_5% QC@ PR234 10K_0402_1%
2
SVD VCCP
1
PR171 PR173 0_0402_5% ISL6267HRZ-T_QFN48_6X6 ISL6208ACRZ-T_QFN8_3X3 3.65K_0402_1%

100K_0402_5%
<25> APU_PWRGD_L 2 1 ALERT# 7 30 PWM3 VSUM+ 2 1 1 2 ISEN2
1 2
PR174 0_0402_5% PWROK PWM3
4
2
2 1 SCLK 8 29 LGATE1 PC196 QC@ PR235
1U_0603_10V6K
<8> APU_SVC SVC LG1
1
PR204 680P_0603_50V7K QC@ PR231 10K_0402_1%
2
100K_0402_5% PHASE1 QC@ PQ57 1_0402_1%
PC144
<36> VR_ON 9 28
2
ENABLE PH1 TPCA8057-H_PPAK56-8-5 VSUM- 2 1
3
2
1
10 27 UGATE1
<36> VGATE PGOOD UG1
11 26 BOOT1 CPU_B+
<8,25,36> EC_THERM# PROC_HOT BOOT1
PR177 3.83K_0402_1% PR178 27.4K_0402_1%
ISEN3/FB2
2 1 2 1 12 25 1 2
NTC PROG1
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_50V7K
ISUMN
0.01U_0402_25V7K
ISUMP
COMP
ISEN2
ISEN1
VSEN
PR179
VDD
RTN
5
VIN
VW
6.65K_0402_1%
FB
TP
2 1
1
PC139
PC140
PC141
PC142
PLACE NEAR Phase1 L-MOS
13
14
15
16
17
18
19
20
21
22
23
24
49
PH5 470K_0402_5%_TSM0B474J4702RE PR221
0_0603_5%
2
CPU_B+ UGATE2 2 1UGATE2-1 4 PQ50 If the layout of each phase to CPU
2 PR180
1 TPCA8065-H_PPAK56-8-5
1U_0603_10V6K
is symmetric, the two res. can be

1
0_0603_5%
1
2 1 +5VS removed.
PR181 PC145 PR182 They are used for phase current
3
2
1
8.06K_0402_1% 1000P_0402_50V7K PC146 1_0603_5% PL20
0.22U_0603_25V7K
2
balance adjustment.
1
33P_0402_50V8J 0.36UH_PCMC104T-R36MN1R17_30A_20%
2
PHASE2
PC148
1 2 1 4
2
PR170 PC143 ISEN2 2 PR168 1 2 3 1 2 ISEN1
1
2.2_0603_1% 0.22U_0603_50V7K 10K_0402_1%
PC147
BOOT2 2 1 2 1 PR215 PR169

ISEN3 4.7_1206_5% PR175 10K_0402_1%
@ PR183 VSUM+ 3.65K_0402_1%
B B
10_0402_5% DC@PC149
DC@PC149 PR184 PC150 VSUM+ 2 1 1 2 ISEN3
1 2
1
2 1 2 1 2 1 2 1 ISEN2 LGATE2 4
PR185 PC179 PR236 QC@
68P_0402_50V8J 332_0402_1% 330P_0402_50V7K 2.61K_0402_1% 680P_0603_50V7K PR176 10K_0402_1%
0.22U_0402_10V6K
0.01U_0402_16V7K
ISEN1 1_0402_1%
11K_0402_1%
2
1
PC155 PR186 PR187 PQ52 VSUM- 2

PC198
1
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
3
2
1
TPCA8057-H_PPAK56-8-5
PC158
PC159
PR188
2 1 2 1 2 1
1
QC@ PC149 470P_0402_50V7K 143K_0402_1% 2.26K_0402_1%

DC@ PH6 CPU_B+
2
2
QC@
PC156
PC157
DC@PR189
DC@PR189 10K_0402_5%_ERTJ0ER103J
PR193 VSUM- 976_0402_1%
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_50V7K
0.01U_0402_25V7K
2
10_0402_5% 2 1 VSUM-
150P_0402_50V8J +CPU_CORE 2 1
1
1
PC151
PC152
PC153
PC154
5
2 1 PC162
PLACE NEAR Phase1 choke 0.1U_0603_50V7K
2
2
@ PC161
<8> APU_VDD_SEN
1
330P_0402_50V7K QC@ PR189 QC@ PC159 PR220

PC163 @ 0_0603_5%
<8> APU_VDD_RUN_FB_L
330P_0402_50V7K UGATE1 2 1UGATE1-1 4
2
2 1 PQ54
PR196 TPCA8065-H_PPAK56-8-5
10_0402_5% PC164
2 1 1000P_0402_50V7K 715_0402_1% 0.1U_0402_10V7K PL21
3
2
1
0.36UH_PCMC104T-R36MN1R17_30A_20%
PHASE1 1 4
PR192 PC160 ISEN1 2 PR190 1 2 3 1 2 ISEN2
5
2.2_0603_1% 0.22U_0603_50V7K 10K_0402_1%
1
BOOT1 2 1 2 1 PR216 PR191
4.7_1206_5% PR194 10K_0402_1%
3.65K_0402_1%
VSUM+ 2 1 1 2 ISEN3
LGATE1 4
1 2
A PC180 PR237 QC@ A
PQ56 680P_0603_50V7K PR195 10K_0402_1%
TPCA8057-H_PPAK56-8-5 1_0402_1%
VSUM- 2 1
3
2
1
2
CPU_COREP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
D
1 D
5
C C
10
B B
11
12
13
14
15
A A
16

PIR (PWR)
Custom 1.0
P5WS5 LA-6973P
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List)

EVT Stage DVT Stage PVT Stage Pre MP Stage
20101124 20110124 20110301 20110416
1. C5 Change to D2 type 1. Unpop R997 / R49 for +3VS leakage current. 1. Add functio field. 1.Add C1465 100p for HW Card Reader
2. JDIMM1 Change to SUYIN 2. Unpop R1113 / R1115 / R122 / R123 / Q62 / Q89 for VGA power sequence. 20110309 2.Change C38,C40,C41,C42 from 10p to 33p for ESD
20101125 3. R119 10K change to 22K 1% for VGA power sequence. 1. Re-name to R03 3.Add APU_PWRGD 0 ohm(R615) on APU side for ESD
1. Del R1223 (P.34) 4. Add Q30 for FCH VDDAN_11_CLK leakage current. 2. Un-pop C954 / C955 for MINI2 not used. APU_RST# 0 ohm(R598) on APU side for ESD
D
2. Del R1107 / R1111 / Q58 (P.39) 5. Add R21 / Q91 for ODD Power sequence. 3. Un-pop C1442 for Audio noise issue. 4.Remove HDT connector and releated nets,pins D
3. Del R1179 (P.31) 6. Add L87 for SWR_V12. 20110324 5.Pop COM_MIC ESD diode:D41 for ESD
4. Update Power SCH 7. C18 22U Change to 47U. 1.Update L29(always on),Q13(@) BOM structure. 20110417
5. Add R33 / R34 (P.21) 8. TEST35 change to PU for HDMI Function. 2..Add AMD VRAM table 1.Mask PJ32,C9 for DFX
20101126 20110127 20110310 20110418
1. Update Power SCH 1. Co-lay KB9012 1. R1067 change to PJ33 JUMP. 2.Remove Power Button SW1.
20101129 2. Add C19 / C27 / C28 / C31 for +3VS noise. 2. R793 change to PJ34 JUMP. 20110419
測測
1. Remove EC debug conn. 3. D26 change to SC600000B00 for BOM. 3. R953 change to PJ35 JUMP. 1.Delete H25 for Layout request
2. Add R35 / R36 / C23 for EMI 4. Update Power SCH. 4. R1177 change to PJ36 JUMP. 2.Add Test point of JTAG for request
3. Add R37 / R38 / R39 / R40 / R41 / R42 for Vender req. 20110208 20110313 3.Unpop C29,C30 for only 2 phase sku
4. R1190 / R1200 change to 47 ohm ro Vender req. 1. Pop Q30 and unpop R25 for FCH A12. 1. Add C35 / C36 / C38 / C40 / C41 / C42 for EDS. 4.Change PCB P/N from DA60000NA00 to DAZ0JU00100
20101130 2. C1522 / C1523 change to 33p for TXC test result. 2. Pop C1376 / C1377 220pF for EMI. 5.Change C391,C392,C393 from 1uF to 0 ohm For UMA SKU
1. Add Project ID R43 / R44 / R45 / R46 / R47 / R48 3. Pop R1167 / R1170 / Q90 for ISP function. 3. Pop R1014 22ohm / C1352 22pF for EMI. 6.For BCM WLAN lost issue:
2. Add R50 for MINI Card option 4. R21 change to +5VS. 4. Pop R1055 10ohm / C1352 22pF for EMI. Change C1339 from 4.7uF to 10uF
3. Add C25 / U3 / R51 for SW req. 5. Add R604 for +1.5VS leakage current. 5. Pop R1203 22ohm / C1515 22pF for EMI. Change C1340,C1341 from 0.1uF to 1uF
20101201 20110210 6. Add C43 10uF for EMI. 20110420
1. Del T4 / T5 1. Add C32 / C33 / C34 for EMI req. 7. Unpop Q30 & Pop R25 for FCH Ver.A13 1.Change C1205,C1206 from 22pF to 15pF For RTC issue
2. Add NEC_USB30_PWR_EN FOR SW req. 2. Remove H12. 8. Del R53. 2.Add HDMI Royalty:RO0000003HM
20101202 3. Update power SCH. 9. R1049 / R1185 / R1078 footprint change to 0603 R-SHORT.
1. Del D41. 20110211 10. R1178/ R1184 / R989 / R988 / R995 / R996 / R1108 / R537 / R538
20101203 1. Add T19 / T20 for ICT&ATE test. R1094 / R985 / R591 / R1161 footprint change to 0402 R-SHORT.
1. Change APU HDMI Port to PEG12~PEG15 for AMD req. 20110214 11. Remove MINI2.
20101206 1. Add C1082 / C1085 / C1106 / C1107 for DDR. 12. Modify HPD level shift.
1. Del C1039. 2. Unpop R29 / R31 / R32 / R51 for USB spec change. 20110314
2. Add R52 for Vender req. 3. Unpop JMINI2 function. 1. Add RP8 / RP9 / RP10 / RP11 / R607 for ESD.
C C
3. R1095 / R1096 change to 51.5 0402 for FSOV acer spec. 4. Unpop ENBKL / ENCDD level shifter. 2. SWAP USB30 pin define.
4. Del R469. 5. R119 change to 30K_0402 1% for VGA Power sequence. 3. R1067 / R793 / R953 change to 0805 R-SHORT
5. Add R53 for EMI req. 6. Pop R1033 / C1357 for EMI req. 4. Add U22 for Fn+F5 issue.
20101207 5. Pop L77 and unpop L87 for LVDS flash issue.
1. Update Power SCH. 6. Add R82 for SW debug<USB PORT0>.
2. Update USB30 Conn. 7. C1512 / C1513 connect to +XDPWR_SDPWR_MSPWR.
20101214 20110317
1. Remove R990 / R991 / R1004 / R1005 1. Update Power SCH.
2. Remove R852 20110318
20101216 1. Add T29 .
1. No any change , for gerber release . 2. Add L30 for FCH M2 .
20101221 20110321
1. Modify VGA 16X BOM structure. 1. Add L31 for FCH M2 .
20101225 2. Add Q13 for AMD req.
1. Update Power SCH. 3. Del Q30 for FCH A13.
20101227 20110322
1. MINI2 USB port change to Port 0. 1. Pop D33 / D34 / D4 for ESD.
20101228 2. Pop R730.
1. Del C27 / C28 / C35 / C36 and move to USB30/B. 3. Q13 change to SB00000FG10 AOS3416.
2. Change MINI1 / MINI2 / GIGA LAN CLK ports. 4. Unpop LED8 / R381 (3G@) for 3G.
3. JUSB3 change to Zif Conn. 5. Add FCH M2 A13 Part number SC000042C60.
20110106 6. SA000008J10 change to SB00000EN00.
1. Unpop SW1. 7. Pop R728 for factory req.
20110107 20110323
B 1. Update MB P/N. 1. C995 / C999 / C994 / C993 / C30 / C29 / C1010 / C1009 / C5 B
Change to SGA20331E10 for Power req.

20110324
1.Add AMD 128M*16 VRAM table of Whistler,Seymour
2.Update L29(pop),Q13(@) BOM Structure
20110327
1. Update Power SCH.
WHISTLER-PRO SEYMOUR-XT
ID3-0 Vendor Size Freq P/N Description Qualify ID3-0 Vendor Size Freq P/N Description Qualify
A A
0000 SAM E-die 64*16 800MHz SA000035720 K4W1G1646E-HC12 V 0000 AMD A-die 128*16 900MHz SA00004U500 23EY4187MA11
0001 SAM C-die 128*16 800MHz SA00003MQ60 K4W2G1646C-HC12 V 0001
0010 SAM G-die 64*16 933MHz SA00004GS10 K4W1G1646G-BC11 * 0010 SAM C-die 128*16 933MHz SA000047Q20 K4W2G1646C-HC11
* 0011 SAM C-die 128*16 933MHz SA000047Q20 K4W2G1646C-HC11 0011 SAM G-die 64*16 933MHz SA00004GS10 K4W1G1646G-BC11
0100 0100 SAM E-die 64*16 800MHz SA000035720 K4W1G1646E-HC12 V
0101 0101 SAM C-die 128*16 800MHz SA00003MQ60 K4W2G1646C-HC12 V
0110 0110
0111 0111
1000 HYN Orion-die 64*16 800MHz SA000032420 H5TQ1G63BFR-12C 1000
1001 HYN Vega-die 128*16 800MHz SA00003VS10 H5TQ2G63BFR-12C V 1001
1010 HYN Vega-die 64*16 900MHz SA000041S40 H5TQ1G63DFR-11C V 1010
1011 HYN Vega-die 64*16 800MHz SA0000324G0 H5TQ1G63DFR-12C 1011 HYN Vega-die 64*16 800MHz SA0000324G0 H5TQ1G63DFR-12C Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
* 1100 HYN Vega-die 128*16 900MHz SA00003YO20 H5TQ2G63BFR-11C 1100 HYN Orion-die 64*16 800MHz SA000032420 H5TQ1G63BFR-12C
1101 1101 HYN Vega-die 128*16 800MHz SA00003VS10 H5TQ2G63BFR-12C V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR / SCREW
1110 1110 HYN Vega-die 64*16 900MHz SA000041S40 H5TQ1G63DFR-11C V AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1111 AMD A-die 128*16 900MHz SA00004U500 23EY4187MA11 * 1111 HYN Vega-die 128*16 900MHz SA00003YO20 H5TQ2G63BFR-11C C 1.0
P5WS5 LA-6973P
Date: Thursday, April 21, 2011 Sheet 50 of 50
5 4 3 2 1

49e90 Compal LA-6973P PDF

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

49e90 Compal LA-6973P PDF

Загружено:

Авторское право:

Доступные форматы

A B C D E

P5WS5 Schematics Document

Security Classification Compal Secret Data Compal Electronics, Inc.

Compal Confidential PCB 46@

-USB20 x1+ USB30 x1 Block Diagrams

CLOCK DISTRIBUTION DISPLAY DISTRIBUTION

RTD2132 DP0_TXP/N[0:1]_R VGA_TXOUT[1:2]+/-

CPU FS1 SOCKET

LVDS Transtator 32.768KHz 25MHz

CRT CONN HDMI CONN

Security Classification Compal Secret Data

+CPU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF

+VSB VSB always on power rail ON ON ON*

Device Address HEX Device Address HEX

AMD APU FS1

LCD panel +5VS FCH AMD Hudson M2/M3

+5VS VDDAN_11_USB_S: 140 mA

Security Classification Compal Secret Data

<13> PCIE_GTX_C_FRX_P[0..15] PCIE_FTX_C_GRX_P[0..15] <13> APU To HDMI

PCI EXPRESS PCIE_FTX_GRX_N[12..15] <23>

AC5 AD4 PCIE_FTX_DRX_P0 C950 1 2 0.1U_0402_16V7K

<33> PCIE_DTX_C_FRX_N1 AC9 AC3 PCIE_FTX_C_DRX_N1 <33>

AE6 AF5 UMI_FTX_MRX_P1 C958 1 2 0.1U_0402_16V7K

Security Classification Compal Secret Data Compal Electronics, Inc.

JCPU1B CONN@ JCPU1C CONN@

EVENT# pull high 0.75V reference voltage +1.5V

R545 1 2 1K_0402_5% MEM_MB_EVENT# +MEM_VREF

DISPLAY PORT MISC.

R791 1 ALERT_L RSVD_2 M_TEST

Power Name Consumption

1 1 1 1 1 1 1 2 22uF x 9 22uF x 6 680uF x 1 100uF x 4 10uF x 1 0.22uF x 2 0.22uF x 4

4 2 2 2 2 2 2 2 1 180uF x 2 180uF x 3 22uF x 3 180pF x 4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

HPD +5VS +1.5VS

Security Classification Compal Secret Data

+VREF_DQ +1.5V +1.5V

Security Classification Compal Secret Data Compal Electronics, Inc.

+VREF_DQ +1.5V +1.5V

+0.75VS +1.5V +1.5V

Security Classification Compal Secret Data Compal Electronics, Inc.

PCI EXPRESS INTERFACE

PCIE_FTX_C_GRX_P5 PCIE_GTX_FRX_P5 C224 1

VGA_RST# AA30 PERSTB

Security Classification Compal Secret Data Compal Electronics, Inc.

AH17 AE38 VGA_CRT_B R425 1 DISO@ 2 150_0402_1%

@ AMD ref:470ohm/1A VGA@

R445 1M_0402_5% AMD ref:470ohm/1A XO_IN AW34

Security Classification Compal Secret Data Compal Electronics, Inc.

MDA18 C26 C32 DQMA#1 MDB18 N4 H1 DQMB#1

MVREFDA MDA23 NC_DQA0_22/DQA_22 NC_WCKA1B_0/DQMA_5 DQMA#6 MDB23 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 DQMB#6

1 MDA25 A22 QSA[0..7] MDB25 V6 QSB[0..7]

R448 VGA@ MDA26 F22 C34 QSA0 MDB26 V1 F6 QSB0

MDA30 NC_DQA0_29/DQA_29 NC_EDCA0_3/QSA_3/RDQSA_3 QSA4 VGA@ MDB30 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 QSB4

MDA39 E14 C16 QSA#4 MDB39 AD5 AC4 QSB#4

MVREFSA MDA44 NC_DQA1_11/DQA_43 ODTA0 MDB44 DQB1_11/DQB_43 ODTB0

1 MDA46 A10 MDB46 AJ4

R452 VGA@ MDA47 C10 H27 CLKA0 1 MDB47 AK3 L9 CLKB0

MDA51 NC_DQA1_18/DQA_50 NC_CLKA1 CLKA1# 2 MDB51 DQB1_18/DQB_50 CLKB1 CLKB1#

R460 243_0402_1% TEST_YCLK AL10 AH11 1 2 1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

VDDC#56 Y23 (GDDR3/DDR3 1.12V@4A VDDCI)

VGA@ VGA@ VGA@ AC12 1 1 1 1 1 1 1 1 1 1 L19 Seymour/Whistler

Security Classification Compal Secret Data Compal Electronics, Inc.