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SIM U L AT I O N O P T I O N
Oscillator
• Support for all oscillator types (LC, ring,
high Q crystal)
• Output frequency, output power,
Figure 3: Inductor synthesis, verification, and modeling with the built-in Virtuoso Passive Component Modeler phase noise, and jitter measurement
• Frequency pushing and frequency
pulling effect
Passive Component Design and • Compiled-model interface (CMI) allows
Analysis for rapid inclusion of user-defined mod- • Tuning sensitivity and linearity
els for a “model once, use everywhere” • Sensitivity of the output frequency and
The Virtuoso Passive Component Modeler
capability phase noise to the noise from the power
is a built-in feature in Virtuoso Spectre RF
• Behavioral modeling capabilities in full supply and ground rails
for the synthesis, electromagnetic analysis,
and modeling of spiral inductors and compliance with Verilog®-A 2.0
transformers. Receiver and Transmitter
Chains
• Synthesis of spiral inductors, transformers,
APPLICATIONS
• I/Q amplitude and phase imbalance
and BALUNs, producing a complete PDK
Virtuoso Spectre RF provides fast and
component with symbol, schematic, • Leakage and feedthrough
accurate RF analysis that covers the full line
layout, and simulation model • Constellation diagrams
of RF applications, from RF to microwave
• Accurate passive component verification and from blocks to complete systems. • Error vector magnitude (EVM)
and coupling analysis based on full- • Bit error rate (BER) and eye diagrams
wave and quasi-static electromagnetic
Amplifier
solvers Phased-Locked Loops
• Generation of inductor and transformer • Small signal measurements (gain,
• Jitter analysis and modeling of critical
equivalent circuits from simulated and S-Parameter, stability factor)
PLL blocks used in frequency synthesiz-
measured S-Parameter data • Inter-modulation and total harmonic ers/clocks and data recovery circuits
distortion such as voltage-controlled oscillators,
Multi-Mode Simulation • Compression point, intercept point, and high-Q reference oscillators, phase
Shared Technology distortion summary detectors, charge pumps, filters, and
• Noise figure and noise summary dividers
• Superior design use model via tight inte-
gration with the Virtuoso Analog Design • Power dissipation and efficiency • Jitter analysis of the complete PLL in
Environment measurements closed loop using transistor-calibrated
behavioral models
• Shared syntax, device models, and equa- • Large-signal S-Parameter supported
tions with other multi-mode simulators by the LSSP wizard
(Virtuoso Spectre Circuit Simulator, • Load-pull measurements
Virtuoso UltraSim Full-chip Simulator • Envelope following analysis for digital
(FastSPICE), and Virtuoso AMS Designer modulation
Simulator (mixed-signal)
• Adjacent channel power ratio (ACPR)
measurement supported by the ACPR
wizard
Platform/OS
• Sun/Solaris (32-bit, 64-bit)
• HP-UX (32-bit, 64-bit)
• IBM (32-bit, 64-bit)
• Linux (32-bit, 64-bit)
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trademarks and the Cadence logo is a registered trademark of Cadence Design Systems, Inc. All others are properties of
their respective holders.