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INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS

Int. J. Numer. Model. 2014; 27:846–862


Published online 7 March 2014 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/jnm.1988

Gate leakage currents model for FinFETs implemented in Verilog-A


for electronic circuits design

Salvador I. Garduño1,*,†, Joaquín Alvarado1, Antonio Cerdeira2, Magali Estrada2,


Valeriya Kilchytska3 and Denis Flandre3
1
Research Center of Semiconductor Devices, BUAP, Av. San Claudio y 14 Sur, 72570 Puebla, Mexico
2
Department of Electrical Engineering, CINVESTAV, Av. IPN No. 2508, A.P. 14-740, 07300 Mexico, Mexico
3
ICTEAM Institute, Université catholique de Louvain (UCL), Place du Levant 3, B-1348 Louvain-la-Neuve, Belgium

ABSTRACT

Because different conduction mechanisms can dominate the gate and drain/source leakage currents, mainly
depending on the insulating materials used as gate dielectric, the dimensions of the gate structure, and the transistor
operation regime, we proposed an improved analytical model to describe the behavior of these currents in silicon
on insulator fin-shaped field-effect transistor devices by taking into account changes in the aforementioned factors.
This model considers the direct tunneling, trap-assisted tunneling, and band-to-band tunneling as the
predominating mechanisms for leakage currents associated with the gate structure. These specific features make
the model valid for a wide operation range and include its impact on the drain leakage current. The implementation
of this model in Verilog-A code is presented in this work, which allows calculating quickly and accurately the
scaling constraint of a specific gate dielectric material and the power consumption that yields such leakage currents in
a circuit by using commercial simulators. All presented results are validated with experimental data from fin-shaped
field-effect transistors with different dimensions and gate dielectric materials and performed under different bias
conditions. Copyright © 2014 John Wiley & Sons, Ltd.

Received 27 August 2013; Revised 11 January 2014; Accepted 16 January 2014

KEY WORDS: FinFET; gate leakage current modeling; direct tunneling; trap-assisted tunneling; gate-induced drain
leakage; double-gate MOSFETs model; Verilog-AMS; analog circuit design

1. INTRODUCTION
The introduction of multiple-gates fully depleted structures based on silicon on insulator (SOI) technology
has become a very important alternative in order to solve some challenges for the next generations of
metal–oxide–semiconductor (MOS) field-effect transistors (FETs) [1], and special attention is currently
focused on their suitability for very high-frequency applications [2]. This is due to the important reduction
of short-channel effects related to a more efficient electrostatic control of the device, required for
MOSFET scaling [3, 4].
On the other hand, the continuous implementation of gate insulating materials with higher dielectric
constant (high-κ) than silicon oxide (SiO2) has given an alternative to offset the significant rise of direct
tunneling current, according to the reduction of the oxide layer thickness to less than 2 nm, which is a
scaling constraint factor with regard to the use of a specific gate dielectric material and the power
consumption of complementary MOS-integrated circuits [5–7]. Among the disadvantages of high-κ
materials, these may present high trap states density at the interface with Si and at intermediate dielectric
interfaces (in the case of two or more stacked insulating layers) and within themselves, which can
considerably increase the leakage current at low gate biases [8]. Moreover, the current due to gate-induced

*Correspondence to: Salvador I. Garduño, Research Center of Semiconductor Devices, BUAP, Av. San Claudio y 14 Sur, 72570,
Puebla, Mexico.

E-mail: garduno.sivan@gmail.com

Copyright © 2014 John Wiley & Sons, Ltd.


GATE LEAKAGE CURRENTS MODEL IMPLEMENTED IN VERILOG-A 847

drain leakage (GIDL) effect is another important issue [9–11]. This is because its magnitude
contributes to the subthreshold leakage current, strongly impacting on drain current (ID) and, thereby,
on the transistor performance.
Although the study of SOI fin-shaped FET (FinFET) devices has been directed to the development
of digital applications [2], and these transistors were successfully implemented on Intel’s processor
based on 22-nm technology node [12]. Nevertheless, because of its three-dimensional structural nature,
FinFETs show high parasitic capacitances and resistances that degrade its analog performance. As a
consequence, nowadays, SOI FinFET devices are far away to fulfill the International Technology
Roadmap Semiconductors goals, and some guidelines have been provided in the literature [13, 14]
in order to overcome such constraints and properly model the behavior of these transistors in the
high-frequency domain by considering intrinsic/extrinsic capacitances and also gate resistance,
although these contributions do not take into account the effect that gate leakage currents can induce
on the gate parasitic capacitances and, at the same time, in the cutoff frequency.
Therefore, the study of leakage currents associated to the gate structure becomes very important for
accurate modeling of MOSFETs, design criteria establishing of very-large-scale integration circuits,
and high-frequency applications of SOI FinFET technology [13–16].
We presented a compact analytical model for symmetric doped double-gate MOSFETs (SDDGM)
[17, 18]. This model is based on potentials calculation through the potential difference between the
center and surface of the Si body film and considers field-dependent mobility and short-channel effects.
These features make it valid in a wide range of doping concentration (from 1 × 1014 to 2 × 1018 cm3),
Si body thickness (from 15 to 50 nm), and effective oxide thickness (from 1.5 to 5 nm), providing an
excellent agreement with experimental and simulated current–voltage (I–V) characteristics. Furthermore,
the implementation in Verilog-A of SDDGM was presented in [19].
Moreover, an improved gate leakage currents model was included in the SDDGM model [20],
which takes into account three main tunneling mechanisms that dominate the leakage currents
associated with the gate structure, the most important gate dielectric material parameters, and the
applied biases to the MOSFET. This model represents the behavior of the gate leakage current (IG)
and also its contribution to ID in SOI FinFETs either with single dielectric layer or stacked layers as
gate insulator, by the impact of each predominant IG component on the total ID and the contribution
of GIDL current (IGIDL) to the off-state leakage current (Ioff).
In this work, we implement the gate leakage currents model for SOI FinFETs in Verilog-A, as a
complement to the respective code of the SDDGM model presented in [19]. In this way, it is possible
to introduce a more accurate model in commercial circuit simulators and provide a useful tool for
electronic circuit design and high-frequency modeling. The implementation in Verilog-A is validated
by measured data on SOI FinFETs with different dimensions and gate dielectric materials and
performed under different bias conditions.

2. GATE LEAKAGE CURRENTS MODEL


The gate leakage currents model for SOI FinFETs was presented in [20]. Thus, the IG component
consists of two parts: the current due to direct tunneling (DT) of carriers from the channel region at
surface inversion conditions (IGDT) and the current that takes place in the overlap regions between drain
or source electrodes and the gate. These overlap currents can be produced by different conduction
mechanisms, depending on the gate dielectric material, the insulator thickness, whether there are
stacked layers of different materials or not, and, of course, the quality of the dielectric material and
its interfaces. Thus, the direct tunneling effect or trap-assisted tunneling (TAT) can be predominant
in subthreshold regime.

2.1. Direct tunneling current


In [20] was presented an improved gate current analytical model that considers the dependence on the
applied drain (or source) voltage, the free available charge in the Si film, and the physically based
parameters of the insulating material, that is, the tunneling barrier height (ϕ b), the electrons mass used

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
848 S. I. GARDUÑO ET AL.

for tunneling process (mi), the gate dielectric permittivity (εi), and its physical thickness (ti). Thereby,
an expression for gate current density due to electrons tunneling directly from Si conduction band
through the gate dielectric material was established as follows:
8 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi " 9
<  3 #
q3 8π 2mi ϕ b 3 qt i F im 2 =
J GDT ¼ EC exp  1 1 ; (1)
8πhϕ b εi : 3qhF im ϕb ;

where q is the electron charge and h is the Planck’s constant. The average electric field across the gate
dielectric material (Fim) is calculated using our previously developed SDDGM model [17, 18]:
ϕt
F im ¼ ðq þ qd þ qb Þ; (2)
2t i s
where ϕ t = kT/q corresponds to the thermal voltage, T to the temperature, and k to the Boltzmann
constant. All charges qs,d,b for Fim calculation are normalized to ϕ tCi; therefore, qs and qd are the
normalized mobile charge concentrations at source and drain, respectively, expressed as functions of
gate and drain bias [18], and qb is the total normalized depletion charge in the Si body film:
qN b t Si
qb ¼ ; (3)
ϕt Ci
where Nb is the doping concentration, tSi is the Si layer thickness, and Ci is the gate insulator capacitance.
By considering the dependence of the gate current on drain voltage (VD) through the free charge and
the applied potential to the Si surface, the empirical correction function is expressed as follows [20]:
ϕ t C i qg  
EC ¼ V G  V FBc  V def ; (4)
ti
where VG is the applied gate voltage, VFBc is the flat band voltage corresponding to the channel region,
and Vdef is defined as the effective drain voltage applied to the channel at the saturation point [18].
Finally, the normalized free charge in the Si film (qg), which corresponds to the area under control
of the gate along the device channel, is expressed as follows [21]:
2q 3 q 3  3
qs þqb
s d
þ ð q s
2
 q d
2
Þ  q ð
b sq  qd Þ þ q b
2
ln q þq
qg ¼ 24  d b 5:
3
 (5)
qs 2 qd 2 qs þqb
2 þ 2ðqs  qd Þ  qb ln q þq
d b

This model allows us to avoid fitting parameters and to consider short-channel effects for JGDT
calculation as channel length modulation, and it is valid at strong inversion operation mode, either
in linear or saturation VD bias conditions.
When the applied VG is reduced until it is no longer enough to provide the strong inversion
condition in the Si surface, the IGDT decreases faster because the direct tunneling is limited by the
number of free electrons, which exponentially depends on the surface potential.

2.2. Trap-assisted tunneling current


If length at the gate overlap regions can be comparable with the transistor channel length, the overlap
current components provide an important contribution to the gate current. In our previous work, we
confirmed that tunneling assisted by dielectric’s trap states, corresponding to the gate overlap regions,
is predominant at subthreshold conditions [20]. Fleischer et al. proposed a simplified model to describe
the TAT mechanism in two stages [22]: the carrier is injected from the interface to the trap state within
the gate insulator; later, the trapped carrier tunnels to the dielectric conduction energy band. Current
density due to TAT conduction mechanism can be calculated as follows:
0 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1
4qATAT N t ϕ it 8π 2qmi ϕ it 3
J GTAT ¼ @
exp  A; (6)
3F iOv 3hF iOv

where Nt is the trap states density and ϕ it is the trap energy; ATAT is a function of electrons energy, and
it is given by the following [22]:

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
GATE LEAKAGE CURRENTS MODEL IMPLEMENTED IN VERILOG-A 849

2 qffiffiffiffiffiffiffiffi 3
 5=2 16π ϕ e 3
mG 4 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi5;
ATAT ¼ (7)
mi 3h ϕ it  ϕ e

where mG is the electron effective mass in the gate electrode, for example, in metal gate mG is the free
electron mass. The total energy of electrons (ϕ e) has an effective value equal to 0.2 eV, according to [22].
The electric field across the dielectric at the overlap regions (FiOv) was proposed depending on the
interface from which the charge carries are injected. For carriers tunneling from Si to the gate electrode,
through the trap states, the electric field can be approached by the following [20]:

V G þ V FBo  αp V S=D
F iOv ¼ ; (8)
ti
where VFBo is the flat band voltage corresponding to MOS structure of the overlap regions (metal-insulator
highly doped Si of the n+–drain and source regions), VS/D is the applied source or drain voltage, and αp is a
proportionality constant related to different factors, for example, the impurities gradient in the p–n
junctions of source or drain or the negative trapped charge at the gate edges, induced by damage during
the manufacturing process [23].
For TAT mechanism from the gate electrode to Si, the electric field can be estimated as follows [20]:

αn V S=D  V G
F iOv ¼ ; (9)
ti
where αn is a fitting parameter whose function is similar to αp. In this case, αn is used for the inverse
path of the TAT process.

2.3. Gate-induced drain leakage current


Gate-induced drain leakage is another important effect that produces a leakage current associated to the
gate structure when transistors are operating at subthreshold conditions [9–11, 20]. As the potential
difference between gate and drain increases in the transistor, near the interface of the n+–drain
overlapped region, the presence of an intense electric field bends enough the energy bands to allow
the electrons tunneling from the valence energy band towards the conduction band. By taking into
account the Wentzel–Kramers–Brillouin approximation for tunneling probability calculation, assuming
that Si is a direct band gap semiconductor and also that the electric field in the drain region underneath
the gate is uniform, the current density for band-to-band tunneling (BBT) conduction mechanism is
expressed as follows [11]:
 
BBBT
J GIDL ¼ 2ABBT F sOv exp  ; (10)
F sOv
where factor ABBT is a pre-exponential parameter and BBBT depends on the effective mass of tunneling
electrons in the n+–Si drain region (meSi) as follows [11]:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
π meSi E g 3
BBBT ¼ : (11)
2qh
Although parameter BBBT is physically based, it has also been used in other works as an empirical one
in order to fit modeled characteristics to measured data [9, 11], because GIDL current depends on the
electric field in the overlapped drain region [20]. Finally, transverse electric field at the Si surface (FsOv)
is expressed as follows [11]:

εi Eg
F sOv ¼ V DG  ; (12)
t i εSi q
where VDG = VD  VG. A band bending of band gap (Eg) is the minimum necessary for BBT process,
and εSi is the Si permittivity.

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
850 S. I. GARDUÑO ET AL.

3. EXPERIMENTAL PART
Experimental drain and gate currents characteristics were measured as a function of VG, in linear and
saturation VD regimes, at room temperature conditions, for two sets of n-channel SOI FinFET devices.
For both transistor groups, channel region is left undoped (with background doping level of
~1015 cm3), and the n+–drain/source regions had a doping level of about ~1020 cm3. Moreover,
the devices had a standard gate-overlapped structure. Details of fabrication processes are described
in [24, 25].
In the first group of SOI FinFETs, the Si body of each transistor has a fin height (HFin) of 60 nm and
a fin width (WFin) of 30 nm, and different gate lengths (LG) are analyzed. Each measured transistor
consist of 50 Si fins × 9 gate fingers. For this set, its MOS structure features a metal gate electrode with
a work function close to Si mid-gap and a Si―O―N film as gate insulator with equivalent oxide
thickness of ~1.6 nm. Therefore, the calculated flat band voltage for the channel region (VFBp) is around
0.43 V, and the corresponding average threshold voltage (VT) is ~0.3 V; for the overlap regions at the
n+–drain/source electrodes, flat band voltage (VFBn) is equal to 0.45 V.
In the second group, each device has a Si body film with HFin = 65 nm and WFin = 20 nm, and
different LG are considered. Only one Si fin constitutes each measured transistor. Its MOS structure
has a metal gate electrode with a work function close to Si mid-gap and a gate stack of HfSixOy/
SiO2, which equivalent oxide thickness is ~1.5 nm. Therefore, the calculated VFBp is around
0.23 V, and the corresponding VT is ~0.5 V; for the overlap regions at the n+–drain/source electrodes,
VFBn is equal to 0.65 V.
The total gate width (WT) was calculated as (2HFin + WFin) × nFin, where nFin is the total number of
fins. The corresponding effective length is Leff = LG  2LOv. In the DG model, the effective channel
width is equal to WT/2; therefore, the leakage currents were calculated as I = (WT/2) × L × J, where L
is Leff for the current in the channel area, or LOv, for currents in the gate overlap regions.

4. GATE LEAKAGE CURRENTS MODEL IMPLEMENTED IN VERILOG-A


Implementation of the gate leakage currents model for circuits design was performed in Verilog-A lan-
guage because it is a very useful tool to introduce a device’s behavioral descriptions in commercial pro-
grams for circuital simulations. The descriptive code of the model was introduced in SmartSpice in
order to compare the results obtained from simulations with the aforementioned experimental drain
and gate measured current characteristics. The Verilog-A code of gate leakage currents model is listed
in Appendix A.
Through SDDGM model validation by comparing the obtained results with experimental measured
data and simulations of triple-gate fully depleted SOI FinFETs [17–19], the devices under study are
analyzed as double-gate structures; this is showed in Figure 1.
The first component of IG corresponds to the DT mechanism from channel region at surface
inversion conditions. Under the aforementioned conditions, Figure 2 shows the excellent agreement
achieved between experimental data and simulated results of IGDT calculation (lines 73–82), for all
analyzed FinFETs either at linear or saturation VD bias conditions. It is very important to notice that
potentials and charge magnitudes (lines 73, 75, and 80) for IGDT are calculated through our previously

Figure 1. Scheme of the analyzed double-gate metal–oxide–semiconductor field-effect transistor structure.

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
GATE LEAKAGE CURRENTS MODEL IMPLEMENTED IN VERILOG-A 851

Figure 2. Comparison of experimental gate current–voltage measurements (symbols) at (a) VD = 0.02 V and (b)
VD = 1.1 V for silicon on insulator (SOI) fin-shaped field-effect transistor (FinFET) with LG = 500 nm and single
Si―O―N gate layer and simulation in Verilog-A of different tunneling effects (solid and dashed lines). Moreover,
experimental data (symbols) for SOI FinFET with LG = 5 μm and HfSixOy/SiO2 gate stack at (c) VD = 0.02 V and
(d) VD = 1.1 V, compared with simulation results obtained in Verilog-A for different tunneling effects (solid and
dashed lines). Modeling parameters for both devices are listed in Tables I and II.

developed SDDGM model. Therefore, variables, parameters, expressions, and details about implementation
of SDDGM model in Verilog-A for circuit simulation are described in [19].
Second component of IG takes place at subthreshold conditions, where TAT mechanism in the
overlap regions or DT assisted by generation process (at the p–n junction between the fully depleted
Si body layer and the n+–Si drain region) can be predominant, depending mainly on the gate dielectric
material. In this way, we observed TAT predominance throughout the subthreshold regime in FinFETs
with single-gate Si―O―N layer [20], as showed in Figure 2(a and b). Calculation of IGTAT is included
from line 83 to 125 in Appendix A; by considering for TAT mechanism, the electrons injection process
either from the semiconductor to the gate electrode or vice versa. Moreover, constraints for electric
field in the overlap regions (lines 85, 90, 107, and 112) are taken into account in order to limit the
contribution of IGTAT to IG at different operation conditions. Table I summarizes the average parameters
that were used in IG and IGIDL calculation for the devices of the first group with Si―O―N.
Because of the potential barrier conditions that represents the HfSixOy/SiO2 gate stack, for the
second group of FinFETs, we observed that IG due to TAT effect only is present when electrons
injection is from n+–Si drain/source overlapped regions to the gate electrode at subthreshold conditions
[20]; this is shown in Figure 2(c and d). On the other hand, as the difference between VD and VG
increases, the inverse bias of the p–n junction enables a hole–electron pairs generation process that
enhances the free charge. This allows the direct tunneling of electrons from gate electrode to the Si
valence band, which increases IG as VG decreases [20]. In this case, leakage current due to DT assisted
by generation process under reverse bias of p–n junction (IGgen) is implemented from line 126 to 132.
Both IGgen and IGDT are caused by DT effect, so that the current density in both cases can be expressed

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
852 S. I. GARDUÑO ET AL.

Table I. Direct tunneling (DT), trap-assisted tunneling (TAT), and gate-induced drain leakage (GIDL) parameters
for total gate leakage current simulation corresponding to fin-shaped field-effect transistor with Si―O―N as gate
insulator.
TAT parameters TAT parameters
DT parameters (from n+–Si to metal gate) (from metal gate to n+–Si) GIDL parameters
Gate
length ϕb ϕ it Nt × 109 ϕ it Nt × 108 ABBT
(nm) ki (eV) mi/m0 (eV) (cm3) αp (eV) (cm3) αn (A/V.cm) meSi/m0
500 5.7 2.4 0.3 0.45 ± 0.1 6.7 ± 2.1 0.15 0.36 ± 0.1 6.0 ± 3.0 0.15 2.5 × 106 0.35
60 0.15 0.15 8.5 × 105

through Equation (1). However, the proposed approach of the voltage drop across the gate dielectric
material (line 126) and the free charge in the Si body film (line 128) for IGgen calculation are different
from those expressed for IGDT (lines 73 and 76, respectively), because of the difference between the
operation conditions under which these currents are present and the different origin of the free charge.
Thereby, considering that the Si body film is fully depleted and assuming that the Shockley–Read–Hall
generation velocity reaches the maximum in the entire space-charge region of the p–n junction, the
charge density of the generated free carriers in the Si body film (Qgen) is expressed as follows:
 

qt Si ni VD  VG
Qgen ¼ exp 1 ; (13)
2τ g ϕ t PU
where ni is the intrinsic carrier concentration, τ g is the carrier lifetime (by assuming that electrons and
holes capture cross-sections are equal), and parameter PU is used to fit the slope of modeled IG–VG
characteristic with measured data.
Figure 2(c and d) shows the contribution of IGgen to IG on FinFETs with HfSixOy/SiO2 gate stack,
where this current is larger as the difference between VD and VG increases. Table II summarizes the
average parameters that were used in IG and IGIDL calculation for devices of the second group.
As can be seen in Figure 3, an excellent agreement between Verilog-A simulation results and
measured IG–VG characteristics of the analyzed FinFETs is achieved from subthreshold to strong
inversion, where DT and TAT conduction mechanisms were added together, either in linear or saturation
VD regimes.
Finally, IGIDL calculation is included from lines 133 to 141 of the Verilog-A code, this is in order to
complete the implementation of gate leakage currents model and to show the importance of suitably
modeling the leakage currents associated with the gate structure, by applying it to circuits design.
By considering BBT mechanism and the aforementioned approaches, we have introduced a constraint
condition for the transverse electric field at the Si surface (from lines 135 to 139) in order to delimit the
contribution of IGIDL to ID inside the operation conditions where BBT is the dominant conduction
mechanism.
Verilog-A code of the SDDGM model [19] was introduced in SmartSpice and used to simulate the
corresponding channel current of the devices under analysis. It is observed in Figure 4 that IG does not
influence ID above the threshold voltage; this is because the magnitude of IG is lower in comparison with
ID, either in linear VD regime or in saturation. We assume that IG does not contribute to ID at VD = 20 mV
and less than VG = 0.2 V because the applied VD bias is not sufficiently high to drift the carriers that leave

Table II. Direct tunneling (DT), trap-assisted tunneling (TAT), and gate-induced drain leakage (GIDL) parameters
for total gate leakage current simulation, corresponding to fin-shaped field-effect transistors with HfSixOy/SiO2
gate stack.
TAT parameters DT parameters
DT parameters (from n+–Si to metal gate) (from metal gate to n+–Si) GIDL parameters
Gate
length ϕb ϕ it Nt × 109 ϕb τg ABBT
(nm) ki (eV) mi/m0 (eV) (cm3) αp (eV) mi/m0 (μs) PU (A/V.cm) meSi/m0
5000 6.4 1.42 0.26 0.43 ± 0.03 23 ± 6 0.26 ± 0.05 2.0 0.24 22.5 12 1.5 × 104 0.065
60 2.6 19 8.5 × 105

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
GATE LEAKAGE CURRENTS MODEL IMPLEMENTED IN VERILOG-A 853

Figure 3. Agreement obtained between measured (open symbols) and total modeled IG (solid lines and dashed
lines) for fin-shaped field-effect transistors (FinFETs) with (a) LG = 500 nm, (b) LG = 60 nm, (c) LG = 5 μm, and
(d) LG = 60 nm; in both linear and saturation VD conditions, corresponding to the first group (above) and the second
group (below).

Figure 4. Measured (symbols) and modeled (solid and dash lines) drain transfer characteristics at linear and
saturation VD bias conditions, appropriately including IGTAT provided by the gate-to-drain overlap zone and
IGIDL, for silicon on insulator fin-shaped field-effect transistor (FinFET) with Si―O―N and LG = 500 nm. Drain
current was simulated by using the symmetric doped double-gate MOSFET model code in Verilog-A [15].

the overlap zone towards the drain electrode, although the electric field in the overlap drain region is high
enough to produce the IGTAT. In the particular case of saturation VD bias conditions, it is remarkable the
agreement obtained between measured and simulated transfer characteristics, by taking into account the

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
854 S. I. GARDUÑO ET AL.

contribution of current due to TAT effect that is provided by the overlap region between gate and drain
(IGDTAT), together with IGIDL due to the BBT effect.
As can be seen in Figure 5(a) at VD = 20 mV, for the FinFET with LG = 5 μm of the second set of
devices, there is an important influence on ID due to the rise of IG, where about half of the current
through DT has higher contribution within the strong inversion towards moderate regime because of
the dimensions of its gate structure. Additionally, at subthreshold conditions, only IGDTAT and IGgen
contribute to the Ioff that was measured on this transistor, that is, IGIDL does not have an effect on ID.
Transfer characteristics for source electrode and the corresponding simulations in Figure 5(b) allow
us to confirm these assumptions, where neither IGIDL nor IGgen contributes to the experimental source
current (IS).
Finally, referring to FinFET of the second group with LG = 60 nm (Figure 6), there is no contribution
of DT or TAT that impacts the magnitude of ID, and therefore, under the conditions where such
conduction mechanisms predominate, there is no influence in the device’s performance because of them.
In the particular case when VD = 20 mV is applied, the agreement obtained in Figure 6(a) is
accomplished with the ID simulation results through the SDDGM model and appropriately adding the
contribution of IGgen. This is because the hole–electron pairs generation process in the p–n junction
associated to the drain region enables available energy states in the valence band of the Si body film;
therefore, the DT of electrons from the gate increases IG, and the generated electrons in the Si body drift
through the drain region, resulting in the Ioff as VG bias is more negative. At saturation VD bias conditions

Figure 5. Measured (open symbols) and simulated results (solid and dashed lines) of (a) drain and (b) source transfer
characteristics at different VD biases for silicon on insulator fin-shaped field-effect transistor (FinFET) of the second
group with LG = 5 μm.

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
GATE LEAKAGE CURRENTS MODEL IMPLEMENTED IN VERILOG-A 855

Figure 6. Measured (open symbols) and simulated results (solid and dashed lines) of (a) drain and (b) source transfer
characteristics at different VD biases for silicon on insulator fin-shaped field-effect transistor (FinFET) of the second
group with LG = 60 nm.

and applied VG less than 0.1 V, simulated ID agrees with measured data by only considering the IGIDL
contribution; this is because BBT effect predominates at deep subthreshold conditions [9–11, 20]. Further-
more, a deviation between modeled and measured transfer characteristics is observed in the 0.1 V < VG
0.2 V range because of the rise of Ioff as a consequence of tunneling effect assisted by the interface states in
the gate overlaps. We have not yet modeled by a simple analytic expression the aforementioned conduction
mechanism.
Figure 6(b) show the comparison between IS and the simulated data by the SDDGM model and the
respective gate leakage current. The contribution of IGgen to IS is not observed at linear VD bias
conditions because the charge transportation by this leakage current only takes place between the gate
and drain electrodes. When VD = 1.0 V is applied, only the corresponding result for IGIDL is added to
the IS calculation; this contribution is due to the generated holes in the BBT process, which can flow
towards the source electrode. Additionally, the same deviation in the 0.1 V < VG < 0.2 V range is
observed because of the presence of the tunneling assisted by interface states.
Finally, Figure 7(a) shows the comparison between the transconductance (gm) from experimental
measurements at different VD and the one obtained from the SDDGM model, by including the gate
leakage currents model, for the case of FinFET with LG = 500 nm of the first group. Moreover,
another important parameter for analog circuit design is shown in Figure 7(b), where gm/ID is a
function of the logarithm of ID. In both cases of Figure 7, a good agreement is observed in a wide
operation range.

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
856 S. I. GARDUÑO ET AL.

Figure 7. Measured (open symbols) and simulated results (solid lines) of (a) transconductance for different VD and
(b) gm/ID versus log(ID) at VD = 1.1 V, for the fin-shaped field-effect transistor (FinFET) with LG = 500 nm of the
first group.

5. CONCLUSIONS
In this work, we present the implementation of the gate leakage currents model in Verilog-A, by
considering direct tunneling, TAT, and BBT effects as the main conduction mechanisms, which were
observed as predominant according to the insulating material used as gate dielectric, the dimensions
of the gate structure, and the transistor operation mode. Measured and simulated IG–VG characteris-
tics of FinFETS either in linear or saturation regions show excellent agreement in the considered
operation range.
Moreover, we show the contribution of the three main conduction mechanisms over the total
drain (or source) current of SOI FinFET devices by including analytical expressions to our
previous description in Verilog-A of the SDDGM model. At the same time, this allows us to
show the importance of gate current calculation within compact modeling in order to accurately
obtain those fundamental transistor parameters for circuits design such as transconductance or gm/ID
characteristic; for example, a transistor whose dimensions enable the increase of the gate leakage
current, until a magnitude that affects its transfer and output characteristics in any operation
regime, may impair the performance of the entire system, while a minimal leakage current
through the gate, negatively impacts the consumption power to an intolerant level on a integration
scale of million transistors.

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
GATE LEAKAGE CURRENTS MODEL IMPLEMENTED IN VERILOG-A 857

Appendix A

Verilog-A code list of the gate leakage currents model.


//** MODULE DECLARATION AND INPUT/OUTPUT TERMINALS
(1) `include "discipline.h"
(2) module DG (d, g, s);
(3) inout d, g, s;
(4) electrical d, g, s;
//** LOCAL VARIABLES
(5) real Vd, Vs, Vg, Vfb, Vdef, Vfbo, Vim, ViGSp, ViGDp, ViGSn, ViGDn, ViappGD;
(6) real epso, epox, epsi, eg0, kB, T, hp, mo, deg, dego, Ego, Nc, Nv, ni, nie, nieo;
(7) real cox, cs, q, Qbx, qb, qs, qd, qG, QGm, Qgen, fit, fif, fifo, fims, fimso;
(8) real L, tph, Eim, FADT, FBDT, JGDT, Inv1, Lch, deltaL, IGDT;
(9) real EiGSp, EiGDp, FD, phitrapp, FCp, Ntrapp, JtatGSp, JtatGDp, JGtatp, ItatGSp;
(10) real ItatGDp, IGtatp, EiGSn, EiGDn, phitrapn, FCn, Ntrapn, JtatGSn, JtatGDn;
(11) real JGtatn, ItatGSn, ItatGDn, IGtatn;
(12) real EiappGD, FADTgen, FBDTgen, JGgen, IGgen
(13) real FBGIDL, EsD, EsDGIDL, JGIDL, IGIDL;
//** PARAMETERS, WHERE CENTIMETERS ARE USED INSTEAD OF METERS
(14) parameter real LG=590E-7 from [0.0:inf]; // gate length
(15) parameter real LOV=8E-7 from [5E-7:10E-7]; // overlap length
(16) parameter real W=3.375E-3 from [0.0:inf]; // total width for one gate
(17) parameter real HFIN= 60E-7 from [1E-7:1E-5]; // fin height
(18) parameter real TS=30E-7 from (0.0:inf); // fin thickness
(19) parameter real TOX=1.6E-7 from (0.0:inf); // equivalent oxide thickness
(20) parameter real NSS=1E11 from (0.0:inf]; // oxide charges
(21) parameter real NA=1E15 from (0.0:inf]; // channel doping
(22) parameter real ND=1E20 from (0.0:inf]; // source/drain doping
(23) parameter real MWF=4.58 from [0.0:inf]; // metal work function
// Direct tunneling for inversion regimen
(24) parameter real KD=5.76 from[3.9:30]; gate dielectric constant
(25) parameter real PHIBECB=2.4 from[1.0:3.5]; tunneling barrier height
(26) parameter real MDECB=0.3 from[0.1:1]; electrons tunneling effective mass
// Trap-assisted tunneling for IG > 0
(27) parameter real AP=1.00E12 from[1e10:1e14];
(28) parameter real BP=-7.12134E8 from[-inf:0];
(29) parameter real EE=0.2 from[1e-2:1];
(30) parameter real ALFAP=-0.15 from[-1:1];
// Trap-assisted tunneling for IG < 0
(31) parameter real AN=1.00E12 from[1e11:1e13];
(32) parameter real BN=-5.12134e8 from[-inf:0];
(33) parameter real ALFAN=-0.15 from[-1:1];
// Direct tunneling assisted by generation process for IG < 0
(34) parameter real PHIBHVB=2.0 from[1:10];
(35) parameter real MDHVB=0.24 from[1e-3:1];
(36) parameter real TAOG =1.1e-4 from[1e-6:1e-3];
(37) parameter real PUG=10.0 from[1:1e2];
// Gate-induced drain leakage
(38) parameter real MESI=0.065 from[0:1];
(39) parameter real FAGIDL=1.5E-4 from[1E-6:1E-3];
//** ANALOG SECTION
(40) analog begin
(41) @(initial_step) begin
// Physical constants and operating conditions

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
858 S. I. GARDUÑO ET AL.

(42) epso=8.86542e-14;
(43) epox=3.46E-13;
(44) epsi=1.05E-12;
(45) q=1.602E-19;
(46) ni=1.45E10;
(47) eg0=1.08;
(48) fit=$vt;
(49) kB=1.378e-23;
(50) T=(fit*q)/kB;
(51) hp=6.62617e-34;
(52) mo=0.91095e-30;
// Effective gate lenght
(53) L=LG-(2*LOV);
// Capacitances and depleted charge
(54) cox=epox/TOX;
(55) cs=epsi/TS;
(56) Qbx=q*NA*TS; // depleted charge in the Si body film
(57) qb= Qbx/(cox*fit); // normalized depleted charge
// Gap calculation
(58) deg=9E-3*(ln(NA/1E17)+sqrt(ln(NA/1E17)*ln(NA/1E17)+0.9));
(59) dego=9E-3*(ln(ND/1E17)+sqrt(ln(ND/1E17)*ln(ND/1E17)+0.9));
// Intrinsic doping
(60) Ego=eg0+4.73e-4*((90e3/(300+636)) - ((T*T)/(T+636)));
(61) Nc=2.8e19*limexp(1.5*ln(T/300));
(62) Nv=1.04e19 * limexp(1.5*ln(T/300));
(63) nie=sqrt(Nc*Nv)*limexp(-(Ego-deg)/(2*fit));
(64) nieo= sqrt(Nc*Nv)*limexp(-(Ego-dego)/(2*fit));
// Fermi voltage and flat band voltage
(65) fif=fit*ln(NA/nie);
(66) fifo=-fit*ln(ND/nieo);
(67) fims=MWF-(4.17+((Ego-deg)/2)+fif);
(68) fimso= MWF-(4.17+((Ego-dego)/2)+fifo);
(69) Vfb=(fims-(q*NSS/cox)+0.08);
(70) Vfbo=(fimso-(q*NSS/cox));
(71) tph=(epso*KD)/cox;
(72) end // this is the end initial step
//** GATE LEAKAGE CURRENTS MODEL
// Direct tunneling – for strong inversion operation mode –
(73) Vim=fit*0.5*(qs+qd+qb); // qs and qd are calculated from SDDGM model
(74) Eim=Vim/(1e-2*tph);
(75) qG=(1/qq)*(((pow(qs,3)-pow(qd,3))/3)+(pow(qs,2)-pow(qd,2))-(qb*(qs-qd))+(pow(qb,2)*(ln
(qs+qb)-ln(qd+qb))));
(76) QGm=cox*fit*qG;
(77) FADT = pow(q,3)/(8*π*hp*q*PHIBECB);
(78) FBDT = (8*π*sqrt(2*MDECB*mo*pow(q*PHIBECB,3)))/(3*hp*q);
(79) Inv1=limexp(-(FBDT/Eim)*(1-pow(1-(Vim/PHIBECB),1.5)));
(80) JGDT=(FADT/(KD*epso))*(Vg-Vfb-(0.25*Vdef))*(QGm/ tph)*Inv1;
(81) Lch=L-deltaL;
(82) IGDT=2*W*Lch*JGinv;
// Trap-assisted tunneling in the overlap regions – for IG > 0 at subthreshold conditions –
(83) ViGSp=Vg+Vfbo-Vs;
(84) ViGDp=Vg+Vfbo-Vd*ALFAP;
(85) if (ViGSp > 0) begin // constraint to limit TAT in the aforementioned conditions
(86) EiGSp=ViGSp/(1e-2*tph);

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
GATE LEAKAGE CURRENTS MODEL IMPLEMENTED IN VERILOG-A 859

(87) end else begin


(88) EiGSp=1E40;
(89) end
(90) if (ViGDp > 0) begin // constraint to limit TAT in the aforementioned conditions
(91) EiGDp=ViGDp/(1e-2*tph);
(92) end else begin
(93) EiGDp = 1e40;
(94) end
(95) FD=(8*π*sqrt(2*q*MDECB*mo))/(3*hp);
(96) phitrapp=pow(-BP/FD,0.6666667);
(97) FCp=pow(1/MDECB,2.5)*((16*π*pow(q*EE,1.5))/(3*hp*sqrt(q*phitrapp-q*EE)));
(98) Ntrapp=(3*AP)/(2*FCp*q*phitrapp);
(99) JtatGSp=((2*FCp*Ntrapp*q*phitrapp)/(1e4*3*EiGSp))*limexp(-(FD*pow(phitrapp,1.5))/
EiGSp);
(100) JtatGDp=((2*FCp*Ntrapp*q*phitrapp)/(1e4*3*EiGDp))*limexp(-(FD*pow(phitrapp,1.5))/
EiGDp);
(101) JGtatp=2*(JtatGSp+JtatGDp);
(102) ItatGSp=W*LOV*JtatGSp;
(103) ItatGDp=W*LOV*JtatGDp;
(104) IGtatp=W*LOV*JGtatp;
// Trap-assisted tunneling in the overlap regions – for IG < 0 at subthreshold conditions –
(105) ViGSn=-VgVfbo+Vs;
(106) ViGDn=-Vg+Vfbo+Vd*ALFAN;
(107) if (ViGSn > 0) begin // constraint to limit TAT in the aforementioned conditions
(108) EiGSn=ViGSn/(1e-2*tph);
(109) end else begin
(110) EiGSn=1E40;
(111) end
(112) if (ViGDn > 0) begin // constraint to limit TAT in the aforementioned conditions
(113) EiGDn=ViGDn/(1e-2*tph);
(114) end else begin
(115) EiGDn = 1E40;
(116) end
(117) phitrapn=pow(-BN/FD,0.6666667);
(118) FCn=pow(1/MDECB,2.5)*((16*π*pow(q*EE,1.5))/(3*hp*sqrt(q*phitrapn-q*EE)));
(119) Ntrapn=(3*AN)/(2*FCn*q*phitrapn);
(120) JtatGSn=-((2*FCn*Ntrapn*q*phitrapn)/(1e4*3*EiGSn))*limexp(-(FD*pow(phitrapn,1.5))/
EiGSn);
(121) JtatGDn=-((2*FCn*Ntrapn*q*phitrapn)/(1e4*3*EiGDn))*limexp(-(FD*pow(phitrapn,1.5))/
EiGDn);
(122) JGtatn=2*(JtatGSn+JtatGDn);
(123) ItatGSn=W*LOV*JtatGSn;
(124) ItatGDn=W*LOV*JtatGDn;
(125) IGtatn=W*LOV*JGtatn;
// Direct tunneling assisted by generation process – for IG < 0 at subthreshold conditions –
(126) ViappGD=Vd-Vg-Vfb;
(127) EiappGD=ViappGD/(1e-2*tph);
(128) Qgen=q*TS*(nie/(2*TAOG))*limexp(((Vd-Vg)/(PUG*fit))-1);
(129) FADTgen=pow(q,3)/(8*π*hp*q*PHIBHVB);
(130) FBDTgen=(8*π*sqrt(2*MDHVB*mo*pow(q*PHIBHVB,3)))/(3*hp*q);
(131) JGgen=-2*(FADTgen/(KD*epso))*EiappGD*Qgen*limexp(-(FBDTgen/EiappGD)*(1-pow
(1-(Vim/PHIBECB),1.5)));
(132) IGgen=HFIN*L*JGgen;
// Gate-induced drain leakage by band-to-band tunneling

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
860 S. I. GARDUÑO ET AL.

(133) FBGIDL=(π*pow(mo*MESI,0.5)*pow(q*(Ego-dego),1.5))/(2*q*hp);
(134) EsD=(KD*epso*(Vd-Vg-(Ego-dego)))/(epsi*tph);
(135) if (EsD > 0) begin // constraints to limit IGIDL contribution to ID
(136) EsDGIDL=EsD;
(137) end else begin
(138) EsDGIDL=10E-15;
(139) end
(140) JGIDL=2*FAGIDL*EsDGIDL*limexp(-FBGIDL/(1E2*abs(EsDGIDL)));
(141) IGIDL=W*LOV*JGIDL;

ACKNOWLEDGMENTS

This work was supported by CONACyT project 127978; CONACyT program ‘Estancias Posdoctorales
Vinculadas al Fortalecimiento de la Calidad del Posgrado Nacional’, by EC FP7 NoE NANOSIL, grant agreement
no. 216171; and FNRS (Belgium). J. Alvarado thanks VIEP-BUAP. The authors thank N. Collaert, R. Rooyakers,
and M. Jurczak from Imec (Belgium) for the provided experimental devices and fruitful discussions.

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AUTHORS’ BIOGRAPHIES

Salvador Ivan Garduño received the Electronics and Communications Engineering degree
from National Polytechnic Institute (IPN), Mexico, in 2004, and the MSc and PhD degrees in
electrical engineering from the Center for Research and Advanced Studies of the National
Polytechnic Institute (CINVESTAV-IPN), Mexico, in 2007 and 2012, respectively. Since
2004 to date, he has been trained for researching and developing in the field of solid-state elec-
tronics. At the present time, he is a Post-Doctoral Research Scientist at the Research Center for
Semiconductor Devices-Autonomous, Benemerita University of Puebla (CIDS-BUAP),
Mexico. He is involved in the research of gate dielectric materials and development of gate
leakage current models. His current research interests include modeling and simulation of
nanoscale MuGFETs, and development and characterization of MOS structures with inor-
ganic and organic materials, as well as radiation effects on these devices.

Joaquín Alvarado received the Electronic and Communications Engineer degree from
Technological University of Mexico, Mexico, D.F., in 2003 and the PhD degree in elec-
trical engineering from SEES CINVESTAV-IPN, Mexico, in 2007. He was a Post-
Doctoral Research Scientist with the Institute ICTEAM, Université Catholique de
Louvain, Louvain-la-Neuve, Belgium, from 2008 to 2010. He is currently a Titular
Professor with the Research Center for Semiconductor Devices, BUAP, Puebla, Mexico.
His current research interests include compact modelling of advanced architectures of
MOSFETs and TFTs, as well as radiation effects and high temperatures.

Antonio Cerdeira received the MSc degree in physics from Moscow State University,
Russia, in 1966 and the PhD degree from the NW Leningrad Polytechnic Institute,
Russia, in 1977. Since 1966, he has been engaged in research, teaching and industrial
development in the field of microelectronics. At present, he is a Titular Professor at
the Section of Solid-State Electronics, Department of Electrical Engineering,
CINVESTAV-IPN, Mexico, D.F. He is the author of more than 250 technical papers
and four patents, head of research projects and invited lecturer. His actual research
interests are in the field of modeling and characterization of TFT and nanometric
MOSFETs, including the nonlinear behavior of devices and circuits.

Magali Estrada received the MSc degree in physics from Moscow State University,
Russia, in 1966 and the PhD degree from the NW Leningrad Polytechnic Institute,
Russia, in 1977. Since 1966, she has been engaged in research, teaching and industrial
development in the field of microelectronics. At present, she is a Titular Professor
at the Section of Solid-State Electronics, Department of Electrical Engineering,
CINVESTAV-IPN, Mexico, D.F. She is the author of more than 150 technical papers,
head of research projects and invited lectured at international conferences. Her actual
research interests are in the field of development, characterization and modeling of
polymeric TFT, LEDs and solar cells, as well as modeling and characterization of
nanometric MOSFETs.

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm
862 S. I. GARDUÑO ET AL.

Valeriya Kilchytska received her MSc degree in solid-state electronics and PhD degree
in semiconductor and dielectric physics from Kiev Shevchenko University, Kiev,
Ukraine, in 1992 and 1997, respectively. She has a long-term experience in advanced de-
vices focused on wide frequency band characterization, simulation and performance as-
sessment and, moreover, in the investigation of wide-temperature range behavior and
radiation effects particularities of SOI MOS devices. She is a Senior Researcher at the
Université Catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, where she has
authored or co-authored more than 150 technical papers and conference contributions.
She has been a principal investigator of numerous research projects funded by regional
and European institutions. She also serves as a reviewer for various international journals
and conferences such as IEEE TED, IEEE EDL and Solid State Electronics; a TPC mem-
ber of several international conferences; and a member of a working group on creation of
European Innovative Nanoelectronics Infrastructure.

Denis Flandre received the Electrical Engineer degree, the PhD degree and the Post-
doctoral thesis degree from the Université Catholique de Louvain (UCL), Louvain-
la-Neuve, Belgium, in 1986, 1990 and 1999, respectively. Since 2001, he is a full-time
Professor at UCL, and from 2003 to 2010, he has been Head of the UCL Microelectronics
Laboratory. He is involved in the research and development of SOI MOS devices, digital
and analog circuits, as well as sensors and MEMS, for special applications, more specifically
high-speed, low-voltage low-power, microwave, biomedical, radiation hardened and high-
temperature electronics and microsystems. He has authored and co-authored more than 600
technical papers or conference contributions. He is co-inventor of 10 patents. Professor
Flandre has been the recipient of several scientific prizes and best paper awards. He partici-
pated, organized or lectured in many short courses on SOI technology, devices and circuits,
in universities, industries and conferences.

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Numer. Model. 2014; 27: 846–862
DOI: 10.1002/jnm

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