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Abstract—A novel damping-factor-control frequency compen- are not sufficient, and the provided bandwidths are narrower
sation (DFCFC) technique is presented in this paper with detailed than the bandwidth of a single-stage amplifier. In addition,
theoretical analysis. This compensation technique improves fre- tradeoffs between bandwidth and other amplifier characteristics
quency response, transient response, and power supply rejection
for amplifiers, especially when driving large capacitive loads. such as settling time and power consumption are required. In
Moreover, the required compensation capacitors are small and particular, higher power consumption is needed to increase
can be easily integrated in commercial CMOS process. the bandwidth when the amplifier is required to drive a large
Amplifiers using DFCFC and nested Miller compensation capacitive load such as the error amplifier in a linear regulator.
(NMC) driving two capacitive loads, 100 and 1000 pF, were
fabricated using a 0.8-m CMOS process with Vtn =
0.72 V and
Furthermore, both small-signal and settling behavior should be
Vtp = 0.75 V. For the DFCFC amplifier driving a 1000-pF load, improved at the same time in order to obtain a fast amplifier
a 1-MHz gain-bandwidth product, 51 phase margin, 0.33-V/s [7]. Nevertheless, the above-mentioned topologies are mainly
slew rate, 3.54-s settling time, and 426-W power consumption concerned with the improvement of the frequency response.
are obtained with integrated compensation capacitors. Compared Another issue to be considered is the optimum number of
to the NMC amplifier, the frequency and transient responses of gain stages. Generally, frequency compensation techniques for
the DFCFC amplifier are improved by one order of magnitude
with insignificant increase on the power consumption. three-stage amplifiers are adequate for practical purposes since
three-stage amplifiers maintain a good compromise between the
Index Terms—Damping factor, frequency compensation, large
capacitive load, multistage amplifier. voltage gain 100 dB) and power consumption. Any extra gain
stage complicates the circuit structure and increases the com-
plexity of the frequency compensation.
I. INTRODUCTION With respect to the above problems, a novel damping-factor-
control frequency compensation (DFCFC) technique [8] is pre-
W ITH the rapid decrease in the supply voltage in VLSI,
more circuit designers are aware of the importance of
low-voltage multistage amplifiers. However, all multistage
sented in this paper. As illustrated in Fig. 1 and shown later in
the paper, this topology substantially increases the bandwidth
amplifiers suffer close-loop stability problems due to their of a three-stage amplifier, especially when driving large capac-
multiple-pole nature. Therefore, many frequency compensation itive loads. The improvement can be as large as one order of
topologies have been proposed [1]–[6]. magnitude. Furthermore, a DFCFC amplifier is able to provide a
As mentioned by Eschauzier et al. [1] and Huijsing et al. wider bandwidth than a single-stage amplifier with significantly
[2], multistage amplifiers suffer bandwidth reduction, and a improved transient response and power supply rejection ratio.
single-stage amplifier is optimum on bandwidth. Compared To achieve the above enhancements, the required values of the
to a single-stage amplifier, the gain-bandwidth products of a compensation capacitors are small, and there is a small increase
two-stage simple Miller compensated (SMC) amplifier and a on the power consumption and circuit complexity.
three-stage nested Miller compensated (NMC) amplifier are In the next section, a brief review on NMC is given. The
reduced to half and one quarter, respectively [1], [2]. As a result, purpose of the review is to take NMC as a common reference
other advanced topologies, such as multipath NMC (MNMC), when comparing DFCFC to all published topologies. DFCFC
hybrid NMC (HNMC), multipath HNMC (MHNMC), and is introduced in Section III. The transfer function, stability cri-
nested Gm-C compensation (NGCC), were developed to teria, transient response, and power supply rejection ratio are ad-
overcome the bandwidth reduction problem [1]–[5]. For these dressed. In Sections IV and V, the implementation of the struc-
topologies, which are based on NMC, pole–zero cancellation ture and experimental results are presented. Finally, the conclu-
and feed-forward technique are used to extend the bandwidth. sion of this paper is given in Section VI.
However, from the findings shown in Fig. 1, the bandwidth
improvements by the above-mentioned topologies over NMC II. BRIEF REVIEW ON NMC
The structure and equivalent circuit of a three-stage amplifier
Manuscript received July 2, 1999; revised September 30, 1999. This
work was supported by the RGC Competitive Earmarked Research Grant using NMC is shown in Fig. 2. The transconductance, output
HKUST6007/97E, Hong Kong SAR Government. resistance, and lumped output parasitic capacitance of the gain
The authors are with the Department of Electrical and Electronic Engineering, stages are notated by , and , respectively.
The Hong Kong University of Science and Technology, Clear Water Bay, Hong
Kong, China. and are the compensation capacitors, and is the
Publisher Item Identifier S 0018-9200(00)00938-0. loading capacitance. It should be noted that in order to obtain
222 IEEE TRANSACTIONS ON SOLID-STATE CIRCUITS, VOL. 35, NO. 2, FEBRUARY 2000
Fig. 1. Bandwidth comparison of different frequency compensation topologies (take NMC as the reference).
(a) (2)
(3)
(6)
224 IEEE TRANSACTIONS ON SOLID-STATE CIRCUITS, VOL. 35, NO. 2, FEBRUARY 2000
(a)
(b)
Fig. 4. (a) Structure of a DFCFC amplifier. (b) Equivalent small-signal circuit of the DFCFC amplifier.
product is controlled by . Moreover, the nondominant poles To obtain (7), the open-loop transfer function should be in the
locate at higher frequencies as the second-order function de- following format:
pends on the parasitic capacitance instead of , which
is loading capacitance dependent in NMC topology.
(8)
C. Stability Criteria, Gain-Bandwidth Product, and Phase
Margin
From the previous section, it is known that the stability of the
amplifier can be controlled by appropriate values of and
. In this section, the dimension conditions are calculated. (9)
We model the transfer function with ideal function first and
then apply the results. To begin, assuming that the effect of
the zeros is negligible and considering that the poles of the Considering a typical second-order function with damping
DFCFC amplifier in unity-feedback configuration have third- factor and corner frequency , is given by
order Butterworth frequency response [9], the transfer func-
tion in unity-gain feedback with cut-off frequency
(10)
is given by
By comparing the denominator of (9) with (10), it is proven that
the damping factor of the nondominant complex pole in open
loop is if the amplifier has third-order Butterworth fre-
quency response in unity-feedback configuration. Therefore, the
(7)
magnitude plot of the amplifier in open loop has no frequency
“peak.” The position of the nondominant complex pole
LEUNG et al.: THREE-STAGE LARGE CAPACITIVE LOAD AMPLIFIER WITH DFCFC 225
is obtained by solving the second-order function in (8) and is and then substituting (18) into (19) to obtain
given by
(20)
(11)
(21)
(22)
where
(23)
(17) (24)
By solving the above equation and rejecting the negative solu- (25)
tion of , the dimension condition of in DFCFC is given
by It can be shown from (24) that the bandwidth of a DFCFC am-
plifier is times that of an NMC amplifier. The improvement
by DFCFC is greater for a larger (i.e., a larger loading ca-
(18) pacitance). Referring to Fig. 1, the bandwidth of the DFCFC
amplifier may be even larger than a single-stage amplifier when
For the dimension condition of , it can be obtained by firstly is larger than 4. Also, there is no degradation on the phase
substituting (15) into (14) to acquire margin when using DFCFC. If the required phase margin is less
than 60 in some applications, a smaller can be used to de-
crease the phase margin and further increase the bandwidth of
(19)
the amplifier.
226 IEEE TRANSACTIONS ON SOLID-STATE CIRCUITS, VOL. 35, NO. 2, FEBRUARY 2000
D. Slew Rate
After the analysis on AC behavior, the transient behavior is
studied in this section and the next section. Assuming that the
output stage is of push–pull or class-AB type, the slew rate is
not limited by the output stage. Thus, the slew rate of a multi-
stage amplifier depends on two factors. One is the value of the
compensation capacitor , and the other is the amount of cur-
rent to charge the compensation capacitor [10]–[15]. In
mathematical expression, the slew rate is expressed as
(26)
From the above expression, the increase in the slew rate can be
achieved by either increasing the bias current or reducing the Fig. 5. High-frequency gain of the NMC and DFCFC amplifiers.
value of the compensation capacitor. Increasing the bias current
will increase the static power consumption, so it is not preferred
in low-power design. Therefore, the most efficient method to single transistor. Moreover, when the compensation network
increase the slew rate is to reduce the value of the compensa- is required, the compensation capacitors are short-circuited
tion capacitor. However, the compensation capacitor cannot be at high frequencies, and the high-frequency supply variations
reduced arbitrarily; otherwise, the amplifier will be unstable in easily bypass through the compensation capacitor to the output
the close-loop operation. of the amplifier.
By comparing (22) with (2), as the required value of the com- The is defined by the following expression [15]:
pensation capacitor in DFCFC is reduced by times, the im-
(27)
provement on the slew rate using DFCFC is improved by
times. Similar to the frequency response, the improvement by where is the open-loop input-to-output voltage gain,
DFCFC on the slew rate is larger for a large to ratio. and is the supply-to-output voltage gain. It
Therefore, the slew rate of a DFCFC amplifier is better than that can be shown from the above equation that the can
of the NMC counterpart, especially when driving a large capac- be improved by obtaining a larger and a smaller
itive load. . A larger can be achieved by increasing
the gain-bandwidth product of the amplifier. As illustrated in
E. Settling Time Fig. 5, at a particular frequency , the gain obtained from
Settling behavior of an amplifier is very essential in analog the DFCFC amplifier is , which is much
design since it directly affects the performance of the circuits larger than of the NMC amplifier. Therefore,
using the amplifier. To enhance the settling behavior, the first compared with NMC, the signal from the input of the DFCFC
thing to investigate is its dependence. Neglecting the short amplifier is amplified larger, and the output signal appearing
duration of the small-signal response before slewing, the at the output is stronger. As a result, the relative effect of the
settling time can be mainly divided into two periods. supply noise is less significant.
They are the slewing period and quasi-linear period A reduction in can be accomplished by using
[10], [11]. The dependence of the slew rate has been smaller values of compensation capacitors or completely elimi-
discussed in the previous section, and the slew rate is proven nating the capacitors. In the DFCFC topology, as no inner com-
to be greatly improved by DFCFC. For the quasi-linear period, pensation capacitor is required, the resulting is
it is a strong function of the phase margin [17], and it also much smaller.
depends on how compressed pole–zero doublet is below the Taking into account both the above-mentioned advantages,
unity-gain frequency of the amplifier [1], [3]. the given by DFCFC is better than that of NMC.
In the case of using DFCFC, as there is no pole–zero doublet,
the quasi-linear period only depends on the phase margin. By G. Physical Dimension of the DFCFC Amplifier
using the stability criteria stated before, the phase margin of the
In the design of multistage amplifiers that drive large capaci-
DFCFC amplifier is approximately 60 , which is a very reason-
tive loads, most of the chip area is occupied by the compensation
able value to obtain a short quasi-linear period. As a result, there
capacitors. As the proposed topology requires smaller compen-
are not many decaying sinusoidal cycles, and the output voltage
sation capacitors to achieve stability, the required dimension of
can settle within a very short duration.
the whole amplifier is significantly reduced.
F. Power Supply Rejection Ratio
IV. IMPLEMENTATION OF THE PROPOSED STRUCTURE
The power supply rejection ratio of a single-stage
cascode amplifier is excellent as the cascode configuration Low-power 2-V DFCFC and NMC amplifiers, illustrated
provides a good isolation between the supply and the output of in Fig. 6, driving two capacitive loads, 100 and 1000 pF,
the amplifier. However, the in a noncascode multistage were fabricated using a double-metal double-poly 0.8- m
amplifier is inferior due to the poorer isolation barrier of a CMOS process with V and V from
LEUNG et al.: THREE-STAGE LARGE CAPACITIVE LOAD AMPLIFIER WITH DFCFC 227
(a)
(b)
Fig. 6. Circuit diagram of the (a) NMC amplifier and (b) DFCFC amplifier.
(a) (a)
(b) (b)
Fig. 8. Frequency responses of the (a) NMC and (b) DFCFC amplifier with Fig. 10. Frequency responses of the (a) NMC and (b) DFCFC amplifier
100-pF loading capacitance (only the frequencies near the unity-gain frequency with 1000-pF loading capacitance (only the frequencies near the unity-gain
are shown). frequency are shown).
amplifiers are small and easy to integrate. On the other hand, the
As shown in the figures and table, by comparing the DFCFC
NMC amplifier driving a 1000-pF load requires unrealistic large
amplifier to the NMC counterpart, DFCFC improves the gain-
compensation capacitors pF and pF),
bandwidth product by 4 times, the slew rate by 6 times, the set-
and thus integration is impossible.
tling time by 3 times, and the negative power supply rejection
ratio by at least 40 dB for the case driving 100 pF. For a larger
V. EXPERIMENTAL RESULTS
loading capacitance of 1000 pF, the improvement is more signif-
The frequency responses measured with the HP4194A icant. The gain-bandwidth product is improved by 18 times. The
impedance/gain-phase analyzer are shown in Figs. 8 and 10, slew rate and settling time are improved by 14 and 9 times, re-
while the transient responses measured with the LeCroy 9354A spectively. In addition, the negative power supply rejection ratio
oscilloscope are shown in Figs. 9 and 11. The performances are is enhanced by at least 60 dB. However, there is only negligible
tabulated in Table I. increase on the power consumption.
LEUNG et al.: THREE-STAGE LARGE CAPACITIVE LOAD AMPLIFIER WITH DFCFC 229
TABLE I
MEASURED RESULTS OF THE NMC AND DFCFC AMPLIFIERS
TABLE II
COMPARISON OF DIFFERENT MULTISTAGE AMPLIFIERS
Since the bandwidth improvement by DFCFC with a 1000-pF A larger figure of merit implies a better frequency compensation
load is 18 times, which is much greater than 4, the bandwidth topology. From Table II, it is clear that DFCFC is better than all
provided by the amplifier is even wider than a single-stage am- existing topologies, especially for the case of 1000-pF loading
plifier under nearly the same power consumption. capacitance.
To provide a clearer picture on the improvements by DFCFC,
a comparison table for some published amplifiers using different VI. CONCLUSION
compensation topologies is shown in Table II. Two figures of In this paper, DFCFC which is targeted for amplifiers driving
merit, [6] and , are defined for small-signal and large capacitive loads has been presented. Theoretical analysis
large-signal performances. on frequency response, transient response, and power supply re-
(28) jection ratio have been firstly discussed. Then, the experimental
results have demonstrated that a DFCFC amplifier is signifi-
(29) cantly better than an NMC amplifier and a single-stage am-
plifier when driving large capacitive loads. Finally, comparison
The units of and are MHz pF/mW and V/ s with other published topologies has been presented, and DFCFC
pF/mW, respectively. An average is used in the calculation. shows better small-signal and large-signal performances.
230 IEEE TRANSACTIONS ON SOLID-STATE CIRCUITS, VOL. 35, NO. 2, FEBRUARY 2000