PART 3

RC CIRCUITS LOGIC GATES

RL CIRCUITS LOGIC CIRCUIT SIMPLIFICATION

TRANSFORMERS SLD PLD

TIME RESPONSE OF REACTIVE CIRCUITS TESTING AND TROUBLESHOOTING

TRANSISTORS AND APPLICATIONS CONBINATIONAL LOGIC CIRCUITS

BASIC OP AMP CIRCUITS FLIP-FLOPS AND TIMERS

SPECIAL PURPOSE OP AMP CIRCUITS SEQUENTIAL LOGIC CIRCUITS

MEASUREMENT ARITHMETIC OPERATIONS AND CIRCUITS

CONVERSION AND CONTROL SEMICONDUCTOR MEMORY

ALTERNATION CURRENT VS DIRECT CURRENT ANALOG AND DIGITAL CONVERTERS

SEMICONDUCTOR PRINCIPLES COMPUTER HARDWARE AND SOFTWARE

BJT DIGITAL CONCEPTS

FET NUMBER SYSTEMS AND CODES

THYRISTORS AND TRANSDUCERS LOGIC GATES

ANALOG TO DIGITAL EX-OR AND EX-NOR GATES

NUMBER SYSTEMS AND CODES BOOLEAN AND LOGIC SIMPLIFICATION

 DESCRIBING LOGIC CIRCUITS

COMBINATIONAL LOGIC ANALYSIS

 INDIABIX 3
RC CIRCUITS 7. Calculate the phase angle in the given 12. What is the total current in the given
circuit. circuit?
1. In a 20 Vac series RC circuit, if 20 V is
read across the resistor and 40 V is
measured across the capacitor, the
applied voltage is
A. 45 Vac
B. 50 Vac A. 0° A. 0.28 A
C. 60 Vac B. 90° B. 0.399 A
D. 65 Vac C. 22.52° C. 909 A
D. 67.48° D. 0.2 A
2.Which of the following is the reference
vector for parallel RC circuits? 8. What is the phase angle for a parallel 13. Which statement about a series RC
A. R circuit consisting of a 500 kHz, 5 Vac circuit is true?
B. V source with a 47 pF capacitor, and a 4.7 A. The capacitor's voltage drop is
C. I kΩ resistor in parallel? in phase with the resistor's
D. XC A. 55.3° voltage drop.
B. –55.3° B. The current leads the source
3. What is the voltage drop across R1 in
C. 34.8° voltage.
the given circuit?
D. –34.8° C. The current lags the source
voltage.
9.
D. The resistor voltage lags the
current.
14. If the frequency increases in the
A. 10 V given circuit, how would the total
B. 4.80 V current change?
C. 4.00 V
D. 5.80 V
Which circuit is represented by the
4. Power that is measured in volt- frequency response curve in the given
amperes is called figure?
A. impedance power A. High-pass filter A. The total current would
B. reactive power B. Low-pass filter increase.
C. true power C. Band-pass filter B. The total current would
D. apparent power D. Band-stop filter decrease.
C. The total current would remain
5. As frequency increases 10. What is the phase angle in the given the same.
A. both series and parallel RC circuit? D. More information is needed in
impedance decrease
order to predict how the total
B. series RC impedance decreases
current would change.
and parallel RC impedance
increases 15. What is the effect of increasing the
C. series RC impedance increases resistance in a series RC circuit?
and parallel RC impedance A. 14.95° A. There will be no effect at all.
decreases B. 36.88° B. The current will increase.
D. both series and parallel RC C. 0° C. The phase shift will decrease.
impedance increase D. 90° D. The input voltage will increase.
6. Calculate the magnitude of the 11. What is the current through XC1 in
impedance in the given circuit. the given circuit?
RL CIRCUITS
1. As frequency increases
A. both series and parallel RL
impedance decrease
A. 24.1 MΩ A. 32.2 mA B. series RL impedance decreases
B. 10 MΩ B. 16 mA and parallel RL impedance
C. 26.1 MΩ C. 12 ma increases
D. 0Ω D. 48 mA

C. series RL impedance increases
and parallel RL impedance
decreases
D. both series and parallel RL
impedance increase
2. Calculate the voltage dropped across
R1 in the given circuit.
INDIABIX 3
7. What is the magnitude of the phase A. An increase in frequency
angle of a 24 Vac parallel RL circuit when causes an increase in phase
R = 45 Ω and XL = 1100 Ω? lag.
A. 0.001° B. An increase in frequency causes
B. 2.3° an increase in the magnitude of
C. 87.6° the output voltage.
D. 89.9° C. A decrease in frequency causes
an increase in phase lag.
8. Which of the following statements is
D. A decrease in frequency causes
true if the frequency decreases in the
a decrease in the magnitude of
circuit in the given circuit?
the output voltage.

A. 14 V TRANSFORMERS
B. 26.8 V
C. 28 V 1. When does maximum power transfer
D. 0V A. The phase angle decreases.
happen from the source to the load?
B. VR decreases.
3. What is the true power of a 24 Vac A. When the source resistance is
C. IT decreases.
parallel RL circuit when R = 45 Ω and XL greater than the load resistance
D. VS decreases.
= 1100 Ω? B. When the source resistance is
A. 313.45 W 9. What is the magnitude of the phase less than the load resistance
B. 12.8 W angle between the source voltage and C. When there is negligible source
C. 44.96 W current when a 100 mH inductor with an resistance
D. 22.3 W inductive reactance of 6 kΩ and a 1 kΩ D. When the source resistance
resistor are in series with a source? equals the load resistance
4. If XL= 100 Ωand R = 100Ω, then A. 0.1°
impedance will be 2. A transformer is plugged into a 120 V
B. 9.0°
A. 141.4 Ω rms source and has a primary current of
C. 61.0°
B. 14.14 Ω 300 mA rms. The secondary is providing
D. 81.0°
C. 100 Ω 18 V across a 10 Ω load. What is the
D. 200 Ω 10. Which of the following statements is efficiency of the transformer?
true if R1 opens in the circuit in the given A. 88%
5. Which of the following statements is circuit? B. 90%
true if the inductor shorts out in the C. 92%
circuit in the given circuit? D. 95%
3. The coefficient of coupling between
two coils is 0.45. The first coil has an
inductance of 75 mH and the second coil
A. IL2 increases. has an inductance of 105 mH. What is
B. ZT decreases. the mutual inductance between the
A. Each component drops 5 V. C. VS increases. coils?
B. The impedance equals 0 Ω. D. VL1 equals 0 V. A. 3.54 mH
C. The power factor equals 1.
11. Which of the following statements is B. 7.88 mH
D. The phase angle equals 90°.
true if R = 100 Ω and XL = 100 Ωin the C. 39.9 mH
6. Calculate the voltage dropped across circuit in the given circuit? D. 189.3 mH
L2 in the given circuit.
4. Increasing the number of turns of wire
on the secondary of a transformer will
A. increase the secondary current
B. decrease the secondary
current
A. Each component drops 5 V. C. have no effect on the secondary
A. 18 V B. The impedance equals 200 Ω. current
B. 6V C. The power factor equals 1. D. increase the primary current
C. 13.5 V D. The phase angle equals 45°.
5. What is the turns ratio of the
D. 0V
12. Which of the following statements is transformer needed to match a 1 kΩ
true about a lag network? source resistance to a 160 Ω load?
 INDIABIX 3
A. 2.5:1 11. A special transformer used to convert B. 4.3 V
B. 0.4:1 unbalanced signals to balanced signals is C. 4.75 V
C. 6.25:1 the D. 4.9 V
D. 16:1 A. balun 2. If a periodic pulse waveform is applied
B. autotransformer to an RC differentiating circuit, which
6. What is the secondary voltage in the
C. center-tapped transformer two conditions are possible?
given circuit?
D. step-across transformer A. tw ≥ 5τ or tw > 5τ
B. tw = 5τ or tw > 5τ
12. If the load doubled in value in the
C. tw ≤ 5τ or tw < 5τ
given circuit, what reflected resistance
D. tw ≥ 5τ or tw < 5τ
would the source see?
A. 13.3 V rms in phase with the 3. An RL integrator and an RC
primary differentiator can act as what types of
B. 120 V rms in phase with the filters, respectively?
primary A. low-pass, low-pass
C. 13.3 V rms out of phase with B. low-pass, high-pass
A. 80 Ω
the primary C. high-pass, high-pass
B. 400 Ω
D. 120 V rms out of phase with the D. high-pass, low-pass
C. 2 kΩ
primary D. 10 kΩ 4. In a repetitive-pulse RC integrator
7. The transformer turns ratio circuit, what would the steady-state
13. If the primary power of an ideal
determines voltage equal at the end of the fifth
transformer having a 2:1 voltage ratio is
A. the ratio of primary and pulse? Assume a Vin of 20 V.
100 W, the secondary power is
secondary voltages A. 1.46 V
A. 100 W
B. the ratio of primary and B. 14.62 V
B. 50 W
secondary currents C. 20 V
C. 75 W
C. the reflected impedance D. 0V
D. 200 W
D. all of the above 5. What is a circuit that produces short-
14. A transformer has
8. Mutual induction is dependent on duration spikes?
A. primary and secondary
A. winding ratios A. A trigger pulse generator
windings, both of which are
B. output polarities B. An RL integrator
considered inputs
C. dc voltage levels C. A timing circuit
B. primary and secondary
D. current changes D. A pulse waveform-to-dc
windings, both of which are
converter
9. What is the current through the load considered outputs
in the given circuit? C. a primary winding used as an
output and a secondary winding
used as an input
D. a primary winding used as an
input and a secondary winding
A. 500 µA used as an output 6.
B. 10 mA In the given circuit, what must the pulse
C. 250 mA width and time between pulses be to
D. 1.25 A TIME RESPONSE OF allow the capacitor to completely charge
REACTIVE CIRCUITS by the end of each pulse and to
10. What is the power dissipated in the completely discharge between each
primary of the transformer in the given 1. pulse?
circuit? A. 940 µs
B. 2.82 ms
C. 3.76 ms
D. 4.7 ms

A. 25 mW
B. 500 mW
C. 12.5 W
What voltage will the capacitor charge
D. 62.5 W
up to in the given circuit for the single
input pulse shown?
A. 3.15 V 7.
 INDIABIX 3
The given circuit is an What is the voltage across the inductor
A. RL integrator in the given circuit on the falling edge of
A.
B. RC differentiator the first input pulse?
B. Av = IC × RC
C. RL differentiator A. –0.2 V
D. RC integrator B. 0.2 V
C. –9.8 V C.
8. Which of the following is true for a
D. 9.8 V
capacitor?
A. A capacitor acts like a short to D.
instantaneous changes in 7. In a class B push-pull amplifier, the
current. TRANSISTORS AND transistors are biased slightly above
B. A capacitor's voltage cannot APPLICATIONS cutoff to avoid
change instantaneously. A. crossover distortion
C. A capacitor acts like an open to 1. The primary function of the bias circuit B. unusually high efficiency
dc. is to C. negative feedback
D. All of the above A. hold the circuit stable at VCC D. a low input impedance
9. If the capacitor in an RC integrator B. hold the circuit stable at vin
8. The depletion-mode MOSFET
shorts, the output C. ensure proper gain is achieved
A. can operate with only positive
A. is at ground D. hold the circuit stable at the
gate voltages
B. would measure the same as the designed Q-point
B. can operate with only negative
input 2. A JFET gate voltages
C. would measure zero volts A. is a current-controlled device C. cannot operate in the ohmic
D. None of the above B. has a low input resistance region
10. C. is a voltage-controlled device D. can operate with positive as
D. is always forward-biased well as negative gate voltages
3. A source follower has a voltage gain 9. Three different points are
(Av) of shown on a dc load line. The upper point
A. AV = gmRd represents the
B. AV = gmRs A. minimum current gain
B. quiescent point
What has the voltage across the resistor C. saturation point
C. D. cutoff point
decayed to by the end of the pulse in the
given circuit?
10. Which of the following conditions are
A. 0V
D. needed to properly bias an npn
B. 0.75 V
transistor amplifier?
C. 5.55 V 4. The capacitor that produces an ac
A. Forward bias the base/emitter
D. 14.25 V ground is called a(n)
junction and reverse bias the
A. coupling capacitor
11. How long will it take the capacitor in base/collector junction.
B. dc open
the given circuit to discharge? B. Forward bias the collector/base
C. bypass capacitor
junction and reverse bias the
D. ac open
emitter/base junction.
5. The formula used to calculate the C. Apply a positive voltage on the
approximate ac resistance of the base- n-type material and a negative
emitter diode (re) is voltage on the p-type material.
D. Apply a large voltage on the
A. 16.4 µs base.
B. 32.8 µs A.
C. 65.6 µs B. re almostequal.jpg 25 mV × IC 11. Often a common-collector will be the
D. 82 µs last stage before the load; the main
function of this stage is to
12. C. A. provide voltage gain
B. buffer the voltage amplifiers
from the low-resistance load
D. C. provide phase inversion
6. The signal voltage gain of an D. provide a high-frequency path
amplifier, Av, is defined as: to improve the frequency
response
 INDIABIX 3
B. the inverted sum of the 13. A two-pole high-pass active filter
12. In order for feedback oscillators to
individual inputs would have a roll-off rate of
have any practical value, the gain has to
C. the sum of the individual inputs A. 40 dB/decade
be
D. the inverted average of the B. –40 dB/decade
A. <1
individual inputs C. 20 dB/decade
B. self-adjusting
D. –20 dB/decade
C. stabilized 6. If the input to a comparator is a sine
D. nonlinear wave, the output is a
A. ramp voltage
13. To get a negative gate-source SPECIAL PURPOSE OP-
B. sine wave
voltage in a self-biased JFET circuit, you
must use a
C. rectangular wave AMP CIRCUITS
D. sawtooth wave
A. voltage divider
B. source resistor 7. A basic series regulator has
C. ground A. an error detector
D. negative gate supply voltage B. a load
C. a reference voltage
D. both an error detector and a 1.
BASIC OP-AMP CIRCUITS reference voltage
8. A comparator is an example of a(n)
1. The center frequency of a band-pass
A. active filter
filter is always equal to the
B. current source
A. bandwidth
C. linear circuit
B. –3 dB frequency
D. nonlinear circuit
C. bandwidth divided by Q
D. geometric average of the
9. Initially, the closed-loop gain (Acl) of a
critical frequencies
Wien-bridge oscillator should be
A. Acl < 3 Which circuit is known as a current-to-
B. Acl > 3 voltage converter?
2. The formula shows that
C. 0 A. a
for a given capacitor, if the voltage
changes at a constant rate with respect D. Acl 1 B. b
to time, the current will 10. In an averaging amplifier, the input C. c
A. increase resistances are D. d
B. decrease A. equal to the feedback 2. When using an OTA in a Schmitt-
C. be constant resistance trigger configuration, the trigger points
D. decrease logarithmically B. less than the feedback are controlled by
3. A zero-level detector is a resistance A. the Iout
A. comparator with a sine-wave C. greater than the feedback B. the Ibias
output resistance C. the Vout
B. comparator with a trip point D. unequal D. both Iout and Ibias
referenced to zero 11. A triangular-wave oscillator can
C. peak detector consist of an op-amp comparator,
D. limiter followed by a(n)
4. A digital-to-analog converter is an A. differentiator
application of the B. amplifier 3.
A. scaling adder C. integrator
B. voltage-to-current converter D. multivibrator
C. noninverting amplifier 12. The ramp voltage at the output
D. adjustable bandwidth circuit of an op-amp integrator
5. If the value of resistor Rf in an A. increases or decreases at a
averaging amplifier circuit is equal to the linear rate
value of one input resistor divided by the B. increases or decreases
number of inputs, the output will be exponentially
equal to C. is always increasing and never
A. the average of the individual decreasing
D. is constant Refer the given circuits. Which circuit is
inputs known as an OTA?
 INDIABIX 3
A. a 8. An instrumentation amplifier has a 2. Which of the following characterizes
B. b high an analog quantity?
C. c A. output impedance A. Discrete levels represent
D. d B. power gain changes in a quantity.
C. CMRR B. Its values follow a logarithmic
4. This circuit is a setup for
D. supply voltage response curve.
C. It can be described with a finite
9. This circuit is a setup for
number of steps.
D. It has a continuous set of
values over a given range.
3. ASCII stands for:
A. an antilog amplifier A. American Serial
B. a constant-current source Communication Interface
C. an instrumentation amplifier B. Additive Signal Coupling
D. an isolation amplifier Interface
C. American Standard Code for
A. an antilog amplifier Information Interchange
B. a constant-current source D. none of the above
C. an instrumentation amplifier
D. an isolation amplifier 4. Which type of signal is represented by
discrete values?
5. 10. Circuits that shift the dc level of a A. noisy signal
signal are called B. nonlinear
A. limiters C. analog
B. clampers D. digital
C. peak detectors
D. dc converters 5. A data conversion system may be
used to interface a digital computer
11. The voltage gain of an OTA can be system to:
calculated using the formula A. an analog output device
B. a digital output device
A. C. an analog input device
Which circuit is known as a voltage-to- D. a digital printer
B.
current converter?
A. a
B. b C. NUMBER SYSTEMS AND
C. c CODES
D. d D.
6. The primary function of the oscillator 12. In the classic three-op-amp 1. Base 10 refers to which number
in an isolation amplifier is to instrumentation amplifier, the system?
A. convert dc to high-frequency differential voltage gain is usually A. binary coded decimal
ac produced by the B. decimal
B. convert dc to low-frequency ac A. first stage C. octal
C. rectify high-frequency ac to dc B. second stage D. hexadecimal
D. produce dual-polarity dc C. mismatched resistors 2. Convert the decimal number 151.75 to
voltages for the input to the D. output op-amp binary.
demodulator
A. 10000111.11
7. Refer to Figure 20-2. This circuit is a B. 11010011.01
setup for
ANALOG TO DIGITAL C. 00111100.00
D. 10010111.11
1. The two basic types of signals are
analog and: 3. Convert the binary number 1011010 to
A. digilog hexadecimal.
B. digital A. 5B
A. an antilog amplifier
C. vetilog B. 5F
B. a constant-current source
D. sine wave C. 5A
C. an instrumentation amplifier
D. 5C
D. an isolation amplifier
 INDIABIX 3
4. The number of bits used to store a B. 00110101 6. Exclusive-OR (XOR) logic gates can be
BCD digit is: C. 00110010 constructed from what other logic
A. 8 D. 00110001 gates?
B. 4 A. OR gates only
12. 3428 is the decimal value for which of
C. 1 B. AND gates and NOT gates
the following binary coded decimal
D. 2 C. AND gates, OR gates, and
(BCD) groupings?
NOT gates
5. Sample-and-hold circuits in ADCs are A. 11010001001000
D. OR gates and NOT gates
designed to: B. 11010000101000
A. sample and hold the output of C. 011010010000010 7. How many truth table entries are
the binary counter during the D. 110100001101010 necessary for a four-input circuit?
conversion process A. 4
13. What is the result when a decimal
B. stabilize the ADCs threshold B. 8
5238 is converted to base 16?
voltage during the conversion C. 12
A. 327.375
process D. 16
B. 12166
C. stabilize the input analog
C. 1388 8. A NAND gate has:
signal during the conversion
D. 1476 A. LOW inputs and a LOW output
process
B. HIGH inputs and a HIGH output
D. sample and hold the ADC
C. LOW inputs and a HIGH
staircase waveform during the LOGIC GATES output
conversion process
D. None of these
6. The weight of the LSB as a binary 1. The output will be a LOW for any case
when one or more inputs are zero in 9. The basic logic gate whose output is
number is:
a(n): the complement of the input is the:
A. 1
A. OR gate A. OR gate
B. 2
B. NOT gate B. AND gate
C. 3
C. AND gate C. INVERTER gate
D. 4
D. NAND gate D. comparator
7. What is the difference between binary
2. If a signal passing through a gate is 10. What input values will cause an AND
coding and binary coded decimal?
inhibited by sending a low into one of logic gate to produce a HIGH output?
A. Binary coding is pure binary.
the inputs, and the output is HIGH, the A. At least one input is HIGH.
B. BCD is pure binary.
gate is a(n): B. At least one input is LOW.
C. Binary coding has a decimal
A. AND C. All inputs are HIGH.
format.
B. NAND D. All inputs are LOW.
D. BCD has no decimal format.
C. NOR
8. Convert the binary number 1001.0010 D. OR
to decimal. LOGIC CIRCUIT
A. 125 3. A single transistor can be used to build SIMPLIFICATION
B. 12.5 which of the following digital logic
C. 90.125 gates? 1. Which statement below best describes
D. 9.125 A. AND gates a Karnaugh map?
B. OR gates A. It is simply a rearranged truth
9. Convert 110010012 (binary) to C. NOT gates
decimal. table.
D. NAND gates B. The Karnaugh map eliminates
A. 201
B. 2001 4. The logic gate that will have HIGH or the need for using NAND and
C. 20 "1" at its output when any one of its NOR gates.
D. 210 inputs is HIGH is a(n): C. Variable complements can be
A. OR gate eliminated by using Karnaugh
10. What is the decimal value of the B. AND gate maps.
hexadecimal number 777? C. NOR gate D. A Karnaugh map can be used to
A. 191 D. NOT gate replace Boolean rules.
B. 1911
C. 19 5. How many NAND circuits are 2. Which of the examples below
D. 19111 contained in a 7400 NAND IC? expresses the commutative law of
A. 1 multiplication?
11. What is the resultant binary of the B. 2 A. A+B=B+A
decimal problem 49 + 1 =? C. 4 B. A•B=B+A
A. 01010101 D. 8 C. A • (B • C) = (A • B) • C
 INDIABIX 3
D. A•B=B•A means that logically there is no A. 0.0 V to 0.4 V
3.The Boolean expression is difference between: B. 0.4 V to 0.8 V
logically equivalent to what single gate? A. a NAND gate and an AND gate C. 0.4 V to 1.8 V
A. NAND with a bubbled output D. 0.4 V to 2.4 V
B. NOR B. a NOR gate and an AND gate
4. When an IC has two rows of parallel
C. AND with a bubbled output
connecting pins, the device is referred to
D. OR C. a NOR gate and a NAND gate
as:
with a bubbled output
4. The observation that a bubbled input A. a QFP
D. a NAND gate and an OR gate
OR gate is interchangeable with a B. a DIP
with a bubbled output
bubbled output AND gate is referred to C. a phase splitter
as: 10. The commutative law of addition and D. CMOS
A. a Karnaugh map multiplication indicates that:
5. Which digital IC package type makes
B. DeMorgan's second theorem A. the way we OR or AND two
the most efficient use of printed circuit
C. the commutative law of variables is unimportant
board space?
addition because the result is the same
A. SMT
D. the associative law of B. we can group variables in an
B. TO can
multiplication AND or in an OR any way we
C. flat pack
want
5. The systematic reduction of logic D. DIP
C. an expression can be expanded
circuits is accomplished by: by multiplying term by term 6. The problem of interfacing IC logic
A. symbolic reduction just the same as in ordinary families that have different supply
B. TTL logic algebra voltages (VCCs) can be solved by using
C. using Boolean algebra D. the factoring of Boolean a:
D. using a truth table expressions requires the A. level-shifter
6. Logically, the output of a NOR gate multiplication of product terms B. tri-state shifter
would have the same Boolean that contain like variables C. translator
expression as a(n): D. level-shifter or translator
11. Which of the following expressions is
A. NAND gate immediately in the sum-of-products (SOP) form? 7. Ten TTL loads per TTL driver is known
followed by an INVERTER A. Y = (A + B)(C + D) as:
B. OR gate immediately followed B. Y = AB(CD) A. noise immunity
by an INVERTER B. power dissipation
C. AND gate immediately C. C. fanout
followed by an INVERTER D. propagation delay
D. NOR gate immediately D.
followed by an INVERTER 8. Which of the following summarizes
STANDARD LOGIC the important features of emitter-
7. Which of the examples below coupled logic (ECL)?
expresses the distributive law of Boolean
DEVICES (SLD) A. negative voltage operation,
algebra? high speed, and high power
A. A • (B • C) = (A • B) + C 1. A digital logic device used as a buffer consumption
B. A + (B + C) = (A • B) + (A • C) should have what input/output B. good noise immunity, negative
C. A • (B + C) = (A • B) + (A • C) characteristics? logic, high frequency capability,
D. (A + B) + C = A + (B + C) A. high input impedance and high low power dissipation, and
output impedance short propagation time
8. Which output expression might B. low input impedance and high C. slow propagation time, high
indicate a product-of-sums circuit output impedance frequency response, low power
construction? C. low input impedance and low consumption, and high output
output impedance voltage swings
A. D. high input impedance and low D. poor noise immunity, positive
output impedance supply voltage operation, good
B.
2. What is the standard TTL noise low-frequency operation, and
C. margin? low power
A. 5.0 V 9. What quantities must be compatible
D.
B. 0.2 V when interfacing two different logic
9. One of DeMorgan's theorems states C. 0.8 V families?
that . Simply stated, this D. 0.4 V A. only the currents
3. The range of a valid LOW input is:
 INDIABIX 3
B. both the voltages and the A. it cannot be reprogrammed. 3. A logic probe is placed on the output
currents B. its outputs are only active of a gate and the display indicator is dim.
C. only the voltages HIGHs A logic pulser is used on each of the
D. both the power dissipation and C. its outputs are only active input terminals, but the output
the impedance LOWs indication does not change. What is
D. its logic capacity is lost wrong?
10. CMOS logic is probably the best all-
A. The dim indication on the logic
around circuitry because of its: 4. The complex programmable logic
probe indicates that the supply
A. packing density device (CPLD) contains several PLD
voltage is probably low.
B. low power consumption blocks and:
B. The output of the gate
C. very high noise immunity A. field-programmable switches
appears to be open.
D. low power consumption and B. AND/OR arrays
C. The LOW indication is the result
very high noise immunity C. a global interconnection
of a bad ground connection on
matrix
11. Low power consumption achieved by the logic probe.
D. a language compiler
CMOS circuits is due to which D. The gate is a tri-state device.
construction characteristic? 5. PLAs, CPLDs, and FPGAs are all which
4. A +5 V PCB power source that has
A. complementary pairs type of device?
been "pulled down" to a +3.4 V level may
B. connecting pads A. SLD
be due to:
C. DIP packages B. PLD
A. a circuit open
D. small-scale integration C. EPROM
B. a faulty regulator
D. SRAM
12. A TTL totem pole circuit is designed C. the half-split method
so that the output transistors are: 6. The difference between a PLA and a D. a circuit short
A. always on together PAL is:
5. Measurement of pulse width should
B. providing phase splitting A. the PLA has a programmable
be taken at a 50% mean of the:
C. providing voltage regulation OR plane and a programmable
A. overshoot and undershoot
D. never on together AND plane, while the PAL
B. rise and fall
only has a programmable
13. The time needed for an output to C. damping and ringing
AND plane
change as the result of an input change D. leading and trailing amplitude
B. the PAL has a programmable
is known as:
OR plane and a programmable 6. Which test equipment best allows a
A. noise immunity
AND plane, while the PLA only comparison between input and output
B. fanout
has a programmable AND plane signals?
C. propagation delay
C. the PAL has more possible A. an oscilloscope
D. rise time
product terms than the PLA B. a logic probe
D. PALs and PLAs are the same C. a spectrum analyzer
thing. D. a multitrace oscilloscope
PROGRAMMABLE LOGIC
7. The duty cycle of a pulse is
DEVICES (PLD) determined by which formula?
TESTING AND
1. Which type of PLD should be used to TROUBLESHOOTING A. Duty Cycle =
program basic logic functions?
A. PLA 1. A series of gradually decreasing sine B. Duty Cycle =
B. PAL wave oscillations is called:
C. CPLD A. ringing C. Duty Cycle =
D. SLD B. slew
D. Duty Cycle =
C. overshooting
2. The content of a simple
D. undershooting 8. What is the next step after discovering
programmable logic device (PLD)
a faulty gate within an IC?
consists of: 2. The determination of a digital signal's
A. repair the gate
A. fuse-link arrays frequency and waveshape is best
B. resolder the tracks
B. thousands of basic logic gates accomplished with which test
C. replace the IC involved
C. advanced sequential logic equipment?
D. recheck the power source
functions A. an oscilloscope
D. thousands of basic logic gates B. a multimeter 9. The use of a multimeter with digital
and advanced sequential logic C. a spectrum analyzer circuits allows the measurement of:
functions D. a frequency generator A. pulse width
3. Once a PAL has been programmed:
 INDIABIX 3
B. voltage or resistance that occur during the 11. A basic multiplexer principle can be
C. current transmission of codes from one demonstrated through the use of a:
D. pulse trains location to another. A. single-pole relay
10. The use of triggered sweep when C. Parity checking is not suitable B. DPDT switch
using an oscilloscope provides more for detecting single-bit errors in C. rotary switch
accuracy in which area? transmitted codes. D. linear stepper
A. frequency D. Parity checking is capable of
12. In a BCD-to-seven-segment
B. amplitude detecting and correcting errors
converter, why must a code converter be
C. graticule activity in transmitted codes.
utilized?
D. timing
5. A multiplexed display: A. No conversion is necessary.
11. The time needed for a pulse to A. accepts data inputs from one B. to convert the 4-bit BCD into
increase from 10% to 90% of its line and passes this data to gray code
amplitude defines: multiple output lines C. to convert the 4-bit BCD into
A. pulse width B. uses one display to present 10-bit code
B. propagation delay two or more pieces of D. to convert the 4-bit BCD into
C. rise time information 7-bit code
D. duty cycle C. accepts data inputs from
multiple lines and passes this
12. Which device would best aid in FLIP FLOPS AND TIMERS
data to multiple output lines
shorted track detection?
D. accepts data inputs from
A. multimeter
several lines and multiplexes 1. Which of the following is correct for a
B. current tracer
this input data to four BCD lines gated D-type flip-flop?
C. logic pulser
D. oscilloscope 6. When two or more inputs are active A. The Q output is either SET or
simultaneously, the process is called: RESET as soon as the D input
A. first-in, first-out processing goes HIGH or LOW.
COMBINATIONAL LOGIC B. priority encoding B. The output complement follows
the input when enabled.
CIRCUITS C. ripple blanking
D. priority decoding C. Only one of the inputs can be
HIGH at a time.
1. How many inputs are required for a 1- 7. Which type of decoder will select one D. The output toggles if one of the
of-10 BCD decoder? of sixteen outputs, depending on the 4- inputs is held HIGH.
A. 4 bit binary input value?
B. 8 A. hexadecimal 2. When both inputs of a J-K flip-flop
C. 10 B. dual octal outputs cycle, the output will:
D. 1 C. binary-to-hexadecimal A. be invalid
D. hexadecimal-to-binary B. not change
2. Most demultiplexers facilitate which
C. change
of the following? 8. A magnitude comparator determines: D. toggle
A. decimal to hexadecimal A. A ≠ B and if A α B or A >> B
B. single input, multiple outputs B. A ≈ B and if A > B or A < b 3. Latches constructed with NOR and
C. ac to dc C. A = B and if A > B or A < b NAND gates tend to remain in the
D. odd parity to even parity D. A B and if A < b or a > B latched condition due to which
configuration feature?
3. One application of a digital 9. A circuit that responds to a specific set A. asynchronous operation
multiplexer is to facilitate: of signals to produce a related digital B. low input voltages
A. code conversion signal output is called a(n): C. gate impedance
B. parity checking A. BCD matrix D. cross coupling
C. parallel-to-serial data B. display driver
conversion C. encoder 4. The 555 timer can be used in which of
D. data generation D. decoder the following configurations?
A. astable, monostable
4. Select one of the following 10. Which digital system translates B. monostable, bistable
statements that best describes the coded characters into a more intelligible C. astable, toggled
parity method of error detection: form? D. bistable, tristable
A. Parity checking is best suited A. encoder
for detecting single-bit errors B. display 5. A basic S-R flip-flop can be
in transmitted codes. C. counter constructed by cross-coupling which
B. Parity checking is best suited D. decoder basic logic gates?
for detecting double-bit errors A. AND or OR gates
 INDIABIX 3
B. XOR or XNOR gates A. There is no known significance A. PIPO
C. NOR or NAND gates in their designations. B. SISO
D. AND or NOR gates B. The J represents "jump," which C. SIPO
is how the Q output reacts D. PISO
6. One example of the use of an S-R flip- whenever the clock goes HIGH
4. Synchronous counters eliminate the
flop is as a(n): and the J input is also HIGH.
delay problems encountered with
A. transition pulse generator C. The letters represent the initials
asynchronous (ripple) counters because
B. astable oscillator of Johnson and King, the co-
the:
C. racer inventors of the J-K flip-flop.
A. input clock pulses are applied
D. switch debouncer D. All of the other letters of the
only to the first and last
alphabet are already in use.
7. If both inputs of an S-R NAND latch stages
are LOW, what will happen to the 13. Which of the following describes the B. input clock pulses are applied
output? operation of a positive edge-triggered only to the last stage
A. The output would become D-type flip-flop? C. input clock pulses are not used
unpredictable. A. If both inputs are HIGH, the to activate any of the
B. The output will toggle. output will toggle. counter stages
C. The output will reset. B. The output will follow the D. input clock pulses are
D. No change will occur in the input on the leading edge of applied simultaneously to
output. the clock. each stage
C. When both inputs are LOW, an
8. The equation for the output frequency 5. One of the major drawbacks to the
invalid state exists.
of a 555 timer operating in the astable use of asynchronous counters is that:
D. The input is toggled into the
A. low-frequency applications
flip-flop on the leading edge of
mode is: are limited because of
the clock and is passed to the
What value of C1 will be required if R1 = 1 internal propagation delays
output on the trailing edge of
kΩ , R2 = 1 kΩ, and f = 1 kHz? B. high-frequency applications
the clock.
A. 0.33 µF are limited because of
B. 0.48 µF 14. What is one disadvantage of an S-R internal propagation delays
C. 480 µF flip-flop? C. Asynchronous counters do
D. 33 nF A. It has no Enable input. not have major
B. It has a RACE condition. drawbacks and are
9. An astable multivibrator is a circuit
C. It has no clock input. suitable for use in high- and
that:
D. It has only a single output. low-frequency counting
A. has two stable states
applications.
B. is free-running
D. Asynchronous counters do
C. produces a continuous output SEQUENTIAL LOGIC not have propagation
signal
D. is free-running and produces a CIRCUITS delays, which limits their use
in high- frequency
continuous output signal
applications.
10. What is another name for a one- 1. A ripple counter's speed is limited by
the propagation delay of: 6. Which type of device may be used to
shot?
A. each flip-flop interface a parallel data format with
A. monostable
B. all flip-flops and gates external equipment's serial format?
B. bistable
C. the flip-flops only with gates A. key matrix
C. astable
D. only circuit gates B. UART
D. tristable
C. memory chip
11. The truth table for an S-R flip-flop 2. To operate correctly, starting a ring D. serial-in, parallel-out
has how many VALID entries? counter requires:
A. clearing all the flip-flops 7. When the output of a tri-state shift
A. 3
B. presetting one flip-flop and register is disabled, the output level is
B. 1
clearing all the others placed in a:
C. 4
C. clearing one flip-flop and A. float state
D. 2
presetting all the others B. LOW state
12. What is the significance of the J and D. presetting all the flip-flops C. high impedance state
K terminals on the J-K flip-flop? D. float state and a high
3. What type of register would shift a impedance state
complete binary number in one bit at a
time and shift all the stored bits out one 8. A comparison between ring and
bit at a time? johnson counters indicates that:
 INDIABIX 3
A. a ring counter has fewer flip- OPERATIONS AND 8. Use the two's complement system to
flops but requires more add the signed numbers 11110010 and
decoding circuitry CIRCUITS 11110011. Determine, in decimal, the
B. a ring counter has an inverted sign and value of each number and their
feedback path 1. When 1100010 is divided by 0101, sum.
C. a johnson counter has more what will be the decimal remainder? A. –14 and –13; –27
flip-flops but less decoding A. 2 B. –113 and –114; 227
circuitry B. 3 C. –27 and –13; 40
D. a johnson counter has an C. 4 D. –11 and –16; –27
inverted feedback path D. 6
9. The selector inputs to an arithmetic-
9. A sequence of equally spaced timing 2. What are the two types of basic adder logic unit (ALU) determine the:
pulses may be easily generated by which circuits? A. selection of the IC
type of counter circuit? A. half adder and full adder B. arithmetic or logic function
A. shift register sequencer B. half adder and parallel adder C. data word selection
B. clock C. asynchronous and D. clock frequency to be used
C. johnson synchronous
D. one's complement and two's 10. Adding in binary, the decimal values
D. binary
complement 26 + 27 will produce a sum of:
10. What is meant by parallel-loading A. 111010
the register? 3. Adding the two's complement of –11 B. 110110
A. Shifting the data in all flip- + (–2) will yield which two's complement C. 110101
flops simultaneously answer? D. 101011
B. Loading data in two of the A. 1110 1101
B. 1111 1001 11. Binary subtraction of a decimal 15
flip-flops from 43 will utilize which two's
C. Loading data in all four flip- C. 1111 0011
D. 1110 1001 complement?
flops at the same time A. 101011
D. Momentarily disabling the 4. The two's complement system is to B. 110000
synchronous SET and RESET be used to add the signed numbers C. 011100
inputs 11110010 and 11110011. Determine, in D. 110001
11. What is a shift register that will decimal, the sign and value of each
number and their sum. 12. When multiplying in binary the
accept a parallel input and can shift data decimal values 13 × 11, what is the third
left or right called? A. –14 and –13; –27
B. –113 and –114; 227 partial product?
A. tri-state A. 100000
B. end around C. –27 and –13; 40
D. –11 and –16; –27 B. 100001
C. bidirectional universal C. 0000
D. conversion 5. The fast carry or look-ahead carry D. 1011
12. What happens to the parallel output circuits found in most 4-bit parallel-
adder circuits: 13. The range of an 8-bit two's
word in an asynchronous binary down complement word is from:
counter whenever a clock pulse occurs? A. increase ripple delay
B. add a 1 to complemented A. +12810 to –12810
A. The output word decreases B. –12810 to +12710
by 1. inputs
C. reduce propagation delay C. +12810 to –12710
B. The output word decreases by D. +12710 to –12710
2. D. determine sign and magnitude
C. The output word increases by 6. How many basic binary subtraction
1. operations are possible? SEMICONDUCTOR
D. The output word increases by A. 4 MEMORY
2. B. 3
13. Mod-6 and mod-12 counters are C. 2
1. A computerized self-diagnostic for a
most commonly used in: D. 1
ROM test uses:
A. frequency counters 7. How many basic binary subtraction A. the check-sum method
B. multiplexed displays combinations are possible? B. a ROM listing
C. digital clocks A. 4 C. ROM comparisons
D. power consumption B. 3 D. a checkerboard test
C. 2 2. How many storage locations are
ARITHMETIC D. 1 available when a memory device has
twelve address lines?
 INDIABIX 3
A. 144 D. the EEPROM can erase and B. reduced requirement for
B. 512 reprogram individual words constant refreshing of the
C. 2048 without removal from the memory contents
D. 4096 circuit C. reduced pin count and
decrease in package size
3. Which of the following memories uses 8. Which of the following RAM timing
D. no requirement for a chip-
a MOSFET and a capacitor as its parameters determine(s) its operating
select input line, thereby
memory cell? speed?
reducing the pin count
A. SRAM A. tacc
B. DRAM B. taa and tacs
C. ROM C. t1 and t3 ANALOG AND DIGITAL
D. DROM D. trc and twc
CONVERTERS
4. Which of the following best describes 9. Memory that loses its contents when
nonvolatile memory? power is lost is:
A. memory that retains stored A. nonvolatile 1. Which of the following is a type of
information when electrical B. volatile error associated with digital-to-analog
power is removed C. random converters (DACs)?
B. memory that loses stored D. static A. nonmonotonic error
information when electrical B. incorrect output codes
10. Select the best description of the C. offset error
power is removed
fusible-link PROM. D. nonmonotonic and offset
C. magnetic memory
A. user programmable, one- error
D. nonmagnetic memory
time programmable
5. The access time (tacc) of a memory IC B. manufacturer programmable, 2. A 4-bit R/2R digital-to-analog (DAC)
is governed by the IC's: one-time programmable converter has a reference of 5 volts.
A. internal address buffer C. user programmable, What is the analog output for the input
B. internal address decoder reprogrammable code 0101.
C. volatility D. manufacturer programmable, A. 0.3125 V
D. internal address decoder and reprogrammable B. 3.125 V
volatility C. 0.78125 V
11. A nonvolatile type of memory that D. –3.125 V
6. Select the best description of read- can be programmed and erased in
only memory (ROM). sectors, rather than one byte at a time is: 3. A binary-weighted digital-to-analog
A. nonvolatile, used to store A. flash memory converter has an input resistor of 100
information that changes B. EPROM . If the resistor is connected to a 5 V
during system operation C. EEPROM source, the current through the resistor
B. nonvolatile, used to store D. MPROM is:
information that does not A. 50 A
12. Which of the following best
change during system B. 5 mA
describes static memory devices?
operation C. 500 A
A. memory devices that are
C. volatile, used to store D. 50 mA
magnetic in nature and do not
information that changes
require constant refreshing 4. What is the resolution of a digital-to-
during system operation
B. semiconductor memory analog converter (DAC)?
D. volatile, used to store
devices in which stored data A. It is the comparison between
information that does not
is retained as long as power the actual output of the
change during system
is applied converter and its expected
operation
C. memory devices that are output.
7. Advantage(s) of an EEPROM over an magnetic in nature and B. It is the deviation between the
EPROM is (are): require constant refreshing ideal straight-line output and
A. the EPROM can be erased D. semiconductor memory the actual output of the
with ultraviolet light in much devices in which stored data converter.
less time than an EEPROM will not be retained with the C. It is the smallest analog
B. the EEPROM can be erased power applied unless output change that can occur
and reprogrammed without constantly refreshed as a result of an increment in
removal from the circuit the digital input.
13. What is the principal advantage of
C. the EEPROM has the ability to D. It is its ability to resolve
using address multiplexing with DRAM
erase and reprogram between forward and reverse
memory?
individual words
A. reduced memory access time
 INDIABIX 3
steps when sequenced over its 10. The resolution of a 0–5 V 6-bit mnemonic codes are in
entire range. digital-to-analog converter (DAC) is: shorthand English.
A. 63% C. Machine codes are in
5. The practical use of binary-weighted
B. 64% shorthand English, mnemonic
digital-to-analog converters is limited
C. 1.56% codes are in binary.
to:
D. 15.6% D. Machine codes are in
A. R/2R ladder D/A converters
shorthand English, mnemonic
B. 4-bit D/A converters 11. In a flash analog-to-digital converter,
codes are a high-level
C. 8-bit D/A converters the output of each comparator is
language.
D. op-amp comparators educing connected to an input of a:
the pin count A. decoder 3. Which bus is bidirectional?
B. priority encoder A. data bus
6. The difference between analog
C. multiplexer B. control bus
voltage represented by two adjacent
D. demultiplexer C. address bus
digital codes, or the analog step size, is
D. multiplexed bus
the: 12. Which is not an analog-to-digital
A. quantization (ADC) conversion error? 4. The software used to drive
B. accuracy A. differential nonlinearity microprocessor-based systems is called:
C. resolution B. missing code A. assembly language
D. monotonicity C. incorrect code programs
D. offset B. firmware
7. The primary disadvantage of the flash
C. BASIC interpreter instructions
analog-to digital converter (ADC) is that: 13. Sample-and-hold circuits in analog-
D. flowchart instructions
A. it requires the input voltage to to digital converters (ADCs) are
be applied to the inputs designed to: 5. A microprocessor unit, a memory
simultaneously A. sample and hold the output of unit, and an input/output unit form a:
B. a long conversion time is the binary counter during the A. CPU
required conversion process B. compiler
C. a large number of output lines B. stabilize the comparator's C. microcomputer
is required to simultaneously threshold voltage during the D. ALU
decode the input voltage conversion process
6. How many buses are connected as
D. a large number of C. stabilize the input analog
part of the 8085 microprocessor?
comparators is required to signal during the conversion
A. 2
represent a reasonable process
B. 3
sized binary number D. sample and hold the D/A
C. 5
converter staircase waveform
8. A binary-weighted digital-to-analog D. 8
during the conversion process
converter has a feedback resistor, Rf, of
12 k . If 50 A of current is through 7. Which of the following is not a
the resistor, the voltage out of the circuit computer bus?
is:
COMPUTER HARDWARE A. data bus
A. 0.6 V AND SOFTWARE B. timer bus
B. –0.6 V C. control bus
C. 0.1 V D. address bus
1. When referring to instruction words, a
D. –0.1 V mnemonic is: 8. The technique of assigning a memory
9. What is the major advantage of the A. a short abbreviation for the address to each I/O device in the SAM
R/2R ladder digital-to-analog (DAC), as operand address system is called:
compared to a binary-weighted digital- B. a short abbreviation for the A. wired I/O
to-analog DAC converter? operation to be performed B. I/O mapping
A. It only uses two different C. a short abbreviation for the C. dedicated I/O
resistor values. data word stored at the D. memory-mapped I/O
B. It has fewer parts for the same operand address
9. How many bits are used in the data
number of inputs. D. shorthand for machine
bus?
C. Its operation is much easier to language
A. 7
analyze. 2. What is the difference between B. 8
D. The virtual ground is mnemonic codes and machine codes? C. 9
eliminated and the circuit is A. There is no difference. D. 16
therefore easier to understand B. Machine codes are in binary,
and troubleshoot. 10. A port can be:
 INDIABIX 3
A. strictly for input 4. The generic array logic (GAL) device is C. both binary and hexadecimal
B. strictly for output ________. can be used.
C. bidirectional A. one-time programmable D. no clock is needed.
D. all the above B. reprogrammable
12. A decoder converts ________.
C. a CMOS device
11. Which of the following is not a basic A. noncoded information into
D. reprogrammable and a CMOS
element within the microprocessor? coded form
device
A. microcontroller B. coded information into
B. arithmetic-logic unit (ALU) 5. The range of voltages between VL(max) noncoded form
C. temporary register and VH(min) are ________. C. HIGHs to LOWs
D. accumulator A. unknown D. LOWs to HIGHs
B. unnecessary
12. How many bits are used in the 13. A DAC changes ________.
C. unacceptable
address bus? A. an analog signal into digital
D. between 2 V and 5 V
A. 7 data
B. 8 6. What is a digital-to-analog converter? B. digital data into an analog
C. 9 A. It takes the digital signal
D. 16 information from an C. digital data into an amplified
audio CD and converts it to signal
13. Exceptions to the 8085
a usable form. D. none of the above
microprocessor normal operation are
B. It allows the use of cheaper
called: 14. The output of a NOT gate is HIGH
analog techniques, which are
A. jump instructions when ________.
always simpler.
B. decoding A. the input is LOW
C. It stores digital data on a hard
C. interrupts B. the input is HIGH
drive.
D. jump instructions or C. the input changes from LOW to
D. It converts direct current to
interrupts HIGH
alternating current.
D. voltage is removed from the
7. What are the symbols used to
gate
DIGITAL CONCEPTS represent digits in the binary number
system? 15. The output of an OR gate is LOW
A. 0,1 when ________.
1. Any number with an exponent of zero B. 0,1,2
is equal to: C. 0 through 8 A. all inputs are LOW
A. zero D. 1,2 B. any input is LOW
B. one C. any input is HIGH
C. that number 8. A full subtracter circuit requires____.
D. all inputs are HIGH
D. ten A. two inputs and two outputs
B. two inputs and three outputs 16. Which of the following is not an
2. In the decimal numbering system, C. three inputs and one output analog device?
what is the MSD? D. three inputs and two A. Thermocouple
A. The middle digit of a stream of outputs B. Current flow in a circuit
numbers C. Light switch
B. The digit to the right of the 9. The output of an AND gate is LOW
D. Audio microphone
decimal point _____.
C. The last digit on the right A. all the time 17. A demultiplexer has ________.
D. The digit with the most B. when any input is LOW A. one data input and a number
weight C. when any input is HIGH of selection inputs, and they
D. when all inputs are HIGH have several outputs
3. Which of the following statements B. one input and one output
does NOT describe an advantage of 10. Give the decimal value of binary
C. several inputs and several
digital technology? 10010.
outputs
A. The values may vary over a A. 610
D. several inputs and one output
continuous range. B. 910
B. The circuits are less affected C. 1810 18. A flip-flop has ________.
by noise. D. 2010 A. one stable state
C. The operation can be B. no stable states
11. Parallel format means that:
programmed. C. two stable states
A. each digital signal has its
D. Information storage is easy. D. none of the above
own conductor.
B. several digital signals are sent
on each conductor.
 INDIABIX 3
19. Digital signals transmitted on a receiver as there are data C. It allows the use of digital
single conductor (and a ground) must be bits. signals in everyday life.
transmitted in: D. is less expensive than the serial D. It stores information on a CD.
A. slow speed. method of data transmission.
33. A multiplexer has ________.
B. parallel.
26. Convert the fractional decimal A. one input and several outputs
C. analog.
number 6.75 to binary.O B. one input and one output
D. serial.
A. 0111.1100 C. several inputs and several
20. In a certain digital waveform, the B. 0110.1010 outputs
period is four times the pulse width. The C. 0110.1100 D. several inputs and one
duty cycle is ________. D. 0110.0110 output
A. 0%
27. What is one relative disadvantage of 34. What is the decimal value of 23 ?
B. 25%
serial transfer? A. 2
C. 50%
A. It requires too many B. 4
D. 100%
conductors. C. 6
21. In positive logic, ________. B. Its interconnect system is D. 8
A. a HIGH = 1, a LOW = 0 complex.
35. An encoder converts ________.
B. a LOW = 1, a HIGH = 0 C. It is slow.
A. noncoded information into
C. only HIGHs are present D. It can only be used over very
coded form
D. only LOWs are present short distances.
B. coded information into
22. Convert the fractional binary number 28. Which format requires fewer noncoded form
0000.1010 to decimal. conductors? C. HIGHs to LOWs
A. 0.625 A. Parallel D. LOWs to HIGHs
B. 0.50 B. Serial
36. What kind of logic device or circuit is
C. 0.55 C. Both are the same
used to store information?
D. 0.10 D. Cannot tell
A. Counter
23. Digital representations of numerical B. Register
29. A pulse has a period of 15 ms. Its
values of quantities may BEST be C. Inverter
frequency is ________.
described as having characteristics: D. Buffer
A. 6.66 Hz
A. that are difficult to interpret
B. 66.66 Hz 37. PLCC packages have leads on ____.
because they are continuously
C. 666.66 Hz A. one side
changing.
D. 15 Hz B. two sides
B. that vary constantly over a
C. three sides
continuous range of values. 30. Give the decimal value of binary
D. four sides
C. that vary in constant and direct 10000110.
proportion to the A. 13410 38. What is the typical invalid voltage for
values they represent. B. 14410 a binary signal?
D. that vary in discrete steps in C. 11010 A. 0.7–2.8 volts
proportion to the values they D. 12610 B. 0.8–3 volts
represent. C. 0.8–2 volts
31. The rise time is the time it takes a
D. 0.7–2.5 volts
24. A common instrument used in pulse to go from ________.
troubleshooting a digital circuit is a(n) A. the base line to the maximum 39. Convert the fractional binary number
_____. HIGH voltage 0001.0010 to decimal.
A. logic probe B. 10% of the pulse amplitude to A. 1.40
B. oscilloscope the maximum HIGH voltage B. 1.125
C. pulser C. the base line to 90% of the C. 1.20
D. all of the above pulse amplitude D. 1.80
D. 10% of the pulse amplitude
25. The parallel transmission of digital 40. Convert the fractional binary number
to 90% of the pulse
data: 10010.0100 to decimal.
amplitude
A. is much slower than the serial A. 24.50
transmission of data. 32. What is an analog-to-digital B. 18.25
B. requires only one signal line converter? C. 18.40
between sender and receiver. A. It makes digital signals. D. 16.25
C. requires as many signal lines B. It takes analog signals and
41. How many binary bits are necessary
between sender and puts them in digital format.
to represent 748 different numbers?
 INDIABIX 3
A. 9 49. A type of digital circuit technology transmission of codes from one
B. 7 that uses bipolar junction transistors is location to another.
C. 10 ________. B. Parity checking is not suitable
D. 8 A. TTL for detecting single-bit errors in
B. CMOS transmitted codes.
42. A periodic digital waveform has a
C. LSI C. Parity checking is best suited
pulse width (tw) of 6 ms and a period (T)
D. NMOS for detecting single-bit errors
of 18 ms. The duty cycle is ______.
in transmitted codes.
A. 3.3% 50. How many unique symbols are used
D. Parity checking is capable of
B. 33.3% in the decimal number system?
detecting and correcting errors
C. 6% A. One
in transmitted codes.
D. 18% B. Nine
C. Ten 2. A logic circuit that provides a HIGH
43. Any number with an exponent of one
D. Unlimited output for both inputs HIGH or both
is equal to:
inputs LOW is a(n):
A. zero. 51. A classification of ICs with
A. Ex-NOR gate
B. one. complexities of 12 to 100 equivalent
B. OR gate
C. two. gates on a chip is known as ________.
C. Ex-OR gate
D. that number. A. SSI
D. NAND gate
B. MSI
44. Serial format means digital signals
C. LSI 3. A logic circuit that provides a HIGH
are:
D. VLSI output if one input or the other input,
A. sent over many conductors
but not both, is HIGH, is a(n):
simultaneously. 52. Which of the following is a
A. Ex-NOR gate
B. sent over one conductor semiconductor memory?
B. OR gate
sequentially. A. RAM
C. Ex-OR gate
C. sent in groups of eight signals. B. MAR
D. NAND gate
D. sent in binary coded decimal. C. CD-ROM
D. CD 4. Identify the type of gate below from
45. What is the decimal value of 2–1 ?
A. 0.5 53. The holes through a PC board are the equation
B. 0.25 ________. A. Ex-NOR gate
C. 0.05 A. smaller with SMT than with B. OR gate
D. 0.1 through-hole mounting C. Ex-OR gate
B. larger with SMT than with D. NAND gate
46. Which format can send several bits
through-hole mounting 5. How is odd parity generated
of information faster?
C. the same size as with differently from even parity?
A. Parallel
through-hole mounting A. The first output is inverted.
B. Serial
D. usually unnecessary B. The last output is inverted.
C. Both are the same
D. Cannot tell 54. A classification of ICs with 6. Parity systems are defined as
complexities of 100 to 10,000 equivalent either________ or ________ and will add
47. The frequency of a pulse train is 2
gates per chip is known as ______. an extra ________ to the digital
kHz. The pulse period is ________.
A. SSI information being transmitted.
A. 5 ms
B. MSI A. positive, negative, byte
B. 50 ms
C. LSI B. odd, even, bit
C. 500 s
D. VLSI C. upper, lower, digit
D. 2 s
D. on, off, decimal
48. What has happened to the advances
in digital technologies over the past EX-OR AND EX-NOR 7. Which type of gate can be used to add
three decades? two bits?
GATES A. Ex-OR
A. Slowed down considerably
B. Continued to increase, but at a B. Ex-NOR
decreasing rate 1. Select the statement that best C. Ex-NAND
C. Made excellent progress describes the parity method of error D. NOR
D. Nothing short of detection: 8. Why is an exclusive-NOR gate also
phenomenal A. Parity checking is best suited called an equality gate?
for detecting double-bit errors A. The output is false if the inputs
that occur during the are equal.
 INDIABIX 3
B. The output is true if the inputs B. OR operation. C. c
are opposite. C. NOT operation. D. d
C. The output is true if the inputs D. AND operation.
8. In VHDL, the mode of a port does not
are equal.
4. For a three-input OR gate, with the define:
9. Show from the truth table how an input waveforms as shown below, which A. an input.
exclusive-OR gate can be used to invert output waveform is correct? B. an output.
the data on one input if the other input is C. both an input and an output.
a special control function. D. the TYPE of the bit.
A. Using A as the control, when A
9. Which of the following equations
= 0, X is the same as B. When A
would accurately describe a 4-input OR
= 1, X is the same as B.
gate when A = 1, B = 1, C = 0, and D = 0?
B. Using A as the control, when A
A. 1+1+0+0=1
= 0, X is the same as B. When
A. a B. 1 + 1 + 0 + 0 = 01
A = 1, X is the inverse of B.
B. b C. 1+1+0+0=0
C. Using A as the control, when A
C. c D. 1 + 1 + 0 + 0 = 00
= 0, X is the inverse of B. When
A = 1, X is the same as B. D. d 10. Which of the examples below
D. Using A as the control, when A 5. Which of the figures given expresses the distributive law?
= 0, X is the inverse of B. When below represents a NOR gate? A. (A + B) + C = A + (B + C)
A = 1, X is the inverse of B. B. A(B + C) = AB + AC
C. A + (B + C) = AB + AC
10. Determine odd parity for each of the
D. A(BC) = (AB) + C
following data words:
A. a
1011101 11110111 1001101 11. Which of the examples below
B. b
A. P = 1, P = 1, P = 0 expresses the associative law of
C. c
B. P = 0, P = 0, P = 0 addition:
D. d
C. P = 1, P = 1, P = 1 A. A + (B + C) = (A + B) + C
D. P = 0, P = 0, P = 1 6. Which of the figures (a to d) is the B. A + (B + C) = A + (BC)
DeMorgan equivalent of Figure (e)? C. A(BC) = (AB) + C
11. The Ex-NOR is sometimes
D. ABC = A + B + C
called the ________.
A. parity gate 12. How are the statements between
B. equality gate A. a BEGIN and END not evaluated in VHDL?
C. inverted OR B. b A. Constantly
D. parity gate or the equality gate C. c B. Simultaneously
D. d C. Concurrently
D. Sequentially
7. Which of the figures in figure (a to d) is
DESCRIBING LOGIC equivalent to figure (e)? 13. Which logic gate does this truth table
CIRCUITS describe?

1. The format used to present the logic

output for the various combinations of
logic inputs to a gate is called a(n):
A. truth table.
B. input logic function. A. AND
C. Boolean constant. B. OR
D. Boolean variable. C. NAND
D. NOR
2. What is the basic difference between
AHDL and VHDL? 14. For a 3-input NAND gate, with the
A. ADHL is used in all PLD's. input waveforms as shown below, which
B. VHDL is used in all PLD's. output waveform is correct?
C. ADHL is proprietary.
D. VHDL is proprietary.
A. a
3. A small circle on the output of a logic
B. b
gate is used to represent the:
A. Comparator operation.
 INDIABIX 3
A. a D.
B. b
27. Which step in this reduction process
C. c
is using DeMorgan's theorem?
D. d
20. Which of the following is a form of
DeMorgan's theorem?
A.
A. a
B.
B. b
C. c C.
D. d D.
15. Which of the figures given below 21. The logic gate that will have HIGH or
represents a NAND gate? "1" at its output when any one of its A. STEP 1
inputs is HIGH is a(n): B. STEP 2
A. NOR gate C. STEP 3
B. OR gate D. STEP 4
A. a C. AND gate
28. Simplify the expression using
B. b D. NOT operation DeMorgan's theorems.
C. c
D. d 22. Which of the symbols shown below A.
represents an AND gate? B.
16. Which timing diagram shown below
is correct for an inverter? C.
D.
A. a 29. For a three-input NOR gate, with the
B. b input waveforms as shown below, which
C. c output waveform is correct?
D. d
23. For a three-input AND gate, with the
input waveforms as shown below, which
A. a output waveform is correct?
B. b A. a
C. c B. b
D. d C. c
17. A NOR gate with one HIGH input and D. d
one LOW input: 24. An OR gate with inverted inputs A. a
A. will output a HIGH functions as: B. b
B. functions as an AND A. an AND gate. C. c
C. will not function B. a NAND gate. D. d
D. will output a LOW C. a NOR gate.
18. A NAND gate has: D. an inverter. LOGIC GATES
A. active-LOW inputs and an 25. The special software application that
active-HIGH output. translates from HDL into a grid of 1's and 1. The output of an AND gate with three
B. active-LOW inputs and an 0's, which can be loaded into a PLD, is inputs, A, B, and C, is HIGH when
active-LOW output. called a: _______.
C. active-HIGH inputs and an A. formatter. A. A = 1, B = 1, C = 0
active-HIGH output. B. compiler. B. A = 0, B = 0, C = 0
D. active-HIGH inputs and an C. programmable wiring. C. A = 1, B = 1, C = 1
active-LOW output. D. CPU. D. A = 1, B = 0, C = 1
19. Which of the figures given below 26. The Boolean equation for a NOR 2. If a 3-input NOR gate has eight input
represents an OR gate? function is: possibilities, how many of those
A. possibilities will result in a HIGH output?
A. 1
B. B. 2
C. C. 7
 INDIABIX 3
D. 8 A. basic gates, a clock oscillator, there a problem with the circuit and if
and a repetitive waveform so, what is the problem?
3. If a signal passing through a gate is
generator
inhibited by sending a LOW into one of
B. basic gates, a clock oscillator, A. Pin 6 should be ON.
the inputs, and the output is HIGH, the
and a Johnson shift counter B. Pin 8 should be ON.
gate is a(n):
C. basic gates, a clock oscillator, C. Pin 8 should be pulsing.
A. AND
and a DeMorgan pulse D. no problem
B. NAND
generator
C. NOR 17. If a 3-input AND gate has eight input
D. basic gates, a clock oscillator, a
D. OR possibilities, how many of those
repetitive waveform generator,
possibilities will result in a HIGH output?
4. A device used to display one or more and a Johnson shift counter
A. 1
digital signals so that they can be
11. TTL operates from a ________. B. 2
compared to expected timing diagrams
A. 9-volt supply C. 7
for the signals is a:
B. 3-volt supply D. 8
A. DMM
C. 12-volt supply
B. spectrum analyzer 18. The Boolean expression for a 3-input
D. 5-volt supply
C. logic analyzer AND gate is ________.
D. frequency counter 12. The output of a NOR gate is HIGH if A. X = AB
_____. B. X = ABC
5. When used with an IC, what does the
A. all inputs are HIGH C. X=A+B+C
term "QUAD" indicate?
B. any input is HIGH D. X = AB + C
A. 2 circuits
C. any input is LOW
B. 4 circuits 19. A CMOS IC operating from a 3-volt
D. all inputs are LOW
C. 6 circuits supply will consume ________.
D. 8 circuits 13. The switching speed of CMOS is A. less power than a TTL IC
now ________. B. more power than a TTL IC
6. The output of an OR gate with three
A. competitive with TTL C. the same power as a TTL IC
inputs, A, B, and C, is LOW when ____.
B. three times that of TTL D. no power at all
A. A = 0, B = 0, C = 0
B. A = 0, B = 0, C = 1 C. slower than TTL 20. What does the small bubble on the
C. A = 0, B = 1, C = 1 D. twice that of TTL output of the NAND gate logic symbol
D. all of the above 14. The format used to present the logic mean?
output for the various combinations of A. open collector output
7. Which of the following logical
logic inputs to a gate is called a(n): B. tristate
operations is represented by the + sign
A. Boolean constant C. The output is inverted.
in Boolean algebra?
B. Boolean variable D. none of the above
A. inversion
B. AND C. truth table 21. What are the pin numbers of the
C. OR D. input logic function outputs of the gates in a 7432 IC?
D. complementation 15. The power dissipation, PD, of a logic A. 3, 6, 10, and 13
8. Output will be a LOW for any case gate is the product of the ________. B. 1, 4, 10, and 13
when one or more inputs are zero for A. dc supply voltage and the peak C. 3, 6, 8, and 11
a(n): current D. 1, 4, 8, and 11
A. OR gate B. dc supply voltage and the 22. The output of a NOT gate is HIGH
B. NOT gate average supply current when ________.
C. AND gate C. ac supply voltage and the peak A. the input is LOW
D. NOR gate current B. the input is HIGH
9. How many pins does the 4049 IC D. ac supply voltage and the C. power is applied to the gate's IC
have? average supply current D. power is removed from the
A. 14 16. gate's IC
B. 16
23. If the input to a NOT gate is A and
C. 18
the output is X, then ________.
D. 20
A. X=A
10. Which of the following choices meets B.
the minimum requirement needed to C. X=0
create specialized waveforms that are D. none of the above
A logic probe is again applied to the pins
used in digital control and sequencing
of a 7421 IC with the following results. Is
circuits?
 INDIABIX 3
24. A logic probe is used to test the pins D. The gate is a tristate device.
36. One advantage TTL has over CMOS
of a 7411 IC with the following results. Is
29. What is the Boolean expression for a is that TTL is ________.
there a problem with the chip and if so,
three-input AND gate? A. less expensive
what is the problem?
A. X=A+B+C B. not sensitive to electrostatic
B. X=A·B·C discharge
C. A–B–C C. faster
D. A$B$C D. more widely available
30. Which of the following gates 37. A 2-input NOR gate is equivalent to a
has the exact inverse output of the OR ______.
gate for all possible input combinations? A. negative-OR gate
A. Pin 6 should be ON.
A. NOR B. negative-AND gate
B. Pin 6 should be pulsing.
B. NOT C. negative-NAND gate
C. Pin 8 should be ON.
C. NAND D. none of the above
D. no problem
D. AND
38. If a 3-input OR gate has eight input
25. How many inputs of a four-input
31. What is the difference between a possibilities, how many of those
AND gate must be HIGH in order for the
7400 and a 7411 IC? possibilities will result in a HIGH output?
output of the logic gate to go HIGH?
A. 7400 has two four-input NAND A. 1
gates; 7411 has three three- B. 2
A. any one of the inputs
input AND gates C. 7
B. any two of the inputs
B. 7400 has four two-input D. 8
C. any three of the inputs
NAND gates; 7411 has three
D. all four inputs 39. Fan-out is specified in terms of ____.
three- input AND gates
A. voltage
26. If the output of a three-input AND C. 7400 has two four-input AND
B. current
gate must be a logic LOW, what must gates; 7411 has three three-
C. wattage
the condition of the inputs be? input NAND gates
D. unit loads
A. All inputs must be LOW. D. 7400 has four two-input AND
B. All inputs must be HIGH. gates; 7411 has three three- 40. How many input combinations
C. At least one input must be input NAND gates would a truth table have for a six-input
LOW. AND gate?
32. Write the Boolean expression for an
D. At least one input must be A. 32
inverter logic gate with input C and
HIGH. B. 48
output Y.
C. 64
27. Logically, the output of a NOR gate A. Y=C
D. 128
would have the same Boolean
B. Y= 41. What is the circuit number of the IC
expression as a(n):
A. NAND gate immediately 33. The output of an exclusive-OR gate is that contains four two-input AND gates
followed by an inverter HIGH if ________. in standard TTL?
B. OR gate immediately followed A. all inputs are LOW A. 7402
by an inverter B. all inputs are HIGH B. 7404
C. AND gate immediately C. the inputs are unequal C. 7408
followed by an inverter D. none of the above D. 7432
D. NOR gate immediately 42. The terms "low speed" and "high
34. A clock signal with a period of 1 µs is
followed by an inverter speed," applied to logic circuits, refer to
applied to the input of an enable gate.
28. A logic probe is placed on the output The output must contain six pulses. How the ________.
of a gate and the display indicator is dim. long must the enable pulse be active? A. rise time
A pulser is used on each of the input A. Enable must be active for 0µs. B. fall time
terminals, but the output indication does B. Enable must be active for 3µ s. C. propagation delay time
not change. What is wrong? C. Enable must be active for 6µs. D. clock speed
A. The dim indication on the logic D. Enable must be active for 12 µs. 43. The NOR logic gate is the same as
probe indicates that the supply the operation of the ________ gate with
35. The AND function can be used to ___
voltage is probably low. an inverter connected to the output.
and the OR function can be used to ___ .
B. The output of the gate A. OR
A. enable, disable
appears to be open. B. AND
B. disable, enable
C. The dim indication is the result C. NAND
C. enable or disable, enable or
of a bad ground connection on D. none of the above
disable
the logic probe.
D. detect, invert
 INDIABIX 3
44. The logic expression for a NOR C. 3 D. Y=A$B$C$D
gate is _______. D. 4
60. How many truth table entries are
A. 52. Which of the following equations necessary for a four-input circuit?
B. would accurately describe a four-input A. 4
OR gate when A = 1, B = 1, C = 0, and D = B. 8
C.
0? C. 12
D. A. 1 + 1 + 0 + 0 = 01 D. 16
45. With regard to an AND gate, which B. 1+1+0+0=1
61. How many entries would a truth
statement is true? C. 1+1+0+0=0
table for a four-input NAND gate have?
A. An AND gate has two inputs D. 1 + 1 + 0 + 0 = 00
A. 2
and one output. 53. What is the name of a digital circuit B. 8
B. An AND gate has two or more that produces several repetitive digital C. 16
inputs and two outputs. waveforms? D. 32
C. If one input to a 2-input AND A. an inverter 62. The Boolean expression for a 3-input
gate is HIGH, the output B. an OR gate OR gate is ________.
reflects the other input. C. a Johnson shift counter A. X=A+B
D. A 2-input AND gate has eight D. an AND gate B. X=A+B+C
input possibilities. C. X = ABC
54. The basic types of programmable
46. The term "hex inverter" refers to: D. X = A + BC
arrays are made up of ________.
A. an inverter that has six inputs A. AND gates 63. From the truth table for a three-input
B. six inverters in a single B. OR gates NOR gate, what is the only condition of
package C. NAND and NOR gates inputs A, B, and C that will make the
C. a six-input symbolic logic device D. AND gates and OR gates output X high?
D. an inverter that has a history of A. A = 1, B = 1, C = 1
failure 55. The logic gate that will have HIGH or
B. A = 1, B = 0, C = 0
"1" at its output when any one (or more)
47. How many inputs are on the logic C. A = 0, B = 0, C = 1
of its inputs is HIGH is a(n):
gates of a 74HC21 IC? D. A = 0, B = 0, C = 0
A. OR gate
A. 1 B. AND gate 64. The logic gate that will have a LOW
B. 2 C. NOR gate output when any one of its inputs is
C. 3 D. NOT operation HIGH is the:
D. 4 A. NAND gate
56. CMOS IC packages are available in
48. The basic logic gate whose output is B. AND gate
______.
the complement of the input is the: C. NOR gate
A. DIP configuration
A. OR gate D. OR gate
B. SOIC configuration
B. AND gate C. DIP and SOIC configurations 65. The output of a NAND gate is LOW if
C. inverter D. neither DIP nor SOIC ______.
D. comparator configurations A. all inputs are LOW
49. When reading a Boolean expression, B. all inputs are HIGH
57. Which of the following is not a basic
what does the word "NOT" indicate? C. any input is LOW
Boolean operation?
A. the same as D. any input is HIGH
A. OR
B. inversion B. NOT
C. high C. AND
D. low
NUMBER SYSTEMS AND
D. FOR
CODES
50. The output of an exclusive-NOR gate 58. Which of the following gates is
is HIGH if ________. described by the expression ?
A. the inputs are equal A. OR 1. Convert hexadecimal value 16 to
B. one input is HIGH, and the B. AND decimal.
other input is LOW C. NOR A. 2210
C. the inputs are unequal D. NAND B. 1610
D. none of the above C. 1010
59. What is the Boolean expression for a D. 2010
51. How many AND gates are four-input OR gate?
found in a 7411 IC? A. Y=A+B+C+D 2. Convert the following decimal number
A. 1 B. Y = A· B · C · D to 8-bit binary.
B. 2 C. Y=A–B–C–D 187
 INDIABIX 3
A. 101110112 D. 580 MB C. 3
B. 110111012 D. 100
11. Convert 59.7210 to BCD.
C. 101111012
20. The BCD number for decimal 347 is
D. 101111002
A. 111011 ________.
3. Convert binary 111111110010 to B. 01011001.01110010 A. 1100 1011 1000
hexadecimal. C. 1110.11 B. 0011 0100 0111
A. EE216 D. 0101100101110010 C. 0011 0100 0001
B. FF216 D. 1100 1011 0110
12. Convert 8B3F16 to binary.
C. 2FE16
A. 35647 21. The binary number for octal 458 is
D. FD216
B. 011010 ________.
4. Convert the following binary number C. 1011001111100011 A. 100010
to decimal. D. 1000101100111111 B. 100101
010112 C. 110101
13. Which is typically the longest: bit,
A. 11 D. 100100
byte, nibble, word?
B. 35
A. Bit 22. The sum of 11101 + 10111 equals
C. 15
B. Byte ________.
D. 10
C. Nibble A. 110011
5. Convert the binary number 1001.00102 D. Word B. 100001
to decimal. C. 110100
14. Assign the proper odd parity bit to
A. 90.125 D. 100100
the code 111001.
B. 9.125
A. 1111011 23. Convert the following binary number
C. 125
B. 1111001 to decimal.
D. 12.5
C. 0111111 100110102
6. Decode the following ASCII message. D. 0011111 A. 154
1010011101010010101011000100101100 B. 155
15. Convert decimal 64 to binary.
1010000010010001000001101001010001 C. 153
A. 01010010
00 D. 157
B. 01000000
A. STUDYHARD
C. 00110110 24. The decimal number 188 is equal to
B. STUDY HARD
D. 01001000 the binary number ________.
C. stydyhard
A. 10111100
D. study hard 16. Convert hexadecimal value C1 to
B. 0111000
binary.
7. The voltages in digital electronics are C. 1100011
A. 11000001
continuously variable. D. 1111000
B. 1000111
A. True
C. 111000100 25. Convert the following binary number
B. False
D. 111000001 to octal.
8. One hex digit is sometimes referred to 0011010112
17. Convert the following octal number
as a(n): A. 1538
to decimal.
A. byte B. 3518
178
B. nibble C. 2538
A. 51
C. grouping D. 3528
B. 82
D. instruction
C. 57 26. How many bits are in an ASCII
9. Which of the following is the most D. 15 character?
widely used alphanumeric code for A. 16
18. Convert the following binary number
computer input and output? B. 8
to octal.
A. Gray C. 7
0101111002
B. ASCII D. 4
A. 1728
C. Parity
B. 2728 27. A binary number's value changes
D. EBCDIC
C. 1748 most drastically when the ________ is
10. If a typical PC uses a 20-bit address D. 2748 changed.
code, how much memory can the CPU A. MSB
19. How many binary digits are required
address? B. frequency
to count to 10010?
A. 20 MB C. LSB
A. 7
B. 10 MB D. duty cycle
B. 2
C. 1 MB
 INDIABIX 3
28. Convert decimal 213 to binary. 45. Convert the following hexadecimal
37. Convert the following decimal
A. 11001101 number to binary.
number to octal.
B. 11010101 C916
281
C. 01111001
A. 1348
D. 11100011 A. 101110012
B. 4318
B. 101110112
29. The decimal number for octal 748 is C. 3318
C. 100111002
________. D. 1338
D. 110010012
A. 74
38. When using even parity, where is the
B. 60 46. Convert the following decimal
parity bit placed?
C. 22 number to hexadecimal.
A. Before the MSB
D. 62 125
B. After the LSB
A. 7D16
30. The sum of the two BCD numbers, C. In the parity word
B. D716
0011 + 0011, is ________. D. After the odd parity bit
C. 7C16
A. 0110
39. Convert the following octal number D. C716
B. 0111
to decimal.
C. 0011 47. A decimal 11 in BCD is ________.
358
D. 1100 A. 00001011
A. 71
B. 00001100
31. Convert binary 01001110 to decimal. B. 17
C. 00010001
A. 4E C. 92
D. 00010010
B. 78 D. 29
C. 76 48. What is the resultant binary of the
40. Convert binary 11001111 to
D. 116 decimal problem 49 + 01 = ?
hexadecimal.
A. 01010101
32. Which is not a word size? A. 8F16
B. 00110101
A. 64 B. CE16
C. 00110010
B. 28 C. DF16
D. 00110001
C. 16 D. CF16
D. 8 49. The difference of 111 – 001 equals
41. Convert 17318 to decimal.
________.
A. 216.4
33. The octal numbering system: A. 100
B. 985
A. simplifies tasks B. 111
C. 3D9
B. groups binary numbers in C. 001
D. 1123
groups of 4 D. 110
C. saves time 42. An analog signal has a range from 0
50. Convert the binary number 1100 to
D. simplifies tasks and saves V to 5 V. What is the total number of
Gray code.
time analog possibilities within this range?
A. 0011
B. 1010
34. The binary number 1110 is equal to A. 5
C. 1100
the decimal number ________. B. 50
D. 1001
A. 3 C. 250
B. 1 D. infinite 51. The binary number
C. 7 11101011000111010 can be written in
43. Hexadecimal letters A through F are
D. 14 hexadecimal as ________.
used for decimal equivalent values from:
A. DD63A16
35. Convert the following octal number A. 1 through 6
B. 1D63A16
to binary. B. 9 through 14
C. 1D33A16
768 C. 10 through 15
D. 1D63116
A. 1101112 D. 11 through 17
B. 1111102 52. Which of the following is an invalid
44. Convert the following decimal
C. 1111002 BCD code?
number to 8-bit binary.
D. 1001112 A. 0011
35
B. 1101
36. Convert 11001010001101012 to A. 000100102
C. 0101
hexadecimal. B. 000100112
D. 1001
A. 121035 C. 001000112
B. CA35 D. 001000102 53. What decimal number does 25
C. 53AC1 represent?
D. 530121 A. 10
 INDIABIX 3
B. 31 D. 100101100100
62. Convert 45710 to hexadecimal.
C. 25
A. 711 71. Express the decimal number –37 as
D. 32
B. 2C7 an 8-bit number in sign-magnitude.
54. Convert the Gray code 1011 to C. 811 A. 10100101
binary. D. 1C9 B. 00100101
A. 1011 C. 11011000
63. Convert the decimal number 151.75
B. 1010 D. 11010001
to binary.
C. 0100
A. 10000111.11 72. Convert the following BCD number
D. 1101
B. 11010011.01 to decimal. 010101101001bcd
55. Determine the decimal equivalent of C. 00111100.00 A. 539
the signed binary number 11110100 in 1's D. 10010111.11 B. 2551
complement. C. 569
64. Convert the following octal number
A. 116 D. 1552
to binary.1048
B. –12
A. 0010001002 73. The binary number 11001110 is equal
C. 11
B. 1000000012 to the decimal number ______.
D. 128
C. 00101002 A. 12
56. What is the difference between D. 10000012 B. 206
binary coding and binary-coded C. 127
65. 3 × 101 + 7 × 100 is equal to ________.
decimal? D. 66
A. 3.7
A. BCD is pure binary.
B. 37 74. The binary number for F3A16 is ___.
B. Binary coding has a decimal
C. 10 A. 111100111010
format.
D. 370 B. 111100111110
C. BCD has no decimal format.
C. 000000111010
D. Binary coding is pure binary. 66. 3428 is the decimal value for which
D. 000011000100
of the following binary-coded decimal
57. Convert the following decimal
(BCD) groupings? 75. Convert the following BCD number
number to BCD. 127
A. 11010001001000 to decimal. 100000000011bcd
A. 011100100001
B. 11010000101000 A. 8003
B. 111010001
C. 011010010000010 B. 803
C. 001010111
D. 110100001101010 C. 1003
D. 000100100111
D. 103
67. The binary-coded decimal (BCD)
58. Digital electronics is based on the
system can be used to represent each of 76. Convert the following hexadecimal
________ numbering system.
the 10 decimal digits as a(n): number to binary.
A. decimal
A. 4-bit binary code 14B16
B. octal
B. 8-bit binary code A. 1011010000012
C. binary
C. 16-bit binary code B. 0001010010112
D. hexadecimal
D. ASCII code C. 0001010011012
59. An informational signal that makes D. 1101010000012
68. The decimal number 18 is equal to
use of binary digits is considered to be:
the binary number ________. 77. What is the result when a decimal
A. solid state
A. 11110 5238 is converted to base 16?
B. digital
B. 10001 A. 327.375
C. analog
C. 10010 B. 12.166
D. non-oscillating
D. 1111000 C. 1388
60. The 1's complement of 10011101 is D. 1476
69. The 2's complement of 11100111 is
________.
_____. 78. The octal number for binary
A. 01100010
A. 11100110 1101110101110110 is ________.
B. 10011110
B. 00011001 A. 6545218
C. 01100001
C. 00011000 B. 5565618
D. 01100011
D. 00011010 C. 1566568
61. The binary number 101110101111010 D. 1565668
70. Convert the following decimal
can be written in octal as ________.
number to BCD.469 79. Convert the following hexadecimal
A. 515628
A. 100101101000 number to decimal. 1CF16
B. 565778
B. 010001101001 A. 463
C. 656278
C. 100001101001 B. 4033
D. 565728
 INDIABIX 3
C. 479 C. 7 C. 01100001
D. 4049 D. 8 D. 01110101
80. Convert the binary number 1011010 89. Convert the following hexadecimal 96. Select one of the following
to hexadecimal. number to decimal. B516 statements that best describes the
A. 5B A. 212 parity method of error detection.
B. 5F B. 197 A. Parity checking is best
C. 5A C. 165 suited for detecting single-
D. 5C D. 181 bit errors in transmitted
codes.
81. Convert the following decimal 90. The BCD number for decimal 16 is
B. Parity checking is not suitable
number to hexadecimal.74 ______.
for detecting single-bit errors
A. A416 A. 00010110
in transmitted codes.
B. B416 B. 00010000
C. Parity checking is capable of
C. 4A16 C. 00010010
detecting and correcting
D. 4B16 D. 11100000
errors in transmitted codes.
82. Convert hexadecimal C0B to binary. 91. Alphanumeric codes should include D. Parity checking is best suited
A. 110000001011 as a minimum: for detecting double-bit errors
B. 110000001001 A. the capacity to represent the that occur during the
C. 110000001100 alphabet upper- and transmission of codes from
D. 110100001011 lowercase characters one location to another.
and the decimal numbers in
83. Convert binary 1001 to hexadecimal. 97. Which of the following is the primary
a straight binary format.
A. 916 advantage of using the BCD code
B. the capacity to code all
B. 1116 instead of straight binary coding?
possible decimal numbers in a
C. 10116 A. Fewer bits are required to
direct octal representation of
D. 1016 represent a decimal number
BCD codes.
with the BCD code.
84. Convert 73116 to decimal. C. the alphabet upper- and
B. The relative ease of
A. 216.4 lowercase letters, the
converting to and from
B. 985 decimal digits, the seven
decimal.
C. 3D9 punctuation marks, and other
C. BCD codes are easily
D. 1841 characters or symbols.
converted to hexadecimal
D. the ability to represent
85. What is the decimal value of the codes.
decimal numbers greater than
hexadecimal number 777? D. BCD codes are easily
12810 in a straight
A. 191 converted to straight binary
binary format..
B. 1911 codes.
C. 19 92. Convert 52716 to binary.
98. How many BCD code bits and how
D. 19111 A. 343
many straight binary bits would be
B. 001101000111
86. Convert 110010012 (binary) to required to represent the decimal
C. 010100100111
decimal. number 643?
D. 011100100101
A. 201 A. 12 BCD, 12 binary
B. 2001 93. Convert 5278 to binary. B. 12 BCD, 10 binary
C. 20 A. 011100111 C. 12 BCD, 9 binary
D. 210 B. 101010111 D. 16 BCD, 9 binary
C. 343
87. Convert the following decimal 99. When using the repeated division by
D. 111010101
number to octal.39 2 method of converting from decimal to
A. 638 94. The base of the hexadecimal system binary, one must write the first
B. 368 is: remainder as the:
C. 478 A. eight. A. MSB
D. 748 B. sixteen. B. MSB, provided the following
C. ten. sequence of remainders are
88. The American Standard Code for
D. two. written in descending order
Information Interchange (ASCII) uses
until the final remainder is
how many individual pulses for any 95. Assign the proper even parity bit to
achieved.
given character? the code 1100001.
C. LSB
A. 1 A. 11100001
D. LSB, provided the final
B. 2 B. 1100001
remainder is used to replace
 INDIABIX 3
the original LSB, which is then D. D. 5
moved to the MSB position.
6. One of De Morgan's theorems states 13. A truth table for the SOP expression
has how many input
that . Simply stated, this
BOOLEAN AND LOGIC means that logically there is no
combinations?
A. 1
SIMPLIFICATION difference between:
B. 2
A. a NOR and an AND gate with
C. 4
inverted inputs
D. 8
1. Convert the following SOP expression B. a NAND and an OR gate with
to an equivalent POS expression. inverted inputs 14. How many gates would be required
C. an AND and a NOR gate with to implement the following Boolean
A. inverted inputs expression before simplification? XY +
D. a NOR and a NAND gate with X(X + Z) + Y(X + Z)
B. inverted inputs A. 1
C. B. 2
7. The commutative law of Boolean
D. C. 4
addition states that A + B = A × B.
D. 5
A. True
2. Determine the values of A, B, C, and D
B. False 15. Determine the values of A, B, C, and
that make the sum term
8. Applying DeMorgan's theorem to the D that make the product term
equal to zero. equal to 1.
A. A = 1, B = 0, C = 0, D = 0 expression , we get ________.
A. A = 0, B = 1, C = 0, D = 1
B. A = 1, B = 0, C = 1, D = 0 A. B. A = 0, B = 0, C = 0, D = 1
C. A = 0, B = 1, C = 0, D = 0 C. A = 1, B = 1, C = 1, D = 1
D. A = 1, B = 0, C = 1, D = 1 B.
D. A = 0, B = 0, C = 1, D = 0
C.
3. Which of the following expressions is D. 16. What is the primary motivation for
in the sum-of-products (SOP) form? using Boolean algebra to simplify logic
A. (A + B)(C + D) 9. The systematic reduction of logic expressions?
B. (A)B(CD) circuits is accomplished by: A. It may make it easier to
C. AB(CD) A. using Boolean algebra understand the overall
D. AB + CD B. symbolic reduction function of the
C. TTL logic circuit.
4. Derive the Boolean expression for the D. using a truth table B. It may reduce the number of
logic circuit shown below: gates.
10. Which output expression might
indicate a product-of-sums circuit C. It may reduce the number of
construction? inputs required.
D. all of the above
A.
A. 17. How many gates would be required
B. to implement the following Boolean
B. expression after simplification? XY + X(X
C.
+ Z) + Y(X + Z)
C. D. A. 1
B. 2
D. 11. An AND gate with schematic
C. 4
5. From the truth table below, determine "bubbles" on its inputs performs the
D. 5
the standard SOP expression. same function as a(n)________ gate.
A. NOT 18. AC + ABC = AC
B. OR A. True
C. NOR B. False
D. NAND
19. When are the inputs to a
12.For the SOP expression
NAND gate, according to De Morgan's
, how many 1s theorem, the output expression could
are in the truth table's output column? be:
A. A. 1 A. X=A+B
B. B. 2
C. C. 3 B.
 INDIABIX 3
C. X = (A)(B) D. were the first gates to be
D. integrated A. (A)
B. (B)
20. Which Boolean algebra property 26. The truth table for the SOP
C. (C)
allows us to group operands in an expression has how many D. (D)
expression in any order without input combinations?
affecting the results of the operation [for A. 1 32. Derive the Boolean expression for
example, A + B = B + A]? B. 2 the logic circuit shown below:
A. associative C. 4
B. commutative D. 8
C. Boolean 27. Converting the Boolean expression
D. distributive LM + M(NO + PQ) to SOP form, we get
A.
21. Applying DeMorgan's theorem to the ________.
A. LM + MNOPQ B.
expression , we get ___
B. L + MNO + MPQ C.
A. C. LM + M + NO + MPQ
D.
D. LM + MNO + MPQ
B.
33. Which is the correct logic function for
C. 28. A Karnaugh map is a systematic way
this PAL diagram?
of reducing which type of expression?
D. A. product-of-sums
22. When grouping cells within a K-map, B. exclusive NOR
the cells must be combined in groups of C. sum-of-products
________. D. those with overbars
A. 2s 29. The Boolean expression
B. 1, 2, 4, 8, etc.
C. 4s is logically equivalent
D. 3s to what single gate? A.
A. NAND
23. Use Boolean algebra to find the most B. NOR B.
simplified SOP expression for C. AND C.
F = ABD + CD + ACD + ABC + ABCD. D. OR
A. F = ABD + ABC + CD D.
30. Applying the distributive law to the
B. F = CD + AD 34. For the SOP expression ,
expression , we get
C. F = BC + AB how many 0s are in the truth table's
________.
D. F = AC + AD output column?
24. Occasionally, a particular logic A.
expression will be of no consequence in B. A. zero
the operation of a circuit, such as a BCD- C. B. 1
to-decimal converter. These result in C. 4
________terms in the K-map and can be D. D. 5
treated as either ________ or ________, 31. Mapping the SOP expression
35. Mapping the standard SOP
in order to ________ the resulting term. , we get
expression
A. don't care, 1s, 0s, simplify ________.
B. spurious, ANDs, ORs, , we get
eliminate
C. duplicate, 1s, 0s, verify
D. spurious, 1s, 0s, simplify
25. The NAND or NOR gates are referred
to as "universal" gates because either:
A. can be found in almost all
digital circuits
B. can be used to build all the
other types of gates
C. are used in all countries of the
world
 INDIABIX 3
38. Which of the examples below
44. The expression W(X + YZ) can be
expresses the distributive law of Boolean
converted to SOP form by applying
algebra?
which law?
A. associative law
A. (A + B) + C = A + (B + C)
B. commutative law
B. A(B + C) = AB + AC
C. distributive law
C. A + (B + C) = AB + AC
D. none of the above
D. A(BC) = (AB) + C
39. Applying DeMorgan's theorem to the 45. The commutative law of addition
and multiplication indicates that:
expression , we get
A. we can group variables in an
________.
AND or in an OR any way we
A. want
B. an expression can be
B.
expanded by multiplying term
C. by term just the same as in
D. ordinary algebra
C. the way we OR or AND two
40. Which of the following is an variables is unimportant
important feature of the sum-of- because the result is the same
products (SOP) form of expression? D. the factoring of Boolean
A. All logic circuits are reduced expressions requires the
to nothing more than multiplication of product
simple AND and OR terms that contain like
gates. variables
B. The delay times are greatly
reduced over other forms. 46. Which of the following combinations
C. No signal must pass through cannot be combined into K-map groups?
A. (A) A. corners in the same row
B. (B) more than two gates, not
including inverters. B. corners in the same column
C. (C) C. diagonal
D. (D) D. The maximum number of gates
that any signal must pass D. overlapping combinations
36. Which statement below best through is reduced by a factor
describes a Karnaugh map? of two.
A. A Karnaugh map can be used COMBINATIONAL LOGIC
to replace Boolean rules. 41. An OR gate with schematic "bubbles" ANALYSIS
B. The Karnaugh map eliminates on its inputs performs the same
the need for using NAND and functions as a(n)________ gate.
A. NOR 1. Referring to the GAL diagram, which
NOR gates.
B. OR is the correct logic function?
C. Variable complements can be
eliminated by using Karnaugh C. NOT
maps. D. NAND
D. Karnaugh maps provide a 42. Which of the examples below
cookbook approach to expresses the commutative law of
simplifying Boolean multiplication?
expressions. A. A+B=B+A
B. AB = B + A
37. Applying DeMorgan's theorem to the C. AB = BA
expression , we get D. AB = A × B
________. 43. Determine the binary values of the A. ̅𝑩
𝑿 = 𝑩𝑪 + 𝑨 ̅ + 𝑨𝑩
̅ +𝑨̅ 𝑩𝑪
A. variables for which the following B. ̅ ̅ ̅ ̅
𝑋 = 𝐵𝐶 + 𝐴𝐵 + 𝐴𝐵 + 𝐴𝐵𝐶
B. standard POS expression is equal to 0. C. 𝑋 = 𝐵𝐶 + 𝐴̅𝐵̅ + 𝐴̅𝐵 + 𝐴̅𝐵𝐶
C. D. 𝑋 = 𝐵𝐶 + 𝐴̅𝐵̅ + 𝐴𝐵̅ + 𝐴̅𝐵 𝐶̅
A. (0 + 1 + 0)(1 + 0 + 1)
D. B. (1 + 1 + 1)(0 + 0 + 0) 2. The output of an exclusive-NOR gate
C. (0 + 0 + 0)(1 + 0 + 1) is 1. Which input combination is correct?
D. (1 + 1 + 0)(1 + 0 + 0) A. A = 1, B = 0
 INDIABIX 3
B. A = 0, B = 1 A. 1 B. three AND gates and four
C. A = 0, B = 0 B. 2 inverters
D. none of the above C. 4 C. three AND gates
D. 5 D. one AND gate
3. The Boolean SOP expression obtained
from the truth table below is ________. 7. The following waveform pattern is for 12. One positive pulse with tw = 75 µs is
a(n) ________. applied to one of the inputs of an
exclusive-OR circuit. A second positive
pulse with tw = 15 µs is applied to the
other input beginning 20 µs after the
leading edge of the first pulse. Which
A. 2-input AND gate statement describes the output in
B. 2-input OR gate relation to the inputs?
C. Exclusive-OR gate A. The exclusive-OR output is a 20
D. None of the above µs pulse followed by a 40 s
A. 𝐴𝐵𝐶 + 𝐴𝐵𝐶
pulse, with a separation of 15
B. 𝐴𝐵̅ 𝐶 + 𝐴𝐵𝐶̅
̅𝑩 ̅
̅ 𝑪 + 𝑨𝑩𝑪 8. Implementing the expression 𝑋 = µs between the pulses.
C. 𝑨
B. The exclusive-OR output is a 20
D. None of these 𝐴̅𝐵̅ + (𝐶 + 𝐷 + 𝐸) with NOR logic, we
µs pulse followed by a 15 µs
get:
pulse, with a separation of 40
4. The 8-input XOR circuit shown has an
µs between the pulses.
output of Y = 1. Which input
C. The exclusive-OR output is a 15
combination below (ordered A – H) is
µs pulse followed by a 40 µs
correct?
pulse.
D. *The exclusive-OR output is a
20 µs pulse followed by a 15 µs
pulse, followed by a 40 µs
pulse.
A. (A)
13. How many AND gates are required to
B. (B)
implement the Boolean expression, 𝑋 =
C. (C)
𝐴𝐵𝐶̅ + 𝐴𝐵̅ 𝐶 + 𝐴̅𝐵𝐶 ?
D. (D)
A. 1
A. 10111100 B. 2
9. A 4-variable AND-OR-Invert circuit
C. 3
B. 10111000 produces a 0 at its Y output. Which
D. 4
C. 11100111 combination of inputs is correct?
D. 00011101 A. 𝐴̅𝐵 + 𝐶̅ 𝐷 14. How many NOT gates are required to
5. Implementing the expression AB + B. 𝐴̅𝐵̅ + 𝐶̅ 𝐷
̅ implement the Boolean expression, 𝑋 =
CDE using NAND logic, we get: C. ̅𝑩
𝑨 ̅ + 𝑪𝑫 𝐴𝐵̅ 𝐶 + 𝐴̅𝐵𝐶 ?
D. None of these A. 1
B. 2
10. The following waveform pattern is C. 4
for a(n) ________. D. 5

15. The inverter can be produced with

how many NAND gates?
A. 1
B. 2
A. 2-input AND gate C. 3
B. 2-input OR gate D. 4
A. (A) C. Exclusive-OR gate
B. (B) D. None of the above 16. A 4-variable AND-OR circuit
C. (C) produces a 0 at its Y output. Which
D. (D) 11. To implement the expression combination of inputs is correct?
𝐴𝐵̅ 𝐶𝐷 + 𝐴𝐵𝐶̅ 𝐷 + 𝐴𝐵𝐶𝐷̅ , it takes one A. A = 0, B = 0, C = 1, D = 1
6. Before an SOP implementation, the OR gate and ________. B. A = 1, B = 1, C = 0, D = 0
expression 𝑋 = 𝐴𝐵(𝐶̅ 𝐷 + 𝐸𝐹) would A. three AND gates and three C. A = 1, B = 1, C = 1, D = 1
require a total of how many gates? inverters D. A = 1, B = 0, C = 1, D = 0
 INDIABIX 3
A. Strain gauge
17. A 4-variable AND-OR circuit B. Thermistor
produces a 1 at its Y output. Which C. Negative-type RTD
combination of inputs is correct? D. Thermocouple
A. A = 0, B = 0, C = 0, D = 0
2. The resistive change of a strain gauge
B. A = 0, B = 1, C = 1, D = 0
A. 2-input AND gate A. is based on the weight placed
C. A = 1, B = 1, C = 0, D = 0
B. 2-input OR gate upon it, but can be many
D. A = 1, B = 0, C = 0, D = 0
C. Exclusive-OR gate thousands of ohms
D. None of the above B. is usually no more than 100 Ω
18. Implementing the expression
C. is based on the gauge factor,
(𝐴̅ + 𝐵̅ )𝐶𝐷𝐸 using NAND logic, we get: but is typically less than an
21. Implementation of the Boolean
ohm
expression 𝑋 = 𝐴𝐵𝐶 + 𝐴𝐵 + 𝐴𝐶̅ results
D. has a positive temperature
in ________.
coefficient
A. three AND gates, one OR gate
B. three AND gates, one NOT 3. The silicon-controlled rectifier can be
gate, one OR gate turned off
C. three AND gates, one NOT A. by a negative gate pulse
gate, three OR gates B. by forced commutation
D. three AND gates, three OR C. with the off switch
gates D. when the breakover voltage is
exceeded
22. One possible output expression for
4. The output voltage of a typical
an AND-OR-Invert circuit having one
thermocouple is
AND gate with inputs A, B, and C and
A. less than 100 mV
one AND gate with inputs D and E is
B. greater than 1 V
________.
C. Thermocouples vary resistance,
A. 𝐴𝐵𝐶 + 𝐷𝐸
not voltage.
B. 𝐴̅ + 𝐵̅ + 𝐶̅ + 𝐷 ̅ + 𝐸̅
̅+𝑩 ̅ +𝑪 ̅)( 𝑫̅ +𝑬 ̅) D. None of the above
C. (𝑨
D. ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵 + 𝐶)(𝐷 + 𝐸) 5. The connections to a thermocouple
A. can produce an unwanted
23. How many 2-input NOR gates does it thermocouple effect, which
take to produce a 2-input NAND gate? must be compensated for
A. 1 B. produce an extra desirable
A. (A) B. 2 thermocouple effect
B. (B) C. 3 C. must be protected, since high
C. (C) D. 4 voltages are present
D. (D) D. produce an extra desirable
19. Implementing the expression 𝐴̅ + 24. A logic circuit with an output 𝑋 = thermocouple effect and must
𝐵̅ + 𝐶𝐷 using NAND logic, we get: 𝐴̅𝐵𝐶 + 𝐴𝐵̅ consists of ________. be protected, since high
A. two AND gates, two OR gates, voltages are present
two inverters
6. What is the zero-voltage switch used
B. three AND gates, two OR gates,
for?
one inverter
A. To reduce radiation of high
C. two AND gates, one OR gate,
frequencies during turn-on of
two inverters
a high current to a load
D. two AND gates, one OR gate
B. To control low-voltage circuits
C. To provide power to a circuit
A. (A) when power is lost
B. (B) D. For extremely low-voltage
C. (C) MEASUREMENT, applications
D. (D) CONVERSION AND
CONTROL 7. Temperature sensing can be achieved
20. The following waveform pattern is by the use of
for a(n) ________. A. thermocouples
1. What device is similar to an RTD but
has a negative temperature coefficient? B. RTDs
 INDIABIX 3
C. thermistors D. fixed and variable
D. All of the above 1. The resistivity of copper is:
10. How many connections does a
A. 9.9 Ω
8. The purpose of compensation for a potentiometer have?
B. 10.7 Ω
thermocouple is A. 1
C. 16.7 Ω
A. to decrease temperature B. 2
D. 17.0 Ω
sensitivity C. 3
B. to increase voltage output 2. How do fixed resistors usually fail? D. 4
C. to cancel unwanted voltage A. slowly over time
11. What current is flowing in the circuit?
output of a thermocouple B. by increasing their value
D. used for high-temperature C. by becoming an open circuit
circuits D. by increasing their value and
9. The change in value of an analog becoming an open circuit
signal during the conversion process 3. With Ohm's law, if voltage increases
produces what is called the A. 288 kA
and resistance stays the same: B. 2 kA
A. quantization error A. current remains the same C. 50 mA
B. resolution error B. power decreases D. 500 µa
C. Nyquist error C. current increases 12. The six basic forms of energy are:
D. sampling error D. resistance decreases A. light, sun, magnetic, chemical,
10. Which of the following performance electrical, and mechanical
4. Which formula shows a direct B. electrical, mechanical, light,
specifications applies to a sample-and- proportionality between power and
hold circuit? heat, magnetic, and chemical
voltage? C. electrical, mechanical, sun,
A. Aperture time A. V = IR
B. Aperture droop heat, chemical, and light
B. P = VI D. potential, sun, light, chemical,
C. Feedback C. P = IR
D. Acquisition jitter electrical, and mechanical
D. I = V/R
11. RTDs are typically connected with 13. How much energy is stored if 6.24 x
5. With 1 mA of current, what wattage 1018 electrons are stored in 4 volts?
other fixed resistors rating should a 470 ohm resistor have?
A. in a pi configuration A. 4 joules
A. 1/4 watt B. 1.56 x 1018 electrons
B. in a bridge configuration B. 1/2 watt
C. and variable resistors C. 1.56 coulombs
C. 1 watt D. 2.496 x 1019 electrons
D. and capacitors in a filter-type D. 2 watts
circuit 14. With Ohm's law:
6. How is a 3.9 k Ω resistor color-coded? A. current is inversely
12. Holding current for an SCR is best A. red, white, red, gold proportional to resistance
described as B. red, green, orange, silver B. resistance is directly
A. the minimum current required C. orange, white, red, gold proportional to voltage
for turn-off D. orange, green, orange, silver C. voltage is indirectly
B. the current required before an 7. What resistor type is found in SIPs and proportional to power
SCR will turn on DIPs? D. current is directly proportional
C. the amount of current A. metal film to resistance
required to maintain B. wirewound
conduction C. metal oxide 15. Power is defined as:
D. the gate current required to D. thick film A. the rate at which energy is
maintain conduction used
8. Ohm's law is not: B. watts
13. What is the moving part of a linear A. V = IR C. energy
variable differential transformer? B. I = V/R D. the rate at which energy is
C. R = IV generated
A. Primary D. R = V/I
B. Secondary 16. What is the most commonly used
C. Diaphragm 9. What are the two major categories conductor in electronics?
D. Core for resistors? A. aluminum
A. low and high ohmic value B. copper
B. commercial and industrial C. gold
RESISTANCE AND POWER C. low and high power value D. silver
 INDIABIX 3
24. If a variable resistor's resistance 32. The source is 24 volts and the load
17. With Ohm's law, no change in
varies in a nonuniform manner as the resistance is 100 Ω. What is the load
resistance means that current and
shaft is moved, it is considered to be: current?
voltage will be:
A. linear A. 2.4 A
A. directly proportional
B. defective B. 240 mA
B. unable to produce energy
C. not wirewound C. 24 mA
C. the same
D. tapered D. 2.4 mA
D. inversely proportional
25. Power is measured in units of: 33. Resistors are identified as to wattage
18. A potentiometer has how many
A. joules x charge by:
leads?
B. joules/work A. size
A. 1
C. joules x voltage B. color code
B. 2
D. joules/time C. types of materials
C. 3
D. internal construction
D. 4 26. How many basic types of resistors
exist? 34. What type of resistors have a
19. What is the ratio of 13 to 47 A. 1 tolerance rating of 5% or greater?
expressed in percent? B. 2 A. precision
A. 2.76% C. 3 B. SIP
B. 27.7% D. 4 C. general-purpose
C. 3.60% D. wirewound
D. 36.1% 27. With a complex circuit, a supply
source senses: 35. Resistor tolerance is either printed on
20. What happens to current and A. open circuit components the component, or is provided by:
resistance if the voltage doubles? B. when voltages need to be A. keyed containers
A. Current doubles and resistance increased B. size
doubles. C. only a single resistive C. color code
connection D. ohmmeter reading
B. Current doubles and resistance
D. when complex currents are
is halved. 36. How many connections does a
needed
C. Current remains the same and rheostat have?
28. How many ohms of resistance allows A. 1
resistance doubles.
a current of 720 µA to flow when 3.6 kV B. 2
D. Current doubles and
is applied? C. 3
resistance remains the A. 200 n Ω D. 4
same. B. 5kΩ
37. What are the parts of a rheostat?
21. One problem with mechanically C. 200 k Ω
A. wiper and resistor track
variable resistors is noticeable in audio D. 5MΩ
B. solenoid and armature
circuits as:
29. Which is the most important step C. contact and wire wound
A. scratchy noise
utilized when measuring resistors? D. center tape and wiper
B. lack of bass response
A. use the highest possible scale
C. variable volume 38. The load resistance increases. How
B. keep test leads short
D. too much treble response will the load current change?
C. zero the meter before using
A. vary
22. A color code of orange, orange, D. remove power from the circuit
B. remain constant
orange is for what ohmic value?
30. Components designed to oppose the C. increase
A. 22 kilohms
flow of current are called: D. decrease
B. 3300 ohms
A. insulators
C. 44000 ohms 39. What is the power dissipated by a 1.2
B. conductors
D. 33 kilohms k Ω resistor with 12 volts across it?
C. resistors
A. 12 W
23. A conductor's cross-sectional area in D. heat exchangers
B. 1.2 W
circular mils for 1/2 inch is:
31. How many amps are used by a 100 C. .12 W
watt, 120 volt light bulb? D. 12 mW
A. 500 cmils
A. 1.2 amps 40. How many joules of energy will a 10
B. 100,000 cmils
B. 12000 amps W lamp dissipate in one minute?
C. 1,000,000 cmils
C. 830 mA A. 10 joules
D. 500,000,000 cmils
D. 12 amps B. 60 joules
C. 600 joules
D. 3600 joules
 INDIABIX 3
A. cold resistance 57. Wirewound resistors are usually used
41. Which type of test equipment is used B. hot resistance in circuits that have:
to measure resistors? C. ballast resistance A. high current
A. ohmmeter D. both cold and hot resistance B. negative temperature
B. ammeter coefficients
50. One advantage of a carbon film
C. voltmeter C. low power
resistor over a carbon composition
D. watt meter D. high voltage
resistor is:
42. Resistance is: A. less circuit noise 58. How is power dissipated in a resistor?
A. the opposition to current flow B. smaller size A. by resistance
accompanied by the C. higher wattage B. by voltage
dissipation of heat D. poor tolerance C. by current
B. symbolized by R, measured in D. by heat
51. If a metallic conductor has a positive
ohms, and directly proportional
temperature coefficient of resistance, 59. Resistance in a circuit is:
to conductance
then: A. opposition to current
C. directly proportional to current
A. as temperature increases, B. opposition to voltage
and voltage
resistance decreases C. the same as current
D. represented by the flow of fluid
B. as current increases, resistance D. the same as voltage
in the fluid circuit
decreases
60. The unit designator for resistance
43. Electrical equipment is protected C. as voltage increases, current
value is the:
against excessive current by a(n): increases
A. ampere
A. fusible wire link D. as temperature increases,
B. ohm
B. insulated glass container resistance increases
C. volt
C. metal ended coil
52. What value of a ±5% 1.3 k Ω resistor D. watt
D. circuit opener
as measured by a digital voltmeter
61. One ampere of current flowing
44. If resistance decreases, then current would be considered within tolerance?
through one ohm of resistance is equal
will: A. 1234 Ω
to:
A. decrease B. 1235 Ω
A. 1 horsepower
B. increase C. 1366 Ω
B. 1 Btu
C. remain the same D. 1367 Ω
C. 1 watt
D. double
53. If a calculator display was "0.00263," D. 1 joule
45. A wire with a smaller cross-sectional what would this answer be in percent?
62. Good insulators:
area will produce: A. 0.026%
A. have few electrons in their
A. less heat B. 0.26%
outer shells
B. more conductance C. 2.63%
B. have a large dielectric
C. less resistance D. 26.3%
strength
D. more heat
54. A 33 kΩ resistor with a 20% tolerance C. have a small breakdown voltage
46. A 22-gauge wire will have a diameter checks out as ok with which of the D. have many electrons in the
in mils of: following ohmmeter readings? nucleus
A. 10.03 A. 26400 ohms
B. 22.35 B. 24183 ohms
C. 45.26 C. 6600 ohms
ALTERNATING CURRENT
D. 71.96 D. 39970 ohms VS DIRECT CURRENT
47. The word work means that: 55. For P = V2/R, a decrease in resistance
1. What are the two main applications
A. energy has been transferred should produce:
for ac?
B. it is inversely related to energy A. a decrease in power
A. direct, pulsating
C. no energy has been transferred B. an increase in ohms
B. electric, magnetic
D. work and energy are not related C. an increase in power
C. power, information
D. a decrease in current
48. A good fuse will have: D. static, dynamic
A. zero ohms resistance 56. After a lamp is turned on, its filament 2. The distance that a signal's energy can
B. a medium resistance resistance will change to become: travel in the time it takes for one cycle to
C. a high resistance A. less resistive occur is called the signal's:
D. an infinite resistance B. cooler A. amplitude
C. brighter B. frequency
49. What property does an incandescent
D. more resistive C. wavelength
lamp possess?
 INDIABIX 3
D. period A. 90° B. 1000 Hz
B. 0° C. 10 kHz
3. One oscilloscope selector knob that
C. –90° D. 100 kHz
allows the major and minor divisions of
D. 360°
the graticule to be used to determine a 18. The phase difference between sine
signal amplitude value is called the: 11. Which percentages of full-amplitude waves of different frequencies is:
A. time/cm control rise time are used for a pulse wave? A. equal to their frequency
B. position control A. 0 to 50 percent differences
C. intensity control B. 0 to 100 percent B. the difference in their fixed
D. volts/cm control C. 5 to 95 percent time displacement
D. 10 to 90 percent C. the same throughout time
4. If current varies periodically from zero
D. constantly changing
to a maximum, back to zero, and then 12. What is the average value of a 12 V
repeats, the signal is: peak wave? 19. If a sine wave signal is 100 mV peak-
A. direct A. 3.82 V to-peak, how many volts would be
B. alternating B. 4.24 V measured by a voltmeter?
C. pulsating C. 7.64 V A. 14.14 mV
D. repetitive D. 9.42 V B. 35.4 mV
C. 63.7 mV
5. What voltage will an ac voltmeter 13. A test equipment item that has the
D. 70.7 mV
display? ability to produce either square,
A. rms triangular, or sawtooth waveforms is 20. What term expresses the frequency
B. average called: of a rectangular wave?
C. peak A. a function generator
D. peak-to-peak B. a radio frequency generator A. Hz
C. an audio frequency generator B. period
6. What is the peak value of a household
D. a frequency meter or counter C. PRF
appliance that uses a 230 V ac source?
D. PRT
A. 163 V 14. The current is flowing in what
B. 230 V direction? 21. AC effective voltage is named:
C. 325 V
D. 480 V A. average
B. peak
7. What is the waveform period
C. peak-to-peak
difference between the 60 Hz electricity
D. root mean square
used in this country and the 50 Hz used A. clockwise
in Europe? B. counterclockwise 22. If a voltmeter measures a sine wave
A. 3 ms C. in both directions at the same as 500 mV, what would be its average
B. 16 ms time value?
C. 4 ms D. 50% of the time clockwise and A. 159.0 mV
D. 20 ms 50% of the time B. 318.5 mV
counterclockwise C. 353.5 mV
8. Test equipment selection enables the
D. 451.0 mv
technician to both generate signals and: 15. What does the CRT oscilloscope
A. change circuit conditions display? 23. One adjustable knob on the
B. inject signals A. voltage and period oscilloscope that allows the trace to be
C. sense circuit conditions B. current and frequency aligned with a reference graticule is
D. change signal frequencies C. rms voltage and current called the:
D. frequency and voltage A. position control
9. Why is ac current transfer more B. focus control
effective than dc current transfer over 16. Power companies supply ac, not dc,
C. intensity control
long distances? because:
D. volts/cm control
A. due to the height of power lines A. it is easier to transmit ac
B. due to the use of ac generators B. there is no longer a need for dc 24. Signal comparisons may be most
C. due to step-up and step-down C. dc is more dangerous easily seen when using which item of
transformers reducing I2R D. there are not enough batteries test equipment?
losses A. spectrum analyzer
17. If a waveform period is determined to
D. due to very high voltages B. multimeter
be 10 microseconds in duration, what is
C. function generator
10. A sine wave reaches maximum the frequency of the signal?
D. dual trace oscilloscope
positive voltage at: A. 100 Hz
 INDIABIX 3
25. The magnitude that an alternation D. cannot tell B. 62.5 ns
varies from zero is called its: C. 31.25 ns
33. What is the rms voltage value of an
A. altitude D. 19.9 ns
ac signal whose peak oscilloscope
B. amplitude
display uses 3 major divisions above the
C. attitude
zero setting? (V/cm = 5) SEMICONDUCTOR
D. polarity
A. 5.3 V
26. The power that is distributed from a B. 10.6 V PRINCIPLE
power plant to your home is: C. 15.0 V
A. high voltage to high voltage D. 21.2 V 1. Intrinsic semiconductor material is
B. low voltage to high voltage characterized by a valence shell of how
34. What is the peak-to-peak current
C. high voltage to low voltage many electrons?
value when an ammeter measures a 20
D. low voltage to low voltage A. 1
mA value?
27. A rectangular wave that has a duty A. 14 mA B. 2
cycle of 50 percent could be called a: B. 28 mA C. 4
A. c wave C. 40 mA D. 6
B. sawtooth wave D. 57 mA 2. Ionization within a P-N junction
C. square wave causes a layer on each side of the barrier
35. How long would it take to transmit
D. triangle wave called the:
an electromagnetic wave to a receiving
28. A triangle wave consists of antenna 1,000 miles away? A. junction
repeating: A. 5.38 ms B. depletion region
A. positive ramps only B. 10.8 ms C. barrier voltage
B. negative ramps only C. 53.8 ms D. forward voltage
C. positive and negative ramps of D. 108 ms
equal value 3. What is the most significant
36. What is the waveform period of a development in electronics since World
D. positive and negative ramps of
square wave signal that horizontally War II?
unequal value
covers 3 major divisions per cycle? A. the development of color TV
29. What is the name of a device used to (time/cm = 50 ms) B. the development of the diode
directly measure the frequency of a A. 50 ms C. the development of the
periodic wave? B. 100 ms transistor
A. oscilloscope C. 150 ms D. the development of the
B. frequency meter or counter D. 200 ms TRIAC
C. audio frequency generator
37. A sine wave has:
D. radio frequency generator 4. What causes the depletion region?
A. four quadrants
30. Which control should be moved B. two alternations A. doping
to display more cycles of a signal on an C. one period B. diffusion
oscilloscope? D. all of the above C. barrier potential
A. horizontal position to left or D. ions
38. What is the peak-to peak voltage of a
right 5. What is an energy gap?
56 Vrms ac voltage?
B. volts/cm to a smaller number A. the space between two orbital
A. 158 V
C. vertical position to top or shells
B. 164 V
bottom B. the energy equal to the energy
C. 82 V
D. time/cm to a higher setting acquired by an electron passing
D. 79 V
31. What is the name of a device that a 1 V electric field
39. One oscilloscope selector knob that C. the energy band in which
converts sound waves to electrical
allows the major and minor divisions of electrons can move freely
waves?
the graticule to be used to determine a D. an energy level at which an
A. an amplifier
waveform period is called a: electron can exist
B. an antenna
C. a filter 6. Silicon atoms combine into an orderly
A. focus control
D. a microphone pattern called a:
B. time/cm control
32. If the frequency of a radio wave is C. intensity control A. covalent bond
increased, then its wavelength will: D. volts/cm control B. crystal
A. increase C. semiconductor
40. What is the period of a 16 MHz sine D. valence orbit
B. decrease
wave?
C. remain the same
A. 196 ns
 INDIABIX 3
7. In "n" type material, majority carriers C. tin D. forward bias
would be: D. carbon
24. What is the voltage across R1 if the
A. holes
16. When and who discovered that more P-N junction is made of silicon?
B. dopants
than one transistor could be constructed
C. slower
on a single piece of semiconductor
D. electrons
material:
8. Elements with 1, 2, or 3 valence A. 1949, William Schockley
electrons usually make excellent: B. 1955, Walter Bratten
A. conductors C. 1959, Robert Noyce
B. semiconductors D. 1960, John Bardeen A. 12 V
C. insulators B. 11.7 V
17. When is a P-N junction formed? C. 11.3 V
D. neutral
A. in a depletion region D. 0V
9. A commonly used pentavalent B. in a large reverse biased region
material is: C. the point at which two 25. If conductance increases as
A. arsenic opposite doped temperature increases, this is known as
B. boron materials come together a:
C. gallium D. whenever there is a forward A. positive coefficient
D. neon voltage drop B. negative current flow
C. negative coefficient
10. Which material may also be 18. A P-N junction mimics a closed D. positive resistance
considered a semiconductor element? switch when it:
A. carbon A. has a low junction resistance 26. Which of the following cannot
B. ceramic B. is reverse biased actually move?
C. mica C. cannot overcome its barrier
D. argon voltage A. majority carriers
D. has a wide depletion region B. ions
11. In "p" type material, minority carriers C. holes
would be: 19. Solid state devices were first D. free electrons
A. holes manufactured during:
B. dopants A. World War 2 27. What electrical characteristic of
C. slower B. 1904 intrinsic semiconductor material is
D. electrons C. 1907 controlled by the addition of impurities?
D. 1960 A. conductivity
12. What can a semiconductor sense? B. resistance
A. magnetism 20. Electron pair bonding occurs when C. power
B. temperature atoms: D. all of the above
C. pressure A. lack electrons
D. all of the above B. share holes
C. lack holes
BIPOLAR JUNTION
13. When an electron jumps from the D. share electrons TRANSISTORS (BJT)
valence shell to the conduction band, it
21. How many valence electrons are in
leaves a gap. What is this gap called? 1. When transistors are used in digital
every semiconductor material?
A. energy gap circuits they usually operate in the:
A. 1
B. hole A. active region
B. 2
C. electron-hole pair B. breakdown region
C. 3
D. recombination C. saturation and cutoff regions
D. 4
D. linear region
14. Forward bias of a silicon P-N junction
22. What is a type of doping material?
will produce a barrier voltage of 2. Three different Q points are shown on
A. extrinsic semiconductor
approximately how many volts? a dc load line. The upper Q point
material
A. 0.2 represents the:
B. pentavalent material
B. 0.3 A. minimum current gain
C. n-type semiconductor
C. 0.7 B. intermediate current gain
D. majority carriers
D. 0.8 C. maximum current gain
23. Minority carriers are many times D. cutoff point
15. Which semiconductor material is
activated by:
made from coal ash? 3. A transistor has a 𝛽𝐷𝐶 of 250 and a
A. heat
A. germanium base current, IB, of 20 µA. The collector
B. pressure
B. silicon current, IC, equals:
C. dopants
 INDIABIX 3
A. 500 µA 11. The C-B configuration is used to
18. When a silicon diode is forward
B. 5 mA provide which type of gain?
biased, what is VBE for a C-E
C. 50 mA A. voltage
configuration?
D. 5A B. current
A. voltage-divider bias
C. resistance
4. A current ratio of IC/IE is usually less B. 0.4 V
D. power
than one and is called: C. 0.7 V
A. beta 12. The Q point on a load line may be D. emitter voltage
B. theta used to determine:
19. What is the current gain for a
C. alpha A. VC
common-base configuration where IE =
D. omega B. VCC
4.2 mA and IC = 4.0 mA?
C. VB
5. With the positive probe on an NPN A. 16.80
D. IC
base, an ohmmeter reading between the B. 1.05
other transistor terminals should be: 13. A transistor may be used as a C. 0.20
A. open switching device or as a: D. 0.95
B. infinite A. fixed resistor
20. With a PNP circuit, the most positive
C. low resistance B. tuning device
voltage is probably:
D. high resistance C. rectifier
A. ground
D. variable resistor
6. In a C-E configuration, an emitter B. VC
resistor is used for: 14. If an input signal ranges from 20–40 C. VBE
A. stabilization µA (microamps), with an output signal D. VCC
B. ac signal bypass ranging from .5–1.5 mA (milliamps),
21. If a 2 mV signal produces a 2 V
C. collector bias what is the ac beta?
output, what is the voltage gain?
D. higher gain A. 0.05
A. 0.001
B. 20
7. Voltage-divider bias provides: B. 0.004
C. 50
A. an unstable Q point C. 100
D. 500
B. a stable Q point D. 1000
C. a Q point that easily varies with 15. Which is beta's current ratio?
22. The symbol hfe is the same as:
changes in the transistor's A. IC/IB
A. 𝜷𝑫𝑪
current gain B. IC/IE
B. 𝛼𝐷𝐶
D. a Q point that is stable and C. IB/IE
C. hi-fi
easily varies with changes in the D. IE/IB
D. 𝛽𝐴𝐶
transistor’s current gain
16. A collector characteristic curve is a
23. Most of the electrons in the base of
8. To operate properly, a transistor's graph showing:
an NPN transistor flow:
base-emitter junction must be forward A. emitter current (IE) versus
A. out of the base lead
biased with reverse bias applied to which collector-emitter voltage (VCE)
B. into the collector
junction? with (VBB) base bias voltage
C. into the emitter
A. collector-emitter held constant
D. into the base supply
B. base-collector B. collector current (IC) versus
C. base-emitter collector-emitter voltage (VCE) 24. In a transistor, collector current is
D. collector-base with (VBB) base bias voltage controlled by:
held constant A. collector voltage
9. The ends of a load line drawn on a
C. collector current (IC) versus B. base current
family of curves determine:
collector-emitter voltage (VC) C. collector resistance
A. saturation and cutoff
with (VBB) base bias voltage D. all of the above
B. the operating point
held constant
C. the power curve
D. collector current (IC) versus 25. Total emitter current is:
D. the amplification factor
collector-emitter voltage (VCC) A. IE – IC
10. If VCC = +18 V, voltage-divider with (VBB) base bias voltage B. IC + IE
resistor R1 is 4.7 kΩ, and R2 is 1500 Ω, held constant C. IB + IC
what is the base bias voltage? D. IB – IC
17. With low-power transistor packages,
A. 8.70 V
the base terminal is usually the:
B. 4.35 V 26. Often a common-collector will be
A. tab end
C. 2.90 V the last stage before the load; the main
B. middle
D. 0.7 V function(s) of this stage is to:
C. right end
A. provide voltage gain
D. stud mount
 INDIABIX 3
B. provide phase inversion D. 1
9. IDSS can be defined as:
C. provide a high-frequency path
2. When an input delta of 2 V produces a A. the minimum possible drain
to improve the frequency
transconductance of 1.5 mS, what is the current
response
drain current delta? B. the maximum possible current
D. buffer the voltage amplifiers
A. 666 mA with VGS held at –4 V
from the low-resistance load
B. 3 mA C. the maximum possible current
and provide impedance
C. 0.75 mA with VGS held at 0 V
matching for maximum power
D. 0.5 mA D. the maximum drain current
transfer
with the source shorted
3. When not in use, MOSFET pins are
27. For a C-C configuration to operate
kept at the same potential through the 10. What is the input impedance of a
properly, the collector-base junction
use of: common-gate configured JFET?
should be reverse biased, while forward
A. very low
bias should be applied to which A. shipping foil
B. low
junction? B. nonconductive foam C. high
A. collector-emitter C. conductive foam D. very high
B. base-emitter D. a wrist strap
C. collector-base 11. JFET terminal "legs" are connections
D. cathode-anode 4. D-MOSFETs are sometimes used in to the drain, the gate, and the:
series to construct a cascode high- A. channel
28. The input/output relationship of the
frequency amplifier to overcome the loss B. source
common-collector and common-base
of: C. substrate
amplifiers is:
A. low output impedance D. cathode
A. 270 degrees B. capacitive reactance 12. A very simple bias for a D-MOSFET is
B. 180 degrees C. high input impedance called:
C. 90 degrees D. inductive reactance A. self biasing
D. 0 degrees 5. A "U" shaped, opposite-polarity B. gate biasing
29. If a transistor operates at the middle material built near a JFET-channel C. zero biasing
of the dc load line, a decrease in the center is called the: D. voltage-divider biasing
current gain will move the Q point: A. gate 13. With the E-MOSFET, when gate
A. off the load line B. block input voltage is zero, drain current is:
B. nowhere C. drain A. at saturation
C. up D. heat sink B. zero
D. down
6. When testing an n-channel D- C. IDSS
30. Which is the higher gain provided by MOSFET, resistance G to D = ∞, D. widening the channel
a C-E configuration? resistance G to S =∞ , resistance D to SS 14. With a 30-volt VDD, and an 8-kilohm
A. voltage = ∞ and 500 Ω, depending on the drain resistor, what is the E-MOSFET Q
B. current polarity of the ohmmeter, and resistance point voltage, with ID = 3 mA?
C. resistance D to S = 500 Ω. What is wrong? A. 6V
D. power A. short D to S B. 10 V
31. What is the collector current for a C-E B. open G to D C. 24 V
configuration with a beta of 100 and a C. open D to SS D. 30 V
base current of 30 µA? D. nothing
15. When an input signal reduces the
A. 30 µA 7. In the constant-current region, how channel size, the process is called:
B. .3 µA will the IDS change in an n-channel JFET? A. enhancement
C. 3 mA A. As VGS decreases ID decreases. B. substrate connecting
D. 3 MA B. As VGS increases ID increases. C. gate charge
C. As VGS decreases ID remains D. depletion
FIELD EFFECT constant.
D. As VGS increases ID remains 16. Which JFET configuration would
TRANSISTORS (FET) constant connect a high-resistance signal source
to a low-resistance load?
1. Junction Field Effect Transistors 8. A MOSFET has how many terminals? A. source follower
(JFET) contain how many diodes? A. 2 or 3 B. common-source
A. 4 B. 3 C. common-drain
B. 3 C. 4 D. common-gate
C. 2 D. 3 or 4
 INDIABIX 3
17. How will electrons flow through a p- D. As frequency decreases input 31. Which component is considered to
channel JFET? impedance is constant. be an "OFF" device?
A. from source to drain A. transistor
25. The type of bias most often used
B. from source to gate B. JFET
with E-MOSFET circuits is:
C. from drain to gate C. D-MOSFET
A. constant current
D. from drain to source D. E-MOSFET
B. drain-feedback
18. When VGS = 0 V, a JFET is: C. voltage-divider 32. In an n-channel JFET, what will
A. saturated D. zero biasing happen at the pinch-off voltage?
B. an analog device A. the value of VDS at which
26. The transconductance curve of a
C. an open switch further increases in VDS will
JFET is a graph of:
D. cut off cause no further increase in ID
A. IS versus VDS
B. the value of VGS at which further
19. When applied input voltage varies B. IC versus VCE
decreases in VGS will cause no
the resistance of a channel, the result is C. ID versus VGS
further increases in ID
called: D. ID × RDS
C. the value of VDG at which
A. saturization
27. The common-source JFET amplifier further decreases in VDG will
B. polarization
has: cause no further increases in ID
C. cutoff
A. a very high input impedance D. the value of VDS at which further
D. field effect
and a relatively low voltage increases in VGS will cause no
20. When is a vertical channel E- gain further increases in ID
MOSFET used? B. a high input impedance and a
A. for high frequencies very high voltage gain THYRISTORS AND
C. a high input impedance and a
B. for high voltages TRANSDUCERS
voltage gain less than 1
C. for high currents D. no voltage gain
D. for high resistances 1. A TRIAC:
21. When the JFET is no longer able to 28. Using voltage-divider biasing, what A. can trigger only on positive gate
control the current, this point is called is the voltage at the gate VGS? voltages
the: B. can trigger only on negative
A. breakdown region gate voltages
B. depletion region C. cannot be triggered with gate
C. saturation point voltages
D. pinch-off region D. can be triggered by either a
positive or a negative gate
22. With a JFET, a ratio of output current voltage
change against an input voltage change
is called: 2. When checking a good SCR or TRIAC
A. transconductance with an ohmmeter it will:
B. siemens A. show high resistance in both
A. 5.2 V directions
C. resistivity
B. 4.2 V B. show low resistance with
D. gain
C. 3.2 V positive on anode and negative
23. Which type of JFET bias requires a D. 2.2 V on cathode, and high resistance
negative supply voltage? when reversed
29. The overall input capacitance of a
A. feedback C. show high resistance with
dual-gate D-MOSFET is lower because
B. source negative on anode and positive
the devices are usually connected:
C. gate on cathode, and low resistance
A. in parallel
D. voltage divider when reversed
B. with separate insulation
24. How will a D-MOSFET input C. with separate inputs D. show low resistance in both
impedance change with signal D. in series directions
frequency? 3. What does a hall effect sensor sense?
30. What is the transconductance of an
A. As frequency increases input
FET when ∆ID = 1 mA and ∆VGS = 1 V? A. temperature
impedance increases.
A. 1 kS B. moisture
B. As frequency increases input
B. 1 mS C. magnetic fields
impedance is constant.
C. 1kΩ
C. As frequency decreases input D. pressure
D. 1mΩ
impedance increases.
4. What causes the piezoelectric effect?
 INDIABIX 3
A. heat or dissimilar metals 14. The DIAC is a:
B. pressure on a crystal A. transistor
C. water running on iron B. unidirectional device
D. a magnetic field C. three-layer device
D. bidirectional device
5. Which is the DIAC?
15. What type of application would use
an injection laser diode?
A. a 10BASE-T Ethernet
A. A. B. a liquid crystal display
C. a fiber optic transmission line
D. a good flashlight
16. The PUT (programmable unijunction
B.
B. transistor) is actually a type of:
A. UJT thyristor
B. FET device
C. C. TRIAC
D. SCR

C. 17. A transducer's function is to:

D. A. transmit electrical energy
B. convert energy
6. A UJT has: C. produce mechanical energy
D. prevent current flow
A. two base leads
B. one emitter lead D.
C. two emitter leads and one base
lead 11. The smallest amount of current that
D. one emitter lead and two base the cathode-anode can have, and still
leads sustain conduction of an SCR is called
the:
7. The only way to close an SCR is with: A. maximum forward current
B. maximum forward gate current
A. a trigger input applied to the C. holding current
gate D. reverse gate leakage current
B. forward breakover voltage
C. low-current dropout 12. Once a DIAC is conducting, the only
D. valley voltage way to turn it off is with:
A. a positive gate voltage
8. What is an SCR? B. a negative gate voltage
A. a PNPN thyristor with 3 C. low-current dropout
terminals D. breakover
B. a PNPN thyristor with 4
terminals 13. Which is the TRIAC?
C. a PNP thyristor with 3 terminals
D. an NPN thyristor with 3
terminals
9. What type of application would use a A.
photovoltaic cell?
A. an automobile horn
B. a TI 92 calculator B.
C. a magnetic field detector
D. a remote power source
10. Which is the seven-segment display? C.

D.