PADS AND ESD PROTECTION

ELC601 Presentation

Ahmed Essa

Cairo University Faculty of Engineering

December 21th ,2019

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 Table of Contents

1 Pads

2 Introduction to ESD

3 Human-Body-Model (HBM)

4 Power-Rail ESD Clamp

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 Table of Contents

1 Pads

2 Introduction to ESD

3 Human-Body-Model (HBM)

4 Power-Rail ESD Clamp

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 Pads

Used to connect the circuit core

to bond wires
Placed on the perimeter of the
chip
Size dictated by the
manufacturing process, usually
between 75µm × 75µm and
100µm × 100µm
The two topmost metal layers
are used to avoid lift-off
An octagon can be used to
reduce the area by 20%

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 Table of Contents

1 Pads

2 Introduction to ESD

3 Human-Body-Model (HBM)

4 Power-Rail ESD Clamp

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 Introduction to ESD

Electrostatic Discharge (ESD) is caused by high potential external

objects touching a connection.
ESD produces a large voltage which may damage the transistors or
the connections.
Several testing standards are used to rate devices/systems.
Device level tests include HBM, MM, and CDM
System level tests include ESD immunity, EFT immunity, and surge
immunity.

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 Table of Contents

1 Pads

2 Introduction to ESD

3 Human-Body-Model (HBM)

4 Power-Rail ESD Clamp

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 HBM
Test Specifications

A device level test that simulates an electrical discharge of a human

onto an electronic component.
Diodes can be used as ESD protection devices.
The voltage range is from 0.5KV up to 15KV .
The typical peak current is around 1.5A

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 HBM
Test Specifications

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 HBM
Test Connections

Positive/Negative-to-VSS /VDD Connections

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 HBM
Test Connections

Pin-to-pin and VDD -to-VSS connections

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 Table of Contents

1 Pads

2 Introduction to ESD

3 Human-Body-Model (HBM)

4 Power-Rail ESD Clamp

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 Power-Rail ESD Clamp
Introduction

R1 is used to limit the ESD current

flowing through the diodes.
ESD devices may impact the
performance of the chip.

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 Power-Rail ESD Clamp
Introduction

A large NMOS transistor(BigFET) connects VDD to VSS .

Provides a low-impedance path from VDD to VSS during ESD events.
Needs an ESD-Transient Detection Circuit to turn on.

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 Power-Rail ESD Clamp
RC-Clamp

Assume the ESD-transient voltage is

applied on VDD .
Vx increases at a much slower rate due
to the RC time constant.
VG turns the clamp on for ton then goes
to zero.
For a large ton large values of R and C
must be used.
The circuit is prone to miss-trigger
under fast-power-on application.

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 Power-Rail ESD Clamp
Feedback

A positive feedback loop is used to

sustain the latch-on of the clamp until
the end of the ESD event.
The feedback loop is triggered using the
parasitic capacitance of the clamp.
Diodes are added to control the holding
voltage

Vh ' nVON (Diode) + |VT HP | > VDD

Area saving can reach up to 54%

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 Power-Rail ESD Clamp
Voltage Wave-forms

ESD-Like Voltage Pulse

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 Power-Rail ESD Clamp
Voltage Wave-forms

Fast-Power-On Voltage Pulse

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