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ATMT 4213 Advanced Materials Testing and Evaluation
(a) (b)
Figure 1.0: (a) P-type semiconductor that is formed by the doping of Boron atoms. The Boron
atom creates a hole. (b) N-type semiconductor that is formed by the doping of phosphorus
atoms. The phosphorus atom creates an extra electron.
Figure 1.1: (a) Diode (inside the red circle) that mounted on the circuit board; (b)
Transistors in various types and forms; (c) An integrated circuit (IC).
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Semiconductor devices consist of two major parts: a tiny and fragile silicon chip (die)
together with a package that intended to protect the internal chip. For an integrated
circuit (IC), diodes and transistors are embedded within the silicon chip. The
manufacturing process of all semiconductor devices is basically almost similar. But a
more complex multi-step processes will be involved if the device is designed for a
higher level of functional purpose such as IC.
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Figure 2.1: The manufacturing of a semiconductor device can be divided into frond-end
processing and back-end processing.
Logic circuit design is a very important part for the manufacturing of semiconductor
devices. It must be done before any manufacturing processes could starts. The
expected functions and performances of device are determined and drawn into a logic
circuit diagram. Stimulations are performed multiple times to test the circuit’s
operation. If there is no any faulty with the operations, the actual layout pattern for the
devices and interconnects is designed by using CAD software. This actual layout is
used to create the mask pattern of devices.
The mask pattern functions as a photomask to transcribe the design onto the
surface of wafer during front-end processing. Photomask is simply a copy of designed
circuit pattern that drawn on a glass plate coated with a metallic film. Light is able to
pass through the glass plate, but the metallic film does not. The circuit pattern is
exposed on the photomask by using a state-of-the-art mask drawing system. Due to
the increasingly high integration and miniaturization of the pattern, the size of the
photomask is usually magnified four to ten times the actual size, depending on the
irradiation equipment.
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Figure 2.2: Photomask is used to transcribe the logic circuit design onto the surface of wafer.
Wafer fabrication is carried out in a wafer fab which is isolated from the outside
environment and contaminants. Wafer fab is a cleanroom that air cleanliness is one
million times better than the air we normally breathe in a city, or some orders of
magnitude better than the air in a heart transplant operating theatre. Silicon chip could
be easily spoiled or failed due to the presence of contaminants such as particles,
metallic impurities, organic contaminants, native oxides and electrostatic discharge.
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Figure 2.3: The overall flow process of frond-end processing to manufacture the die on
wafer.
Wafer is a thin, circular slice of semiconductor material that made from silicon ingot
with purity as high as 99.999999999% (eleven-nine) through either the Czochralski
[3]
(CZ) or the Float Zone (FZ) method. It is a single-crystal silicon substrate with
near-perfect crystalline properties where the logic circuit will build within the silicon
lattice. Quartzite is a type of sand that used as the raw material for wafers. The sand
will undergoes a complicated refining process to become electronic grade polysilicon
(EGS). [5] In Czochralski method, the EGS (silicon chunks) are loaded and heated in a
crucible of furnace at temperature about 1600°C. Once the chunks of silicon are
melted, a seed crystal will be lowered into the furnace until it touches the melt. The
seed will begin to rotate and slowly retracted by CZ crystal puller from the furnace at
a controlled rate. A cylindrical, single crystal silicon ingot is grown from the
withdrawal process.
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Figure 2.4: Process of withdrawing the single-crystal silicon ingot from furnace.
The ingots will subject to a series of routine evaluation to ensure they meet the
quality requirements. It is then ground using diamond wheels to make it a perfect
cylinder with the right diameter. An etching process is done on the ingots to remove
the mechanical imperfections left by the grinding process. The cylindrical ingot will
undergoes another round of grinding to produce one or more ‘flat’ on its surface.
Once these completed, the ingots are sliced into thin wafer with a diamond saw, each
of which will be subjected to further etching to remove damage and contamination,
followed by polishing to create mirror-finish surface on the wafer. The wafer is ready
to be used as the substrate for production of chip. [6]
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Figure 2.5: The ingot is sliced into thin wafer and mirror-finished on one side of its surface.
2.2.2 Deposition
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consumption of original wafer. The silicon dioxide is created with the purpose such as
acts as a protection layer of the device from scratches and contaminations, field
isolation (surface passivation), gate dielectric material, doping barrier and deposited
dielectric layer between metal conductor layers. [7]
Figure 2.6: The growth of oxide layer on the wafer by thermal growing process.
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Figure 2.7: Chemical Vapour Deposition (CVD) is used to produce new layer such as
polycrystalline thin films, silicon nitride, SiO2, and epitaxial layer on the wafer.
Figure 2.8: Physical Vapour Deposition (PVD) in the form of sputtering is used to carry out
metallization process on the wafer.
2.2.3 Photolithography
Photolithography is a process that defined the pattern of depositing layers and the
doping region on the substrate. The fabrication of circuit on silicon wafer requires
several different layers. Each of the layers has different pattern where the deposition
is done one at the time on that particular surface. The doping of active regions is
carried out in very controlled amount over tiny regions of precise areas. [10]
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in the resist is the same pattern as the photomask whereas negative photoresist
produced a resist image which is negative of the pattern found on the photomask. [7]
Figure 2.10: Two type of photoresist layer is produced after development: positive
photoresist and negative photoresist.
2.2.4 Etching
Etching is the process of removing regions of the underlying material that are no
longer protected by the photoresist after development. It is done by using either
chemical or physical means. There are two types of etching process which are dry
etch and wet etch.
Dry etch exposes the wafer to a plasma (ionized gas) that interacts physically
or chemically (or both) to remove the surface material. It is normally used to deal with
metallic films. Wet etch uses liquid chemicals to chemically remove the wafer surface
material. Wet etch normally is used for oxide films. [7]
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When an etching process is proceed in all directions at the same rate, the
etching process is said to be isotropic. Inversely, if it is proceeds in only one direction,
it is completely anisotropic. Wet etching is generally isotropic whereas dry etching
process is anisotropic in nature. [10]
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concentration gradient of dopant is remains between them. After certain times, the
dopant gases “drive in” into the silicon lattice with the aid of thermal energy. The
concentration gradient of dopant at the surface of the substrate is decreases with time.
The used of thermal diffusion as the doping method has gradually declined nowadays
due to its poor control of doping concentration and depth. [11]
Figure 2.11: Dopant is introduced into silicon substrate through thermal diffusion.
Ion implantation method has steadily replaced thermal diffusion method due to
its superior advantages to doping the silicon substrate. The process is simpler but
more costly as the ion implanters are quite expensive. During ion implantation,
doping atoms are vaporized and accelerated toward the silicon substrate. These high-
energy atoms enter the crystal lattice and lose their energy by colliding with some
silicon atoms before finally coming to rest at some depth. Adjustment on the
acceleration energy could control the average depth of depositing dopants. [12]
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But the introduction of dopant into the lattice could cause the damage to the
lattice. The damage caused by atomic collisions or displacement by both methods
changes the electrical characteristics of the target. Many target atoms are displaced,
creating deep electron and hole traps which capture mobile carriers and increase
resistivity. Annealing is therefore needed to repair the lattice damage and put dopant
atoms in substitutional sites where they can be electrically active again. This is
known as activation where the the crystal lattice disturbances are repaired by making
the dopant as the part of silicon substrate.
Figure 2.13: Annealing is done on wafer to repair the silicon lattice which is damaged by
doping process.
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2.2.6 Passivation
Passivation is a process that involved the deposition of final passivating layer on top
of the wafer to protect the completed chip (die) from mechanical damage and
corrosion. The final layer often is made up of an amorphous insulating material or
glass. Silicon nitride (Si3N4) is one of the common passivating materials because of its
high resistant to diffusion, which is almost impenetrable to moisture and ionic
contaminants. It can be easily deposited with a low residual compressive stress that
making it less prone to cracking. Its interfacing with the underlying metal layers is
also very conformal. Besides that, it can be prepared with very low pinhole density.
Silicon nitride can be deposited using plasma-enhanced chemical vapour deposition
(PECVD) or low-pressure chemical vapour deposition (LPCVD). The overall front-
[13]
end processing can be said is totally completed after passivation.
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Figure 2.15: The overall flow process of back-end processing to assembly the dies into
individual package.
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(a) (b)
Figure 2.16: (a) The wafer is surface laminated by a protective film prior to backgrind
process. (b) Wafer is being backgrinding by the machine.
Die preparation is a process by which the wafer is cut into individual die in
preparation for assembly. Die preparation consists of two major steps, namely,
wafer mounting and wafer sawing.
Wafer mounting is done to provide the support to the wafer to facilitate the
processing of wafer during sawing through die attach. During wafer mounting, the
wafer frame and wafer are loaded subsequently on the machine. The wafer is
mounted on the frames by dicing tape (wafer film). Excess tape is cut off and the
mounted wafer is unloaded after completion of mounting. Dicing tape is just a PVC
sheet with synthetic adhesive on one side to hold the wafer frame and wafer
together. [15]
Figure 2.17: Wafer is mounted on the frames by dicing tape (wafer film).
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Wafer sawing is then carried out to cut the wafer into individual die for
package assembly. The frame-mounted wafer is automatically aligned into position
for cutting. The wafer is cut thru its thickness based on the programmed die
dimensions using a resin bonded diamond wheel rotating at very high rpm. The
wafer goes through a cleaning process using high pressure DI water sprayed on the
rotating workpiece and then dried by air-blowing. [15]
Figure 2.18: Wafer is cut into individual die by the diamond wheel of sawing machine.
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During wire bonding, a gold ball is formed by the melting the end of wire by a
bonding tool known as a capillary. The free-air ball is brought into contact with the
bond pad of the chip. An initial metallurgical weld is formed between the ball and the
bond pad. The application of pressure, heat, and ultrasonic forces in adequate
amounts for a specific period causes the ball bond itself deformed into the final
shape. The wire is then run to the corresponding finger of lead frame by forming a
gradual arc between the bond pad and leadfinger. Similar step is done on the wire to
form the fishtail bond (second bond) with the leadfinger. The wire bonding machine
breaks the wire by clamping the wire and raising the capillary in preparation for the
next wire bonding cycle. [17]
Figure 2.20: (a) Needle lowered. (b)Welding the ball to bond pad. (c) Welding the wire to
leadfinger. (d) Cutting the wire.
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2.3.5 Encapsulation
Encapsulation is the process of moulding the die and the cavity of the lead frame
together with moulding resin for protection. Transfer moulding is one of the most
widely used moulding process in semiconductor industry due to its capability to
mould small parts with complex features.
In this process, the moulding compound is preheated before loading it into the
moulding chamber. After preheating, the hydraulic plunger is rotated to force the
moulding compound moving into the pot. The moulding compound becomes fluid
gradually as it reaching the melting temperature. The fluid (molten resin) is forced
into the runners of mould chase by the continuously rotation of plunger. The runners
serve as canals where the molten resin travels until it the cavities, which contain lead
frames for encapsulation. Once the encapsulation is done, the excess flashes from the
package of the newly moulded parts are trimmed. The tie bars that connecting the
individual units to the lead frame are cut so that each unit is separated into individual
packages. The leads protruding from the package are formed into the correct shape
and position. [18]
Figure 2.21: The tie bars are cut to separate the each unit into individual packages.
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Figure 2.22: Information such as device name, company logo, date code, and lot id is
marked on the surface of package.
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evaluate the test results. Different devices require different levels of sophistication in
ATE equipment.
ATE assist the testing based on written software called test program. The test
program consists of a series of subroutines known as test blocks. Each test block
represents a corresponding device parameter to test under specific conditions. The
device under test (DUT) is subjected to specific excitation and the resulting response
of the device is measured. The measurement is used to compare with the pass/fail
limits that set in the test program. Once the device tested, the handler of ATE will
classify the device either as a reject or as a good unit.
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3.1.1 Temperature Cycling Test (TCT) and Thermal Shock Test (TST) [20] [21]
Semiconductor devices are very prone to fail when subject to sudden temperature
changes during their real-life application. Hence, it is important to ensure their
reliability in such environment. There are two testing method that being employed in
semiconductor industry for this purpose, which are Temperature Cycling Test (TCT)
and Thermal Shock Test (TST).
TCT is performed to determine the ability of devices to resist extremely low
and extremely high temperatures, as well as their ability to withstand cyclical
exposures to these temperature extremes. It is a testing that accelerates fatigue failure.
During TCT, the sample is firstly exposes under specified low (or high) temperature;
follow by subjects the same unit to the specified high (or low) temperature for a
specified number of cycles using Temperature Cycle Chamber.
TST is a test that closely resembles TCT for some aspects but it is more on
determines the resistance of the devices to sudden temperature changes in a much
shorter period of time. In this test, the sample undergoes a specified number of cycles
that starts at ambient temperature. The sample is then exposed to an extremely low (or
high) temperature and, within a short period of time, exposed to an extremely high (or
low) temperature, before going back to ambient temperature.
After final cycle, external visual examination is carried out in TCT and TST.
The inspection on the case, leads and seals should be performed at a magnification of
10 X to 20 X. The marking should also be inspected at a magnification not greater
than 3 X. If there is any illegal mark and/or any evidence of damage to the case, lead,
or seals after stress test, the sample is considered as failure. For both of the test,
electrical testing is done on the sample via ATE in order to detect electrical failures
accelerated by temperature cycle. Generally, failure mechanisms accelerated by both
tests include die cracking, package cracking, neck/heel/wire breaks, and bond lifting.
Failure acceleration due to Thermal Shock and Temp Cycling depends on the
following factors:
difference between the high and low temperatures used;
transfer time between the two temperatures;
dwell times at the extreme temperatures.
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For reliability testing or qualification of new devices, 1000 temp cycles are
usually performed, with intermediate visual inspection and electrical testing read
points at 200X and 500X.
(a) (b)
Figure 3.0: (a) Temperature Cycle Machine. (b)Thermal Shock Chamber.
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repetitive in nature, it can also cause the damage on device that is similar to those
caused by extreme vibration.
After the mechanical shock test has been completed, external visual inspection
of the case, leads, and seals is performed at a magnification of 10 X to 20 X. The
marking is also inspected with or without magnification, but with the magnification
not greater than 3 X. If any illegible mark and/or any evidence of damage to the case,
leads, or seals after the stress test are identified, the device is considered a failure.
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Vibration test are tests performed to determine the effects of mechanical vibration
within a specified frequency range on semiconductor devices. Basically, there are
two different types of vibration tests, which are vibration fatigue test and variable
frequency vibration test. Both of them are similar in many aspects, but each of them
is intended to reveal different types of vibration-related failures.
For vibration fatigue test, the sample is subjected to sustained vibration within
specified levels. There is optical and electrical equipment that used to perform post-
test measurements. During the test, the sample is fixed on the vibration platform with
its lead adequately secured. The sample is then subjected to a simple harmonic
vibration that a constant amplitude having a peak acceleration corresponding to the
specified test condition. The vibration is performed for minimum of 32+/- 8 hours in
each of X-, Y- and Z- orientations, for a total of 96 hours minimum.
For variable frequency variation test, the sample is subjected to variable
frequency vibration at specified levels. It is same as vibration fatigue test in which
there is also optical and electrical equipment to perform the post-test measurements.
During the test, the sample is firmly fastened on the vibration platform with its leads
adequately secured. The sample is then subjected to a simple harmonic vibration that
has either peak-to-peak amplitude of 0.06 inch +/- 10% or a peak acceleration of the
specified test condition. The vibration frequency is varied approximately
logarithmically between 20 and 2,000 Hz. The entire frequency range of 20-2000 Hz
and the return to 20 Hz must be traversed in not less than 4 minutes. This cycle is
performed 4 times in each of the orientations X, Y, and Z, for a total of 12 times.
Once the vibration test has been completed, external visual inspection of the
case, leads, and seals is performed at the magnification of 10 X to 20 X. The marking
is also inspected with or without magnification, but with the magnification not
greater than 3 X. If there is any illegible mark and/or any evidence of damage to the
case, leads, or seals after the stress test, the device is considered as a failure.
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Table 3.6: Mil-Std-883 Method 2005 Vibration Fatigue Testing Test Conditions
Table 3.7: Mil-Std-883 Method 2007 Variable Frequency Vibration Testing Test
Conditions
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Burn-in test is an electrical test that accelerates the electrical failure of a device
through the application of voltage and temperature under over range condition. The
electrical excitation applied during burn-in may mirror the worst case bias that the
device will be subjected to in the course of its usable life. Thus, burn-in essentially
stimulates the operating life of the device. Depending on the burn-in duration used,
the reliability information obtained may pertain to the device’s early life or its wear-
out.
Burn-in is usually carried out by applying the electrical excitation to the
sample at temperature about 125°C. During the testing, the samples are loaded into
the burn-in boards. These burn-in boards are then inserted into the burn-in oven in
which the samples are supplied with necessary voltages while maintaining the
temperature at 125°C. The electrical bias applied may either be static or dynamic,
depending on the failure mechanism being accelerated.
(a) (b)
Figure 3.1: (a) Burn-in boards. (b)Burn-in ovens.
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Early Life Failure (ELF) is a type of burn-in test that perform to screen out
potential early life failures. Inversely, High Temperature Operating Life (HTOL) and
Low Temperature Operating Life (LTOL) is burn-in test that identify the reliability of
the samples in their wear-out phase.
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(a) (b)
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Figure 3.4: (a) HAST system: the Trio Tech 6000X (b) the chamber of the Trio Tech
6000X
3.1.7 High Temperature Storage (HTS) [29]
High Temperature Storage test is performed to determine the effect of long-term
storage at elevated temperature without any electrical stresses applied. HTS is not
substitute for burn-in because it does not subject the sample to electrical stresses
(bias). This test is effective for testing the sample in terms of mechanism accelerated
by temperature only such as oxidation, bond and lead finish intermetallic growth, etc.
Any oven or chamber capable for providing controlled elevated temperature
can be used for HTS. It is similar to stabilization bake, except that HTS is done over a
much longer period of time at specific temperature. For example, HTS is conducted at
150°C for duration 1000 hours instead of 24 hours for stabilization bake. The purpose
of HTS is to assess the long-term reliability of devices under high temperature
conditions while that of stabilization bake is merely to serve as a preconditioning
treatment prior to conduct other tests.
The example of High Temperature Storage (HTS) test specification that used in
semiconductor industry:
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4.0 Conclusions
Semiconductor devices had change the human world tremendously in this past few
year decades. They are the fundamental of electronic equipment for many applications
such as mobile phones, automobiles and computers. Its related technology is growing
in a rapid and unbelievable rate. The current semiconductor device is undergoes the
trend of miniaturization in size and complexity of device functions. Hence, this result
in more difficulties arises during the manufacturing of devices. The manufacturers
have the responsibility to ensure the quality for each batch of product is within the
safety limits. Otherwise, this would incur a huge lost if the device fail to perform as
intended.
As a result, reliability issue of the devices become the primary concern in all
the semiconductor industries. Reliability testing indirectly becomes the efficient tools
to assess and evaluate the performance of the manufactured devices. In addition,
semiconductor devices are manufactured in mass volume to gain economic scale of
benefits. The manufacturing of the device is high in complexity and involve multi-
step process. Any mishandling either by worker or the machine during the
manufacturing process could the whole batch of the devices to be failed. Thus,
reliability testing is important because these tests function as a mean to control and
monitor the whole process. The successful for the flow of manufacturing process is
depends greatly on the use of reliability testing.
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5.0 References
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23. Siliconfareast, 2006, Vibration Tests - Mil-Std-883 Methods 2005 and 2007,
viewed 23 July 2010, <http://www.siliconfareast.com/vibration-tests.htm>
24. Siliconfareast, 2006, Burn-in, viewed 23 July 2010
<http://www.siliconfareast.com/burnin.htm>
25. Siliconfareast, 2006, High Temperature Operating Life (HTOL) Test,
viewed 23 July 2010 <http://www.siliconfareast.com/HTOL.htm>
26. Siliconfareast, 2006, Low Temperature Operating Life (LTOL) Test,
viewed 23 July 2010, <http://www.siliconfareast.com/LTOL.htm>
27. Siliconfareast, 2006, Temperature, Humidity, Bias (THB) Test,
viewed 23 July 2010, <http://www.siliconfareast.com/THB.htm>
28. Siliconfareast, 2006, Highly Accelerated Stress Test (HAST), viewed 23 July
2010, <http://www.siliconfareast.com/HAST.htm>
29. Siliconfareast, 2006, High Temperature Storage (HTS) , viewed 23 July 2010
<http://www.siliconfareast.com/HTS.htm>
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